Hi Mohammed,
I am not quite sure what you mean “sacrifice coherency for timing”. Even though you simulate a multi-core processor later, the memory can still work as long as you have a shared last level cache. In other words, the cache system will handle the coherency issue. The simpleDRAM does report many statistical results. If you are using the most recent version of gem5, you can even specify the memory model you want to use in the command line by “--mem-type=”. The available options are “simple_mem” (by default), “ddr3-1600” (an instance of SimpleDDR3), “lpddr2_s4-1066” (an instance of SimpleLPDDR2_S4), and “wio-200” (an instance of SimpleWideIO). You can refer to configs/common/Options.py for the definition of command line option, and configs/common/MemConfig.py for the list of available options. After you finish a simulation, you can see the performance report in m5out/stats.txt. -Tao From: [email protected] [mailto:[email protected]] On Behalf Of Mohammed G. Khatib Sent: Tuesday, May 28, 2013 5:26 PM To: gem5 users mailing list Subject: Re: [gem5-users] Configuring a 3 level memory hierarchy Hi Tao, Thanks for your answers. I read about simpleDRAM which I can use. But it seems, from my readings so far, is that I need to sacrifice coherency for timing in case I want to go mutli-core later. Is that correct? Can you point out how I can use simpleDRAM (an example) and also activate its statistics (heatmap, distributions, latencies, ...? Thank you, Mohammed -- Mohammed G. Khatib, PhD. Postdoctoral Researcher NEC Laboratories America, Inc. T: +1 (609) 902 6375 4 Independence Way, Suite 200 E: [email protected] Princeton, NJ 08540 W: www.nec-labs.com/~khatib USA On Tue, May 28, 2013 at 5:15 PM, Tao Zhang <[email protected]> wrote: Hi Mohammed, Please see my answers to your questions below. -Tao From: [email protected] [mailto:[email protected]] On Behalf Of Mohammed G. Khatib Sent: Tuesday, May 28, 2013 4:43 PM To: [email protected] Subject: [gem5-users] Configuring a 3 level memory hierarchy Hi all, This is my first time using gem5 and I want to simulate a single-core systen. I want to make sure that I got the caches, their protocol and the CPU right and realistic for "accurate" timings. Here is what I need: 1. A single-core cpu with all cache levels (I want to try with and without L3 cache). 2. I want to use the SE execution model since I think this is sufficient. 3. A time-accurate memory model for DRAM where I can get latency distribution of accesses, total number of accesses, number of writes to each memory work/byte, number of reads. - I am not sure if ruby is of good use here or your a DRAM model is sufficient? What do you suggest? Ruby does not have a time-accurate DRAM model yet. Alternatively, classic memory system has relatively higher accuracy. You can leverage classic memory system directly. - In the config.ini file cpu clock and cache latency do not have units, what are the units? The default unit is picosecond (ps). A 2GHz clock is therefore shown as “clock = 500”. - Can anyone point me or help set up a configuration file? You can refer to the thread http://www.mail-archive.com/[email protected]/msg07019.html to create your own configuration file. Basically I want to test running a program on DRAM and see the distribution of writes and reads to memory addresses. Also I want to gather latency information to see DRAM contribution to the overall performance. Thanks, Mohammed _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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