Hi Nilay,
Maybe I didn't make it clear. What I want is to run Multi-programmed
simulation rather than multi-threaded simulation. In other words, I want
4 cores to run 4 benchmarks (though they are all same) and each core has
only 1 thread. As a result, I set "np = 4 and numThreads = 1" in my
configuration script. I also produced 4 identical LiveProcess() and
assigned them to each core. However, the simulation immediately
terminated after the cpu switching from atomic to detailed, with message
"a thread reached the max instruction count". I go through the
Simulation.py, src/cpu/base.cc, src/cpu/O3/commit_impl.cc but didn't
find the clue that I have wrongly set the -F and -I with the same number
(100000000).
If the instruction count is based on the thread and no change during the
cpu switching, why I can use -F and -I together for single-core
simulation? The final results show that the atomic cpu run the first
100000000 instructions and then the detailed cpu run the second half
instruction. The total "sim_insts" in the final stats is 200000001.
Also, I did a simple test to change the -F and -I number as "-F 1000 -I
6000", which is supposed to work well. Unfortunately, I got the same
result...
It should be easy to fix as soon as I can find the codes for the cpu
switch. Do you mind tell me where it is so that I can work it out? Also,
I have another question: Even though the benchmarks are same, I assume
the physical address range to accommodate each benchmark is still
different since gem5 generates 4 process stacks with different address
mapping. Is it correct?
Thanks a lot!
Tao
On 10/03/2012 11:24 AM, Nilay Vaish wrote:
On Wed, 3 Oct 2012, Tao Zhang wrote:
Dear all,
I was trying to run multiple SAME spec2006 benchmarks under SE mode. For
example, I employed 4 cores and each core run bzip2 independently.
When I
used fastforward "-F" and maximum instruction "-I", the whole simulation
terminated exactly after the CPU switching. It seems like the
switched CPU
thought it has hit the maximum instruction number. Originally, I
think it
What do you mean by seems like? Is it happening in a non-deterministic
fashion? gem5 should have printed the reason for exiting the simulation.
may be caused by the use of the same binary file. However, after I
read the
Simulation.py, both "-F" and "-I" are applied to the cpu models,
rather than
the processes. Therefore, the switched CPU should start with instruction
number 0..
Instruction accounting is done on a per thread basis, so the
simulation will end after switching of cpus as the threads still
remain the same. I guess you know what you need to do to keep the
simulation going after switching of cpus.
--
Nilay
_______________________________________________
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
