example, at the beginning I have 4 cores running one threads per core.
> Then I want to move thread 2 to core 0 and thread 3 to core 1, leaving core
> 2&3 idle. Is it possible to do it on the Gem5 side only, without changing
> the Linux OS?
>
> Thanks in advance
>
Hi Ignatios,
I think you're running into a problem that I recently experienced.
Try applying this patch and see if it solves your problem.
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -1049,7 +1049,8 @@
if
HI David,
I imagine this has something to do with thumb vs ARM code and the
implementation of the code not being able to recognize and properly handle that
distinction when setting break points.
Thanks,
Ali
On Apr 7, 2013, at 1:58 PM, David Gloe wrote:
> Hello,
>
> I'm testing some instrume
Hi Tianyun,
There isn't a particularly easy way because it's difficult to know what
application is running (it can be done though) and then when you know that you
need to get symbols which are only on the disk image. If you have a particular
app you should be able to hack gem5 a bit and read in
users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On
> Behalf Of Ali Saidi
> Sent: Monday, March 25, 2013 8:34 PM
> To: gem5 users mailing list
> Subject: Re: [gem5-users] How to adjust the window size of VNC
>
> The code you're pointing to specifies the max size
The issue with ARM was that the TLB was holding onto squashed
instructions for a long time trying to translate them. The fix was to
squash the walks. See http://repo.gem5.org/gem5/rev/baa17ba80e06
Something similar probably needs to be done with x86.
Ali
On
16.04.2013 13:35, Jiachen Xue wrot
Hi David,
On 18.04.2013 12:30, David Miller wrote:
> Of course,
BARs are a PCI thing.
>
>> and if you add a range that is unique (not
in the normal memory range for example) it should work fine. The bus
will tell you if there are multiple destinations for the same address.
Could you perhaps
I'd guess that all the writes are being captured in your large l2
and never spilled back to memory.
Ali
On 18.04.2013 13:40, tejasi
pimpalkhute wrote:
> Hi All,
>
> I am running splash2 benchmarks in
SE mode and I am getting the number of write requests to the memory
controller as 0 for
Depends on what you're after. You can have gem5 create an ever on linux's
__switch_to function and see what thread is running on which core by inspecting
some kernel data structures. This is done for Alpha and for ARM.
Ali
On Apr 23, 2013, at 6:16 AM, tod wrote:
>
> hi everyone!
>
> what
Hi Mehmet,
You have to have a kernel that has some symbols (like thread_info_size,
thread_info_task, …) in it so gem5 can find these values.
You probably need to add these to your kernel:
http://repo.gem5.org/linux-patches/file/0ab58d9bd9a5/m5/m5struct.diff
Ali
On Apr 22, 2013, at 8:11 AM,
Hi Amin,
Maybe, but the way it's written also makes some sense in that accesses is
accesses that were from a cpu request, as opposed to a write back which is
cache generated.
Ali
On Apr 21, 2013, at 7:04 PM, Amin Farmahini wrote:
> I have a question about the stats generated in classic memo
On Apr 19, 2013, at 10:38 AM, Panagiwtis Mitsis wrote:
> Hello guys i'm having the following problem with the gem5 simulator for ALPHA
> architecture.I'm running the parsec benchmark suite and specifically the
> blackscholes application with the input file "in_4.txt". My cross compiler
> vers
On Apr 19, 2013, at 10:33 AM, Yijie Bai wrote:
> But I am using OSX 10.7.4 instead Yes, before installing gcc45 w
> macport, I have used that compiler for several times and it definitely work
> fine.
Have you looked at what is in the scons_config.log?
Ali
___
On Apr 18, 2013, at 6:41 PM, Nandhini wrote:
> I am new to GEM5. I would like to profile a particular function in my program
> in the following way :
>
> m5_dumpreset_stats(0,0);
> ///function
> m5_dumpreset_stats(0,0);
>
> I compiled my benchmark with $GEM5_DIR/util/m5/m5op_arm.S. This worked
On 24.04.2013 09:07, huangyongbing wrote:
> Hi all,
>
> I want
to save the changing of disk image. According to the introduction in
http://gem5.org/Bbench-gem5 [2], I boot the simulation using the raw
idle disk, and execute "busybox sync" and "busybox halt -f". Then, the
system is pending th
On 24.04.2013 21:02, Ding, Hongyuan wrote:
> Hi all,
> I want to
print all the virtual addresses of instruction cache misses. I noticed
that in the function Cache::access() in cache_impl.hh, the
DPRINTF will print the address of a cache access: pit->getAddr(). But
I'm not sure it's the virtual
Do you mean when android is running? Because the code below looks like it will
attach both to the simulator.
Ali
On Apr 16, 2013, at 12:33 AM, huangyongbing wrote:
> Hi all,
>
> I create two images for ARM platform using the following codes. But
> I don’t know how to mount the seco
Both the TimingSimpleCPU and the O3 CPU use sendTimingReq() to send a
transaction to the memory system, however both do not use the same code you
referenced. The PC is a member of the Request object that the Packet object
points to, but I'm not sure how it is captured with ruby.
Ali
On May 1
On May 10, 2013, at 11:26 AM, Amin Farmahini wrote:
> On Fri, May 10, 2013 at 10:10 AM, Erik Tomusk wrote:
>
> *It shouldn't be too difficult to re-introduce the access limit set by
> cachePorts. However, this change would be undone and superseded by patch
> #1422 on the reviewboard if it ev
Hi Negar,
When you restore you need to pass --at-instruction so the code that is
restoring from the checkpoint knows that the format should be by instruction
count and not tick count.
Thanks,
Ali
On May 10, 2013, at 8:14 AM, Negar Miralaei wrote:
> Hi,
>
> I'm trying to create a checkpoint
On May 9, 2013, at 8:04 PM, ignacio charalabidis wrote:
> Hello,
>
> in my last emails I had a problem when simulating for large of instructions
> (100 intervals of 10M instructions each), the assertion !freeList.empty() was
> raised.
>
> What actually made my system, run without any proble
Hi Mohammad,
Could you put this on the wiki somewhere or perhaps on qa.gem5.org so it will
be more easily searchable in the future?
Thanks,
Ali
On May 9, 2013, at 10:38 AM, Mohammad Sadegh Sadri
wrote:
> Dear All,
>
> I found the solution to my problem.
>
> In fact the problem was,
> when
Running bbench to completion can take more than 1 day of simulated time. I
believe it's around 45 seconds of simulated time, which is quite long.
Ali
On Apr 30, 2013, at 7:11 PM, Xiangyang Guo wrote:
> Hi, Gem5 user,
>
> I want to run Bbench FS mode with arm_detailed CPU, with the gb image
On May 1, 2013, at 4:00 PM, Newton Singh wrote:
> Hi all,
>
> I want to create a single core and multiple threads to execute the workload.
>
> I want to know what changes i should do for the same.
> Is modifying here and rebuilding gem5.XXX sufficient to change num of threads.
> smtNumFetching
On May 2, 2013, at 7:02 PM, Rodrigo Reynolds Ramírez
wrote:
> I have continued trying to understand how gem5 manage a writeback, but I am
> block in one function.
>
> The chain of calls is this, recvTimingReq (CacheImpl.hh) ->
> allocateWriteBuffer (base.hh) -> allocateBufferInternal (base.
t; So I have been trying to build one. Which version of gcc would you
>> suggest using? And I couldn't figure out what my target platform would
>> be. I tried to compile for alpha-dec-vms using gcc-4.8.0 and
>> bin-utils-2.23 but could find the required resources.
>>
The caches aren't guaranteed to be inclusive.
Ali
On May 2, 2013, at 10:15 PM, Chao Zhang wrote:
> Dear all,
>
> I met an issue when observing the cache is that I could not prove myself that
> gem5 classic cache model provides cache inclusive guarantee. I looked at the
> "Cache" debug trace,
Hi Andrea,
Some stats have a prerequisite defined prereq(). If the
stat itself is the prerequisite it's only printed if non-zero. If some
other stat is a prerequisite, it's only printed if that stat is
non-zero.
Thanks,
Ali
On 12.05.2013 18:16, Andrea Lottarini wrote:
> Hello Everyone,
- 원본 메일 ---------
보낸사람: Ali Saidi 받는사람 : tod 날짜: 2013년 5월 13일 월요일, 08시 05분 41초 +0900제목: Re: [gem5-users] gem5 FS mode and threads
If you change one of those python files you need to recompile the simulator, but you don't need to change them to actually change a parameter. You
Hi Uday,
The alarm event is used to check if any of the sockets
that gem5 is waiting on have any activity (e.g. gem5 terminal, vnc
server, ...). If you don't want to connect anything to a running process
it probably isn't necessary, and if you do you could probably come up
with an alternate so
Hi Divya,
I've never seen this issue before and a fresh copy of
the repository compiles and runs fine for me. I'd guess that something
weird is going on with python or swig and the scoping rulses, but I'm
not sure what it could be. What versions of python and swig are you
using?
Thanks,
Al
On May 22, 2013, at 3:56 AM, amina belhaj messaoud
wrote:
>
> hello ,
>
> I want to clone the version 8930 of gem5 , but I have this problem :
>
> hg clone http://repo.gem5.org/gem5
> destination directory: gem5
> abandon : destination 'gem5' is not empty
>
You're local copy of gem5 a
The bus that connects all the caches is busy and can't handle the next response
until the first one completely traverses it.
Ali
On May 21, 2013, at 11:43 AM, ignacio charalabidis wrote:
> Hello,
>
> I am having a question on how requests and responses are being routed. If on
> the same tick
You could compare an instruction trace from both cases.
Ali
On May 21, 2013, at 5:55 AM, Negar Miralaei wrote:
> Hi,
>
> I'm wondering if anyone could tell me why I'm getting completely different
> IPC and L2-miss-rate results for the two below situations:
>
> 1) Creating a checkpoint at a
There have been a lot of fixes to how gem5 switches cpus in the development
repository. I'd suggest you use that.
ali
On May 20, 2013, at 10:22 AM, zhangwuxiang wrote:
>
> Hi!
> I take a checkpoint with detailed cpu(o3) and add ruby module. But when
> restored it and put the option "--resto
On May 20, 2013, at 2:16 PM, ignacio charalabidis wrote:
> Hello again,
>
> I moved forward a little bit from my previous question and the things are
> more weird right now. I have made some changes in the gem5 and I have these:
>
> For example for some read requests in the data cache:
>
> 3
Try removing your build directory and recompiling.
Ali
On May 16, 2013, at 7:43 PM, Jyothish Soman wrote:
> Hi,
> I was trying to follow the adding CPU documentation on the m5 website, tried
> to extrapolate the information. Now I am unable to compile, with a seemingly
> unconnected error.
Hi Xuhao,
I'm not exactly sure how it would work, but in principle you'd need to have the
dynamic loader (e.g. ld.so) and the libraries available somewhere for the
target you're using. I believe that ld.so is a elf binary and when passed the
appropriate command line arguments it loads the elf
Hi Serdar,
Could you fire up gdb and see what mode it thinks it's in? If you could trace
back to where it was set that would be helpful. I've never seen anything like
this before. Do you have any changes in your gem5 repository?
Thanks,
Ali
On May 15, 2013, at 7:03 AM, Serdar Zafer Can wro
On May 8, 2013, at 8:58 PM, YuLicheng wrote:
> Hello,
>
> I have read that gem5 is well supported on Mac OS X (from
> http://gem5.org/Dependencies).
> But I can't find any guide for OS X, documents are obviously Linux oriented.
> I have successfully compiled gem5.debug, but can't figure out ho
On May 8, 2013, at 7:09 AM, R.J. Douma wrote:
> Howdy!
>
> In short:
> I want to know where my program is during execution.
>
> The slightly longer question:
> I am looking at the memory access pattern of my program. Now I want to
> know which accesses belong to a certain set of lines in my pr
On May 7, 2013, at 5:10 PM, Chao Chen wrote:
> Hi,
>
> I am using the up-to-date gem5 version (repo.gem5.org/gem5). and run
> the ALPHA arch with FS mode.
> The system have many stalls due to lack of free ROB, IQ or LSQ,
> although the simulation still procedes slowly.
> I increase the ROB and
Something in your system is trying to read a contextId() on the
packet but that packet doesn't have a contextId(). This is likely
because something in your system is trying to read the contextId() of a
request that originated at an I/O device.
Ali
On 30.05.2013 00:11,
donguk Kim wrote:
> N
I've seen this bug pop up before, but it's been hard to track down. Some how a
load ends up getting executed that is uncachable and not at the head of the
ROB. Exactly what conditions lead to this isn't clear from the code and I
haven't found the behavior to be particularly repeatable to be able
You might check when you add the include paths, we make multiple copies of the
environment for different things and perhaps you're adding it too late. Also,
are you sure you're not supposed to be including libxml2/parser.h?
Ali
On May 28, 2013, at 12:33 PM, Yanqi Zhou wrote:
> Dear everyone,
Hi Maciej,
gem5 just provides enough of PCI config space so Linux can detect, enumerate,
and configure the device models.
Ali
On May 27, 2013, at 1:21 PM, Maciej Besta wrote:
> Hello everyone,
>
> I can see that gem5 somehow supports also PCI devices. However, in the source
> code there is
On May 29, 2013, at 3:29 AM, Albert wrote:
> Hello,
>
> I'm trying to modify a cache on the memory system hierarchy to be able to not
> to store certain requests, and therefore, act as a bypass cache for those
> packets.
>
> I added an extra condition to every " if (system->bypassCaches()) "
It's not partitioned.
Ali
On May 27, 2013, at 2:28 AM, Ulkesh Deshmukh wrote:
> Mahmood Naderan gmail.com> writes:
>
>>
>> Yes
>> Currenty I only set num_cpus to number of cores. I hope that this mean
>> a shared L2 among all cores with one bank. So if the size is set to
>> 2MB, then each co
Could you provide us with a gdb back trace of when this occurs?
What version of gem5 are you using? Are you using a 32 bit or 64 bit host?
There was a rather recent fix to (9533:dbf5a2fd479e) that fixed some issues
when running on 32 bit platforms and having disk images > 4GB in size.
Thanks,
Normally you see a bad_alloc when a program tries to allocate memory
and it can't (because there isn't enough in the system). Could you run
the simulator in the debugger and see where it's actually coming from?
Ali
On 04.06.2013 08:06, Maxime Chéramy wrote:
> Hi,
>
> I've
just updated my
It's likely that your axf and the memory map you've selected
(implicitly since you haven't configured a machine type) don't agree.
Ali
On 04.06.2013 06:22, Diviya Jain wrote:
> When I try to use
the command line you mentioned to run a sample binary on a bare-metal
machine, I get:
>
> com
Hi Guru,
You can use the static method SimObject::find() and pass the name of the ISA
object, you can also probably get there from a system pointer by going through
the ThreadContext.
As far as registering a stat, since the ISA object has become a simobject, if
you override the regStats method
elieve rules out method 1 and 3..(I don't know the 'name' of the
> instance of the ISA object..for the moment I tried everything from ArmISA,
> TheISA, isa, ISA..but since it doesn't extend SimObject, this was probably
> futile)
>
> I will try to get there usi
It looks like you don't have libssl installed.
Ali
On Jun 10, 2013, at 7:48 AM, Erfan Azarkhish wrote:
> Dear All,
>
> I have been using gem5 on Ubuntu 11.10 without any problems. However,
> recently I reinstalled my Ubuntu (the same version) and now when I try to
> compile gem5 I get the
Hi Diviya,
Are you sure the shared object is available in that directory? Have you set
LIBRARY_PATH?
Thanks,
Ali
On Jun 10, 2013, at 6:16 AM, Jain Diviya-B12553 wrote:
> Hi,
>
> I am trying to build gem5 shared library using following command:
> scons build/ARM/libgem5_debug.so
>
> I h
The operations you mention are floating point loads and stores.
Ali
On Jun 9, 2013, at 10:50 AM, Yuanbo Fan wrote:
> Hi everyone,
>
> I tried to run some floating point benchmarks on gem5 in atomic cpu mode, but
> the instruction traces I got from the ARM FS simulation are mostly integer
> i
:
> Hi Ali,
>
> I can replay this panic now. So what kind of information do you need
> in order to debug it.
>
> Thanks.
>
> Best regards,
> Yongbing Huang
>
> From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On
> Beha
Actual data is stored in the caches.
Ali
On Jun 13, 2013, at 11:49 PM, biswabandan panda wrote:
>
> Hi,
> I have modified the access function in cache to service a miss as hit even
> when a particular block is not found. (This is just to collect some
> statistics). I initially had assumed
tried to print it in schedSendTiming. It shows 0 as value for all the
> packets when I print it using (int)*(pkt->data).
> Is the data that is fetched from cache being sent to cpu? If yes how do I
> track(print) it?
> Thank you once again for your time.
>
>
> On Fri, Ju
different from when there is a hit in the cache -- should it not
> depend on cache?
>
>
>
> On Sat, Jun 15, 2013 at 9:33 PM, Ali Saidi wrote:
> Are you looking at a request or a response. The request very well could not
> have any data associated with it, but the response
the CPU, should it
> not be independent of cache? Is the CPU making use of the data that is sent
> from Cache in case of store request? Thank you once again for your time.
>
>
>
> On Mon, Jun 17, 2013 at 1:30 AM, Ali Saidi wrote:
> Remember that the cache much coherently update
eg 12 to physical reg 11 old
mapping was 10
>
> 2378200522460: system.cpu1.rename: [tid:0]:
Renaming arch reg 12 to physical reg 11.
>
> 2378200522460:
system.cpu1.rename: [tid:0]: Adding instruction to history buffer
(size=35), [sn:49750716].
>
> Hope that above information ar
I don't know hat many people have run SMT on non-Alpha system. What
errors are you seeing?
Ali
On 18.06.2013 08:37, Anway Mukherjee
wrote:
> Hello,
>
> Is there a patch to run multiple
workloads/Benchmarks on a single CPU in SE mode for X86/ARM processors.
I am trying to make the SMT wor
There aren't calls to do this, you'd need to hack on the simulator
to make it happen. For the turning on/off you'd probably need to create
a new event for the CPU that will wake it up after the period is over,
and for to get the llc misses you'd probably need to add a variable to
the llc and fig
You need to enable a trace using the --debug-fags= command line
option. The trace will be printed to stdout in this case. If you'd like
to write to a file instead use --trace-file= on the command line as well
(please see some of the documentation on the website). The trace files
will show up in
Unfortunately, mounting an image requires root access.
Ali
On Jun 25, 2013, at 4:49 AM, Mahmood Naderan wrote:
> Hi
> Maybe the question is not directly related to gem5, but the problem is
> users (not sudoers) can not execute mount command because of the
> permission set by the so they can not
That code ends up in src/arch/arm/isa/insts/mult.isa which ultimately calls
buildMultInst() and that function emits two versions of Mul one that sets the
condition codes and one that does not. The prior has Cc appended to the name.
Ali
On Jun 24, 2013, at 4:13 PM, Jianghao wrote:
> I have a q
You could create a VectorStatistic and output it that way. We don't do a good
job of calling all the destructors in the system when we exit.
Ali
On Jun 23, 2013, at 10:54 PM, "Ding, Hongyuan" wrote:
> Hi everyone,
> I defined an array under public section of BaseCache class. I changed
>
I don't know that anyone has really looked at SMT with the ARM ISA in gem5. A
good start to debugging the problem would be to run the simulator in gdb and
see where you're getting a segmentation fault.
Ali
On Jun 21, 2013, at 2:18 PM, Nithesh Kurella wrote:
> Hi all
>
> I have encountered th
Hi Uday,
You would have to create a new command type to do this. However I think the
flush requests as they are implemented are only supported in Ruby the classic
memory system doesn't support them at the moment.
Thanks,
Ali
On Jun 25, 2013, at 4:25 AM, "Ranga, L Udaya" wrote:
> Hi,
>
> I
The loops per jiffy is passed to the kernel (see FSConfig.py) so the kernel
doesn't try to compute it (as it takes a long time). It probably should be
based on a the CPU frequency gem5 is simulating, but it's just fixed at the
moment. As long as you have a homogenous system it shouldn't be a pro
and/or invalidate cache line in Classic Memory System?
>
> Thanks,
> Uday
> From: gem5-users-boun...@gem5.org [gem5-users-boun...@gem5.org] on behalf of
> Ali Saidi [sa...@umich.edu]
> Sent: Wednesday, June 26, 2013 9:22 AM
> To: gem5 users mailing list
> Subject: Re: [gem5-
format/mult.isa and src/arch/arm/isa/insts/mult.isa.
>
> So what's the link among those files under /format, /templates and /insts
> directories?
>
>
> On 6/25/2013 11:32 PM, Ali Saidi wrote:
>> That code ends up in src/arch/arm/isa/insts/mult.isa which ultimately calls
There are things other than the explicit source registers that need to be
accounted for (for example flag registers).
Ali
On Jun 30, 2013, at 3:08 PM, Xiangyang Guo wrote:
> Hi, Deal all,
>
> I use SE mode, ARM ISA and O3 cpu. I print out the num_src_regs, "unsigned
> num_src_regs = inst->n
ize to variable length. Thanks for attention.
>
> Regards
>
> Xiangyang
>
> On Mon, Jul 1, 2013 at 12:37 AM, Ali Saidi
wrote:
>
>> There are things other than the explicit
source registers that need to be accounted for (for example flag
registers).
>>
>>
the explicit
source registers", why it account for 3 times in one instruction? Thanks
very much.
>
> regards
>
> Xiangyang
>
> On Mon, Jul 1, 2013 at 12:37
AM, Ali Saidi wrote:
>
>> There are things other than
the explicit source registers that need to be a
Hrm... We'll see what we can do.
Ali
On 02.07.2013 17:46, Guru
Prasad wrote:
> Hi,
>
> I've noticed that the link to the kernel
sources provided on the Gem5
> Downloads page is broken.
>
> This repo
enabled users to build custom kernels that could succesfully
> simulate
more than 256MB R
The link has been fixed.
Ali
On Jul 2, 2013, at 5:46 PM, Guru Prasad wrote:
> Hi,
>
> I've noticed that the link to the kernel sources provided on the Gem5
> Downloads page is broken.
>
> This repo enabled users to build custom kernels that could succesfully
> simulate more than 256MB RAM.
>
Assuming the page table maps the address as cacheable it should just
happen. Do you mean the line needs to be locked in the cache?
Ali
On
10.07.2013 06:25, Ranga, L Udaya wrote:
> Hi all,
>
> I need to
ensure that a particular address is cached by ARM's L1/L2 cache.
>
>
Can anyone plea
On 11.07.2013 14:48, Fulya Kaplan wrote:
> Hi all,
> I am running
Parsec on X86 architecture. I would like to fastforward until ROI is
reached. How do I decide on the #of instructions to fastforward? Doesn't
it depend on the benchmark and other parameters?
> I have also read on
Parsec docume
Have you made any changes to the simulator? It seems like something
is going wrong with the coherence protocol. What version are you
running?
With the atomic CPU you should be able to trace the execution
with and without the L3 cache and see where they diverge using the
tracediff script in the
2013 9:34 AM
> TO:
sa...@umich.edu; gem5 users mailing list
> SUBJECT: Re: [gem5-users]
Cache an address in ARM System
>
> Ali,
>
> That's correct! I need
to edit my page table to map a particular address as cacheable and
locked.
>
> -Uday
>
> FROM: gem5-users-bo
On 10.07.2013 01:03, Zheng Wu wrote:
> Hi All,
>
> I am trying to
understand the source code. I want to know where in the code does the
CPUs execute instructions.
>
> I am currently looking at:
>
> -
src/cpu/base.hh
> - src/cpu/thread_context.hh
> - src/cpu/cpuevent.hh
>
> Q1: Shouldn't t
On 10.07.2013 06:24, Hui Zhao wrote:
> Hello I am running
multithreaded applications on Gem5. I want to stop the simulation when
the sum of all cores' executed instructions reaches some million. But
the current -I n will stop when any core reaches the n instructions. How
can I do this?
>
> Th
i Ali,
>
> Let's assume bare metal applications for this discussion. The
application will use a simple memory module (derived from SimpleMemory)
and ARM CPU will access it during the execution as data memory.
>
>
-Uday
>
> FROM: Ali Saidi [mailto:sa...@umich.edu]
> SENT:
No, switching CPUs doesn't change the debug flags. Creating a checkpoint and
restoring from it would. Are you sure the DPRINTFs you're seeing it atomic are
also called in timing mode?
Ali
On Jul 22, 2013, at 4:59 PM, George Michelogiannakis
wrote:
> Hello everyone,
>
>I'm using an old v
You should use the committedInsts statistic.
Ali
On Jul 19, 2013, at 4:27 PM, Fulya Kaplan wrote:
> Hi all,
> I am using the precompiled binaries for Parsec, so I decided to follow this
> procedure to switch to detailed mode at the beginning of ROI:
> 1)Do a simple run.
> 2) Parsec precompile
I don't believe write file is implemented for alpha, but you can add it. You'll
need to add the instruction to src/arch/alpha/isa/decoder.cc and
util/m5/m5op_alpha.S and recompile the m5 binary and put it on your disk image.
Ali
On Jul 19, 2013, at 5:20 AM, Konstantinos Parasyris wrote:
> Hel
On Jul 16, 2013, at 11:03 AM, Fulya Kaplan wrote:
> Hi all,
> I am running Parsec on X86 and trying to use dumpresetstats periodically.
> Since I am using the precompiled Parsec binaries, I use the m5op
> dumpresetstats for this purpose. I am using the command line:
>
> ../build/X86/gem5.opt
I th
On Jul 8, 2013, at 2:21 PM, Mona Jalal wrote:
> Hi,
> I am using hooks and have modified them in a way to just run the ROI in code
> for X86. But unfortunately m5_exit(0) in the end of ROI_end in hooks.c
> doesn't work though I have provided its assembly code and continues to run
> to the en
Hi Jack,
I don't think this is exactly correct. A number of C++ objects are wrapped with
SWIG so they're accessible as python objects. For every SimObject there is both
a Python class (that handles configuration) and a c++ class (that handles
simulation). I'm not aware of a case in the simulato
Hi Tayyar,
It should be possible to run a 3.7 kernel, but you'll need to create a suitable
dtb for gem5 and possibly play with the configuration option a bit.
Unfortunately, it just takes some time to get going. I'd start with the fewest
possible changes from a known working configuration and s
Hi,
Some architectures do support a other-endian mode (e.g. ARM
supports BE loads). I don't know that anything has been done to prevent
this from working, but similarly nothing has been done to enable it.
Assuming you can compile a program like hello world in this mode you
coun try it and see.
You've likely found a bug. SMT support in the O3 cpu isn't
frequently used, so it's very possible some bugs have crept in that
code.
Ali
On 24.07.2013 09:23, Jordan Dean wrote:
> I understand
what you mean, but my problem is a bit different. When I pass 2 programs
to a processor in SE mode
Just as previously posted, this is likely masking the issue, not
solving it. I don't see a reason why the application would be generating
an address that large. Either a instruction isn't being simulated
correctly or a syscall is incorrect. In short it's a bug in the
simulator and you're just ig
gem5 doesn't currently support this, but it should be rather easy to
add.
Ali
On 29.07.2013 06:48, Sophiane SENNI wrote:
> Hi
everybody,
>
> Does someone know how can I set write latency different
from read latency for both cache and main memory ?
>
> Thank you very
much.
>
> Sophian
The IEW statistics based on instruction class for the o3 CPU might
provide what you want. If you want to print OpClass information out in
the simple CPU it should be doable.
Ali
On 26.07.2013 17:36, Mahshid
Sedghi wrote:
> Hi,
>
> I need to find out the instruction mix for
some benchmark
ewExecutedInsts V.S. 1758659165 for committedInsts.
>>
>> So
what is the reason? It cannot be caused just because of branch
misprediction.
>>
>> Thanks.
>>
>> Best regards,
>>
>> Yongbing
Huang
>>
>> FROM: gem5-users-boun...@
The checkpoint has been created after the binary has been run. The
current processor and memory state of the benchmark loaded and executing
is saved in the checkpoint.
Ali
On 01.08.2013 12:20, Fulya Kaplan
wrote:
> Hi all,
> I have a very basic queston about restoring from a
checkpoint. I
gem5 opens up a number of ports when it starts for the terminal, debugging,
etc. However if a number of gem5 instances startup at the same time they can
conflict and you'll see the issue below.
If you add m5.disableAllListeners() to the python script your problem will go
away.
Ali
On Aug 4,
101 - 200 of 741 matches
Mail list logo
