On May 29, 2013, at 3:29 AM, Albert <[email protected]> wrote:
> Hello,
>
> I'm trying to modify a cache on the memory system hierarchy to be able to not
> to store certain requests, and therefore, act as a bypass cache for those
> packets.
>
> I added an extra condition to every " if (system->bypassCaches()) " condition
> on cache_impl.hh file to recognize those packets and don't store them.
> When running in functional mode it works out well, but when in timing mode it
> results on a panic message saying:
>
> panic: Packet ReadReq already has bus delay (1000, 500) that should be
> accounted for.
This is a check to make sure that the caches actually account for the time the
bus has said it will take to transfer the entire packet across it. You can
remove them for your situation.
>
> If I force those delays to 0 by doing:
> "pkt->busFirstWordDelay = pkt->busLastWordDelay = 0;"
> The method recvTimingResp doesn't find the a valid mshr and fails on the
> assertion.
I doubt this is caused by the fix above. I think you're just experiencing
another bug with your changes.
Ali
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