On 10.07.2013 01:03, Zheng Wu wrote:
> Hi All, > > I am trying to understand the source code. I want to know where in the code does the CPUs execute instructions. > > I am currently looking at: > > - src/cpu/base.hh > - src/cpu/thread_context.hh > - src/cpu/cpuevent.hh > > Q1: Shouldn't there be some kind of queue for instructions or some program counter somewhere? > Q2: where is the code that reads the program binary and pass the instruction to the cpu? > > Any comments are much appreciated!! > > Best Regards, > Zheng Wu > _______________________________________________ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users [1] The program counter is dependent on the CPU model, but if you grep for PCState you'll find it. The simple model don't really have an instruction queue, but the o3 one does (see src/cpu/o3/*) for queues of instructions starting in fetch and progressing through to the rest of the processor. Ali Links: ------ [1] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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