Hi Amin, Maybe, but the way it's written also makes some sense in that accesses is accesses that were from a cpu request, as opposed to a write back which is cache generated.
Ali On Apr 21, 2013, at 7:04 PM, Amin Farmahini <amin...@gmail.com> wrote: > I have a question about the stats generated in classic memory model. I > realized that overall_access is always the sum of ReadReq_accesses and > ReadExReq_accesses. > > system.l2.ReadReq_accesses::total 3816827 > system.l2.Writeback_accesses::total 5433149 > system.l2.UpgradeReq_accesses::total 656 > system.l2.ReadExReq_accesses::total 4813881 > system.l2.overall_accesses::total 8630708 > > As far as I know ReadReq reads the cache line and data is sent back via > ReadResp. > ReadExReq reads the cache line, invalidates it, and data is sent back via > ReadExResp. > Writeback writes a cache line when a dirty line is evicted from a higher > level cache (e.g. L1). > So I think overall_accesses should be the sum of ReadReq_accesses, > ReadExReq_accesses, and Writeback_accesses. Any thoughts? > > My architecture: two cores with private L1s and a shared L2; ARM; SE; classic > memory > > Thanks, > Amin > > _______________________________________________ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users _______________________________________________ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
