My experience was that:
DebugFlag("Tube")
Did not generate a file debug/Tube.hh
Whereas
DebugFlag("tube")
DID generate a file debug/tube.hh.
I am assuming that this is because the name of the corresponding file in the
src tree was tube.hh not Tube.hh.
This is an assumption but I can't think of
Never mind. I figured it out. I moved the newly compiled console binary to the
binary folder of the full_system_image_files. Now it works!
From: Iordan Alexandru
To: gem5 users mailing list
Sent: Wednesday, October 3, 2012 10:41 AM
Subject: Re: [gem5-users] H
Hi, I want to sharing one L1 cache with two cpu o3. It is necessary
that each cpu have permission to access L1 in the way alternating at
positive and negative time of clock. Is it necessary the Ruby for make
it? Any idea for me? I am working alone and it is very dificult to
start. Thank you.
--
E
On Thu, 4 Oct 2012, Robert PINSKER wrote:
My experience was that:
DebugFlag("Tube")
Did not generate a file debug/Tube.hh
Whereas
DebugFlag("tube")
DID generate a file debug/tube.hh.
I am assuming that this is because the name of the corresponding file in the
src tree was tube.hh not Tube.h
On Tue, 2 Oct 2012, tejasi pimpalkhute wrote:
Hi Tushar,
Thanks for looking into the code, I tried running the Network_test protocol
and got this error:
Global frequency set at 10 ticks per second
info: Entering event queue @ 0. Starting simulation...
gem5.debug:
build/ALPHA_SE_Networ
On Mon, 1 Oct 2012, Veydan Wu wrote:
Hi, all,
I wonder if anyone encountered this before. I ran a SPEC2006 application
(GemsFDTD), there are two instructions 1: stq r24, 16(r30) followed by 2:
ldt f0, 16(r30), very close.
In the unmodified OOO execution, 1 forwards the value (0x17) to 2
correc
On Sun, 30 Sep 2012, Mann Mann wrote:
Hi All
I am working on GEM5 for my project.
objective is to explore various Cache Architectures on multiprocessor
systems.
My aim to add a Cache layer on MESI protocol, I have gone through GEM5
source number of times,
but couldnt identify where to start. I
Hi Nilay,
Maybe I didn't make it clear. What I want is to run Multi-programmed
simulation rather than multi-threaded simulation. In other words, I want
4 cores to run 4 benchmarks (though they are all same) and each core has
only 1 thread. As a result, I set "np = 4 and numThreads = 1" in my
There are specific comments inline. Overall, I think you need to have a
better understanding of the options that you are trying to work with.
On Thu, 4 Oct 2012, Tao Zhang wrote:
Hi Nilay,
Maybe I didn't make it clear. What I want is to run Multi-programmed
simulation rather than multi-threa
On 04.10.2012 11:43, Nilay Vaish wrote:
> There are specific
comments inline. Overall, I think you need to have a
> better
understanding of the options that you are trying to work with.
>
> On
Thu, 4 Oct 2012, Tao Zhang wrote:
>
>> Hi Nilay, Maybe I didn't make it
clear. What I want is to r
Thank you very much , Ali. I will try to figure it out.
On 10/04/2012 12:48 PM, Ali Saidi wrote:
On 04.10.2012 11:43, Nilay Vaish wrote:
There are specific comments inline. Overall, I think you need to have a
better understanding of the options that you are trying to work with.
On Thu, 4 Oct
Hi Nilay,
Thanks for throwing light on this. I want to arbitrate request packets
originated the core (requiring off-chip memory access) at the router. Do
you think this is possible in Gem5?
My understanding was that both the memory request flits as well as network
flits are routed via interconnec
Hi all,
I never got any responses on this, so instead I'll ask: is there a better forum
or resource to find information and opinions on these questions? Seems like
this mailing list is not the place.
Thanks,
Rich
From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On
Behalf
Rich,
Sorry for the delay in responding. Ali and I were comparing notes to come
up with a unified response.
We appreciate your interest in gem5. We're very curious about what you are
looking for in a simulation tool, and what features or capabilities you see
are missing from other tools. Even
On Thu, 4 Oct 2012, tejasi pimpalkhute wrote:
Hi Nilay,
Thanks for throwing light on this. I want to arbitrate request packets
originated the core (requiring off-chip memory access) at the router. Do
you think this is possible in Gem5?
My understanding was that both the memory request flits as
The problem was at my end, after trying different versions of
build-dependencies, swig was the problem. Swig versions 2.0.7 and 2.0.8
both break garnet; I am now using 2.0.4, which works. I would recommend
to anyone else having this issue to use an older version of swig.
-- Marco
On 28/09/12 23:1
Thanks a ton for explaining this, I think I was mistaken earlier. In that
case, can I know beforehand the physical address of the request flits which
will be going to the directory controller? Can I calculate the rank and
bank address of that flit as done in the memory controller (if the router
has
On Thu, 4 Oct 2012, tejasi pimpalkhute wrote:
Thanks a ton for explaining this, I think I was mistaken earlier. In that
case, can I know beforehand the physical address of the request flits which
will be going to the directory controller? Can I calculate the rank and
When router forwards a fli
Hi,
I have some questions about the cache access in Ruby. As shown in file
src/mem/protocol/MESI_CMP_directory-L1.sm:
in_port(mandatoryQueue_in, RubyRequest, mandatoryQu
Finally, I fixed the problem. This is a gem5's bug when using both "-I"
and "-F" in a multi-core simulation under SE mode. Simply speaking, the
problem is caused by 'stale' exit events scheduled by Atomic CPUs, which
gem5 fails to delete before the cpu switching.
For example, if 4 cores are em
I have got some progress. It seems like the function "StaticInstPtr
decode(ArmISA::PCState &nextPC)" is the only decode function that
returns the right StaticInst. Things like setting the isMisc bit in the
ExtMachInst seems to be crucial before decoding.
But I'm stuck with the next problem. No
Dear All,
I'm new to gem5. Recently I tired to integrate McPAT on gem5. I found two
possible tools:
1. m5-mcpat-parse-se.py, http://cseweb.ucsd.edu/~rstrong/
2. m5-mcpat.pl, https://www.cl.cam.ac.uk/~acr31/sicsa/
I tried a simple example in gem5 to get the output files:
build/ARM/gem5.opt configs
Hi Tobias,
If memory serves, only direct control instructions have
branch targets because the target information is encoded in the
instruction. Indirect control targets don't because the instruction
itself is insufficient to provide a target; it requires reading a
register and branching to the
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