Hi,
I have some questions about the cache access in Ruby. As shown in file
src/mem/protocol/MESI_CMP_directory-L1.sm:
--------------------------------------------------------------------------------------------------------------------------------
in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...", rank =
0) {
... ...
// *** DATA ACCESS ***
Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
if (is_valid(L1Dcache_entry)) {
// The tag matches for the L1, so the L1 ask the L2 for it
*trigger(mandatory_request_type_to_event(in_msg.Type),
in_msg.LineAddress,*
* L1Dcache_entry, L1_TBEs[in_msg.LineAddress]);*
} else {
... ...
if (L1DcacheMemory.cacheAvail(in_msg.LineAddress)) {
// L1 does't have the line, but we have space for it in the
L1 let's see if the L2 has it
* trigger(mandatory_request_type_to_event(in_msg.Type),
in_msg.LineAddress,*
* L1Dcache_entry, L1_TBEs[in_msg.LineAddress]);*
}
... ...
}
}
---------------------------------------------------------------------------------------------------------------------------------------
1/ why the two triggered actions are the same? I've no idea when the
L1Dcache_entry is valid (which I think means there is the requested block
available in the L1D cache), why it still asks the L1 for it (as commented)
by triggering the same action as if the cache block is not in L1D? I think
it should be responded to the processor. Is it correct? If so, should the
action be "send data to requestor" or anything else? I am really confused
with the cache access part in Ruby, could you please give me any
instructions/explanations?
2/ the function is_valid(xxx) is called many times in the *.sm files. But
I've no idea where it is defined?
Thanks,
Yingying
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