On Thu, 4 Oct 2012, tejasi pimpalkhute wrote:
Hi Nilay,
Thanks for throwing light on this. I want to arbitrate request packets
originated the core (requiring off-chip memory access) at the router. Do
you think this is possible in Gem5?
My understanding was that both the memory request flits as well as network
flits are routed via interconnection networks. So, I modified the
SWallocator_d code. But now I am confused, if the memory request flits
don't travel through the GARNET network towards the main memory, what path
do the take to access main memory? I would really appreciate if you could
elaborate more on this. Thanks!
In a typical case a core would generate load/store requests for the
caches. The cache controllers and the directory controllers are connected
using a network. So, if a controller is unable to handle some request, it
forwards it to the next level controller. The forwarded message goes
through the on-chip network. If a request reaches the directory
controller, it forwards it to the memory controller. A Memory Msg (in
gem5's terminology) is message from a directory controller to a memory
controller or vice-versa. These message travel on dedicated links between
directory controllers and memory controllers. These links are not part of
Garnet.
--
Nilay
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