Hello all,
I have a question about the stats when I run multi-core simulation with gem5.
For example, if I run a 4-thread script in a 4 ARM OoO core environment, after
simulation, I found only 3 cores have stats in the stats file, which I guess
that only 3 cores got used. Does anyone know why?
Hi all,
I'm currently doing some research in Ruby, therefore I've been trying to modify
some .sm file such as 'src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm'. I
was wondering how come this C++-like language cannot recognize simplest syntax
such as a simple semicolon.
Also, if I want to
Hi everyone,
I was running the following command in gem5 the other day:
..gem5.opt configs/example/fs.py --ruby --cpu-type=O3_ARM_N1
--script=tests/test-progs/hello/bin/arm/linux/hello
--kernel=/home/hippo/full_system_images/binaries/vmlinux.vexpress_gem5_v1.20170616
and I noticed this appe
Hello all,
I am trying to run multiple O3 CPUs in FS mode. But right now I can only run
one O3 CPU successfully. I wonder if gem5 X86 architecture supports multiple O3
CPUs in FS mode. If yes, what configurations are you using?
Thanks in advance for any help.
-Jimmy
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--
Message: 6
Date: Wed, 9 Jul 2014 13:13:52 +
From: Besta Maciej via gem5-users
To: "gem5-users@gem5.org"
Subject: [gem5-users] A question about DMA/zero-copy
Hello everyone,
I need to measure the latency/bandwidth of data exchange between two ARM
machines
connected with an Ethernet link in a gem5 full system simulation.
I cannot simply use Ping/Netperf, because this data exchange has to be done
using
DMA/zero-copy/OS bypass.
Implementing this is no
@sina.com>"
mailto:ko115.stud...@sina.com>>, gem5 users mailing
list mailto:gem5-users@gem5.org>>
Date: Friday, 28 March 2014 05:42
To: gem5-users mailto:gem5-users@gem5.org>>
Subject: [gem5-users] A Question on recvFunctional() and recvTiming() in DRAM
class
Hello! I&
Hello! I'am studying the file src/mem/simple_dram.cc and confused by the
functional and timing access.
It seems that the functional access recvFunctional() is called first during
which a memcpy() accesses data in DRAM; then the timing one recvTiming() is
called to calculate latency.
While each t
Hi, Fernando
Thanks for your advice.
We will try.
Regards,
Zhiguo
From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On
Behalf Of Fernando Endo
Sent: Thursday, March 13, 2014 2:43 AM
To: gem5 users mailing list
Subject: Re: [gem5-users] A question about InOrderCPU model in
Hello,
To simulate a correct execution time, although it's an cycle approximate
in-order simulator, you should do this in the O3 model:
- Patch the O3:
- to issue only the oldest instruction in the IQ, except re-issuing
instructions
- to implement and extra register scoreboard to track regist
ROB not keeping pipeline depth 1 is to resemble more closely intel inorder
atom core. They have dispatch width 2 and issue2 and issue queue entries of
16
This is OOO core. If ROB is not pipeline depth then you can plug in the
above parameters . You can do ROB=1 with issue queue entries to be 1 bu
Hi, Sudarshan
Thanks for your reply.
My concern is the load store queue in O3CPU may cause performance error as
loads and stores are executed out of order which is not the case in InOrder
CPU.
You said that "ROB entries can be made to pipeline depth than keeping it
1". May I know why ROB entry sh
Yes u can do that..ROB entries can be made to pipeline depth than keeping
it 1.if Rob is made to 1 then u can't keep issue width of 2 since Intel
atom inorder processor have fetch and issue width 2.. Intel atom does not
have a load store queue...but load store queue entries could be made to
have sa
Hi, All
In GEM5, there is a separate InOrderCPU model which is not as well as supported
as O3CPU.
My question is why not modify the dispatch/issue part of O3CPU to emulate an
InOrderCPU?
Are there any issues to affect the accuracy of InOrderCPU model by making the
O3CPU issuing the instructions
Hi.
I solved the problem I mentioned below.
To completely install an apk file on a gem5 disk image, it seems like
simply copying the apk file to the "/system/app" path is not enough for
some cases.
I reinstalled an apk using " adb install -r app_name.apk ", and I was able
to successfully launch
Hi, everyone.
I am trying to run Android applications using gem5, however, I am having
some difficulties.
I am new to Android and I am not familiar with Java, so I wish some one can
shed me some light.
I am using 2.6.35 Android kernel and the ICS disk image with BBench
provided by the gem5 websit
Meng Wang tupleapes.com> writes:
>
> Thanks Mitch! Your script does a great favor for me. I think It's very
helpful to anyone who wants to reduce the simulation runtime or make the
interval analysis more efficiently. Thanks again.
> Meng
> On Apr 5, 2013, at 6:54 PM, Mitch Hayenga
gmail.com>
On 20/06/2013 18:47, Fangfei Liu wrote:
I'm sorry to bother you. I'm a gem5 user. I saw your question about
adding a NIC to x86. I was wondering whether you have got any luck to
get this work?
I've not got the interrupt sorted yet.
I added an Ethernet device IGbE_igb to the x86 system and
con
Thanks Mitch! Your script does a great favor for me. I think It's very helpful
to anyone who wants to reduce the simulation runtime or make the interval
analysis more efficiently. Thanks again.
Meng
On Apr 5, 2013, at 6:54 PM, Mitch Hayenga wrote:
> Hi Meng,
>
> I'm CC'ing the mailing list in
Hi Meng,
I'm CC'ing the mailing list in case anyone else has interest in running
with the simpoint patch.
This part of the patch was coded by Ali I think. I originally wrote the
profiling bit that generated the bbv file. I use this current patch with
with my own custom se.py script. I've linked
On Thu, January 24, 2013 11:18 pm, Lu Hang wrote:
> I see. I miss-config the vmlinux binary path. The kernal can now booted
> up. However, there is also another issue coming up. There are two warn
> messages while simulating and it exits really fast. I'm not sure if the
> benchmark has finished run
:04
Subject: Re: [gem5-users] A question to gem5 mounting disk image
On Thu, January 24, 2013 8:34 pm, Lu Hang wrote:
> The figure cannot be displayed. Below is the error message.
>
> [luhang113@attl113 gem5]$ gem5.opt configs/example/fs.py
> --script=configs/boot/blackscholes.rcS
> gem5
On Thu, January 24, 2013 8:34 pm, Lu Hang wrote:
> The figure cannot be displayed. Below is the error message.
>
> [luhang113@attl113 gem5]$ gem5.opt configs/example/fs.py
> --script=configs/boot/blackscholes.rcS
> gem5 Simulator System. http://gem5.org
> gem5 is copyrighted software; use the --co
of Computer System and Architecture
Institute of Computing Technology,Chinese Academy of Sciences
Beijing 100190, China
- Original Message -
From: Nilay
To: gem5 users mailing list
Date: 2013-01-25, 03:56:05
Subject: Re: [gem5-users] A question to gem5 mounting disk image
On Wed, January
On Wed, January 23, 2013 11:46 pm, Lu Hang wrote:
> Hi everyone,
> I'm a new user of gem5, and I've got a problem when booting the linux
> image specified as follows.
> I have mounted the 'linux-parsec-2-1-m5-with-test-inputs.img' file
> (provided by the URL at gem5 documentation page) at $GEM5/mnt
Ali,
Although I roughly understand how a Python object and C++ object are glued
together after one day code-reading (in particular BaseCache object), my
understanding is certainly not as deep as the original developers. Let me
spend more time reading the source code, and I will do that once I feel
Hi Chen,
Please take a moment and write up a page on the wiki about what you found. I've
seen the question before and I don't think we have any good documentation on it.
Thanks,
Ali
On Jan 17, 2013, at 6:22 PM, Chen Tian wrote:
> I am able to answer the question by myself. Thanks for any atte
I am able to answer the question by myself. Thanks for any attention.
chen
On Wed, Jan 16, 2013 at 5:00 PM, Chen Tian wrote:
> Hi,
>
> I am reading the source code of GEM5. I am curious about how a python
> object gets translated to a C++ object. In particular, how does the
> statement "self._c
Hi,
I am reading the source code of GEM5. I am curious about how a python
object gets translated to a C++ object. In particular, how does the
statement "self._ccObject = params.create()" in SimObject.py eventually
call the C++ constructor? Using cache object as an example,
I can see the value of p
On Sat, 1 Dec 2012, leonardo wrote:
Hello everyone
Is there any chance that I could use Ruby without any cache coherence protocols?
What should i do?
Thanks.
Does not seem possible to me. You can use the classic memory system, if it
serves your purpose.
--
Nilay
___
Hi:
I have a question about the cache in gem5. In the file of cache_impl.hh,
there are three different kinds of accesses: atomic, timing and functional.
So what is functional access mean here?
When I look at the packet from functional access, it seems that these
packets doesn't have a valid threa
Hi:
I have a question about the cache in gem5. In the file of cache_impl
--
Tianwei Zhang
Department of Electrical Engineering
Princeton University
NJ, USA
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In the file MOESI_hammer-cache.sm, should the following transition be changed?
transition(MM, Other_GETS, I) {
c_sendExclusiveData;
l_popForwardQueue;
}
The above transition should be changed to:
transition(MM, Other_GETS, O) {
ee_sendDataShared;
l_popForwardQueue;
}
T
In the file MOESI_hammer-cache.sm, should the following transition be changed?
transition(MM, Other_GETS, I) {
c_sendExclusiveData;
l_popForwardQueue;
}
The above transition should be changed to:
transition(MM, Other_GETS, O) {
ee_sendDataShared;
l_popForwardQueue;
}
Th
In the file MOESI_hammer-cache.sm, should the following transition be changed
to a more suitable transition?
transition(MM, Other_GETS, I) {
c_sendExclusiveData;
l_popForwardQueue;
}
The above transition should be:
transition(MM, Other_GETS, O) {
ee_sendDataShared;
l_popFo
On Tue, 3 Jan 2012, Hamid Reza Khaleghzadeh wrote:
Could you tell what architecture this command simulates?
./build/ALPHA_FS/m5.opt configs/example/ruby_fs.py -n 16 --l1i_size=32kB
--l1d_size=32kB --l2_size=32MB --num-l2caches=4 --topology=Crossbar --timing
I think this command simulate a mul
Could you tell what architecture this command simulates?
./build/ALPHA_FS/m5.opt configs/example/ruby_fs.py -n 16 --l1i_size=32kB
--l1d_size=32kB --l2_size=32MB --num-l2caches=4 --topology=Crossbar --timing
I think this command simulate a multi-core processor that consists of 4
package. Each pac
see "num_cpus" in command line options
On 1/3/12, Hamid Reza Khaleghzadeh wrote:
> In Gems simulator, there is g_PROCS_PER_CHIP parameter that sets number of
> cpu per chip. Is there any similar parameter in Gem5?
>
> Thanks
>
--
--
// Naderan *Mahmood;
In Gems simulator, there is g_PROCS_PER_CHIP parameter that sets number of
cpu per chip. Is there any similar parameter in Gem5?
Thanks
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In Gems simulator, there is g_PROCS_PER_CHIP parameter that sets number of
cpu per chip. Is there any similar parameter in Gem5
Thanks
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yes.
in O3CPU (-d option) the ipc is a stat name. In other cpu models, you
can see the total execution cycles and instructions.
On 12/30/11, juhua wrote:
> I want to know after running a testbench on for example the SE gem5 program
> ,can I get the cpi or some number about the execution time.
>
>
I want to know after running a testbench on for example the SE gem5 program
,can I get the cpi or some number about the execution time.
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