Yes u can do that..ROB entries can be made to pipeline depth than keeping it 1.if Rob is made to 1 then u can't keep issue width of 2 since Intel atom inorder processor have fetch and issue width 2.. Intel atom does not have a load store queue...but load store queue entries could be made to have same as Rob..increasing entries in lsq will not have any effect in performance unless entries in Rob have increased.. On Mar 10, 2014 5:18 AM, "GE ZHIGUO" <ge.zhi...@huawei.com> wrote:
> Hi, All > > In GEM5, there is a separate InOrderCPU model which is not as well as > supported as O3CPU. > > My question is why not modify the dispatch/issue part of O3CPU to emulate > an InOrderCPU? > > Are there any issues to affect the accuracy of InOrderCPU model by making > the O3CPU issuing the instructions in-order? > > > > Thanks! > > > > Zhiguo > > > > _______________________________________________ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
_______________________________________________ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
