Hi, Sudarshan Thanks for your reply. My concern is the load store queue in O3CPU may cause performance error as loads and stores are executed out of order which is not the case in InOrder CPU.
You said that "ROB entries can be made to pipeline depth than keeping it 1". May I know why ROB entry should be set to pipeline depth? Regards, Zhiguo On Mon, Mar 10, 2014 at 8:06 PM, Sudarshan <sud...@gmail.com> wrote: > Yes u can do that..ROB entries can be made to pipeline depth than keeping > it 1.if Rob is made to 1 then u can't keep issue width of 2 since Intel > atom inorder processor have fetch and issue width 2.. Intel atom does not > have a load store queue...but load store queue entries could be made to > have same as Rob..increasing entries in lsq will not have any effect in > performance unless entries in Rob have increased.. > On Mar 10, 2014 5:18 AM, "GE ZHIGUO" <ge.zhi...@huawei.com> wrote: > >> Hi, All >> >> In GEM5, there is a separate InOrderCPU model which is not as well as >> supported as O3CPU. >> >> My question is why not modify the dispatch/issue part of O3CPU to emulate >> an InOrderCPU? >> >> Are there any issues to affect the accuracy of InOrderCPU model by making >> the O3CPU issuing the instructions in-order? >> >> >> >> Thanks! >> >> >> >> Zhiguo >> >> >> >> _______________________________________________ >> gem5-users mailing list >> gem5-users@gem5.org >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >> > > _______________________________________________ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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