All passed, include overloaded and non-overloaded.
# of expected passes10885
Pan
From: Li, Pan2
Sent: Tuesday, February 6, 2024 4:17 PM
To: juzhe.zh...@rivai.ai; gcc-patches
Cc: Wang, Yanzhang ; kito.cheng
Subject: RE: [PATCH v1] RISC-V: Bugfix for RVV overloaded intrinisc ICE
2
for avoiding overflow.
Pan
From: juzhe.zh...@rivai.ai
Sent: Wednesday, February 7, 2024 6:21 PM
To: Li, Pan2 ; gcc-patches
Cc: Li, Pan2 ; Wang, Yanzhang ;
kito.cheng
Subject: Re: [PATCH v1] RISC-V: Bugfix for RVV overloaded intrinsic ICE in
function checker
Why is it 2 not 1 or other
Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Thursday, February 8, 2024 2:43 PM
To: Li, Pan2 ; gcc-patches
Cc: Wang, Yanzhang ; kito.cheng
Subject: Re: RE: [PATCH v1] RISC-V: Bugfix for RVV overloaded intrinsic ICE in
function checker
LGTM
CC Robin and Jeff.
Pan
-Original Message-
From: Li, Pan2
Sent: Saturday, February 10, 2024 7:04 PM
To: gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; Li, Pan2 ; Wang, Yanzhang
; kito.ch...@gmail.com
Subject: [PATCH v1] RISC-V: Fix misspelled term args in error_at message
From: Pan
Committed, thanks Robin.
Pan
-Original Message-
From: Robin Dapp
Sent: Monday, February 12, 2024 8:09 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: rdapp@gmail.com; juzhe.zh...@rivai.ai; kito.ch...@gmail.com; Robin Dapp
; Jeff Law
Subject: Re: [PATCH v1] RISC-V: Fix misspelled
Hi Edwin,
Sorry for late reply due to holiday. I double-checked the
calling-convernsion-*.c dump, it is safe to adjust the asm check to the number
as you mentioned.
Pan
-Original Message-
From: Edwin Lu
Sent: Tuesday, February 6, 2024 2:42 AM
To: Li, Pan2 ; juzhe.zh...@rivai.ai; gcc
For calling-convention-*.c, LGTM but one nit about change log. Take **Update**
here may make others not easy to learn what you did about the file.
You can say similar to "Rearrange and adjust the asm-checker times" or
likewise. Of course, you can refine the changelog when commit.
> * gcc.target/
ey
share the same mode as vector integer. For example, RVVM1SI in
vector-iterators.md. Kito
and Juzhe can help to correct me if any misunderstandings.
Pan
-Original Message-
From: Richard Biener
Sent: Monday, February 19, 2024 3:36 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...
Thanks Andrew, I will go thru for more details.
Pan
-Original Message-
From: Andrew Pinski
Sent: Monday, February 19, 2024 4:31 PM
To: Richard Biener
Cc: Li, Pan2 ; gcc-patches@gcc.gnu.org;
juzhe.zh...@rivai.ai; Wang, Yanzhang ;
kito.ch...@gmail.com; tamar.christ...@arm.com
Subject
fter try DEF_INTERNAL_SIGNED_OPTAB_FN, will keep
you posted.
Pan
-Original Message-
From: Tamar Christina
Sent: Monday, February 19, 2024 4:55 PM
To: Li, Pan2 ; Richard Biener
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang
; kito.ch...@gmail.com
Subject: RE: [PATCH v1]
-
From: Li, Pan2
Sent: Wednesday, February 21, 2024 12:27 PM
To: gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; Li, Pan2 ; Wang, Yanzhang
; kito.ch...@gmail.com
Subject: [PATCH v1] RISC-V: Upgrade RVV intrinsic version to 0.12
From: Pan Li
Upgrade the version of RVV intrinsic from 0.11 to 0.12
Committed, thanks Kito.
Pan
From: Kito Cheng
Sent: Thursday, February 22, 2024 7:35 AM
To: Li, Pan2
Cc: GCC Patches ; 钟居哲 ; Wang,
Yanzhang
Subject: Re: [PATCH v1] RISC-V: Upgrade RVV intrinsic version to 0.12
LGTM for the patch
Li, Pan2 mailto:pan2...@intel.com>> 於 2024年2月21日 週三 12
> But I'd like to CC more RISC-V GCC folks to see the votes.
> If most of the people don't want this in GCC-14 and defer it to GCC-15, I
> won't insist on it.
Sure, let’s wait for a while.
Pan
From: juzhe.zh...@rivai.ai
Sent: Friday, February 23, 2024 4:38 PM
To:
Hi Edwin,
Looks like 6ec84c45a19403d3435b2affe4ec60e518fc1f97 result in sorts of rvv.exp
asm check failure (I list some but not all of them in below) in upstream.
Could you please help to double check about it? Ping me if any more information
is needed. Thanks.
= Summary
: Tamar Christina
Sent: Monday, February 19, 2024 9:05 PM
To: Li, Pan2 ; Richard Biener
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang
; kito.ch...@gmail.com
Subject: RE: [PATCH v1] Internal-fn: Add new internal function SAT_ADDU
> -Original Message-
> From: Li
day, February 26, 2024 11:41 AM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
richard.guent...@gmail.com; Wang, Yanzhang ;
rdapp@gmail.com
Subject: Re: [PATCH v1] RTL: Bugfix ICE after allow vector type in DSE
On Mon, Feb 26, 2024 at 11:26 AM wr
Got it, we need to combine that together up to point.
Thanks Tamar for the explanation. Help a lot and will have a try in v3.
Pan
-Original Message-
From: Tamar Christina
Sent: Sunday, February 25, 2024 5:02 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; Wang
> validate_subreg is a can of worms, can you try to fix the issue in DSE
> by avoiding to form the subreg in the first place?
Sure thing, will have a try in v2.
Pan
-Original Message-
From: Richard Biener
Sent: Monday, February 26, 2024 3:38 PM
To: Li, Pan2
Cc: gcc-p
a
Sent: Tuesday, February 27, 2024 5:57 PM
To: Richard Biener
Cc: Li, Pan2 ; gcc-patches@gcc.gnu.org;
juzhe.zh...@rivai.ai; Wang, Yanzhang ;
kito.ch...@gmail.com; richard.sandiford@arm.com2; jeffreya...@gmail.com
Subject: RE: [PATCH v2] Draft|Internal-fn: Introduce internal fn saturation
US_PLUS
>
-Original Message-
From: Richard Biener
Sent: Tuesday, February 27, 2024 9:42 PM
To: Tamar Christina
Cc: Li, Pan2 ; gcc-patches@gcc.gnu.org;
juzhe.zh...@rivai.ai; Wang, Yanzhang ;
kito.ch...@gmail.com; richard.sandiford@arm.com2; jeffreya...@gmail.com
Subject: Re: [PATCH v2] Draft|Interna
> Pan, can you confirm what path we take through extract_low_bits?
Thanks Jeff for comments, will have a try soon and keep you posted.
Pan
-Original Message-
From: Jeff Law
Sent: Tuesday, February 27, 2024 11:03 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai
s are always untieable to its' int mode, and
then return NULL_RTX.
Pan
-Original Message-----
From: Li, Pan2
Sent: Wednesday, February 28, 2024 9:41 AM
To: Jeff Law ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; richard.guent...@gmail.com;
Wang, Yanzhang ; rdapp..
march=zvl* + mrvv-vector-bits=zvl means exactly the VLEN like 128 bits. I
will update it in
v3 accordingly for the difference semantics here.
Pan
-Original Message-
From: Kito Cheng
Sent: Wednesday, February 28, 2024 2:17 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh
Updated in v3, please help to continue review below link. Sorry for sending
another v3 by mistake.
https://gcc.gnu.org/pipermail/gcc-patches/2024-February/646734.html
Pan
-Original Message-
From: Li, Pan2
Sent: Wednesday, February 28, 2024 2:33 PM
To: Kito Cheng
Cc: gcc-patches
ght behavior here, when mrvv-vector-bits is
given while riscv-autovec-preference is none...
Pan
-Original Message-
From: Kito Cheng
Sent: Wednesday, February 28, 2024 8:57 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang
; rdapp@gmail.com; jeffreya.
To: 钟居哲
Cc: Li, Pan2 ; gcc-patches ; Wang,
Yanzhang ; rdapp.gcc ; Jeff Law
Subject: Re: Re: [PATCH v3] RISC-V: Introduce gcc option mrvv-vector-bits for
RVV
Hmm, maybe only keep --param=riscv-autovec-preference=none and remove other two
if we think that might still useful? But anyway I have
|| !(GET_MODE_CLASS (mode1) == MODE_FLOAT
&& GET_MODE_CLASS (mode2) == MODE_FLOAT));
}
Pan
-Original Message-
From: Jeff Law
Sent: Thursday, February 29, 2024 1:33 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; rich
: Wednesday, January 10, 2024 1:46 AM
To: Richard Biener ; Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang
; kito.ch...@gmail.com
Subject: Re: [PATCH v3] RISC-V: Bugfix for doesn't honor no-signed-zeros option
On 1/8/24 03:45, Richard Biener wrote:
> On Tue, Jan 2, 2
Committed, thanks Kito.
Pan
-Original Message-
From: Kito Cheng
Sent: Wednesday, January 10, 2024 3:12 PM
To: Juzhe-Zhong
Cc: gcc-patches@gcc.gnu.org; kito.ch...@sifive.com; jeffreya...@gmail.com;
rdapp@gmail.com
Subject: Re: [PATCH] RISC-V: Refine unsigned avg_floor/avg_ceil
LGT
Thanks Richard, will delete the test case pr30957-1.c in patch V5.
Pan
-Original Message-
From: Richard Biener
Sent: Thursday, January 11, 2024 4:33 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang
; kito.ch...@gmail.com; jeffreya...@gmail.com
Subject
Committed, thanks Richard.
Pan
-Original Message-
From: Richard Biener
Sent: Thursday, January 11, 2024 5:22 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang
; kito.ch...@gmail.com; jeffreya...@gmail.com
Subject: Re: [PATCH v5] LOOP-UNROLL: Leverage
Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Friday, January 12, 2024 10:54 AM
To: Li, Pan2 ; gcc-patches
Cc: Li, Pan2 ; Wang, Yanzhang ;
kito.cheng
Subject: Re: [PATCH v1] RISC-V: Update the comments of riscv_v_ext_mode_p [NFC]
OK
juzhe.zh
> Yes, I'm seeing the problem using glibc. Looking at our postcommit ci
> reports, it appears to only affect linux rv32gcv.
Just FYI. Double confirmed rv64gcv with glibc works well with this patch.
Pan
-Original Message-
From: Edwin Lu
Sent: Wednesday, January 17, 2024 9:45 AM
To: juz
Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Wednesday, January 17, 2024 5:02 PM
To: Li, Pan2 ; gcc-patches
Cc: Li, Pan2 ; Wang, Yanzhang ;
kito.cheng
Subject: Re: [PATCH v1] RISC-V: Fix asm checks regression due to recent
middle-end change
LGTM
Committed, thanks Juzhe.
Pan
From: juzhe.zhong
Sent: Thursday, January 25, 2024 9:08 PM
To: Wang, Yanzhang
Cc: gcc-patches@gcc.gnu.org; kito.ch...@sifive.com; Li, Pan2
; Wang, Yanzhang
Subject: Re: [PATCH v2] RISC-V: remove param riscv-vector-abi. [PR113538]
lgtm
Replied Message
Thanks Kito for comments, rebase the upstream and always goes to GPR in V2.
https://gcc.gnu.org/pipermail/gcc-patches/2024-January/644291.html
Pan
-Original Message-
From: Kito Cheng
Sent: Monday, January 29, 2024 9:23 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai
Thanks Kito, will add assertion here, and commit it if there is no surprise in
riscv regression test.
Pan
-Original Message-
From: Kito Cheng
Sent: Tuesday, January 30, 2024 8:54 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang
Subject: Re: [PATCH
Thanks Kito. Committed with assertion, as well as pass the riscv regression
test.
Pan
-Original Message-
From: Li, Pan2
Sent: Tuesday, January 30, 2024 9:11 PM
To: Kito Cheng
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang
Subject: RE: [PATCH v2] RISC-V: Bugfix for
Committed, thanks all.
Pan
From: juzhe.zh...@rivai.ai
Sent: Wednesday, December 13, 2023 7:16 PM
To: demin.han ; gcc-patches
Cc: Li, Pan2
Subject: Re: [PATCH v2] RISC-V: Fix dynamic lmul tests depended on abi
LGTM.
juzhe.zh...@rivai.ai<mailto:juzhe
Committed with below comments, thanks Juzhe and Robin.
Pan
-Original Message-
From: Robin Dapp
Sent: Wednesday, December 13, 2023 9:56 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: rdapp@gmail.com; juzhe.zh...@rivai.ai
Subject: Re: [PATCH v1] RISC-V: Refine test cases for both
Committed, thanks Kito.
Pan
From: Kito Cheng
Sent: Thursday, December 14, 2023 2:45 PM
To: Juzhe-Zhong
Cc: GCC Patches ; Kito Cheng ;
Jeff Law ; Robin Dapp
Subject: Re: [PATCH] RISC-V: Add RVV builtin vectorization cost model
LGTM
Juzhe-Zhong mailto:juzhe.zh...@rivai.ai>> 於 2023年12月14日
週四
Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Monday, December 18, 2023 3:37 PM
To: Li, Pan2 ; gcc-patches
Cc: Li, Pan2 ; Wang, Yanzhang ;
kito.cheng
Subject: Re: [PATCH v2] RISC-V: Bugfix for the RVV const vector
OK. LGTM. It's an obvious fix and not easy to add the
Oh, I see. Thanks Jeff for suggestion, will refine the commit log in V2.
Pan
-Original Message-
From: Jeff Law
Sent: Wednesday, December 20, 2023 12:03 PM
To: juzhe.zh...@rivai.ai; Li, Pan2 ; gcc-patches
Cc: Wang, Yanzhang ; kito.cheng
Subject: Re: [PATCH v1] RISC-V: Bugfix for the
Committed, thanks all.
Pan
From: juzhe.zh...@rivai.ai
Sent: Wednesday, December 20, 2023 7:18 PM
To: demin.han ; gcc-patches
Cc: Li, Pan2
Subject: Re: Re: [PATCH] RISC-V: Fix calculation of max live vregs
I see. LGTM. Thanks for explanation.
I will ask Li Pan commit it for you.
Thanks
Thanks all for comments, will have a try for riscv_v and send V2 if everything
goes well.
Pan
From: 钟居哲
Sent: Friday, December 22, 2023 6:44 AM
To: Jeff Law ; Li, Pan2 ; gcc-patches
Cc: Wang, Yanzhang ; kito.cheng
; richard.guenther ; Tamar
Christina
Subject: Re: Re: [PATCH v1] RISC-V
Committed, thanks Jeff.
Pan
-Original Message-
From: Jeff Law
Sent: Saturday, December 23, 2023 11:38 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; Wang, Yanzhang ;
kito.ch...@gmail.com; richard.guent...@gmail.com; tamar.christ...@arm.com
Subject: Re: [PATCH v2
n
> effective target test (check_effective_target_vect_variable_length perhaps?)
Sure, will have a try for this.
Pan
-Original Message-
From: Jeff Law
Sent: Sunday, December 24, 2023 1:20 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; Wang, Yanzhang ;
kito.ch...@gmail.com; richard.guent...@gmail.com
S
d.
Sure, will have a try for making the -0.0 happen in aarch64.
Pan
-Original Message-
From: Jeff Law
Sent: Friday, December 29, 2023 12:39 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; Wang, Yanzhang ;
kito.ch...@gmail.com; richard.guent...@gmail.com
Subject: Re
NOR_SIGNED_ZEROS (GET_MODE (x));
10874 return real_equal (CONST_DOUBLE_REAL_VALUE (x), &dconst0);
10875 }
I think that explain why we have +0.0 in aarch64 here.
Pan
-Original Message-
From: Jeff Law
Sent: Friday, December 29, 2023 9:04 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc
2 (set (reg:SF 136)
(mem/u/c:SF (lo_sum:DI (reg:DI 135)
(symbol_ref/u:DI ("*.LC0") [flags 0x82])) [0 S4 A32]))
"test.c":21:6 -1
(nil))
I will have a try to fix it in V3.
Pan
-Original Message-
From: Jeff Law
Sent: Saturday, December 30, 2023
--Original Message-
From: Richard Biener
Sent: Monday, January 8, 2024 6:45 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang
; kito.ch...@gmail.com; jeffreya...@gmail.com
Subject: Re: [PATCH v3] RISC-V: Bugfix for doesn't honor no-signed-zeros option
On Tue
misunderstanding.
Pan
-Original Message-
From: Li, Pan2
Sent: Tuesday, January 9, 2024 9:22 AM
To: Richard Biener
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang
; kito.ch...@gmail.com; jeffreya...@gmail.com
Subject: RE: [PATCH v3] RISC-V: Bugfix for doesn't honor no-s
Committed, thanks Juzhe.
Pan
From: 钟居哲
Sent: Saturday, December 2, 2023 9:10 AM
To: Li, Pan2 ; gcc-patches
Cc: Li, Pan2 ; Wang, Yanzhang ;
kito.cheng
Subject: Re: [PATCH v4] RISC-V: Bugfix for legitimize move when get vec mode in
zve32f
LGTM
juzhe.zh
Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Monday, December 4, 2023 4:10 PM
To: Li, Pan2 ; gcc-patches
Cc: Li, Pan2 ; Wang, Yanzhang ;
kito.cheng
Subject: Re: [PATCH v1] RISC-V: Add test case for bug PR112813
LGTM Thanks.
juzhe.zh
Hi Richard,
It looks like this patch result in one ICE for RISC-V backend for case
tree-ssa.exp=ssa-sink-16.c, could you please help to double check about it?
Any more information required please feel free to let me know. Thanks.
compiler error: Segmentation fault
0x1903067 crash_signal
Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Friday, December 8, 2023 4:03 PM
To: Li, Pan2 ; gcc-patches
Cc: Li, Pan2 ; Wang, Yanzhang ;
kito.cheng
Subject: Re: [PATCH v1] RISC-V: Fix ICE for incorrect mode attr in
V_F2DI_CONVERT_BRIDGE
LGTM
FYI. I have the some failures as juzhe mentioned, with the emulator qemu
version qemu-riscv64 version 8.1.93 (v8.2.0-rc3). The entire log may look like
below:
Executing on host:
/home/box/panli/riscv-gnu-toolchain/build-gcc-newlib-stage2/gcc/xgcc
-B/home/box/panli/riscv-gnu-toolchain/build-gcc
deprecated. Please use 'zve64f'
instead
foo is 50, foo2 is 12800, i,j is 1, 0
FAIL: gcc.target/riscv/rvv/autovec/builtin/strcmp-run.c execution test
Pan
-Original Message-----
From: Robin Dapp
Sent: Monday, December 11, 2023 4:34 PM
To: Li, Pan2 ; 钟居哲 ; gcc-patches
; palmer
: Monday, December 11, 2023 9:15 PM
To: Li, Pan2 ; 钟居哲 ; gcc-patches
; palmer ; kito.cheng
; Jeff Law
Cc: rdapp@gmail.com
Subject: Re: [PATCH] RISC-V: Add vectorized strcmp.
Hi Pan,
> I reduced the SZ size from 10 to 1, and the below case with SZ = 2
> will fail. The failed location i
Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Tuesday, December 12, 2023 4:30 PM
To: Li, Pan2 ; gcc-patches
Cc: Li, Pan2 ; Wang, Yanzhang ;
kito.cheng
Subject: Re: [PATCH v1] RISC-V: Disable RVV VCOMPRESS avl propagation
lgtm.
juzhe.zh
Committed, thanks Kito.
Pan
-Original Message-
From: Kito Cheng
Sent: Tuesday, November 7, 2023 10:47 AM
To: Juzhe-Zhong
Cc: gcc-patches@gcc.gnu.org; kito.ch...@sifive.com; jeffreya...@gmail.com;
rdapp@gmail.com
Subject: Re: [PATCH] RISC-V regression test: Fix FAIL of bb-slp-39.c
Committed, thanks Jeff.
Pan
-Original Message-
From: Jeff Law
Sent: Tuesday, November 7, 2023 11:25 AM
To: Juzhe-Zhong ; gcc-patches@gcc.gnu.org
Cc: rguent...@suse.de
Subject: Re: [PATCH] test: Fix FAIL of bb-slp-cond-1.c for RVV
On 11/6/23 16:03, Juzhe-Zhong wrote:
> This patch fixe
Committed, thanks Robin.
Pan
-Original Message-
From: Robin Dapp
Sent: Tuesday, November 7, 2023 2:59 PM
To: Juzhe-Zhong ; gcc-patches@gcc.gnu.org
Cc: rdapp@gmail.com; kito.ch...@gmail.com; kito.ch...@sifive.com;
jeffreya...@gmail.com
Subject: Re: [PATCH] RISC-V: Enhance AVL propag
Committed, thanks Richard.
Pan
-Original Message-
From: Richard Biener
Sent: Tuesday, November 7, 2023 8:51 PM
To: Juzhe-Zhong
Cc: gcc-patches@gcc.gnu.org; jeffreya...@gmail.com
Subject: Re: [PATCH] test: Fix FAIL of pr65518.c for RVV[PR112420]
On Tue, 7 Nov 2023, Juzhe-Zhong wrote:
Committed, thanks Richard.
Pan
-Original Message-
From: Richard Biener
Sent: Wednesday, November 8, 2023 2:58 PM
To: Juzhe-Zhong
Cc: gcc-patches@gcc.gnu.org
Subject: Re: [PATCH V2] test: Fix bb-slp-33.c for RVV
On Tue, 7 Nov 2023, Juzhe-Zhong wrote:
> gcc/testsuite/ChangeLog:
OK.
>
Committed, thanks Kito.
Pan
-Original Message-
From: Kito Cheng
Sent: Thursday, November 9, 2023 10:43 AM
To: Juzhe-Zhong
Cc: gcc-patches@gcc.gnu.org; kito.ch...@gmail.com; jeffreya...@gmail.com;
rdapp@gmail.com
Subject: Re: [PATCH] RISC-V: Fix dynamic LMUL cost model ICE
LGTM, t
Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Thursday, November 9, 2023 2:54 PM
To: Li, Pan2 ; gcc-patches
Cc: Li, Pan2 ; Wang, Yanzhang ;
kito.cheng
Subject: Re: [PATCH v1] RISC-V: Refine frm emit after bb end in succ edges
OK。
juzhe.zh
Committed, thanks Richard.
Pan
-Original Message-
From: Richard Biener
Sent: Thursday, November 9, 2023 11:12 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@sifive.com; Wang,
Yanzhang
Subject: Re: [PATCH v1] Internal-fn: Add FLOATN support for l/ll
Committed, thanks Juzhe.
Pan
From: juzhe.zhong
Sent: Friday, November 10, 2023 2:32 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; Li, Pan2 ; Wang, Yanzhang
; kito.ch...@gmail.com
Subject: Re: [PATCH v1] RISC-V: Support vec_init for trailing same element
lgtm
Replied Message
From
Committed, thanks Robin.
Pan
-Original Message-
From: Robin Dapp
Sent: Friday, November 10, 2023 4:12 PM
To: Juzhe-Zhong ; gcc-patches@gcc.gnu.org
Cc: rdapp@gmail.com; kito.ch...@gmail.com; kito.ch...@sifive.com;
jeffreya...@gmail.com
Subject: Re: [PATCH] RISC-V: Robustify vec_init
This patch only add new modes to iterator, I failed to find a way to test it.
Maybe I can add underlying lrint autovec implment together, which is more
straightforward
to add test cases here.
Pan
From: juzhe.zh...@rivai.ai
Sent: Friday, November 10, 2023 4:16 PM
To: Li, Pan2 ; gcc-patches
Cc
u posted.
Pan
-Original Message-
From: Richard Sandiford
Sent: Saturday, November 11, 2023 11:23 PM
To: Jeff Law
Cc: Li, Pan2 ; gcc-patches@gcc.gnu.org;
juzhe.zh...@rivai.ai; Wang, Yanzhang ;
kito.ch...@gmail.com; richard.guent...@gmail.com
Subject: Re: [PATCH v2] DSE: Allow vector type
Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Monday, November 13, 2023 11:11 AM
To: Li, Pan2 ; gcc-patches
Cc: Li, Pan2 ; Wang, Yanzhang ;
kito.cheng
Subject: Re: [PATCH v1] RISC-V: Fix RVV dynamic frm tests failure
OK
juzhe.zh...@rivai.ai
Update v4 in below link, please help to ignore v3.
https://gcc.gnu.org/pipermail/gcc-patches/2023-November/636216.html
Sorry for inconvenience.
Pan
-Original Message-
From: Li, Pan2
Sent: Sunday, November 12, 2023 10:31 AM
To: Richard Sandiford ; Jeff Law
Cc: gcc-patches@gcc.gnu.org
Sorry for the unexpected impact, good to know the rule about git revert, will
pay more attention for it.
Pan
-Original Message-
From: Jakub Jelinek
Sent: Tuesday, November 14, 2023 8:28 PM
To: juzhe.zh...@rivai.ai
Cc: Richard Biener ; Li, Pan2 ;
gcc-patches ; Wang, Yanzhang
iginal Message-
From: Jeff Law
Sent: Tuesday, November 14, 2023 4:12 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; Wang, Yanzhang ;
kito.ch...@gmail.com; richard.guent...@gmail.com; richard.sandiford@arm.com2
Subject: Re: [PATCH v4] DSE: Allow vector type for get_stored
Li, Pan2 would like to recall the message, "[PATCH v4] DSE: Allow vector type
for get_stored_val when read < store".
Sorry for disturbing, looks I have a typo for Richard S's email address, cc the
right email address for awareness.
Pan
-Original Message-
From: Li, Pan2
Sent: Wednesday, November 15, 2023 8:18 AM
To: Jeff Law ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; Wang, Yanzhang ;
ki
Committed, thanks Kito.
Pan
-Original Message-
From: Kito Cheng
Sent: Wednesday, November 15, 2023 3:36 PM
To: juzhe.zh...@rivai.ai
Cc: Kito.cheng ; gcc-patches ;
jeffreyalaw ; Robin Dapp
Subject: Re: Re: [PATCH] RISC-V: Disallow RVV mode address for any
load/store[PR112535]
LGTM, a
Committed, thanks Robin..
Pan
-Original Message-
From: Robin Dapp
Sent: Wednesday, November 15, 2023 4:59 PM
To: Juzhe-Zhong ; gcc-patches@gcc.gnu.org
Cc: rdapp@gmail.com; kito.ch...@gmail.com; kito.ch...@sifive.com;
jeffreya...@gmail.com
Subject: Re: [PATCH] RISC-V: Support traili
Hi Richard S,
Thanks a lot for reviewing and comments. May I know is there any concern or
further comments for landing this patch to GCC-14?
Pan
-Original Message-
From: Li, Pan2
Sent: Wednesday, November 15, 2023 8:25 AM
To: gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; Wang
> It looks like Jeff approved the patch?
Yes, just would like to double check the way of this patch is expected as
following the suggestion of Richard S.
Pan
-Original Message-
From: Richard Biener
Sent: Wednesday, November 22, 2023 4:02 PM
To: Li, Pan2
Cc: richard.sandif...@arm.
Committed, thanks all.
Pan
-Original Message-
From: Richard Sandiford
Sent: Thursday, November 23, 2023 2:39 AM
To: Li, Pan2
Cc: Richard Biener ; juzhe.zh...@rivai.ai; Wang,
Yanzhang ; kito.ch...@gmail.com; Jeff Law
; gcc-patches@gcc.gnu.org
Subject: Re: [PATCH v4] DSE: Allow vector
Committed, thanks Kito.
Pan
-Original Message-
From: Kito Cheng
Sent: Friday, November 24, 2023 2:30 PM
To: Juzhe-Zhong
Cc: gcc-patches@gcc.gnu.org; kito.ch...@gmail.com; jeffreya...@gmail.com;
rdapp@gmail.com
Subject: Re: [PATCH V2] RISC-V: Optimize a special case of VLA SLP
The
Committed with the test file rename, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Wednesday, November 29, 2023 2:45 PM
To: Li, Pan2 ; gcc-patches
Cc: Li, Pan2 ; Wang, Yanzhang ;
kito.cheng
Subject: Re: [PATCH v1] RISC-V: Bugfix for ICE in block move when zve32f
pr112743-0.c
> Why does get_vector_mode doesn't exist a vector mode ?
Because we set the zve32f here, but try to get_vect_mode with E_V1DFmode.
According to the ISA, FP64 is not support when zve32F.
Pan
From: juzhe.zh...@rivai.ai
Sent: Thursday, November 30, 2023 3:24 PM
To: Li, Pan2 ; gcc-patches
: juzhe.zh...@rivai.ai
Sent: Thursday, November 30, 2023 3:33 PM
To: Li, Pan2 ; gcc-patches
Cc: Wang, Yanzhang ; kito.cheng
Subject: Re: RE: [PATCH v1] RISC-V: Bugfix for legitimize move when get vec
mode in zve32f
What it the RTX of the operand ?
juzhe.zh
Got it, will have a try for the suggestion.
Pan
From: juzhe.zh...@rivai.ai
Sent: Thursday, November 30, 2023 3:54 PM
To: Li, Pan2 ; gcc-patches
Cc: Wang, Yanzhang ; kito.cheng
Subject: Re: RE: [PATCH v1] RISC-V: Bugfix for legitimize move when get vec
mode in zve32f
I see.
Is it possible
Committed, thanks Jeff.
Pan
-Original Message-
From: Jeff Law
Sent: Wednesday, September 20, 2023 9:39 PM
To: Wang, Yanzhang ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@sifive.com; Li, Pan2
Subject: Re: [PATCH] RISC-V: Support simplifying x/(-1) to neg for vector
Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Friday, September 22, 2023 9:17 AM
To: Li, Pan2 ; gcc-patches
Cc: Li, Pan2 ; Wang, Yanzhang ;
kito.cheng
Subject: Re: [PATCH v1] RISC-V: Leverage __builtin_xx instead of math.h for test
LGTM
Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Friday, September 22, 2023 11:45 AM
To: Li, Pan2 ; gcc-patches
Cc: Li, Pan2 ; Wang, Yanzhang ;
kito.cheng
Subject: Re: [PATCH v1] RISC-V: Remove arch and abi option for run test case.
LGTM
Committed, thanks Juzhe.
Pan
From: juzhe.zhong
Sent: Friday, September 22, 2023 12:18 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; Li, Pan2 ; Wang, Yanzhang
; kito.ch...@gmail.com
Subject: Re: [PATCH v1] RISC-V: Rename the test macro for math autovec test
ok
Replied Message
From
Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Friday, September 22, 2023 5:14 PM
To: Li, Pan2 ; gcc-patches
Cc: Li, Pan2 ; Wang, Yanzhang ;
kito.cheng
Subject: Re: [PATCH v1] RISC-V: Move ceil test cases to unop folder
ok
juzhe.zh
Sure thing, will send V2 for this.
Pan
From: juzhe.zh...@rivai.ai
Sent: Friday, September 22, 2023 7:26 PM
To: Li, Pan2 ; gcc-patches
Cc: Li, Pan2 ; Wang, Yanzhang ;
kito.cheng
Subject: Re: [PATCH v1] RISC-V: Refine the code gen for ceil auto vectorization.
I prefer change
Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Friday, September 22, 2023 8:19 PM
To: Li, Pan2 ; gcc-patches
Cc: Li, Pan2 ; Wang, Yanzhang ;
kito.cheng
Subject: Re: [PATCH v2] RISC-V: Refine the code gen for ceil auto vectorization.
LGTM
Committed, thanks Juzhe.
Pan
From: 钟居哲
Sent: Saturday, September 23, 2023 9:07 AM
To: Li, Pan2 ; gcc-patches
Cc: Li, Pan2 ; Wang, Yanzhang ;
kito.cheng
Subject: Re: [PATCH v1] RISC-V: Remove FP run test for ceil.
Ok
juzhe.zh...@rivai.ai<mailto:juzhe
Sure, will re-visit this part later.
Pan
-Original Message-
From: Kito Cheng
Sent: Saturday, September 23, 2023 3:47 PM
To: Li, Pan2
Cc: 钟居哲 ; gcc-patches ; Wang,
Yanzhang
Subject: Re: [PATCH v1] RISC-V: Remove FP run test for ceil.
I guess it just needs more checks than `target
Committed, thanks Juzhe.
Pan
From: 钟居哲
Sent: Sunday, September 24, 2023 2:06 PM
To: Li, Pan2 ; gcc-patches
Cc: Li, Pan2 ; Wang, Yanzhang ;
kito.cheng ; patrick
Subject: Re: [PATCH v2] RISC-V: Fix fortran ICE/PR111546 when RV32 vec_init
LGTM
juzhe.zh
Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Tuesday, September 26, 2023 11:18 AM
To: Li, Pan2 ; gcc-patches
Cc: Li, Pan2 ; Wang, Yanzhang ;
kito.cheng
Subject: Re: [PATCH v1] RISC-V: Rename rounding const fp function for refactor
LGTM
Committed as passed x86 bootstrap and regression test, thanks Richard.
Pan
-Original Message-
From: Richard Biener
Sent: Tuesday, September 26, 2023 7:35 PM
To: Juzhe-Zhong
Cc: gcc-patches@gcc.gnu.org; richard.sandif...@arm.com
Subject: Re: [PATCH V2] MATCH: Optimize COND_ADD_LEN reduc
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