Oops, this is more complicated than original expectation. Consider somehow the mrvv-vector-bits (zvl or scalable) decides how we perform the auto-vec. I may have one proposal to combine them together?
For example, mrvv-vector-bits=zvl indicates we will auto-vect in fixed-vlmax way, and mrvv-vector-bits=scalable indicates we will perform scalable auto-vec. That may make things clean and get ride of the conflict code in many places (maybe). Please help to correct me if any misunderstandings. Meanwhile, this change is sort of now or never up to point IMO. We can only do it before GCC-14 release or never I guess (to avoid breaking changes). > However here is something we need some fix, since > --param=riscv-autovec-preference=none still disable VLS code gen for > now, you can see some example here: > https://godbolt.org/z/fMTr3eW7K I am not quite sure about the right behavior here, when mrvv-vector-bits is given while riscv-autovec-preference is none... Pan -----Original Message----- From: Kito Cheng <kito.ch...@gmail.com> Sent: Wednesday, February 28, 2024 8:57 PM To: Li, Pan2 <pan2...@intel.com> Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang <yanzhang.w...@intel.com>; rdapp....@gmail.com; jeffreya...@gmail.com Subject: Re: [PATCH v3] RISC-V: Introduce gcc option mrvv-vector-bits for RVV Take one more look, I think this option should work and integrate with --param=riscv-autovec-preference= since they have similar jobs but slightly different. We have 3 value for --param=riscv-autovec-preference=: none, scalable and fixed-vlmax -mrvv-vector-bits=scalable is work like --param=riscv-autovec-preference=scalable and -mrvv-vector-bits=zvl is work like --param=riscv-autovec-preference=fixed-vlmax. So I think...we need to do some conflict check, like: -mrvv-vector-bits=zvl can't work with --param=riscv-autovec-preference=scalable -mrvv-vector-bits=scalable can't work with --param=riscv-autovec-preference=fixed-vlmax but it may not just alias since there is some useful combinations like: -mrvv-vector-bits=zvl with --param=riscv-autovec-preference=none: NO auto vectorization but intrinsic code still could benefit from the -mrvv-vector-bits=zvl option. -mrvv-vector-bits=scalable with --param=riscv-autovec-preference=none Should still work for VLS code gen, but just disable auto vectorization per the option semantic. However here is something we need some fix, since --param=riscv-autovec-preference=none still disable VLS code gen for now, you can see some example here: https://godbolt.org/z/fMTr3eW7K But I think it's really the right behavior here, this part might need to be fixed in vls_mode_valid_p and some other places. Anyway I think we need to check all use sites with RVV_FIXED_VLMAX and RVV_SCALABLE, and need to make sure all use site of RVV_FIXED_VLMAX also checked with RVV_VECTOR_BITS_ZVL. > -/* Return the VLEN value associated with -march. > +static int > +riscv_convert_vector_bits (int min_vlen) Not sure if we really need this function, it seems it always returns min_vlen? > +{ > + int rvv_bits = 0; > + > + switch (rvv_vector_bits) > + { > + case RVV_VECTOR_BITS_ZVL: > + case RVV_VECTOR_BITS_SCALABLE: > + rvv_bits = min_vlen; > + break; > + default: > + gcc_unreachable (); > + } > + > + return rvv_bits; > +} > + > +/* Return the VLEN value associated with -march and -mwrvv-vector-bits.
