Committed, thanks Juzhe. Pan
From: juzhe.zh...@rivai.ai <juzhe.zh...@rivai.ai> Sent: Monday, December 4, 2023 4:10 PM To: Li, Pan2 <pan2...@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org> Cc: Li, Pan2 <pan2...@intel.com>; Wang, Yanzhang <yanzhang.w...@intel.com>; kito.cheng <kito.ch...@gmail.com> Subject: Re: [PATCH v1] RISC-V: Add test case for bug PR112813 LGTM Thanks. ________________________________ juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai> From: pan2.li<mailto:pan2...@intel.com> Date: 2023-12-04 16:09 To: gcc-patches<mailto:gcc-patches@gcc.gnu.org> CC: juzhe.zhong<mailto:juzhe.zh...@rivai.ai>; pan2.li<mailto:pan2...@intel.com>; yanzhang.wang<mailto:yanzhang.w...@intel.com>; kito.cheng<mailto:kito.ch...@gmail.com> Subject: [PATCH v1] RISC-V: Add test case for bug PR112813 From: Pan Li <pan2...@intel.com<mailto:pan2...@intel.com>> The bugzilla 112813 has been fixed recently, add below test case for the bug. PR target/112813 gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/vsetvl/pr112813-1.c: New test. Signed-off-by: Pan Li <pan2...@intel.com<mailto:pan2...@intel.com>> --- .../gcc.target/riscv/rvv/vsetvl/pr112813-1.c | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112813-1.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112813-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112813-1.c new file mode 100644 index 00000000000..5aab9c2bf09 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112813-1.c @@ -0,0 +1,32 @@ +/* Test that we do not have ice when compile */ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -O3" } */ + +int a, c, d, f, j; +int b[7]; +long e; +char *g; +int *h; +long long *i; + +void k() { + int l[][1] = {{}, {1}, {1}}; + int *m = &d, *n = &l[0][0]; + + for (; e;) + { + f = 3; + + for (; f >= 0; f--) + { + *m &= b[f] >= 0; + j = a >= 2 ? 0 : 1 >> a; + *i |= j; + } + + for (; c;) + *g = 0; + } + + h = n; +} -- 2.34.1
