[committed] Fix typo/thinko in recent tree-ssa-dse.c change

I meant to mask off low bits in the head trim and wrote... -*trim_head &= (UNITS_PER_WORD - 1); Which, of course is wrong as it's missing the bit-not. This led to a regression on at least one 32bit target for pr30375's testcase. This patch adds the missing bit-not. It fixes the regressi

[committed] And now fixing alignment stuff for ARM

Just like the others.Committing to the trunk. Jeff diff --git a/gcc/ChangeLog b/gcc/ChangeLog index bccc0c76b04..0249082f618 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,8 @@ 2018-07-17 Jeff Law + * config/arm/arm.c (get_label_padding): Update for recent

Re: cleanup cross product code in VRP

On 07/19/2018 03:06 AM, Aldy Hernandez wrote: > > > On 07/19/2018 04:18 AM, Richard Biener wrote: >> On Wed, Jul 18, 2018 at 2:05 PM Aldy Hernandez wrote: >>> >>> Hi again! >>> >>> Well, since this hasn't been reviewed and I'm about to overhaul the >>> TYPE_OVERFLOW_WRAPS code anyhow, might as w

Re: [PATCH] Use __builtin_memmove for trivially copy assignable types

On 07/19/2018 08:39 AM, Jonathan Wakely wrote: > On 19/07/18 10:01 -0400, Glen Fernandes wrote: >> On Thu, Jul 19, 2018 at 9:25 AM Jonathan Wakely >> wrote: >>> Sorry for the delay in reviewing this properly, as I've only just >>> realised that this introduces undefined behaviour, doesn't it? >>>

Re: [PATCH][GCC][front-end][build-machinery][opt-framework] Allow setting of stack-clash via configure options. [Patch (4/6)]

On 07/19/2018 06:55 AM, Tamar Christina wrote: >>> >>> What's the purpose of including auto-host in params-list and >>> params-options? It seems like you're putting a property of the target >>> (guard size) into the wrong place (auto-host.h). >>> >> >> The reason for this is because there's a test

Re: [PATCH, obvious?] Some minor nits in string folding functions

On 07/19/2018 12:04 PM, Bernd Edlinger wrote: > Hi, > > > this fixes a few minor nits, which I spotted while > looking at the string folding functions: > > string_constant: Remove impossible check: TREE_CODE (arg) > can't be COMPONENT_REF and MEM_REF at the same time. Shouldn't they all be != te

Re: [PATCH] restore -Warray-bounds for string literals (PR 83776)

On 07/13/2018 05:45 PM, Martin Sebor wrote: >> >> +  offset_int ofr[] = { >> +   wi::to_offset (fold_convert (ptrdiff_type_node, vr->min)), >> +   wi::to_offset (fold_convert (ptrdiff_type_node, vr->max)) >> +  }; >> >> huh.  Do you maybe want to use widest_int for ofr[]?  What's >>

Re: [PATCH] specify large command line option arguments (PR 82063)

On 06/24/2018 03:05 PM, Martin Sebor wrote: > Storing integer command line option arguments in type int > limits options such as -Wlarger-than= or -Walloca-larger-than > to at most INT_MAX (see bug 71905).  Larger values wrap around > zero.  The value zero is considered to disable the option, > mak

Re: [PATCH][GCC][front-end][build-machinery][opt-framework] Allow setting of stack-clash via configure options. [Patch (4/6)]

On 07/20/2018 05:03 AM, Tamar Christina wrote: >> Understood. Thanks for verifying. I wonder if we could just bury this >> entirely >> in the aarch64 config files and not expose the default into params.def? >> > > Burying it in config.gcc isn't ideal because if your C runtime is > configurable

Re: [PATCH][GCC][front-end][build-machinery][opt-framework] Allow setting of stack-clash via configure options. [Patch (4/6)]

On 07/20/2018 09:39 AM, Tamar Christina wrote: >> >> On 07/20/2018 05:03 AM, Tamar Christina wrote: Understood. Thanks for verifying. I wonder if we could just bury this entirely in the aarch64 config files and not expose the default into >> params.def? >>> >>> Burying it in config

Re: [PATCH 11/11] Increase MAX_MAX_OPERANDS limit

On 07/19/2018 08:12 PM, Dimitar Dimitrov wrote: > On събота, 23 юни 2018 г. 20:35:23 EEST Jakub Jelinek wrote: >> On Sat, Jun 23, 2018 at 03:26:50PM +0300, Dimitar Dimitrov wrote: >>> I took arm/ldmstm.md as an inspiration. See attached machine description >>> for PRU that requires the increase. I

Re: [1/5] C-SKY port: Configury

On 07/23/2018 10:19 PM, Sandra Loosemore wrote: > 2018-07-23  Jojo  >     Huibin Wang  >     Sandra Loosemore  >     Chung-Lin Tang  >     Andrew Jenner  > >     C-SKY port: Configury > >     gcc/ >     * config.gcc (csky-*-*): New. >     * con

Re: [3/5] C-SKY port: Documentation

On 07/23/2018 10:23 PM, Sandra Loosemore wrote: > 2018-07-23  Sandra Loosemore  > >     C-SKY port: Documentation > >     gcc/ >     * doc/extend.texi (C-SKY Function Attributes): New section. >     * doc/invoke.texi (Option Summary): Add C-SKY options. >     (C-SKY Options):

Re: [4/5] C-SKY port: Testsuite

On 07/23/2018 10:25 PM, Sandra Loosemore wrote: > 2018-07-23  Sandra Loosemore  >     Chung-Lin Tang  > >     C-SKY port: Testsuite > >     gcc/testsuite/ >     * g++.dg/Wno-frame-address.C: Adjust for C-SKY. >     * g++.dg/torture/type-generic-1.C: Likewise. >     *

Re: [5/5] C-SKY port: libgcc

On 07/23/2018 10:26 PM, Sandra Loosemore wrote: > 2018-07-23  Jojo  >     Huibin Wang  >     Sandra Loosemore  >     Chung-Lin Tang  > >     C-SKY port: libgcc > >     libgcc/ >     * config.host: Add C-SKY support. >     * config/csky/*: New. Obviousl

Re: [2/5] C-SKY port: Backend implementation

On 07/23/2018 10:21 PM, Sandra Loosemore wrote: > 2018-07-23  Jojo  >     Huibin Wang  >     Sandra Loosemore  >     Chung-Lin Tang  > >     C-SKY port: Backend implementation > >     gcc/ >     * config/csky/*: New. >     * common/config/csky/*: New.

Re: Fix ceil_log2(0) (PR 86644)

On 07/24/2018 12:11 PM, Richard Sandiford wrote: > This PR shows a pathological case in which we try SLP vectorisation on > dead code. We record that 0 bits of the result are enough to satisfy > all users (which is true), and that led to precision being 0 in: > > static unsigned int > vect_elemen

Re: [PATCH] combine: Allow combining two insns to two insns

On 07/24/2018 11:18 AM, Segher Boessenkool wrote: > This patch allows combine to combine two insns into two. This helps > in many cases, by reducing instruction path length, and also allowing > further combinations to happen. PR85160 is a typical example of code > that it can improve. > > This p

Re: [2/5] C-SKY port: Backend implementation

On 07/24/2018 12:18 PM, Sandra Loosemore wrote: > On 07/24/2018 09:45 AM, Jeff Law wrote: >> On 07/23/2018 10:21 PM, Sandra Loosemore wrote: >>> 2018-07-23  Jojo  >>> Huibin Wang  >>> Sandra Loosemore  >>>

Re: [PATCH 6/7] AArch64 - new pass to add conditional-branch speculation tracking

On 07/23/2018 08:33 AM, Richard Earnshaw (lists) wrote: > [sorry, missed this mail somehow] > > On 11/07/18 22:01, Jeff Law wrote: >> On 07/09/2018 10:38 AM, Richard Earnshaw wrote: >>> This patch is the main part of the speculation tracking code. It adds >>> a

Re: [PATCH] Make strlen range computations more conservative

On 07/24/2018 01:59 AM, Bernd Edlinger wrote: > Hi! > > This patch makes strlen range computations more conservative. > > Firstly if there is a visible type cast from type A to B before passing > then value to strlen, don't expect the type layout of B to restrict the > possible return value range

Re: [PATCH] Explain asan parameters in params.def (PR sanitizer/79635).

On 07/24/2018 06:18 AM, Martin Liška wrote: > Hi. > > That's simple patch that improves documentation as requested > in the PR. > > Ready for trunk? > Martin > > gcc/ChangeLog: > > 2018-07-24 Martin Liska > > PR sanitizer/79635 > * params.def: Explain ASan abbreviation and pro

Re: [PATCH] fix a couple of bugs in const string folding (PR 86532)

On 07/24/2018 02:16 PM, Martin Sebor wrote: > On 07/20/2018 04:20 AM, Richard Biener wrote: >> On Thu, 19 Jul 2018, Martin Sebor wrote: >> >>> Here's one more update with tweaks addressing a couple more >>> of Bernd's comments: >>> >>> 1) correct the use of TREE_STRING_LENGTH() where a number of >>

Re: [2/5] C-SKY port: Backend implementation

On 07/24/2018 06:17 PM, Sandra Loosemore wrote: > On 07/24/2018 03:24 PM, Jeff Law wrote: >>> >>>> Any thoughts on using the newer function descriptor bits rather than >>>> old >>>> style stack trampolines? >>> >>> Has that be

Re: [PATCH] Make strlen range computations more conservative

On 07/24/2018 05:18 PM, Bernd Edlinger wrote: > On 07/24/18 23:46, Jeff Law wrote: >> I'd like to ask we hold on this until I return from PTO (Aug 1) so that >> we can discuss the best thing to do here for each class of change. >> > > Okay. > >> I think

[committed] [RISC-V] Fix expected diagnostic messages in testsuite

Whoops, this should have gone in with the fixes to the RISC-V diagnostics from earlier this week. Committed to the trunk. Jeff commit 6f709f79c915a1ea82220a44e9f4a144d5eedfd1 Author: Jeff Law Date: Wed Jul 26 19:25:33 2023 -0600 [committed] [RISC-V] Fix expected diagnostic messages in

[committed] [RISC-V] Avoid sub-word mode comparisons with Zicond

tch changes the 6 zicond patterns to use the X iterator on the comparison inputs. That at least makes the patterns correct and fixes this particular testcase. There's a few other lurking problems that I'll address in additional patches. Committed to the trunk, Jeff commit 2d73f2eb8

Re: Fix profile upate after vectorizer peeling

On 8/3/23 04:13, Jan Hubicka wrote: Note most of the profile consistency checks FAIL when testing with -m32 on x86_64-unknown-linux-gnu ... For example vect-11.c has ;; basic block 4, loop depth 0, count 719407024 (estimated locally, freq 0.6700), maybe hot ;; Invalid sum of incoming co

Re: Fix profile upate after vectorizer peeling

On 8/3/23 08:23, Jan Hubicka wrote: Jeff, an help would be appreciated here :) I will try to debug this. One option would be to disable branch prediciton on vect_check for time being - it is not inlined anyway Not a lot of insight. The backwards threader uses a totally different API for th

Re: [committed] [RISC-V] Avoid sub-word mode comparisons with Zicond

On 8/5/23 01:46, Xiao Zeng wrote: The operands to the comparison need to be in DImode for rv64 and SImode for rv32.  That's the X iterator. After analyzing the rtl log, I can't agree more with this sentence. Note the mode of the comparison operands may be different than the mode of the de

[committed][RISC-V]Don't reject constants in cmov condition

This test is too aggressive. Constants have VOIDmode, so we need to let the through this phase of conditional move support. Fixes several missed conditional moves with the trunk. Committed to the trunk, Jeff commit 18c453f0e633abb9b317947b011ec6e07780fba8 Author: Jeff Law Date: Mon Aug

[committed] [RISC-V] Fix bug in condition canonicalization for zicond

itable testcase. Committed to the trunk, Jeff commit 20659be04c2749f9f47b085f1789eee0d145fb36 Author: Jeff Law Date: Tue Aug 8 15:32:38 2023 -0600 [committed] [RISC-V] Fix bug in condition canonicalization for zicond Vineet's glibc build triggered an ICE building glibc with the la

Re: [PING] [PATCH] Harmonize headers between both dg-extract-results scripts

On 10/18/23 03:35, Thomas Schwinge wrote: Is this (case variants) maybe something that has changed in DejaGnu at some point in time? (I have not checked.) No idea :-) I suggest that we adapt all remaining upper-case instances in GCC, similar to your change. And/or, as applicable, recogn

Re: [PATCH v2 0/2] riscv: Adding support for XTHead(F)MemIdx

available on the market for quite some time. The ISA spec can be found here: https://github.com/T-head-Semi/thead-extension-spec An initial version of these patches has been sent a while ago. Jeff Law suggested to use INSNs instead of peepholes to let the combiner do the optimization. This is the

Re: [PATCH] RISC-V: 'Zfa' extension is now ratified

On 10/20/23 23:32, Tsukasa OI wrote: From: Tsukasa OI Since this extension is ratified, it now has the version number 1.0. Reference: gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_ext_version_table): Chang

Re: [PATCH] RISC-V: Prohibit combination of 'E' and 'H'

On 10/20/23 23:32, Tsukasa OI wrote: From: Tsukasa OI According to the ratified privileged specification (version 20211203), it says: The hypervisor extension depends on an "I" base integer ISA with 32 x registers (RV32I or RV64I), not RV32E, which has only 16 x registers. Also in the la

Re: Darwin: Replace environment runpath with embedded [PR88590]

On 10/8/23 16:14, Iain Sandoe wrote: + Jeff On 8 Oct 2023, at 14:07, Nathanael Nerode wrote: I hope a global maintainer can step up. I've been on hiatus from GCC work for some years, and this was never my part of the build system anyway -- and I don't use Darwin -- so I'm not qualified

Re: [PATCH] gcc.c-torture/execute/builtins/pr93262-chk.c: Remove return statement

On 10/22/23 01:46, Florian Weimer wrote: The main_test function returns void, so return with an expression is a constraint violation. The test case still fails with this change applied before the fix for PR 93262 in r14-4813. gcc/testsuite/ * gcc.c-torture/execute/builtins/pr93262-c

Re: [PATCH] gcc.c-torture/execute/builtins/fputs.c: Define _GNU_SOURCE

On 10/22/23 01:47, Florian Weimer wrote: Current glibc headers only declare fputs_unlocked for _GNU_SOURCE. Defining the macro avoids an implicit function declaration. gcc/testsuite/ * gcc.c-torture/execute/builtins/fputs.c (_GNU_SOURCE): Define. OK jeff

Re: [PATCH] gcc.c-torture/execute/builtins/fputs.c: Define _GNU_SOURCE

On 10/22/23 10:09, Andrew Pinski wrote: On Sun, Oct 22, 2023 at 12:47 AM Florian Weimer wrote: Current glibc headers only declare fputs_unlocked for _GNU_SOURCE. Defining the macro avoids an implicit function declaration. This does not help targets that don't use glibc though. Note for bu

Re: [PATCH] RISC-V: Prohibit combination of 'E' and 'H'

On 10/21/23 19:33, Tsukasa OI wrote: Hmm, I generally agree with your opinion and I made a board file for DejaGnu (running qemu-riscv64) to run "make check-gcc RUNTESTFLAGS='--target_board=riscv-sim riscv.exp'" because it already contains many execute tests (and annoys me if I don't do that)

Re: [PATCH] RISC-V: Fix AVL_TYPE attribute of tuple mode mov

On 10/22/23 16:46, Juzhe-Zhong wrote: The tuple mode mov pattern doesn't have avl_type so it is invalid attribute. gcc/ChangeLog: * config/riscv/vector.md: Fix avl_type attribute of tuple mov. Presumably you got a fault or something similar trying to compute the avl_type attr when

Re: [PATCH 1/6] rtl-ssa: Ensure global registers are live on exit

On 10/24/23 04:50, Richard Sandiford wrote: RTL-SSA mostly relies on DF for block-level register liveness information, including artificial uses and defs at the beginning and end of blocks. But one case was missing. DF does not add artificial uses of global registers to the beginning or end

Re: [PATCH 2/6] rtl-ssa: Create REG_UNUSED notes after all pending changes

On 10/24/23 04:50, Richard Sandiford wrote: Unlike REG_DEAD notes, REG_UNUSED notes need to be kept free of false positives by all passes. function_info::change_insns does this by removing all REG_UNUSED notes, and then using add_reg_unused_notes to add notes back (or create new ones) where a

Re: [PATCH 3/6] rtl-ssa: Fix ICE when deleting memory clobbers

On 10/24/23 04:50, Richard Sandiford wrote: Sometimes an optimisation can remove a clobber of scratch registers or scratch memory. We then need to update the DU chains to reflect the removed clobber. For registers this isn't a problem. Clobbers of registers are just momentary blips in the r

Re: [PATCH 4/6] rtl-ssa: Handle artifical uses of deleted defs

On 10/24/23 04:50, Richard Sandiford wrote: If an optimisation removes the last real use of a definition, there can still be artificial uses left. This patch removes those uses too. These artificial uses exist because RTL-SSA is only an SSA-like view of the existing RTL IL, rather than a nat

Re: [PATCH 5/6] rtl-ssa: Calculate dominance frontiers for the exit block

On 10/24/23 04:50, Richard Sandiford wrote: The exit block can have multiple predecessors, for example if the function calls __builtin_eh_return. We might then need PHI nodes for values that are live on exit. RTL-SSA uses the normal dominance frontiers approach for calculating where PHI node

Re: [PATCH 6/6] rtl-ssa: Handle call clobbers in more places

On 10/24/23 04:50, Richard Sandiford wrote: In order to save (a lot of) memory, RTL-SSA avoids creating individual clobber records for every call-clobbered register. It instead maintains a list & splay tree of calls in an EBB, grouped by ABI. This patch takes these call clobbers into account

Re: [PATCH] recog/reload: Remove old UNARY_P operand support

On 10/24/23 04:14, Richard Sandiford wrote: reload and constrain_operands had some old code to look through unary operators. E.g. an operand could be (sign_extend (reg X)), and the constraints would match the reg rather than the sign_extend. > This was previously used by the MIPS port. But r

Re: [PATCH] gcov-io.h: fix comment regarding length of records

On 10/24/23 06:41, Jose E. Marchesi wrote: The length of gcov records is stored as a signed 32-bit number of bytes. Ok? OK. jeff

Re: [PATCH] testsuite: Fix _BitInt in gcc.misc-tests/godump-1.c

On 10/24/23 09:26, Stefan Schulze Frielinghaus wrote: Currently _BitInt is only supported on x86_64 which means that for other targets all tests fail with e.g. gcc.misc-tests/godump-1.c:237:1: sorry, unimplemented: '_BitInt(32)' is not supported on this target 237 | _BitInt(32) b32_v;

Re: [PATCH 1/3] rtl-ssa: Use frequency-weighted insn costs

On 10/24/23 11:58, Richard Sandiford wrote: rtl_ssa::changes_are_worthwhile used the standard approach of summing up the individual costs of the old and new sequences to see which one is better overall. But when optimising for speed and changing instructions in multiple blocks, it seems bette

Re: [PATCH 2/3] rtl-ssa: Extend make_uses_available

On 10/24/23 11:58, Richard Sandiford wrote: The first in-tree use of RTL-SSA was fwprop, and one of the goals was to make the fwprop rewrite preserve the old behaviour as far as possible. The switch to RTL-SSA was supposed to be a pure infrastructure change. So RTL-SSA has various FIXMEs for

Re: [PATCH 3/3] rtl-ssa: Add new helper functions

On 10/24/23 11:58, Richard Sandiford wrote: This patch adds some RTL-SSA helper functions. They will be used by the upcoming late-combine pass. The patch contains the first non-template out-of-line function declared in movement.h, so it adds a movement.cc. I realise it seems a bit over-the-

Re: [RFC] RISC-V: elide sign extend when expanding cmp_and_jump

On 10/25/23 01:12, Robin Dapp wrote: Hi Vineet, I was thinking of two things while skimming the code: - Couldn't we do this in the expanders directly? Or is the subreg-promoted info gone until we reach that? Well, it doesn't seem like there's a lot of difference between doing it in t

Re: [RFC] RISC-V: elide sign extend when expanding cmp_and_jump

On 10/25/23 07:47, Robin Dapp wrote: Well, it doesn't seem like there's a lot of difference between doing it in the generic expander bits vs target expander bits -- the former just calls into the latter for the most part. Thus if the subreg-promoted state is available in the target expander

Re: [PING^2] More '#ifdef ASM_OUTPUT_DEF' -> 'if (TARGET_SUPPORTS_ALIASES)' etc.

On 10/25/23 02:38, Thomas Schwinge wrote: Hi! Ping. Grüße Thomas On 2023-09-19T10:47:56+0200, I wrote: Hi! Ping. Grüße Thomas On 2023-09-08T14:02:50+0200, I wrote: Hi! On 2017-08-10T15:42:13+0200, Jan Hubicka wrote: On 07/31/2017 11:57 AM, Yuri Gribov wrote: On Mon, Jul 31,

Re: [PATCH v2] PR 91865: Avoid ZERO_EXTEND of ZERO_EXTEND in make_compound_operation.

On 10/25/23 03:21, Roger Sayle wrote: Hi Jeff, Many thanks for the review/approval of my fix for PR rtl-optimization/91865. Based on your and Richard Biener's feedback, I’d like to propose a revision calling simplify_unary_operation instead of simplify_const_unary_operation (i.e. Richi's reco

Re: [RFC] RISC-V: elide sign extend when expanding cmp_and_jump

On 10/25/23 10:25, Vineet Gupta wrote: Hey Robin, On 10/25/23 00:12, Robin Dapp wrote: Hi Vineet, I was thinking of two things while skimming the code:   - Couldn't we do this in the expanders directly?  Or is the     subreg-promoted info gone until we reach that? Following is the call s

Re: [PATCH] Ignore case of header line in dg-extract-results.py

On 10/25/23 22:09, Alexandre Oliva wrote: On Oct 24, 2023, Paul Iannetta wrote: * dg-extract-results.py: Make the test_run regex case insensitive. It looks reasonable to me, but I'm not sure this is a change I'm entitled to approve. Thanks! Even so, I trust your judgme

Re: [PATCH] RISC-V: Pass abi to g++ rvv testsuite

On 10/25/23 18:13, Patrick O'Neill wrote: On rv32gcv testcases like g++.target/riscv/rvv/base/bug-22.C fail with: FAIL: g++.target/riscv/rvv/base/bug-22.C (test for excess errors) Excess errors: cc1plus: error: ABI requires '-march=rv32' This patch adds the -mabi argument to g++ rvv tests. g

Re: [PING] libffi: Consider '--with-build-sysroot=[...]' for target libraries' build-tree testing (instead of build-time 'CC' etc.) [PR109951]

On 10/25/23 02:30, Thomas Schwinge wrote: Hi! Ping. Grüße Thomas On 2023-09-12T12:58:27+0200, I wrote: Hi! On 2020-04-20T14:18:40+0100, "Maciej W. Rozycki via Gcc-patches" wrote: Fix a problem with the libffi testsuite using a method to determine the compiler to use resulting in th

Re: [PING] libatomic: Consider '--with-build-sysroot=[...]' for target libraries' build-tree testing (instead of build-time 'CC' etc.) [PR109951]

On 10/25/23 02:32, Thomas Schwinge wrote: Hi! Ping. Grüße Thomas On 2023-09-12T13:03:28+0200, I wrote: Hi! On 2020-04-04T00:00:44+0100, "Maciej W. Rozycki via Gcc-patches" wrote: Fix a problem with the libatomic testsuite using a method to determine the compiler to use resulting in

Re: [PATCH] RISC-V: Add rawmemchr expander.

On 10/27/23 01:38, Robin Dapp wrote: Suggested adapt codes as follows: unsigned int element_size = GET_MODE_SIZE (mode).to_constant (); poly_int64 nunits = exact_div (BYTES_PER_RISCV_VECTOR *TARGET_MAX_LMUL, element_size); if (!get_vector_mode(mode, nunits).exists(&vmode))   gcc_unreachable

Re: [PATCH] RISC-V: Fix wrong tune parameters on int_div

On 10/27/23 01:37, juzhe.zh...@rivai.ai wrote: LGTM from my side. The original integer division COST seems too low. Almost certainly, though there may be good reasons why it was initially set so low. I'm generally hesitant to change things like that without either someone with knowledge of

Re: [PATCH] RISC-V: Fix wrong tune parameters on int_div

On 10/27/23 01:49, Robin Dapp wrote: @@ -346,7 +346,7 @@ static const struct riscv_tune_param rocket_tune_info = { {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_mul */ {COSTS_N_INSNS (20), COSTS_N_INSNS (20)}, /* fp_div */ {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* int_mu

Re: [ARC PATCH] Improved SImode shifts and rotates with -mswap.

On 10/27/23 08:22, Roger Sayle wrote: This patch improves the code generated by the ARC back-end for CPUs without a barrel shifter but with -mswap. The -mswap option provides a SWAP instruction that implements SImode rotations by 16, but also logical shift instructions (left and right) by 16

Re: [PATCH] RISC-V: Fix wrong tune parameters on int_div

On 10/26/23 12:50, Yangyu Chen wrote: This patch fixes an issue with the cost on "int_div" in various RISC-V tune parameters including those for Rocket, SiFive U7 series, and T-Head C906. This incorrect cost value interferes with the optimization process. For example, it prevents the optimizat

Re: [PATCH] recog: Fix propagation into ASM_OPERANDS

On 10/24/23 04:15, Richard Sandiford wrote: An inline asm with multiple output operands is represented as a parallel set in which the SET_SRCs are the same (shared) ASM_OPERANDS. insn_propgation didn't account for this, and instead propagated into each ASM_OPERANDS individually. This meant th

Re: [PATCH] C99 testsuite readiness: Some unverified test case reductions

On 10/20/23 13:05, Florian Weimer wrote: gcc/testsuite/ * gcc.c-torture/compile/2412-2.c (f): Call __builtin_strleninstead of strlen. * gcc.c-torture/compile/2427-1.c (FindNearestPowerOf2): Declare. * gcc.c-torture/compile/2802-1.c (

Re: [committed] RISC-V: Make stack_save_restore tests more robust

On 10/27/23 11:34, Patrick O'Neill wrote: On 8/25/23 15:36, Jeff Law wrote: Spurred by Jivan's patch and a desire for cleaner testresults, I went ahead and make the stack_save_restore tests independent of the precise stack size by using a regexp. Pushed to the trunk. Jeff

Re: [PATCH] RISC-V: Fix wrong tune parameters on int_div

On 10/27/23 11:39, Andrew Waterman wrote: On Fri, Oct 27, 2023 at 6:44 AM Jeff Law wrote: On 10/27/23 01:37, juzhe.zh...@rivai.ai wrote: LGTM from my side. The original integer division COST seems too low. Almost certainly, though there may be good reasons why it was initially set so

Re: [PATCH] RISC-V: Make stack_save_restore_2 more robust

On 10/27/23 11:56, Patrick O'Neill wrote: GCC recently changed to emit __riscv_restore_5 which causes this testcase to fail. This patch updates the regex to be more robust to change by accepting any number after __riscv_save_ and __riscv_restore_. gcc/testsuite/ChangeLog: * gcc.targe

Re: [PATCH v1] RISC-V: Remove unnecessary asm check for vec cvt

On 10/23/23 03:54, pan2...@intel.com wrote: From: Pan Li The vsetvl asm check is unnecessary for the vector convert. We should be focus for constrait and leave the vsetvl test to the vsetvl pass. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/unop/cvt-0.c: Remove the vsetv

Re: [PATCH v2] gcc.c-torture/execute/builtins/fputs.c: fputs_unlocked prototype

On 10/23/23 02:37, Florian Weimer wrote: Current glibc headers only declare fputs_unlocked for _GNU_SOURCE, so define it to obtain an official prototype. Add a fallback prototype declaration for other systems that do not have fputs_unlocked. This seems to the most straightforward approach to

Re: [PATCH] A new copy propagation and PHI elimination pass

On 10/20/23 07:52, Filip Kastl wrote: On Fri 2023-10-20 15:50:25, Filip Kastl wrote: Bootstraped and tested* on x86_64-pc-linux-gnu. * One testcase (pr79691.c) did regress. However that is because the test is dependent on a certain variable not being copy propagated. I will go into more deta

Re: [PATCH 1/3] [V6] [RISC-V] support cm.push cm.pop cm.popret in zcmp

On 10/27/23 14:31, Patrick O'Neill wrote: Hi Fei, A recent change to GCC [1] updated the  the registers in the cm.push and cm.pop insns for these testcases: |FAIL: gcc.target/riscv/rv32i_zcmp.c -Os check-function-bodies test1 FAIL: gcc.target/riscv/rv32i_zcmp.c -Os check-function-bodies

Re: [PATCH 1/3] [V6] [RISC-V] support cm.push cm.pop cm.popret in zcmp

On 10/27/23 14:31, Patrick O'Neill wrote: Hi Fei, A recent change to GCC [1] updated the  the registers in the cm.push and cm.pop insns for these testcases: |FAIL: gcc.target/riscv/rv32i_zcmp.c -Os check-function-bodies test1 FAIL: gcc.target/riscv/rv32i_zcmp.c -Os check-function-bodies

Re: [PATCH v1] RISC-V: Fix one range-loop-construct warning of avlprop

On 10/28/23 08:51, pan2...@intel.com wrote: From: Pan Li This patch would like to fix one warning of avlprop as below. ../../gcc/config/riscv/riscv-avlprop.cc: In member function 'virtual unsigned int pass_avlprop::execute(function*)': ../../gcc/config/riscv/riscv-avlprop.cc:346:23: error:

Re: [PATCH v2 1/2] riscv: thead: Add support for the XTheadMemIdx ISA extension

On 10/20/23 03:53, Christoph Muellner wrote: From: Christoph Müllner The XTheadMemIdx ISA extension provides a additional load and store instructions with new addressing modes. The following memory accesses types are supported: * load: b,bu,h,hu,w,wu,d * store: b,h,w,d The following addres

Re: [PATCH v2 2/2] riscv: thead: Add support for the XTheadFMemIdx ISA extension

On 10/20/23 03:53, Christoph Muellner wrote: From: Christoph Müllner The XTheadFMemIdx ISA extension provides additional load and store instructions for floating-point registers with new addressing modes. The following memory accesses types are supported: * load/store: [w,d] (single-precisi

Re: [ARC PATCH] Convert (signed<<31)>>31 to -(signed&1) without barrel shifter.

On 10/28/23 10:47, Roger Sayle wrote: This patch optimizes PR middle-end/101955 for the ARC backend. On ARC CPUs with a barrel shifter, using two shifts is (probably) optimal as: asl_s r0,r0,31 asr_s r0,r0,31 but without a barrel shifter, GCC -O2 -mcpu=em currently ge

Re: [ARC PATCH] Improved ARC rtx_costs/insn_cost for SHIFTs and ROTATEs.

On 10/29/23 03:16, Roger Sayle wrote: This patch overhauls the ARC backend's insn_cost target hook, and makes some related improvements to rtx_costs, BRANCH_COST, etc. The primary goal is to allow the backend to indicate that shifts and rotates are slow (discouraged) when the CPU doesn't hav

Re: [ARC PATCH] Improve DImode left shift by a single bit.

On 10/28/23 07:05, Roger Sayle wrote: This patch improves the code generated for X << 1 (and for X + X) when X is 64-bit DImode, using the same two instruction code sequence used for DImode addition. For the test case: long long foo(long long x) { return x << 1; } GCC -O2 currently generat

Re: [PATCH 1/4] [RISC-V]add hook to control Zicond based ifcvt opt

On 10/30/23 01:25, Fei Gao wrote: TARGET_HAVE_COND_ZERO is added to control ifcvt optimization for targets with RISC-V Zicond like insns. Co-authored-by: Xiao Zeng gcc/ChangeLog: * config/riscv/riscv.cc (riscv_have_cond_zero): Implement TARGET_HAVE_COND_ZERO (TARGET_HAVE_

Re: [ARC PATCH] Improve DImode left shift by a single bit.

On 10/30/23 09:27, Roger Sayle wrote: WRT H8. Bug filed so we don't lose track of it. We don't have DImode operations defined on the H8. First step would be DImode loads/stores and basic arithmetic. The H8's machine description is impressively well organized. Would it make sense to add

Re: [PATCH 2/4] [ifcvt] if convert x=c ? y+z : y by RISC-V Zicond like insns

On 10/30/23 01:25, Fei Gao wrote: Conditional add, if zero rd = (rc == 0) ? (rs1 + rs2) : rs1 --> czero.nez rd, rs2, rc add rd, rs1, rd Conditional add, if non-zero rd = (rc != 0) ? (rs1 + rs2) : rs1 --> czero.eqz rd, rs2, rc add rd, rs1, rd Co-authored-by: Xiao Zeng gcc/ChangeLog:

Re: [PATCH] RISC-V: Make rv32i_zcmp testcase more robust

On 10/30/23 10:37, Patrick O'Neill wrote: GCC recently changed its register allocator which causes this testcase to fail. This patch updates the regex to be more robust to change by accepting any s register in the range of 1-9 for cm.push and cm.popret insns. gcc/testsuite/ChangeLog:

Re: [PATCH 2/4] [ifcvt] if convert x=c ? y+z : y by RISC-V Zicond like insns

On 10/30/23 01:25, Fei Gao wrote: Conditional add, if zero rd = (rc == 0) ? (rs1 + rs2) : rs1 --> czero.nez rd, rs2, rc add rd, rs1, rd Conditional add, if non-zero rd = (rc != 0) ? (rs1 + rs2) : rs1 --> czero.eqz rd, rs2, rc add rd, rs1, rd Co-authored-by: Xiao Zeng gcc/ChangeLog:

Re: [PATCH 4/4] [ifcvt] if convert x=c ? y&z : y by RISC-V Zicond like insns

On 10/30/23 01:25, Fei Gao wrote: Conditional and, if zero rd = (rc == 0) ? (rs1 & rs2) : rs1 --> and rd, rs1, rs2 czero.eqz rtmp, rs1, rc or rd, rd, rtmp Conditional and, if non-zero rd = (rc != 0) ? (rs1 & rs2) : rs1 --> and rd, rs1, rs2 czero.nez rtmp, rs1, rc or rd, rd, rtmp Co-authored-

Re: [PATCH 2/4] [ifcvt] if convert x=c ? y+z : y by RISC-V Zicond like insns

On 10/30/23 01:25, Fei Gao wrote: Conditional add, if zero rd = (rc == 0) ? (rs1 + rs2) : rs1 --> czero.nez rd, rs2, rc add rd, rs1, rd Conditional add, if non-zero rd = (rc != 0) ? (rs1 + rs2) : rs1 --> czero.eqz rd, rs2, rc add rd, rs1, rd Co-authored-by: Xiao Zeng gcc/ChangeLog:

Re: [PATCH v3] RISC-V: elide unnecessary sign extend when expanding cmp_and_jump

On 10/29/23 21:21, Vineet Gupta wrote: RV64 compare and branch instructions only support 64-bit operands. At Expand time, the backend conservatively zero/sign extends its operands even if not needed, such as incoming 32-bit function args which ABI/ISA guarantee to be sign-extended already. An

Re: [RFC] RISC-V: Support -mcmodel=large.

On 10/25/23 19:49, KuanLin Chen wrote: This is a RFC patch for large code model implementation. gcc/ChangeLog: * gcc/config/riscv/predicates.md(move_operand): Check SYMBOL_REF and LABEL_REF type. (call_insn_operand): Support for CM_Large. (pcrel_symbol_operand): New. * gcc/config/riscv/riscv-

Re: [PATCH] genemit: Split insn-emit.cc into ten files.

On 10/27/23 13:04, Robin Dapp wrote: After working with Sam off-list (thanks) I managed to get hppa to build. Initially it looked as if hppa just had a very small number of instruction patterns so we wouldn't generate all 10 output files. However, the actual issue (which we will only hit with

Re: [PATCH 0/2] RISC-V: Define not broken prefetch builtins

dicates" in GCC. OK. So you might want to read the machine description part of the GCC manual. It describes operand predicates, operand constraints, insn conditions, the difference between define_insn vs define_expand and much more. On 2023/08/29 6:20, Jeff Law wrote: What I would

Re: [PATCH 1/4] RISC-V: Recategorize "prefetch" availabilities

On 10/23/23 01:22, Tsukasa OI wrote: From: Tsukasa OI Because they are for all prefetch instructions, "prefetch" fits better than "prefetchi". But there's a significant difference between the cases. prefetch.i in particular fetches into the icache. While prefetch.r and prefetch.w would

Re: [PATCH] RISC-V: Enable ztso tests on rv32

On 10/30/23 18:47, Patrick O'Neill wrote: This patch transitions the ztso testcases to use the testsuite infrastructure, enabling the tests on both rv64 and rv32 targets. gcc/testsuite/ChangeLog: * gcc.target/riscv/amo-table-ztso-amo-add-1.c: Add Ztso extension to dg-options

Re: [PATCH 1/2] RISC-V: Let non-atomic targets use optimized amo loads/stores

On 10/30/23 18:49, Patrick O'Neill wrote: Non-atomic targets are currently prevented from using the optimized fencing for seq_cst load/seq_cst store. This patch removes that constraint. gcc/ChangeLog: * config/riscv/sync-rvwmo.md (atomic_load_rvwmo): Remove TARGET_ATOMIC cons

Re: [PATCH 2/2] RISC-V: Require a extension for testcases with atomic insns

On 10/30/23 18:49, Patrick O'Neill wrote: Add testsuite infrastructure for the A extension and use it to require the A extension for dg-do run and add the add extension for non-A dg-do compile. gcc/testsuite/ChangeLog: * gcc.target/riscv/amo-table-a-6-amo-add-1.c: Add A extension to

Re: [PATCH] RISC-V: fix TARGET_PROMOTE_FUNCTION_MODE hook for libcalls

On 10/31/23 12:35, Vineet Gupta wrote: riscv_promote_function_mode doesn't promote a SI to DI for libcalls case. The fix is what generic promote_mode () in explow.cc does. I really don't understand why the old code didn't work, but stepping thru the debugger shows old code didn't and fixed do

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