Re: [PATCH] RISC-V: THead: Fix missing CFI directives for th.sdd in prologue.

* config/riscv/thead.cc (th_mempair_save_regs): Fix missing CFI > directives for store-pair instruction. > > gcc/testsuite/ > * gcc.target/riscv/xtheadmempair-4.c: New test. LGTM, I've also tested it. Reviewed-by: Christoph Müllner Tested-by: Christop

Re: xthead regression with [COMMITTED] RISC-V: const: hide mvconst splitter from IRA

On Mon, Oct 9, 2023 at 10:36 PM Vineet Gupta wrote: > > Hi Christoph, > > On 10/9/23 12:06, Patrick O'Neill wrote: > > > > Hi Vineet, > > > > We're seeing a regression on all riscv targets after this patch:| > > > > FAIL: gcc.target/riscv/xtheadcondmov-indirect.c -O2 > > check-function-bodies ConN

Re: xthead regression with [COMMITTED] RISC-V: const: hide mvconst splitter from IRA

On Mon, Oct 9, 2023 at 10:48 PM Vineet Gupta wrote: > > On 10/9/23 13:46, Christoph Müllner wrote: > > Given that this causes repeated issues, I think that a fall-back to > > counting occurrences is the right thing to do. I can do that if that's ok. > > Thanks Chr

Re: [PATCH] RISC-V: Make xtheadcondmov-indirect tests robust against instruction reordering

> > On Mon, Oct 9, 2023 at 3:47 PM Christoph Muellner > wrote: > > > > From: Christoph Müllner > > > > Fixes: c1bc7513b1d7 ("RISC-V: const: hide mvconst splitter from IRA") > > > > A recent change broke the xtheadcondmov-indirect tests, be

Re: [PATCH] riscv: thead: Fix failing XTheadCondMov tests (indirect-rv[32|64])

On Wed, Jul 12, 2023 at 4:05 AM Jeff Law wrote: > > > > On 7/10/23 22:44, Christoph Muellner wrote: > > From: Christoph Müllner > > > > Recently, two identical XTheadCondMov tests have been added, which both > > fail. > > Let's fix that by changing

Re: [gcc r14-2455] riscv: Prepare backend for index registers

On Fri, Jul 14, 2023 at 12:28 PM Andreas Schwab wrote: > > Why didn't you test that? Thanks for reporting, and sorry for introducing this warning. I test all patches before sending them. In the case of RISC-V backend patches, I build a 2-stage cross-toolchain and run all regression tests for RV3

Re: [gcc r14-2455] riscv: Prepare backend for index registers

On Mon, Jul 17, 2023 at 9:24 AM Andreas Schwab wrote: > > On Jul 17 2023, Christoph Müllner wrote: > > > The build process shows a lot of warnings. > > Then you are using a bad compiler. The build is 100% -Werror clean. My host compiler is: gcc version 13.1.1 20230614 (R

Re: [gcc r14-2455] riscv: Prepare backend for index registers

On Mon, Jul 17, 2023 at 9:31 AM Andrew Pinski wrote: > > On Sun, Jul 16, 2023 at 11:49 PM Christoph Müllner > wrote: > > > > On Fri, Jul 14, 2023 at 12:28 PM Andreas Schwab > > wrote: > > > > > > Why didn't you test that? > > > >

Re: [gcc r14-2455] riscv: Prepare backend for index registers

On Mon, Jul 17, 2023 at 9:44 AM Andreas Schwab wrote: > > On Jul 17 2023, Christoph Müllner wrote: > > > My host compiler is: gcc version 13.1.1 20230614 (Red Hat 13.1.1-4) (GCC) > > Too old. Ok understood. Thanks, Christoph > > -- > Andreas Schwab, sch...@linux-

Re: [PATCH 10/11] riscv: thead: Add support for the XTheadMemIdx ISA extension

On Sat, Jun 10, 2023 at 7:53 PM Jeff Law wrote: > > > > On 4/28/23 00:23, Christoph Muellner wrote: > > From: Christoph Müllner > > > > The XTheadMemIdx ISA extension provides a additional load and store > > instructions with new addressing modes. > > &

Re: [PATCH 11/11] riscv: thead: Add support for the XTheadFMemIdx ISA extension

On Sat, Jun 10, 2023 at 7:54 PM Jeff Law wrote: > > > > On 4/28/23 00:23, Christoph Muellner wrote: > > From: Christoph Müllner > > > > The XTheadFMemIdx ISA extension provides additional load and store > > instructions for floating-point registers wi

Re: [PATCH 10/11] riscv: thead: Add support for the XTheadMemIdx ISA extension

On Wed, Jun 28, 2023 at 8:23 PM Jeff Law wrote: > > > > On 6/28/23 06:39, Christoph Müllner wrote: > > >>> +;; XTheadMemIdx overview: > >>> +;; All peephole passes attempt to improve the operand utilization of > >>> +;; XTheadMemIdx instructions,

Re: [PATCH 10/11] riscv: thead: Add support for the XTheadMemIdx ISA extension

On Thu, Jun 29, 2023 at 4:09 PM Jeff Law wrote: > > > > On 6/29/23 01:39, Christoph Müllner wrote: > > On Wed, Jun 28, 2023 at 8:23 PM Jeff Law wrote: > >> > >> > >> > >> On 6/28/23 06:39, Christoph Müllner wrote: > >> > >>&

Re: [PATCH 1/1] riscv: thead: Fix ICE when enable XTheadMemPair ISA extension.

Hi Cooper, I addressed this in April this year. It even got an "ok", but nobody pushed it: https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616972.html BR Christoph On Tue, Jul 11, 2023 at 5:39 PM Xianmiao Qu wrote: > > The frame related load/store instructions should not been > scheduled

Re: [PATCH 1/1] riscv: thead: Fix ICE when enable XTheadMemPair ISA extension.

es tomorrow. > > On Tue, Jul 11, 2023 at 11:42 PM Christoph Müllner > wrote: > > > > Hi Cooper, > > > > I addressed this in April this year. > > It even got an "ok", but nobody pushed it: > > https://gcc.gnu.org/pipermail/gcc-patches/2023-Apri

Re: [PATCH v2 0/2] riscv: Adding support for XTHead(F)MemIdx

On Fri, Oct 20, 2023 at 4:33 PM Jeff Law wrote: > > > > On 10/20/23 03:53, Christoph Muellner wrote: > > From: Christoph Müllner > > > > This two patches add support for the XTheadMemIdx > > and XTheadFMemIdx ISA extensions, that support additional >

Re: [PATCH v2 1/2] riscv: thead: Add support for the XTheadMemIdx ISA extension

On Sun, Oct 29, 2023 at 10:44 PM Jeff Law wrote: > > > > On 10/20/23 03:53, Christoph Muellner wrote: > > From: Christoph Müllner > > > > The XTheadMemIdx ISA extension provides a additional load and store > > instructions with new addressing modes. > &g

Re: [PATCH v2 2/2] riscv: thead: Add support for the XTheadFMemIdx ISA extension

On Sun, Oct 29, 2023 at 11:25 PM Jeff Law wrote: > > > > On 10/20/23 03:53, Christoph Muellner wrote: > > From: Christoph Müllner > > > > The XTheadFMemIdx ISA extension provides additional load and store > > instructions for floating-point registers wi

Re: [RE] [7/7] riscv: Add basic extension support for XTheadFmv and XTheadInt

On Thu, Nov 2, 2023, 08:32 Jin Ma wrote: > Hi, I see that XTheadInt is not implemented in the compiler. Is there any > plan here? > If there is no patch for it, can I try to implement it with you? > Yes, sounds good. Let me know if you have any questions. We don't have any plans to work on this

Re: [PATCH v3 09/11] riscv: thead: Add support for the XTheadMemPair ISA extension

On Fri, Feb 24, 2023 at 10:01 AM Kito Cheng wrote: > > Got one fail: > > FAIL: gcc.target/riscv/xtheadmempair-1.c -O2 scan-assembler-times > th.luwd\t 4 > > It should scan lwud rather than luwd? Yes, this should be th.lwud. Must have been introduced after testing. I also ran the whole patchs

Re: [PATCH v3 03/11] riscv: thead: Add support for the XTheadBa ISA extension

sion will be preferred over the custom extension. > > On Fri, Feb 24, 2023 at 2:52 PM Andrew Pinski via Gcc-patches > wrote: > > > > On Thu, Feb 23, 2023 at 9:55 PM Christoph Muellner > > wrote: > > > > > > From: Christoph Müllner > > > >

Re: [PATCH v3 04/11] riscv: thead: Add support for the XTheadBs ISA extension

On Fri, Feb 24, 2023 at 8:37 AM Kito Cheng wrote: > > > diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md > > index 158e9124c3a..2c684885850 100644 > > --- a/gcc/config/riscv/thead.md > > +++ b/gcc/config/riscv/thead.md > > @@ -29,3 +29,14 @@ (define_insn "*th_addsl" > >"th.ad

Re: [PATCH v3 03/11] riscv: thead: Add support for the XTheadBa ISA extension

On Fri, Feb 24, 2023 at 11:05 AM Christoph Müllner wrote: > > On Fri, Feb 24, 2023 at 10:54 AM Kito Cheng wrote: > > > > My impression is that md patterns will use first-match patterns? so > > the zba will get higher priority than xtheadba if both patterns are > >

Re: [PATCH v3 00/11] RISC-V: Add XThead* extension support

ckends. Thanks, Christoph > > > > > On Fri, Feb 24, 2023 at 1:52 PM Christoph Muellner > wrote: > > > > From: Christoph Müllner > > > > This series introduces support for the T-Head specific RISC-V ISA extensions > > which are available e.g. on the T-Head Xuan

Re: [PATCH v3 04/11] riscv: thead: Add support for the XTheadBs ISA extension

On Sun, Feb 26, 2023 at 12:42 AM Hans-Peter Nilsson wrote: > > On Fri, 24 Feb 2023, Christoph Muellner wrote: > > diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md > > index 158e9124c3a..2c684885850 100644 > > --- a/gcc/config/riscv/thead.md > > +++ b/gcc/config/riscv/thead.md > >

Re: [PATCH v3 04/11] riscv: thead: Add support for the XTheadBs ISA extension

On Wed, Mar 1, 2023 at 1:19 AM Hans-Peter Nilsson wrote: > > > > On Tue, 28 Feb 2023, Christoph Müllner wrote: > > > On Sun, Feb 26, 2023 at 12:42 AM Hans-Peter Nilsson > > wrote: > > > > > > On Fri, 24 Feb 2023, Christoph Muellner wrote: > &g

Re: [PATCH] RISC-V: Add Zawrs ISA extension support

On Thu, Oct 27, 2022 at 8:11 PM Christoph Muellner < christoph.muell...@vrull.eu> wrote: > From: Christoph Muellner > > This patch adds support for the Zawrs ISA extension. > The patch depends on the corresponding Binutils patch > to be usable (see [1]) > > The specification can be found here: >

Re: [PATCH] RISC-V: Add Zawrs ISA extension support

On Thu, Oct 27, 2022 at 10:51 PM Palmer Dabbelt wrote: > On Thu, 27 Oct 2022 11:23:17 PDT (-0700), christoph.muell...@vrull.eu > wrote: > > On Thu, Oct 27, 2022 at 8:11 PM Christoph Muellner < > > christoph.muell...@vrull.eu> wrote: > > > >> From: Christoph Muellner > >> > >> This patch adds sup

Re: [PATCH] RISC-V: Add Zawrs ISA extension support

On Wed, Nov 2, 2022 at 3:38 PM Philipp Tomsich wrote: > > On Wed, 2 Nov 2022 at 15:21, Christoph Müllner > wrote: > > > > > > > > On Thu, Oct 27, 2022 at 10:51 PM Palmer Dabbelt wrote: > >> > >> On Thu, 27 Oct 2022 11:23:17 PDT (-0700), chr

Re: [PATCH 02/11] riscv: xtheadmempair: Fix CFA reg notes

On Fri, Apr 28, 2023 at 8:12 AM Christoph Muellner wrote: > > From: Christoph Müllner > > The current implementation triggers an assertion in > dwarf2out_frame_debug_cfa_offset() under certain circumstances. > The standard code uses REG_FRAME_RELATED_EXPR notes instead > of

[PATCH] RISC-V: Don't add fractional LMUL types to V_VLS for XTheadVector

` instructions instead of triggering an ICE. Signed-off-by: Christoph Müllner PR 114194 gcc/ChangeLog: * config/riscv/vector-iterators.md: Split VI into VI_FRAC and VI_NOFRAC. Only include VI_NOFRAC in V_VLS without TARGET_XTHEADVECTOR. gcc/testsuite/ChangeLog

Re: [PATCH] RISC-V: Don't add fractional LMUL types to V_VLS for XTheadVector

le tuning parameters, as my primary goal was to eliminate the reason for the ICE with XTheadVector. > > On Fri, Mar 22, 2024 at 12:46 PM Christoph Müllner > wrote: > > > > The expansion of `memset` (via expand_builtin_memset_args()) > > uses clear_by_pieces() and store_b

Re: [PATCH] RISC-V: Don't add fractional LMUL types to V_VLS for XTheadVector

On Fri, Mar 22, 2024 at 2:18 AM juzhe.zh...@rivai.ai wrote: > > LGTM. Pushed. Thanks! > > > juzhe.zh...@rivai.ai > > > From: Christoph Müllner > Date: 2024-03-22 07:45 > To: gcc-patches; Kito Cheng; Palmer Dabbelt; Andrew Water

Re: [PATCH v2] RISC-V: THEAD: Fix improper immediate value for MODIFY_DISP instruction on 32-bit systems.

On Sat, Feb 3, 2024 at 2:11 PM Andreas Schwab wrote: > > On Jan 30 2024, Christoph Müllner wrote: > > > retested > > Nope. Sorry for this. I tested for no regressions in the test suite with a cross-build and QEMU and did not do a Werror bootstrap build. I'll provide

Re: [PATCH v2] RISC-V: THEAD: Fix improper immediate value for MODIFY_DISP instruction on 32-bit systems.

On Mon, Feb 5, 2024 at 3:56 PM Jeff Law wrote: > > > > On 2/5/24 05:00, Christoph Müllner wrote: > > On Sat, Feb 3, 2024 at 2:11 PM Andreas Schwab > > wrote: > >> > >> On Jan 30 2024, Christoph Müllner wrote: > >> > >>> retested >

Re: [PATCH] RISC-V: Add new option -march=help to print all supported extensions

bility. If I remember correctly, then this feature was requested several times in the past. Thanks for working on this! Reviewed-by: Christoph Müllner I have done a quick feature test (no bootstrapping, no check for compiler warnings) as well. Below you find all supported RISC-V extension in toda

Re: [PATCH v2] RISC-V: T-HEAD: Add support for the XTheadInt ISA extension

On Tue, Jan 9, 2024 at 6:59 PM Jeff Law wrote: > > > > On 11/17/23 00:33, Jin Ma wrote: > > The XTheadInt ISA extension provides acceleration interruption > > instructions as defined in T-Head-specific: > > * th.ipush > > * th.ipop > > > > Ref: > > https://github.com/T-head-Semi/thead-extension-sp

Re: [PATCH] RISC-V: THEAD: Fix ICE caused by split optimizations for XTheadFMemIdx.

On Thu, Jan 11, 2024 at 4:36 PM Kito Cheng wrote: > > LGTM > > On Thu, Jan 11, 2024 at 7:23 PM Jin Ma wrote: > > > > Due to the premature split optimizations for XTheadFMemIdx, GPR > > is allocated when reload allocates registers, resulting in the > > following insn. LGTM. This was most likely n

Re: [PATCH v4 0/3] RISC-V: Add intrinsics for Bitmanip and Scalar Crypto extensions

On Mon, Jan 15, 2024 at 9:35 AM Liao Shihua wrote: > > Update v3 -> v4: > 1.Typo fix. > 2.Only test *intrinsic-32 on rv32 and *intrinsic-64 on rv64. > 3.Update Copyright year to 2024. Thanks, for fixing the rv32/rv64 issues! I've tested this series: no regressions and all new tests pass. I'

Re: [PATCH v4 0/3] RISC-V: Add intrinsics for Bitmanip and Scalar Crypto extensions

On Mon, Jan 15, 2024 at 4:35 PM Kito Cheng wrote: > > Ok :) I've re-created changelog entries in commit messages (commit hook rejected the commits) and pushed. Thanks, Christoph > > > Christoph Müllner 於 2024年1月15日 週一 23:17 寫道： >> >> On Mon, Jan 15, 20

Re: [PATCH v5] RISC-V: Support XTheadVector extension

rns in vector.md. > > We have run the GCC test suite and can confirm that there > are no regressions. > > Furthermore, we have run the tests in > https://github.com/riscv-non-isa/rvv-intrinsic-doc/tree/main/examples, > and all the tests passed. > > Co-authored-by: Jin Ma &g

Re: [PATCH v2] RISC-V: THEAD: Fix improper immediate value for MODIFY_DISP instruction on 32-bit systems.

On Mon, Jan 29, 2024 at 1:32 PM Kito Cheng wrote: > > LGTM I've rebased, retested (rv64+rv32) and merged this patch. Thanks! > > Jin Ma 於 2024年1月29日 週一 17:57 寫道： >> >> When using '%ld' to print 'long long int' variable, 'fprintf' will >> produce messy output on a 32-bit system, in an incorrec

[PATCH] riscv: Move UNSPEC_XTHEAD* from unspecv to unspec

patch we have again 0 fails in riscv.exp. gcc/ChangeLog: * config/riscv/riscv.md: Move UNSPEC_XTHEADFMV* to unspec enum. Signed-off-by: Christoph Müllner --- gcc/config/riscv/riscv.md | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/gcc/config/riscv/riscv.md

Re: [PR target/110201] Fix operand types for various scalar crypto insns

On Tue, Jun 20, 2023 at 12:34 AM Jeff Law via Gcc-patches wrote: > > > A handful of the scalar crypto instructions are supposed to take a > constant integer argument 0..3 inclusive. A suitable constraint was > created and used for this purpose (D03), but the operand's predicate is > "register_ope

Re: [PATCH] RISC-V: fix scalar crypto pattern

On Thu, Dec 14, 2023 at 1:40 AM Jeff Law wrote: > On 12/13/23 02:03, Christoph Müllner wrote: > > On Wed, Dec 13, 2023 at 9:22 AM Liao Shihua wrote: > >> > >> In Scalar Crypto Built-In functions, some require immediate parameters, > >> But register_operand

Re: [PR target/110201] Fix operand types for various scalar crypto insns

On Fri, Dec 15, 2023 at 12:36 AM Jeff Law wrote: > > > > On 12/14/23 02:46, Christoph Müllner wrote: > > On Tue, Jun 20, 2023 at 12:34 AM Jeff Law via Gcc-patches > > wrote: > >> > >> > >> A handful of the scalar crypto instructions are sup

Re: [PATCH v4] RISC-V: Change csr_operand into vector_length_operand for vsetvl patterns.

; > * config/riscv/vector.md: > Use vector_length_operand for vsetvl patterns. > > Co-authored-by: Jin Ma > Co-authored-by: Xianmiao Qu > Co-authored-by: Christoph Müllner > --- > gcc/config/riscv/vector.md | 8 > 1 file changed, 4 insertions(+), 4 deletions(

Re: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.

居哲; Jeff Law; gcc-patches > 抄送： jim.wilson.gcc; palmer; andrew; philipp.tomsich; Christoph Müllner; > jinma; Cooper Qu > 主题： Re：Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of > XTheadVector. > Hi Juzhe, > > So is the following patch that this pa

Re: [PATCH V3 0/3] RISC-V: Add intrinsics for Bitmanip and Scalar Crypto extensions

The tests still fail. gcc: Unexpected fails for rv64gc lp64d medlow FAIL: gcc.target/riscv/scalar_bitmanip_intrinsic-32.c -O0 (test for excess errors) FAIL: gcc.target/riscv/scalar_bitmanip_intrinsic-32.c -O1 (test for excess errors) FAIL: gcc.target/riscv/scalar_bitmanip_intrinsic-32.c -O

[PATCH] RISC-V: Document optimization parameter riscv-strcmp-inline-limit

This patch documents the optimization parameter riscv-strcmp-inline-limit, which can be used to tweak the behaviour of -minline-strcmp and -minline-strncmp. gcc/ChangeLog: PR target/112650 * doc/invoke.texi: Document riscv-strcmp-inline-limit. Signed-off-by: Christoph Müllner

Re: [PATCH] RISC-V: Check if zcd conflicts with zcmt and zcmp

On Mon, Dec 4, 2023 at 8:48 AM Kito Cheng wrote: LGTM I've double-checked this in the Zc-1.0.4-3.pdf: * Zcmp is incompatible with Zcd * Zcmp depends on Zca * Zcmt is incompatible with Zcd * Zcmt depends on Zca and Zicsr The implies-relations are already implemented. This patch enforces the inco

[PATCH v2] RISC-V: Document optimization parameter riscv-strcmp-inline-limit

This patch documents the optimization parameter riscv-strcmp-inline-limit, which can be used to tweak the behaviour of -minline-strcmp and -minline-strncmp. gcc/ChangeLog: PR target/112650 * doc/invoke.texi: Document riscv-strcmp-inline-limit. Signed-off-by: Christoph Müllner

Re: [PATCH] RISC-V: Document optimization parameter riscv-strcmp-inline-limit

> > LGTM > > > > On Sun, Dec 3, 2023 at 5:16 AM Christoph Müllner > > wrote: > >> > >> This patch documents the optimization parameter > >> riscv-strcmp-inline-limit, which can be used to tweak the behaviour > >> of -minline-strcmp and

Re: [PATCH 0/2] RISC-V: Add intrinsics for Bitmanip and Scalar Crypto extensions.

On Tue, Dec 5, 2023 at 1:05 PM Liao Shihua wrote: > > > It's a little patch add just provides a mapping from the RV intrinsic to the > builtin > names within GCC. Thanks for working on this! I checked with ./contrib/check_GNU_style, which found a two issues: * Trailing whitespace (most likely c

[PATCH] RISC-V: xtheadfmemidx: Disable if xtheadmemidx is not available

-xtheadmemidx.c: New test. Reported-by: Jin Ma Signed-off-by: Christoph Müllner --- gcc/config/riscv/thead.cc | 3 +- gcc/config/riscv/thead.md | 19 - .../xtheadfmemidx-without-xtheadmemidx.c | 39 +++ 3 files changed, 51 in

[PATCH] RISC-V: xtheadmemidx: Document inline asm issue with memory constraint

ment this behavior for now as a known issue by adding xfail tests until we have an acceptable fix. gcc/testsuite/ChangeLog: * gcc.target/riscv/xtheadmemidx-inline-asm-1.c: New test. Reported-by: Jin Ma Signed-off-by: Christoph Müllner --- .../riscv/xtheadmemidx-inline-asm-1.c |

Re: [PATCH V2 0/2] RISC-V: Add intrinsics for Bitmanip and Scalar Crypto extensions

On Thu, Dec 7, 2023 at 11:18 AM Liao Shihua wrote: > > In accordance with the suggestions of Christoph Müllner, the following > amendments are made > > Update v1 -> v2: > 1. Rename *_intrinsic-* to *_intrinsic-XLEN. > 2. Typo fix. > 3. Intrinsics with immediate a

Re: [PATCH v2] RISC-V: Supports RISC-V Profiles in '-march' option.

On Tue, Dec 12, 2023 at 1:08 PM Jiawei wrote: > > Supports RISC-V profiles[1] in -march option. > > Default input set the profile is before other formal extensions. > > V2: Fixes some format errors and adds code comments for parse function > Thanks for Jeff Law's review and comments. > > [1]https:

Re: [PATCH] RISC-V: fix scalar crypto pattern

On Wed, Dec 13, 2023 at 9:22 AM Liao Shihua wrote: > > In Scalar Crypto Built-In functions, some require immediate parameters, > But register_operand are incorrectly used in the pattern. > > E.g.: >__builtin_riscv_aes64ks1i(rs1,1) >Before: > li a5,1 > aes64ks1i a0,a0,a5 > >

Re: [PATCH v2 02/11] riscv: Restructure callee-saved register save/restore code

regno, unsigned > int limit, > >if (inc) > > regno++; > > > > - while (regno <= limit) > > + while (regno <= limit && regno != INVALID_REGNUM) > > { > >if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_F

Re: [PATCH v2 02/11] riscv: Restructure callee-saved register save/restore code

at 9:08 AM Christoph Muellner > wrote: > > > > From: Christoph Müllner > > > > This patch restructures the loop over the GP registers > > which saves/restores then as part of the prologue/epilogue. > > No functional change is intended by this patch, but it >

Re: [PATCH] RISC-V: Add ABI requirement for XTheadFMemIdx tests

> > On Tue, Nov 7, 2023 at 3:44 AM Christoph Muellner > wrote: > > > > From: Christoph Müllner > > > > The XTheadFMemIdx tests set the required ABI for RV32, but not > > for RV64, which has the effect that the tests are expected to > > succeed for RV6

Re: [PATCH] RISC-V: Use stdint-gcc.h in rvv testsuite

2023年11月7日 週二 17:45 寫道： >> >> From: Christoph Müllner >> >> stdint.h can be replaced with stdint-gcc.h to resolve some missing >> system headers in non-multilib installations. >> >> gcc/testsuite/ChangeLog: >> >> * gcc.targe

Re: [PATCH] minimal support for xtheadv

On Thu, Nov 9, 2023 at 8:39 AM Kito Cheng wrote: > > Hi Yi Xuan: > > This patch is trivial, and generally LGTM, but I would require putting > the spec into https://github.com/riscv-non-isa/riscv-toolchain-conventions > before merging this, also don't forget include "RISC-V:" in the title, > it wou

Re: [PATCH] RISC-V: Fix the illegal operands for the XTheadMemidx extension.

On Thu, Nov 9, 2023 at 8:40 AM Jin Ma wrote: > > The pattern "*extend2_bitmanip" and > "*zero_extendhi2_bitmanip" in bitmanip.md are similar > to the pattern "*th_memidx_bb_extendqi2" and > "*th_memidx_bb_zero_extendhi2" in thead.md, which will > cause the wrong instruction to be generated and rep

Re: [PATCH] RISC-V: Fix bug that XTheadMemPair extension caused fcsr not to be saved and restored before and after interrupt.

hey need to > exchange positions in the function "riscv_for_each_saved_reg". RISCV_PROLOGUE_TEMP_REGNUM needs indeed to be treated special in case of ISRs and fcsr. This patch just moves the TARGET_XTHEADMEMPAIR block after the ISR/fcsr block. Reviewed-by: Christoph Müllner > >

Re: [PATCH] RISC-V: Fix bug that XTheadMemPair extension caused fcsr not to be saved and restored before and after interrupt.

On Fri, Nov 10, 2023 at 2:20 PM Kito Cheng wrote: > > LGTM Committed after shortening the commit message's heading. > > Christoph Müllner 於 2023年11月10日 週五，20:55寫道： >> >> On Fri, Nov 10, 2023 at 8:14 AM Jin Ma wrote: >> > >> > The t0 register is

Re: [PATCH] riscv: thead: Add support for the XTheadInt ISA extension

On Tue, Nov 7, 2023 at 4:04 AM Jin Ma wrote: > > The XTheadInt ISA extension provides acceleration interruption > instructions as defined in T-Head-specific: > > * th.ipush > * th.ipop Overall, it looks ok to me. There are just a few small issues to clean up (see below). > > gcc/ChangeLog: > >

Re: [PATCH] RISC-V: Save/restore ra register correctly [PR112478]

irst test (not global reg, not used_or_fixed, and ever_live_p). After this commit, this does not happen anymore, because the test for not used_or_fixed fails and we don't test for ever_live_p in the following. And this patch restores this behavior. Reviewed-by: Christoph Müllner Tested-by: Chr

Re: [PATCH v2] RISC-V: Implement target attribute

nique_ptr rather than alloca to prevent memory issue. > - Error rather than warning when attribute duplicated. > > [1] https://github.com/riscv-non-isa/riscv-c-api-doc/pull/35 I've reviewed with a focus on the utilized backend hooks and macros. Reviewed-by: Christoph Müllner Note,

Re: RISC-V: Support XTheadVector extensions

On Fri, Nov 17, 2023 at 12:40 PM juzhe.zh...@rivai.ai wrote: > > 90% theadvector extension reusing current RVV 1.0 instructions patterns: > Just change ASM, For example: > > @@ -2923,7 +2923,7 @@ (define_insn "*pred_mulh_scalar" > (match_operand:VFULLI_D 3 "register_operand" "vr,vr, vr, vr"

Re: RISC-V: Support XTheadVector extensions

Hi Juzhe, Sorry for the late reply, but I was not on CC, so I missed this email. On Fri, Nov 17, 2023 at 2:41 PM juzhe.zh...@rivai.ai wrote: > > Ok. I just read the theadvector extension. > > https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadvector.adoc > > Theadvector is not

Re: Re: RISC-V: Support XTheadVector extensions

.". I know that it is not likely to run into this problem (such a machine does not exist in real hardware), but it is possible to trigger this issue easily and approach 1) would not have this potential issue. Thanks, Christoph > > Thanks. > > ____ &g

Re: RISC-V: Support XTheadVector extensions

ith an additional patch on top, which implements the ASM_OUTPUT_OPCODE hook (with a comment that clarifies why "ptr[0] == 'v'" is sufficient there). So the decision about this can be postponed and we can focus on the rest of the patchset as Jeff suggested. Thanks for the inputs!

Re: [PATCH] Add C intrinsics for scalar crypto extension

On Mon, Nov 27, 2023 at 9:36 AM Liao Shihua wrote: > > This patch add C intrinsics for scalar crypto extension. > Because of riscv-c-api > (https://github.com/riscv-non-isa/riscv-c-api-doc/pull/44/files) includes > zbkb/zbkc/zbkx's > intrinsics in bit manipulation extension, this patch only supp

Re: [PATCH] Add C intrinsics for scalar crypto extension

On Wed, Nov 29, 2023 at 5:49 PM Liao Shihua wrote: > > > 在 2023/11/29 23:03, Christoph Müllner 写道: > > On Mon, Nov 27, 2023 at 9:36 AM Liao Shihua wrote: > > This patch add C intrinsics for scalar crypto extension. > Because of riscv-c-api > (https://github.com/ri

Re: [RFC PATCH] RISC-V: Remove f{r,s}flags builtins

sing > -freport-bug). > Please include the complete backtrace with any bug report. > See <https://gcc.gnu.org/bugs/> for instructions. > compiler exited with status 1 > FAIL: gcc.dg/c11-atomic-2.c (internal compiler error: Segmentation fault) > > Let me know if you need a

[PATCH 1/6] RISC-V: testsuite: Properly gate LTO tests

aligned.c: Remove "-fno-fat-lto-objects" from skip condition. * gcc.target/riscv/pr93202.c: Likewise. Signed-off-by: Christoph Müllner --- gcc/testsuite/gcc.target/riscv/interrupt-misaligned.c | 2 +- gcc/testsuite/gcc.target/riscv/pr93202.c | 2 +- 2 files

[PATCH 2/6] RISC-V: Deduplicate arch subset list processing

tring): Replace duplicated code by a call to riscv_set_arch_by_subset_list. Signed-off-by: Christoph Müllner --- gcc/common/config/riscv/riscv-common.cc | 32 + 1 file changed, 6 insertions(+), 26 deletions(-) diff --git a/gcc/common/config/riscv/riscv-common.cc

[PATCH 0/6] RISC-V: Rewrite target arch attribute handling

while analysing a build issue with a patchset to introduce optimized string processing routines for RISC-V in glibc. See also: https://sourceware.org/pipermail/libc-alpha/2024-June/157627.html Christoph Müllner (6): RISC-V: testsuite: Properly gate LTO tests RISC-V: Deduplicate arch subset list proce

[PATCH 4/6] RISC-V: Fix comment/naming in attribute parsing code

ff-by: Christoph Müllner --- gcc/config/riscv/riscv-target-attr.cc | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/gcc/config/riscv/riscv-target-attr.cc b/gcc/config/riscv/riscv-target-attr.cc index e59cc53f23c6..3d7753f64574 100644 --- a/gcc/config/riscv/riscv-target-attr.cc

[PATCH 3/6] RISC-V: Attribute parser: Use alloca() instead of new + std::unique_ptr

: * config/riscv/riscv-target-attr.cc (riscv_target_attr_parser::parse_arch): Replace new + std::unique_ptr by alloca(). (riscv_process_one_target_attr): Likewise. (riscv_process_target_attr): Likewise. Signed-off-by: Christoph Müllner --- gcc/config/riscv/riscv-target

[PATCH 5/6] RISC-V: Rewrite target attribute handling

: New test. * gcc.target/riscv/target-attr-13.c: New test. * gcc.target/riscv/target-attr-14.c: New test. * gcc.target/riscv/target-attr-15.c: New test. Signed-off-by: Christoph Müllner --- gcc/common/config/riscv/riscv-common.cc | 113 +- gcc/con

[PATCH 6/6] RISC-V: Allow adding enabled extension via target arch attributes

riscv-target-attr.cc (riscv_target_attr_parser::parse_arch): Allow adding enabled extensions. gcc/testsuite/ChangeLog: * gcc.target/riscv/pr115554.c: Change expected fail to expected pass. * gcc.target/riscv/target-attr-16.c: New test. Signed-off-by: Christoph Müllner --- gcc/commo

Re: [PATCH 3/6] RISC-V: Attribute parser: Use alloca() instead of new + std::unique_ptr

64: https://gcc.gnu.org/git/?p=gcc.git;a=blob;f=gcc/config/aarch64/aarch64.cc;h=7f0cc47d0f071de9297068baa85c6d5fc4d7fa5b;hb=HEAD#l19408 So, my assumption was that it should be fine for RISC-V as well. However, I won't insist on this patch. > > On Tue, Jul 9, 2024 at 8:48 PM Christ

Re: [PATCH 5/6] RISC-V: Rewrite target attribute handling

On Tue, Jul 9, 2024 at 8:50 PM Christoph Müllner > wrote: > > > > The target-arch attribute handling in RISC-V is only a few months old, > > but already saw a rewrite (9941f0295a14), which addressed an important > > issue. This rewrite introduced a hash table in the back

Re: [PATCH 5/6] RISC-V: Rewrite target attribute handling

On Tue, Jul 16, 2024 at 4:45 AM Kito Cheng wrote: > > On Tue, Jul 16, 2024 at 1:09 AM Christoph Müllner > wrote: > > > > On Mon, Jul 15, 2024 at 11:10 AM Kito Cheng wrote: > > > > > > LGTM, and could you backport this to the GCC 14 branch as well? > &g

[committed][GCC-14] RISC-V: testsuite: Properly gate LTO tests

isaligned.c: Remove "-fno-fat-lto-objects" from skip condition. * gcc.target/riscv/pr93202.c: Likewise. (cherry picked from commit 0717d50fc4ff983b79093bdef43b04e4584cc3cd) Signed-off-by: Christoph Müllner --- gcc/testsuite/gcc.target/riscv/interrupt-misaligned.c | 2 +-

[committed][GCC-14] RISC-V: Fix comment/naming in attribute parsing code

from commit 5ef0b7d2048a7142174ee3e8e021fc1a9c3e3334) Signed-off-by: Christoph Müllner --- gcc/config/riscv/riscv-target-attr.cc | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/gcc/config/riscv/riscv-target-attr.cc b/gcc/config/riscv/riscv-target-attr.cc index 19eb7b

[committed][GCC-14] RISC-V: Allow adding enabled extension via target arch attributes

d1a3fd6341a4) Signed-off-by: Christoph Müllner --- gcc/common/config/riscv/riscv-common.cc | 17 +++ gcc/config/riscv/riscv-subset.h | 5 gcc/config/riscv/riscv-target-attr.cc | 3 ++ gcc/testsuite/gcc.target/riscv/pr115554.c | 2 -- .../gcc.target/

[committed][GCC-14] RISC-V: Deduplicate arch subset list processing

tring): Replace duplicated code by a call to riscv_set_arch_by_subset_list. (cherry picked from commit 85fa334fbcaa8e4b98ab197a8c9410dde87f0ae3) Signed-off-by: Christoph Müllner --- gcc/common/config/riscv/riscv-common.cc | 32 + 1 file changed, 6 insertions(+

[committed][GCC-14] RISC-V: Rewrite target attribute handling

* gcc.target/riscv/target-attr-12.c: New test. * gcc.target/riscv/target-attr-13.c: New test. * gcc.target/riscv/target-attr-14.c: New test. * gcc.target/riscv/target-attr-15.c: New test. (cherry picked from commit aa8e2de78cae4dca7f9b0efe0685f3382f9ecb9a) Signed-off-by: Christoph Müllner ---

Re: [PATCH] RISC-V: Fix testcase missing arch attribute

gt; Signed-off-by: Edwin Lu > --- > gcc/testsuite/gcc.target/riscv/target-attr-16.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Christoph Müllner In my defense, I tested the following combinations: = Summary of gcc testsuite =

Re: [PATCH 1/2] RISC-V: Add tests for cpymemsi expansion

s might be the issue? Thanks, Christoph > > Thanks, > > Patrick > > On 5/7/24 22:52, Christoph Müllner wrote: > > cpymemsi expansion was available for RISC-V since the initial port. > > However, there are not tests to detect regression. > > This patch adds suc

[PATCH] RISC-V: Fix cbo.zero expansion for rv32

-string.cc (riscv_expand_block_clear_zicboz_zic64b): Fix expansion for rv32. gcc/testsuite/ChangeLog: * gcc.target/riscv/cmo-zicboz-zic64-1.c: Fix for rv32. Signed-off-by: Christoph Müllner --- gcc/config/riscv/riscv-string.cc | 5 ++- .../gcc.target/riscv/cmo-zicboz-zic64-1.

[PATCH v2 2/2] RISC-V: strcmp expansion: Use adjust_address() for address calculation

ttern. Signed-off-by: Christoph Müllner --- gcc/config/riscv/riscv-string.cc | 10 -- 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/gcc/config/riscv/riscv-string.cc b/gcc/config/riscv/riscv-string.cc index a4c7f27d904..488e781aea3 100644 --- a/gcc/config/riscv/riscv-string.cc

[PATCH v2 1/2] RISC-V: Add cmpmemsi expansion

msi): New cmpmem expansion. gcc/testsuite/ChangeLog: * gcc.target/riscv/cmpmemsi-1.c: New test. * gcc.target/riscv/cmpmemsi-2.c: New test. * gcc.target/riscv/cmpmemsi-3.c: New test. * gcc.target/riscv/cmpmemsi.c: New test. Signed-off-by: Christoph Müllner ---

Re: [PATCH 2/2] RISC-V: Add cmpmemsi expansion

On Thu, May 9, 2024 at 4:50 PM Jeff Law wrote: > > > > On 5/7/24 11:52 PM, Christoph Müllner wrote: > > GCC has a generic cmpmemsi expansion via the by-pieces framework, > > which shows some room for target-specific optimizations. > > E.g. for comparing two ali

Re: [PATCH] RISC-V: Fix cbo.zero expansion for rv32

On Wed, May 15, 2024 at 9:14 AM Kito Cheng wrote: > > LGTM :) Jeff already committed a fix before, which also disables the test for rv32. I'll send up a follow-up patch to enable the test for rv32. > > On Wed, May 15, 2024 at 2:48 PM Christoph Müllner > wrote: > >

[PATCH] RISC-V: Test cbo.zero expansion for rv32

We had an issue when expanding via cmo-zero for RV32. This was fixed upstream, but we don't have a RV32 test. Therefore, this patch introduces such a test. gcc/testsuite/ChangeLog: * gcc.target/riscv/cmo-zicboz-zic64-1.c: Fix for rv32. Signed-off-by: Christoph Mü

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