On Tue, Jan 2, 2024 at 2:35 AM juzhe.zh...@rivai.ai <juzhe.zh...@rivai.ai> wrote: > > LGTM assume you have passed the regression.
Committed. I've rebased this patch, validated that there are no regressions with the patch, and reworded the commit message a bit before that. > > > ________________________________ > juzhe.zh...@rivai.ai > > > From: Jun Sha (Joshua) > Date: 2023-12-29 12:10 > To: gcc-patches > CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw; > christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu > Subject: [PATCH v4] RISC-V: Change csr_operand into vector_length_operand for > vsetvl patterns. > This patch use vector_length_operand instead of csr_operand for > vsetvl patterns, so that changes for vector will not affect scalar > patterns using csr_operand in riscv.md. > > gcc/ChangeLog: > > * config/riscv/vector.md: > Use vector_length_operand for vsetvl patterns. > > Co-authored-by: Jin Ma <ji...@linux.alibaba.com> > Co-authored-by: Xianmiao Qu <cooper...@linux.alibaba.com> > Co-authored-by: Christoph Müllner <christoph.muell...@vrull.eu> > --- > gcc/config/riscv/vector.md | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md > index f607d768b26..b5a9055cdc4 100644 > --- a/gcc/config/riscv/vector.md > +++ b/gcc/config/riscv/vector.md > @@ -1496,7 +1496,7 @@ > (define_insn "@vsetvl<mode>" > [(set (match_operand:P 0 "register_operand" "=r") > - (unspec:P [(match_operand:P 1 "csr_operand" "rK") > + (unspec:P [(match_operand:P 1 "vector_length_operand" "rK") > (match_operand 2 "const_int_operand" "i") > (match_operand 3 "const_int_operand" "i") > (match_operand 4 "const_int_operand" "i") > @@ -1542,7 +1542,7 @@ > ;; in vsetvl instruction pattern. > (define_insn "@vsetvl_discard_result<mode>" > [(set (reg:SI VL_REGNUM) > - (unspec:SI [(match_operand:P 0 "csr_operand" "rK") > + (unspec:SI [(match_operand:P 0 "vector_length_operand" "rK") > (match_operand 1 "const_int_operand" "i") > (match_operand 2 "const_int_operand" "i")] UNSPEC_VSETVL)) > (set (reg:SI VTYPE_REGNUM) > @@ -1564,7 +1564,7 @@ > ;; such pattern can allow us gain benefits of these optimizations. > (define_insn_and_split "@vsetvl<mode>_no_side_effects" > [(set (match_operand:P 0 "register_operand" "=r") > - (unspec:P [(match_operand:P 1 "csr_operand" "rK") > + (unspec:P [(match_operand:P 1 "vector_length_operand" "rK") > (match_operand 2 "const_int_operand" "i") > (match_operand 3 "const_int_operand" "i") > (match_operand 4 "const_int_operand" "i") > @@ -1608,7 +1608,7 @@ > [(set (match_operand:DI 0 "register_operand") > (sign_extend:DI > (subreg:SI > - (unspec:DI [(match_operand:P 1 "csr_operand") > + (unspec:DI [(match_operand:P 1 "vector_length_operand") > (match_operand 2 "const_int_operand") > (match_operand 3 "const_int_operand") > (match_operand 4 "const_int_operand") > -- > 2.17.1 > >
