On Fri, Feb 24, 2023 at 8:37 AM Kito Cheng <kito.ch...@sifive.com> wrote: > > > diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md > > index 158e9124c3a..2c684885850 100644 > > --- a/gcc/config/riscv/thead.md > > +++ b/gcc/config/riscv/thead.md > > @@ -29,3 +29,14 @@ (define_insn "*th_addsl" > > "th.addsl\t%0,%3,%1,%2" > > [(set_attr "type" "bitmanip") > > (set_attr "mode" "<X:MODE>")]) > > + > > +;; XTheadBs > > + > > +(define_insn "*th_tst" > > + [(set (match_operand:X 0 "register_operand" "=r") > > + (zero_extract:X (match_operand:X 1 "register_operand" "r") > > + (const_int 1) > > + (match_operand 2 "immediate_operand" "i")))] > > + "TARGET_XTHEADBS" > > Add range check like *bexti pattern? > > TARGET_XTHEADBS && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)
Ok. Thanks, Christoph > > > + "th.tst\t%0,%1,%2" > > + [(set_attr "type" "bitmanip")])
