On Wed, Jul 17, 2024 at 3:15 AM Edwin Lu <e...@rivosinc.com> wrote:
>
> The C + F extentions implies the zcf extension on rv32. Add missing zcf
> extension for the rv32 target.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/target-attr-16.c: Update expected assembly
>
> Signed-off-by: Edwin Lu <e...@rivosinc.com>
> ---
> gcc/testsuite/gcc.target/riscv/target-attr-16.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Christoph Müllner <christoph.muell...@vrull.eu>
In my defense, I tested the following combinations:
========= Summary of gcc testsuite =========
| # of unexpected case / # of unique unexpected case
| gcc | g++ | gfortran |
rv32imac/ ilp32/ medlow | 33 / 8 | 0 / 0 | 0 / 0 |
rv32imafdc/ ilp32d/ medlow | 33 / 8 | 0 / 0 | 0 / 0 |
rv64imac/ lp64/ medlow | 25 / 8 | 0 / 0 | 0 / 0 |
rv64imafdc/ lp64d/ medlow | 25 / 8 | 0 / 0 | 0 / 0 |
But it seems I missed looking into the details of the failing rv32 tests, where
reg_subreg_costs.c does not fail, but target-attr-16.c does.
FWIW, GCC-14 is not affected.
> diff --git a/gcc/testsuite/gcc.target/riscv/target-attr-16.c
> b/gcc/testsuite/gcc.target/riscv/target-attr-16.c
> index 1c7badccdee..c6b626d0c6c 100644
> --- a/gcc/testsuite/gcc.target/riscv/target-attr-16.c
> +++ b/gcc/testsuite/gcc.target/riscv/target-attr-16.c
> @@ -24,5 +24,5 @@ void bar (void)
> {
> }
>
> -/* { dg-final { scan-assembler-times ".option arch,
> rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0_zbb1p0"
> 4 { target { rv32 } } } } */
> +/* { dg-final { scan-assembler-times ".option arch,
> rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0_zba1p0_zbb1p0"
> 4 { target { rv32 } } } } */
> /* { dg-final { scan-assembler-times ".option arch,
> rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0_zbb1p0"
> 4 { target { rv64 } } } } */
> --
> 2.34.1
>
