Hi Mike,
As discussed on irc, I'm applying the following as obvious to fix a
bug in the vsx fusion peepholes. The bug is simply that the peepholes
are enabled when -mno-vsx, which leads to replacing RTL that would
emit lvx insns with RTL that emits lxvw4x or lxvd2x. This is clearly
wrong, and wor
On Mon, Jul 29, 2013 at 2:39 PM, Michael Meissner
wrote:
> This is the revised version of my patch #8 for power8 support. I have removed
> all of the incidental changes, and only added the support for load fusion. I
> have added support for fusion on 32-bit Linux. I have added a test to make
>
This is the revised version of my patch #8 for power8 support. I have removed
all of the incidental changes, and only added the support for load fusion. I
have added support for fusion on 32-bit Linux. I have added a test to make
sure the fusion ops are being generated.
I have built a compiler
On Mon, Jul 15, 2013 at 5:43 PM, Michael Meissner
wrote:
> Are these patches ok to install?
>
> 2013-07-15 Michael Meissner
>
> * config/rs6000/vector.md (xor3): Move 128-bit boolean
> expanders to rs6000.md.
> (ior3): Likewise.
> (and3): Likewise.
> (on
On Thu, Jun 06, 2013 at 11:57:01AM -0400, David Edelsohn wrote:
> But I view this as a preliminary step. The logical instructions need
> an iterator and TImode needs to be cleaned up on 32 bit.
>
> Thanks, David
Here is my proposed cleanup of the logical support. It adds DI expanders,
which on
On Mon, Jun 24, 2013 at 12:31 PM, Michael Meissner
wrote:
>> This really should have been a separate patch.
>
> Yes, you are right. I can separate it to be a separate patch if desired. The
> last I checked, there were still problems in moving to use LRA. It would be
> nice if we could get the
On Tue, Jun 18, 2013 at 02:30:49PM -0400, David Edelsohn wrote:
> On Wed, May 22, 2013 at 4:52 PM, Michael Meissner
> wrote:
>
> > 2013-05-22 Michael Meissner
> >
> > * config/rs6000/predicates.md (fusion_gpr_addis): New predicates
> > to support power8 load fusion.
> >
On Fri, Jun 7, 2013 at 3:22 PM, Pat Haugen wrote:
> This patch adds instruction scheduling support for the Power8 processor.
> Bootstrap/regression test with no new failures. Ok for trunk?
>
>
> 2013-06-07 Michael Meissner
> Pat Haugen
> Peter Bergner
>
> * config/rs6000/p
On Wed, May 22, 2013 at 4:52 PM, Michael Meissner
wrote:
> 2013-05-22 Michael Meissner
>
> * config/rs6000/predicates.md (fusion_gpr_addis): New predicates
> to support power8 load fusion.
> (fusion_gpr_mem_load): Likewise.
>
> * config/rs6000/rs6000-modes.def (
On Tue, Jun 11, 2013 at 7:53 PM, Michael Meissner
wrote:
> I needed to rework the sync.md so that it would work correctly with no
> optimization (using SUBREG's at -O0 did not give us the even registers for
> holding PTImode values, so I created a PTImode temporary in load_lockedti and
> store_con
I needed to rework the sync.md so that it would work correctly with no
optimization (using SUBREG's at -O0 did not give us the even registers for
holding PTImode values, so I created a PTImode temporary in load_lockedti and
store_conditionalti, which is normally optimized out.
[gcc]
2013-06-11 Mi
On Mon, Jun 10, 2013 at 11:41:20AM -0400, David Edelsohn wrote:
> Mike,
>
> This patch is okay, but something seems really broken with respect to
> TImode. I don't know if we have to separate TImode from V1TImode or
> some distinction for atomics from other uses of TImode. This isn't
> like floa
Mike,
This patch is okay, but something seems really broken with respect to
TImode. I don't know if we have to separate TImode from V1TImode or
some distinction for atomics from other uses of TImode. This isn't
like float modes where they mostly live in FPRs and only occassionally
need to live i
This patch adds instruction scheduling support for the Power8 processor.
Bootstrap/regression test with no new failures. Ok for trunk?
2013-06-07 Michael Meissner
Pat Haugen
Peter Bergner
* config/rs6000/power8.md: New.
* config/rs6000/rs6000-cpus.def (RS6000_CPU t
I checked in the tests that went with power8 patches #3 and #4 (which have been
committed) as subversion id 199768.
2013-06-06 Michael Meissner
Pat Haugen
Peter Bergner
* gcc.target/powerpc/p8vector-builtin-1.c: New test to test
power8 builtin function
On Wed, Jun 5, 2013 at 12:13 PM, Michael Meissner
wrote:
> On Wed, Jun 05, 2013 at 10:28:02AM -0400, David Edelsohn wrote:
>> +;; The canonical form is to have the negated elment first, so we need to
>> +;; reverse arguments.
>>
>> Please fix the typo in the comment: "element".
>
> Ok. I need to
On Wed, Jun 05, 2013 at 10:06:08PM +0200, Segher Boessenkool wrote:
> >I also wonder whether it would be useful to have 32-bit do the
> >vector logical
> >ops in gprs as well. At the moment, the patches don't allow it
> >(vector types
> >must be done in the altivec/vsx registers, an TImode is done
I also wonder whether it would be useful to have 32-bit do the
vector logical
ops in gprs as well. At the moment, the patches don't allow it
(vector types
must be done in the altivec/vsx registers, an TImode is done by
splitting the
operation into 4 separate categories). On the 64-bit side,
On Wed, Jun 5, 2013 at 12:13 PM, Michael Meissner
wrote:
> I thought I had deleted VSX_M2 from this patch. It will be needed in patch #8
> for the fusion peephole. The difference is VSX_L2 avoids TImode altogether,
> and was used by the logical ops to prevent TImode operations in VSX registers
On Wed, Jun 05, 2013 at 10:28:02AM -0400, David Edelsohn wrote:
> +;; The canonical form is to have the negated elment first, so we need to
> +;; reverse arguments.
>
> Please fix the typo in the comment: "element".
Ok. I need to proof-read the patches before sending them out.
> +;; Like VSX_L,
On Wed, Jun 05, 2013 at 05:50:21PM +0200, Segher Boessenkool wrote:
> >* config/rs6000/rs6000.md (eqv3): Add support for powerp eqv
> >instruction.
>
> [Typo, "powerp". There are many more typos and non-grammatical
> sentences.]
>
> >Why isn't this covered by boolean_operator and %q output opera
* config/rs6000/rs6000.md (eqv3): Add support for powerp eqv
instruction.
[Typo, "powerp". There are many more typos and non-grammatical
sentences.]
Why isn't this covered by boolean_operator and %q output operand?
The existing patterns (boolc3_...) do for eqv:
(set reg (xor (not
On Tue, Jun 4, 2013 at 2:48 PM, Michael Meissner
wrote:
> I revised this patch for power8 to add new miscellaneous vector instructions
> to
> not turn off splitting wide moves. In doing the patch, I discovered that we
> never supported the 'eqv' instruction, and I have added support for eqv in t
On Fri, May 31, 2013 at 11:10:54AM +0200, Segher Boessenkool wrote:
> >Ok, I tracked down what the problem is. We never implemented the
> >EQV, ORC, or
> >NAND insns in the GPRs. When I added the power8 vector versions,
> >the split
> >wide types pass tried to do its thing in the GPRs, it creates
Ok, I tracked down what the problem is. We never implemented the
EQV, ORC, or
NAND insns in the GPRs. When I added the power8 vector versions,
the split
wide types pass tried to do its thing in the GPRs, it creates a bad
insn. I
originally saw it in the atomic ops, because I was testing al
On Sat, May 25, 2013 at 12:03:51AM -0400, David Edelsohn wrote:
> On Tue, May 21, 2013 at 7:47 PM, Michael Meissner
> wrote:
>
>
> > * config/rs6000/rs6000.c (rs6000_option_override_internal): Only
> > allow power8 quad mode in 64-bit. Turn off splitting wide types
> > i
On Sat, May 25, 2013 at 12:07:32AM -0400, David Edelsohn wrote:
> [gcc/testsuite]
> 2013-05-20 Michael Meissner
>
> * gcc.target/powerpc/crypto-builtin-1.c: New file, test for power8
> crypto builtins.
>
> The testcase needs to check something more than
>
> /* { dg-require-eff
On Wed, May 29, 2013 at 04:29:07PM -0400, David Edelsohn wrote:
> - if (mode == QImode || mode == HImode)
> + /* On power8, we want to use SImode for the operation. On previoius
> systems,
> + use the operation in a subword and shift/mask to get the proper byte or
> + halfword. */
> +
On Wed, May 29, 2013 at 03:53:43PM -0400, David Edelsohn wrote:
> + if (TARGET_DIRECT_MOVE)
> +{
> + if (TARGET_POWERPC64)
> +{
> + reload_gpr_vsx[TImode]= CODE_FOR_reload_gpr_from_vsxti;
> + reload_gpr_vsx[V2DFmode] = CODE_FOR_reload_gpr_from_vs
- if (mode == QImode || mode == HImode)
+ /* On power8, we want to use SImode for the operation. On previoius systems,
+ use the operation in a subword and shift/mask to get the proper byte or
+ halfword. */
+ if (TARGET_SYNC_HI_QI && (mode == QImode || mode == HImode))
+{
+ v
+ if (TARGET_DIRECT_MOVE)
+{
+ if (TARGET_POWERPC64)
+{
+ reload_gpr_vsx[TImode]= CODE_FOR_reload_gpr_from_vsxti;
+ reload_gpr_vsx[V2DFmode] = CODE_FOR_reload_gpr_from_vsxv2df;
+ reload_gpr_vsx[V2DImode] = CODE_FOR_reload_gpr_from_vsxv2
[gcc/testsuite]
2013-05-20 Michael Meissner
* gcc.target/powerpc/crypto-builtin-1.c: New file, test for power8
crypto builtins.
The testcase needs to check something more than
/* { dg-require-effective-target powerpc_vsx_ok } */
I don't know if we need to separate the new VSX
On Tue, May 21, 2013 at 7:47 PM, Michael Meissner
wrote:
> * config/rs6000/rs6000.c (rs6000_option_override_internal): Only
> allow power8 quad mode in 64-bit. Turn off splitting wide types
> if we have quad mode.
Completely turning off splitting wide types seems like a
On Tue, May 21, 2013 at 11:42 AM, Michael Meissner
wrote:
> This is patch #3 of our power8 changes. It adds support for vectorizing
> 64-bit
> integer types (V2DI) for plus, subtract, absolute value, minimum, maximum,
> shift, rotate, and comparison. Like the other patches, I have bootstraped
>
On Wed, May 22, 2013 at 11:41:44PM -0400, David Edelsohn wrote:
> Mike,
>
> When you committed the patch, you did not add the new rs6000/crypto.md
> file to the repository.
Right. I remembered to add the new test, but not crypto.me. I just committed
it. I'm sorry about that.
--
Michael Meiss
Mike,
When you committed the patch, you did not add the new rs6000/crypto.md
file to the repository.
- David
On Tue, May 21, 2013 at 11:30 PM, David Edelsohn wrote:
> On Mon, May 20, 2013 at 7:13 PM, Michael Meissner
> wrote:
>> This patch adds the builtins for the new ISA 2.07 crypto instruc
This is the final set of patches that I have available right now. We will be
doing additional patches over the summer.
The primary thing in this patch is to add support for load fusion in the
power8. Power8 has two types of fusion:
addi ,,
lxvd2x ,,
and:
addis ,,
This patch adds support for the byte, half-word, and quad-word atomic memory
operations that were added in ISA 2.07 (i.e. power8). Like the other patches,
this passes bootstrap and had no regressions in make check. Is it ok to commit
this patch after the previous 6 patches have been applied?
[gc
On Mon, May 20, 2013 at 7:13 PM, Michael Meissner
wrote:
> This patch adds the builtins for the new ISA 2.07 crypto instructions. It
> bootstraps and causes no regressions, is it ok to install after patch #1 has
> been applied?
>
> [gcc]
> 2013-05-20 Michael Meissner
>
> * doc/extend.t
This patch provides the tests for the new vector instructions added in patches
3 and 4. In addition, it provides the target support for power8 systems.
Is this patch acceptable to be checked in once the previous 4 patches have been
applied?
2013-05-21 Michael Meissner
* gcc.target/po
On Mon, 2013-05-20 at 16:40 -0400, Michael Meissner wrote:
> Note, in order to build code for power8, you will need a power8 assembler,
> which will shortly be submitted to the binutils mailing lists.
Already submitted and committed upstream:
http://sourceware.org/ml/binutils/2013-05/msg00235.h
This patch adds the builtins for the new ISA 2.07 crypto instructions. It
bootstraps and causes no regressions, is it ok to install after patch #1 has
been applied?
[gcc]
2013-05-20 Michael Meissner
* doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions): Add
documentation
On May 10th, the Power Architecture Advisory Council announced the public
availability of Power ISA 2.07.
https://www.power.org/documentation/power-isa-version-2-07/
I will start submitting patches shortly which are our initial support for the
future power8 cpu which will implement the ISA 2.07 in
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