Ok, I tracked down what the problem is. We never implemented the
EQV, ORC, or
NAND insns in the GPRs. When I added the power8 vector versions,
the split
wide types pass tried to do its thing in the GPRs, it creates a bad
insn. I
originally saw it in the atomic ops, because I was testing all of the
combinations provided, but I can reproduce it just by using
__int128_t.
The boolc<mode>3_internal1 pattern uses non-canonical RTL for
eqv: (xor (not x) y) instead of (not (xor x y)). You'll need
to add a correct pattern, or wait for my patch series (which
I'll start sending later today) to get in.
(There are problems with the dot forms of xor, nand, nor, and
eqv as well, but I don't think you will hit that?)
Segher
