On Tue, Jun 4, 2013 at 2:48 PM, Michael Meissner <meiss...@linux.vnet.ibm.com> wrote: > I revised this patch for power8 to add new miscellaneous vector instructions > to > not turn off splitting wide moves. In doing the patch, I discovered that we > never supported the 'eqv' instruction, and I have added support for eqv in the > GPR registers. > > I also fixed the issue David raised in patch #2, that I did not protect the > crypt tests in case an assembler that does not understand ISA 2.07 > instructions > was used to build the compiler. I brought in the changes to > target-supports.exp from patch #5 to fix this. > > This patch bootstraps and causes no regressions, is it ok to check in? > > [gcc] > 2013-06-04 Michael Meissner <meiss...@linux.vnet.ibm.com> > Pat Haugen <pthau...@us.ibm.com> > Peter Bergner <berg...@vnet.ibm.com> > > * doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions): > Document new power8 builtins. > > * config/rs6000/vector.md (and<mode>3): Add a clobber/scratch of a > condition code register, so TImode logical operations can be done > either in VSX registers or GPRs. > (nor<mode>3): Use the canonical form for nor. > (eqv<mode>3): Add expanders for power8 xxleqv, xxlnand, xxlorc, > vclz*, and vpopcnt* vector instructions. > (nand<mode>3): Likewise. > (orc<mode>3): Likewise. > (clz<mode>2): LIkewise. > (popcount<mode>2): Likewise. > > * config/rs6000/predicates.md (int_reg_operand): Rework tests so > that only the GPRs are recognized. > > * config/rs6000/rs6000-builtin.def (xscvspdpn): Add new power8 > builtin functions. > (xscvdpspn): Likewise. > (vclzb): Likewise. > (vclzh): Likewise. > (vclzw): Likewise. > (vclzd): Likewise. > (vpopcntb): Likewise. > (vpopcnth): Likewise. > (vpopcntw): Likewise. > (vpopcntd): Likewise. > (vgbbd): Likewise. > (vmrgew): Likewise. > (vmrgow): Likewise. > (eqv_v16qi3): Likewise. > (eqv_v8hi3): Likewise. > (eqv_v4si3): Likewise. > (eqv_v2di3): Likewise. > (eqv_v4sf3): Likewise. > (eqv_v2df3): Likewise. > (nand_v16qi3): Likewise. > (nand_v8hi3): Likewise. > (nand_v4si3): Likewise. > (nand_v2di3): Likewise. > (nand_v4sf3): Likewise. > (nand_v2df3): Likewise. > (orc_v16qi3): Likewise. > (orc_v8hi3): Likewise. > (orc_v4si3): Likewise. > (orc_v2di3): Likewise. > (orc_v4sf3): Likewise. > (orc_v2df3): Likewise. > (vclz): Likewise. > (vclzb): Likewise. > (vclzh): Likewise. > (vclzw): Likewise. > (vclzd): Likewise. > (vpopcnt): Likewise. > (vpopcntb): Likewise. > (vpopcnth): Likewise. > (vpopcntw): Likewise. > (vpopcntd): Likewise. > (vgbbd): Likewise. > (eqv): Likewise. > (nand): Likewise. > (orc): Likewise. > (vmrgew): Likewise. > (vmrgow): Likewise. > > * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add > support for new power8 builtins. > > * config/rs6000/rs6000.c (rs6000_option_override_internal): Only > allow power8 quad mode in 64-bit. > (rs6000_builtin_vectorized_function): Vectorize count leading > zeros, population count builtins. > (rs6000_expand_vector_init): On power8 use xscvdpspn to form V4SF > vectors instead of xscvdpsp to avoid IEEE related traps. > (builtin_function_type): Add vgbbd builtin function which takes an > unsigned argument. > (altivec_expand_vec_perm_const): Add support for new power8 merge > instructions. > > * config/rs6000/vsx.md (VSX_L2): New iterator for 128-bit types, > that does not include TImdoe for use with 32-bit. > (UNSPEC_VSX_CVSPDPN): Support for power8 xscvdpspn and xscvspdpn > instructions. > (UNSPEC_VSX_CVDPSPN): Likewise. > (vsx_xscvdpspn): Likewise. > (vsx_xscvspdpn): Likewise. > (vsx_xscvdpspn_scalar): Likewise. > (vsx_xscvspdpn_directmove): Likewise. > (vsx_and<mode>3): Split logical operations into 32-bit and > 64-bit. Add support to do logical operations on TImode as well as > VSX vector types. Allow logical operations to be done in either > VSX registers or in general purpose registers in 64-bit mode. Add > splitters if GPRs were used. For and, add clobber of CCmode to > allow use of ANDI on GPRs. > (vsx_and<mode>3_32bit): Likewise. > (vsx_and<mode>3_64bit): Likewise. > (vsx_ior<mode>3): Likewise. > (vsx_ior<mode>3_32bit): Likewise. > (vsx_ior<mode>3_64bit): Likewise. > (vsx_xor<mode>3): Likewise. > (vsx_xor<mode>3_32bit): Likewise. > (vsx_xor<mode>3_64bit): Likewise. > (vsx_one_cmpl<mode>2): Likewise. > (vsx_one_cmpl<mode>2_32bit): Likewise. > (vsx_one_cmpl<mode>2_64bit): Likewise. > (vsx_nor<mode>3): Likewise. > (vsx_nor<mode>3_32bit): Likewise. > (vsx_nor<mode>3_64bit): Likewise. > (vsx_andc<mode>3): Likewise. > (vsx_andc<mode>3_32bit): Likewise. > (vsx_andc<mode>3_64bit): Likewise. > (vsx_eqv<mode>3_32bit): Add support for power8 xxleqv, xxlnand, > and xxlorc instructions. > (vsx_eqv<mode>3_64bit): Likewise. > (vsx_nand<mode>3_32bit): Likewise. > (vsx_nand<mode>3_64bit): Likewise. > (vsx_orc<mode>3_32bit): Likewise. > (vsx_orc<mode>3_64bit): Likewise. > > * config/rs6000/rs6000.h (VLOGICAL_REGNO_P): Update comment. > > * config/rs6000/altivec.md (UNSPEC_VGBBD): Add power8 vgbbd > instruction. > (p8_vmrgew): Add power8 vmrgew and vmrgow instructions. > (p8_vmrgow): Likewise. > (altivec_and<mode>3): Add clobber of CCmode to allow AND using > GPRs to be split under VSX. > (p8v_clz<mode>2): Add power8 count leading zero support. > (p8v_popcount<mode>2): Add power8 population count support. > (p8v_vgbbd): Add power8 gather bits by bytes by doubleword > support. > > * config/rs6000/rs6000.md (eqv<mode>3): Add support for powerp eqv > instruction. > > * config/rs6000/altivec.h (vec_eqv): Add defines to export power8 > builtin functions. > (vec_nand): Likewise. > (vec_vclz): Likewise. > (vec_vclzb): Likewise. > (vec_vclzd): Likewise. > (vec_vclzh): Likewise. > (vec_vclzw): Likewise. > (vec_vgbbd): Likewise. > (vec_vmrgew): Likewise. > (vec_vmrgow): Likewise. > (vec_vpopcnt): Likewise. > (vec_vpopcntb): Likewise. > (vec_vpopcntd): Likewise. > (vec_vpopcnth): Likewise. > (vec_vpopcntw): Likewise. > > [gcc/testsuite] > 2013-06-04 Michael Meissner <meiss...@linux.vnet.ibm.com> > Pat Haugen <pthau...@us.ibm.com> > Peter Bergner <berg...@vnet.ibm.com> > > * gcc.target/powerpc/bool.c: New file, add eqv, nand, nor tests. > > * gcc.target/powerpc/crypto-builtin-1.c: Use effective target > powerpc_p8vector_ok instead of powerpc_vsx_ok. > > * lib/target-supports.exp (check_p8vector_hw_available) Add power8 > support. > (check_effective_target_powerpc_p8vector_ok): Likewise. > (is-effective-target): Likewise. > (check_vect_support_and_set_flags): Likewise.
Thanks for the changes and fixes. It's looking better. +;; The canonical form is to have the negated elment first, so we need to +;; reverse arguments. Please fix the typo in the comment: "element". +;; Like VSX_L, but don't support TImode for doing logical instructions in +;; 32-bit +(define_mode_iterator VSX_L2 [V16QI V8HI V4SI V2DI V4SF V2DF]) + ;; Iterator for memory move. Handle TImode specially to allow ;; it to use gprs as well as vsx registers. (define_mode_iterator VSX_M [V16QI V8HI V4SI V2DI V4SF V2DF]) +(define_mode_iterator VSX_M2 [V16QI + V8HI + V4SI + V2DI + V4SF + V2DF + (TI "TARGET_VSX_TIMODE")]) The patch adds new iterators VSX_L2 and VSX_M2. The original ChangeLog only mentioned M2 and the new ChangeLog only mentions L2. What's going on? * config/rs6000/rs6000.md (eqv<mode>3): Add support for powerp eqv instruction. Why isn't this covered by boolean_operator and %q output operand? And why can't that predicate and output operand handle vsx as well, e.g., *vsx_eqv? Why don't we simply have vsx_bool<mode>3, etc. Thanks, David
