Re: [PATCH] testsuite: arm: Use effective-target for memset-inline* tests

On 2024-11-04 15:41, Richard Earnshaw wrote: On 01/11/2024 18:40, Richard Earnshaw (lists) wrote: On 24/10/2024 09:50, Torbjörn SVENSSON wrote: Ok for trunk and releases/gcc-14? -- As these tests are set to execute and require neon hardware to do so, add the missing dg-require-effective-ta

Re: [PATCH] middle-end: Use rtx_equal_p in notice_stack_pointer_modification_1 [PR117359]

On Tue, Nov 5, 2024 at 1:08 AM Jeff Law wrote: > > > > On 11/1/24 10:44 AM, Uros Bizjak wrote: > > On Fri, Nov 1, 2024 at 3:51 PM Jeff Law wrote: > >> > >> On 11/1/24 8:45 AM, Uros Bizjak wrote: > >>> On Fri, Nov 1, 2024 at 2:18 PM Jeff Law wrote: > > > > On 11/1/24 5:34 AM,

Re: [PATCH v2 2/4] vect: disable multiple calls of poly simdclones

On Tue, 5 Nov 2024, Victor Do Nascimento wrote: > The current codegen code to support VF's that are multiples of a simdclone > simdlen rely on BIT_FIELD_REF to create multiple input vectors. This does not > work for non-constant simdclones, so we should disable using such clones when > the VF is

Re: [PATCH v2 1/4] vect: Pass stmt_vec_info to TARGET_SIMD_CLONE_USABLE

On Tue, 5 Nov 2024, Victor Do Nascimento wrote: > This patch adds stmt_vec_info to TARGET_SIMD_CLONE_USABLE to make sure the > target can reject a simd_clone based on the vector mode it is using. > This is needed because for VLS SVE vectorization the vectorizer accepts > Advanced SIMD simd clones

Re: [PATCH] [x86_64] Add flag to control tight loops alignment opt

On Tue, Nov 5, 2024 at 2:34 PM Liu, Hongtao wrote: > > > > > -Original Message- > > From: MayShao-oc > > Sent: Tuesday, November 5, 2024 11:20 AM > > To: gcc-patches@gcc.gnu.org; hubi...@ucw.cz; Liu, Hongtao > > ; ubiz...@gmail.com > > Cc: ti...@zhaoxin.com; silviaz...@zhaoxin.com; loui..

RE: [PATCH] [x86_64] Add flag to control tight loops alignment opt

> -Original Message- > From: MayShao-oc > Sent: Tuesday, November 5, 2024 11:20 AM > To: gcc-patches@gcc.gnu.org; hubi...@ucw.cz; Liu, Hongtao > ; ubiz...@gmail.com > Cc: ti...@zhaoxin.com; silviaz...@zhaoxin.com; loui...@zhaoxin.com; > cobec...@zhaoxin.com > Subject: [PATCH] [x86_64] A

Re: [PATCH v2] i386: Handling exception input of __builtin_ia32_prefetch. [PR117416]

On Tue, Nov 5, 2024 at 2:41 PM Hu, Lin1 wrote: > > > -Original Message- > > From: Hu, Lin1 > > Sent: Tuesday, November 5, 2024 1:34 PM > > To: gcc-patches@gcc.gnu.org > > Cc: Liu, Hongtao ; ubiz...@gmail.com > > Subject: [PATCH v2] i386: Handling exception input of > > __builtin_ia32_pref

[PATCH] [x86_64] Add flag to control tight loops alignment opt

Hi all: This patch add -malign-tight-loops flag to control pass_align_tight_loops. The motivation is that pass_align_tight_loops may cause performance regression in nested loops. The example code as follows: #define ITER 2 #define ITER_O 10 int i, j,k; int array[I

[PATCH v2] i386: Handling exception input of __builtin_ia32_prefetch. [PR117416]

Add handler for op3, and the previously stated fail is a random fail not related to this change, OK for trunk? op1 should be between 0 and 2. Add an error handler, and op3 should be 0 or 1, raise a warning, when op3 is an invalid value. gcc/ChangeLog: PR target/117416 * config/i3

Re: [PATCH] Optimize incoming integer argument promotion

On 11/4/24 8:13 PM, H.J. Lu wrote: On Tue, Nov 5, 2024 at 10:57 AM Jeff Law wrote: On 11/4/24 7:52 PM, H.J. Lu wrote: On Tue, Nov 5, 2024 at 8:48 AM Jeff Law wrote: On 11/4/24 5:42 PM, H.J. Lu wrote: On Tue, Nov 5, 2024 at 8:07 AM Jeff Law wrote: On 11/1/24 4:32 PM, H.J. Lu wr

Re: [PATCH v3] c++: Implement P2662R3, Pack Indexing [PR113798]

On 10/30/24 4:59 PM, Marek Polacek wrote: On Wed, Oct 30, 2024 at 09:01:36AM -0400, Patrick Palka wrote: On Tue, 29 Oct 2024, Marek Polacek wrote: +/* Substitute ARGS into T, which is a pack index (i.e., PACK_INDEX_TYPE or + PACK_INDEX_EXPR). Returns a single type or expression, a PACK_INDEX

Re: [PATCH 1/2] aarch64: Remove scheduling models for falkor and saphira

On Thu, Oct 31, 2024 at 3:16 PM Richard Sandiford wrote: > > Andrew Pinski writes: > > These 2 qualcomm cores have been long gone in that Qualcomm has not > > supported since at least 2019. Removing them will make it easier I think > > to change the insn type attributes instead of keeping them up

Re: [PATCH v2] Fix MV clones can not redirect to specific target on some targets

Ping and also CC Jeff and Kito. This is also useful for RISC-V since RISC-V uses target_version, which defines TARGET_HAS_FMV_TARGET_ATTRIBUTE to zero. On 10/28/24 00:00, Yangyu Chen wrote: Following the implementation of commit b8ce8129a5 ("Redirect call within specific target attribute among

Re: [PATCH] fold fold_truth_andor field merging into ifcombine

On Oct 20, 2024, Alexandre Oliva wrote: > the x86 hits are newer, and > the line numbers didn't help me find the errors, so I don't even know > whether it's macros that we're talking about. These new warnings were > encouraging, for they showed that the ifcombine incarnation of the patch > cover

[PATCH v5 5/8] RISC-V: Implement TARGET_COMPARE_VERSION_PRIORITY and TARGET_OPTION_FUNCTION_VERSIONS

This patch implements TARGET_COMPARE_VERSION_PRIORITY and TARGET_OPTION_FUNCTION_VERSIONS for RISC-V. The TARGET_COMPARE_VERSION_PRIORITY is implemented to compare the priority of two function versions based on the rules defined in the RISC-V C-API Doc PR #85: https://github.com/riscv-non-isa/ris

[PATCH v5 7/8] RISC-V: Implement TARGET_GENERATE_VERSION_DISPATCHER_BODY and TARGET_GET_FUNCTION_VERSIONS_DISPATCHER

This patch implements the TARGET_GENERATE_VERSION_DISPATCHER_BODY and TARGET_GET_FUNCTION_VERSIONS_DISPATCHER for RISC-V. This is used to generate the dispatcher function and get the dispatcher function for function multiversioning. This patch copies many codes from commit 0cfde688e213 ("[aarch64]

[PATCH v5 4/8] RISC-V: Implement TARGET_OPTION_VALID_VERSION_ATTRIBUTE_P

This patch implements the TARGET_OPTION_VALID_VERSION_ATTRIBUTE_P for RISC-V. This hook is used to process attribute ((target_version ("..."))). As it is the first patch which introduces the target_version attribute, we also set TARGET_HAS_FMV_TARGET_ATTRIBUTE to 0 to use "target_version" for func

[PATCH v5 8/8] RISC-V: Add Multi-Versioning Test Cases

This patch adds test cases for the Function Multi-Versioning (FMV) feature for RISC-V, which reuses the existing test cases from the aarch64 and ported them to RISC-V. Signed-off-by: Yangyu Chen gcc/testsuite/ChangeLog: * g++.target/riscv/mv-symbols1.C: New test. * g++.target/ri

[PATCH v5 6/8] RISC-V: Implement TARGET_MANGLE_DECL_ASSEMBLER_NAME

This patch implements the TARGET_MANGLE_DECL_ASSEMBLER_NAME for RISC-V. This is used to add function multiversioning suffixes to the assembler name. Signed-off-by: Yangyu Chen gcc/ChangeLog: * config/riscv/riscv.cc (riscv_mangle_decl_assembler_name): New function. (TARGE

[PATCH v5 2/8] RISC-V: Implement Priority syntax parser for Function Multi-Versioning

This patch adds the priority syntax parser to support the Function Multi-Versioning (FMV) feature in RISC-V. This feature allows users to specify the priority of the function version in the attribute syntax. Chnages based on RISC-V C-API PR: https://github.com/riscv-non-isa/riscv-c-api-doc/pull/85

[PATCH v5 3/8] RISC-V: Implement riscv_minimal_hwprobe_feature_bits

This patch implements the riscv_minimal_hwprobe_feature_bits feature for the RISC-V target. The feature bits are defined in the libgcc/config/riscv/feature_bits.c to provide bitmasks of ISA extensions that defined in RISC-V C-API. Thus, we need a function to generate the feature bits for IFUNC reso

[PATCH v5 1/8] Introduce TARGET_CLONES_ATTR_SEPARATOR for RISC-V

Some architectures may use ',' in the attribute string, but it is not used as the separator for different targets. To avoid conflict, we introduce a new macro TARGET_CLONES_ATTR_SEPARATOR to separate different clones. As an example, according to RISC-V C-API Specification [1], RISC-V allows ',' in

[PATCH v5 0/8] RISC-V: Add Function Multi-Versioning support

This patch series adds support for Function Multi-Versioning (FMV) to RISC-V. The FMV feature allows users to specify multiple versions of a function and select the version at runtime based on the target_clones and target_version attributes, which follow the RISC-V C-API Docs [1] and the existing p

Re: [PATCH] Optimize incoming integer argument promotion

On Tue, Nov 5, 2024 at 10:57 AM Jeff Law wrote: > > > > On 11/4/24 7:52 PM, H.J. Lu wrote: > > On Tue, Nov 5, 2024 at 8:48 AM Jeff Law wrote: > >> > >> > >> > >> On 11/4/24 5:42 PM, H.J. Lu wrote: > >>> On Tue, Nov 5, 2024 at 8:07 AM Jeff Law wrote: > > > > On 11/1/24 4:32 PM

Re: [PATCH] i386: Handling exception input of __builtin_ia32_prefetch. [PR117416]

On Tue, Nov 5, 2024 at 10:52 AM Hu, Lin1 wrote: > > Hi, all > > __builtin_ia32_prefetch's op1 should be between 0 and 2. So add an error > handler. > > Bootstrapped and regtested on x86_64-pc-linux-gnu, there is a unrelated FAIL > that has yet to be found root cause, just send patch for review. >

Re: [PATCH v2 1/3] RISC-V: Remove skip of decl in registered_function.

On 11/4/24 6:06 PM, Kito Cheng wrote: Hi Jeff: This should work with the second patch in the patch set, but I think that's not ready yet... Ah. I didn't see anything indicating it relied on the 2nd patch for correctness. I'll let you own this since it hits stuff you know far better than

Re: [PATCH] Optimize incoming integer argument promotion

On 11/4/24 7:52 PM, H.J. Lu wrote: On Tue, Nov 5, 2024 at 8:48 AM Jeff Law wrote: On 11/4/24 5:42 PM, H.J. Lu wrote: On Tue, Nov 5, 2024 at 8:07 AM Jeff Law wrote: On 11/1/24 4:32 PM, H.J. Lu wrote: For targets, like x86, which define TARGET_PROMOTE_PROTOTYPES to return true, all i

Re: [PATCH] Optimize incoming integer argument promotion

On Tue, Nov 5, 2024 at 8:48 AM Jeff Law wrote: > > > > On 11/4/24 5:42 PM, H.J. Lu wrote: > > On Tue, Nov 5, 2024 at 8:07 AM Jeff Law wrote: > >> > >> > >> > >> On 11/1/24 4:32 PM, H.J. Lu wrote: > >>> For targets, like x86, which define TARGET_PROMOTE_PROTOTYPES to return > >>> true, all integer

[PATCH] i386: Handling exception input of __builtin_ia32_prefetch. [PR117416]

Hi, all __builtin_ia32_prefetch's op1 should be between 0 and 2. So add an error handler. Bootstrapped and regtested on x86_64-pc-linux-gnu, there is a unrelated FAIL that has yet to be found root cause, just send patch for review. BRs, Lin gcc/ChangeLog: PR target/117416 * co

Re: [PATCH v2] c++: Fix crash during NRV optimization with invalid input [PR117099, PR117129]

On 10/30/24 12:34 PM, Simon Martin wrote: Hi Jason, On 22 Oct 2024, at 17:07, Jason Merrill wrote: On 10/17/24 10:30 AM, Simon Martin wrote: Hi, The issue reported in PR117129 is pretty similar to the one in PR117099, so here’s an updated version of the patch that fixes both issues, by ensu

Re: [PATCH 0/2] Add arch support for Intel CPUs

On Fri, Nov 1, 2024 at 11:24 AM Haochen Jiang wrote: > > Hi all, > > I have just landed new ISA patches on trunk. The next step will > be the arch support for ISE055 mentioned CPUs. > > There are two changes in ISE055 on CPUs: > > - A new model number is added for Arrow Lake. > - Diamond Rapid

Re: [PATCH v2 1/3] RISC-V: Remove skip of decl in registered_function.

Hi Jeff: This should work with the second patch in the patch set, but I think that's not ready yet... Jeff Law 於 2024年11月5日 週二 08:52 寫道： > > > On 11/1/24 2:19 AM, KuanLin Chen wrote: > > Hi Jeff, > > > > I'm really sorry for the regression failure. > > I missed one patch to fix these issues. >

Re: [PATCH] PR117350: Keep assembler name for abstract decls for autofdo

On 10/31/24 4:40 PM, Andi Kleen wrote: From: Andi Kleen autofdo looks up inline stacks and tries to match them with the profile data using their symbol name. Make sure all decls that can be in a inline stack have a valid assembler name. This fixes a bootstrap problem with autoprofiledbootstrap

Re: [PATCH v2 1/3] RISC-V: Remove skip of decl in registered_function.

On 11/1/24 2:19 AM, KuanLin Chen wrote: Hi Jeff, I'm really sorry for the regression failure. I missed one patch to fix these issues. Thanks for your review. The GTY skip makes GGC clean the registered functions wrongly in lto. Example: riscv64-unknown-elf-gcc -flto gcc/testsuite/gcc.target

Re: [PATCH] Optimize incoming integer argument promotion

On 11/4/24 5:42 PM, H.J. Lu wrote: On Tue, Nov 5, 2024 at 8:07 AM Jeff Law wrote: On 11/1/24 4:32 PM, H.J. Lu wrote: For targets, like x86, which define TARGET_PROMOTE_PROTOTYPES to return true, all integer arguments smaller than int are passed as int: [hjl@gnu-tgl-3 pr14907]$ cat x.c e

Re: [PATCH] c++: Don't crash upon invalid placement new operator [PR117101]

On 11/1/24 1:22 PM, Simon Martin wrote: We currently crash upon the following invalid code (notice the "void void**" parameter) === cut here === using size_t = decltype(sizeof(int)); void *operator new(size_t, void void **p) noexcept { return p; } int x; void f() { int y; new (&y) int(

Re: [PATCH 3/4] sched1: model: only promote true dependecies in predecessor promotion

On 10/31/24 1:35 PM, Vineet Gupta wrote: An INSN can have multiple dependencies/predecessor nodes, some of them being true dependency REG_DEP_TRUE meaning the predecessor register output is a must have for the INSN to be scheduled. e.g. In the sched1 dump below, insn 70 has multiple deps, bu

Re: [PATCH] c++/modules: Handle location exhaustion in write_location [PR105443]

On 11/4/24 5:35 PM, Nathaniel Shead wrote: This patch is missing a testcase because I wasn't able to easily construct one that reliably exhausts all location_t values and then causes an error. Bootstrapped and regtested on x86_64-pc-linux-gnu, OK for trunk? OK. -- >8 -- The 'location_t' typ

Re: [PATCH] Optimize incoming integer argument promotion

On Tue, Nov 5, 2024 at 8:07 AM Jeff Law wrote: > > > > On 11/1/24 4:32 PM, H.J. Lu wrote: > > For targets, like x86, which define TARGET_PROMOTE_PROTOTYPES to return > > true, all integer arguments smaller than int are passed as int: > > > > [hjl@gnu-tgl-3 pr14907]$ cat x.c > > extern int baz (cha

Re: [PATCH v2 4/4] vect: Disable `omp declare variant' tests for aarch64

cc'ing Jakub due to email address typo in original patch submission. Apologies, Victor Victor Do Nascimento writes: > gcc/testsuite/ChangeLog: > > * c-c++-common/gomp/declare-variant-14.c: Make i?86 and x86_64 target > only test. > * gfortran.dg/gomp/declare-variant-14.f90:

[PATCH v2 4/4] vect: Disable `omp declare variant' tests for aarch64

gcc/testsuite/ChangeLog: * c-c++-common/gomp/declare-variant-14.c: Make i?86 and x86_64 target only test. * gfortran.dg/gomp/declare-variant-14.f90: Likewise. --- gcc/testsuite/c-c++-common/gomp/declare-variant-14.c | 12 +--- .../gfortran.dg/gomp/declare-variant-1

Re: [PATCH] c++/modules: Merge default arguments [PR99274]

On 11/2/24 7:05 AM, Nathaniel Shead wrote: On Fri, Nov 01, 2024 at 11:23:41AM -0400, Jason Merrill wrote: On 8/22/24 8:02 PM, Nathaniel Shead wrote: On Thu, Aug 22, 2024 at 02:20:14PM -0400, Patrick Palka wrote: On Mon, 12 Aug 2024, Nathaniel Shead wrote: Bootstrapped and regtested on x86_64

[PATCH v2 3/4] aarch64: Add SVE support for simd clones [PR 96342]

This patch finalizes adding support for the generation of SVE simd clones when no simdlen is provided, following the ABI rules where the widest data type determines the minimum amount of elements in a length agnostic vector. gcc/ChangeLog: * config/aarch64/aarch64-protos.h (add_sve_type_a

[PATCH v2 2/4] vect: disable multiple calls of poly simdclones

The current codegen code to support VF's that are multiples of a simdclone simdlen rely on BIT_FIELD_REF to create multiple input vectors. This does not work for non-constant simdclones, so we should disable using such clones when the VF is a multiple of the non-constant simdlen until we change th

Re: [PATCH 4/6] expmed, aarch64: Optimize vector rotates as vector permutes where possible

On 10/31/24 9:50 AM, Kyrylo Tkachov wrote: Is there a reason why we don't have the target reject the vector rotation cases it can't natively handle and the expander code would then try the rotate via permuation? It seems like your patch defers everything to the target which calls back int

Re: [PATCH] c++, v2: Mark replaceable global operator new/delete with const std::nothrow_t& argument as DECL_IS_REPLACEABLE_OPERATOR [PR117370]

On 11/1/24 3:17 PM, Jakub Jelinek wrote: On Fri, Nov 01, 2024 at 12:28:52PM -0400, Jason Merrill wrote: Can this block be if (aligned_allocation_fn_p (decl)) args = TREE_CHAIN (args); ? Yes. + && TREE_CODE (t) == RECORD_TYPE + && DECL_NAMESPACE_ST

Re: [PATCH] phiopt: do factor_out_conditional_operation for all phis [PR112418]

On 10/21/24 3:18 AM, Richard Biener wrote: Bootstrapped and tested on x86_64-linux-gnu. PR tree-optimization/112418 gcc/ChangeLog: * tree-ssa-phiopt.cc (is_factor_profitable): New function. (factor_out_conditional_operation): Add merge argument. Remove arg0/arg

Re: [PATCH v2] c++: Defer -fstrong-eval-order processing to template instantiation time [PR117158]

On 11/4/24 10:19 AM, Simon Martin wrote: Hi Jason, On 1 Nov 2024, at 16:31, Jason Merrill wrote: On 11/1/24 5:07 AM, Simon Martin wrote: Since r10-3793-g1a37b6d9a7e57c, we ICE upon the following valid code with -std=c++17 and above === cut here === struct Base { unsigned int *intarray; }

[PATCH v2 1/4] vect: Pass stmt_vec_info to TARGET_SIMD_CLONE_USABLE

This patch adds stmt_vec_info to TARGET_SIMD_CLONE_USABLE to make sure the target can reject a simd_clone based on the vector mode it is using. This is needed because for VLS SVE vectorization the vectorizer accepts Advanced SIMD simd clones when vectorizing using SVE types because the simdlens mig

[PATCH v2 1/4] vect: Pass stmt_vec_info to TARGET_SIMD_CLONE_USABLE

This patch adds stmt_vec_info to TARGET_SIMD_CLONE_USABLE to make sure the target can reject a simd_clone based on the vector mode it is using. This is needed because for VLS SVE vectorization the vectorizer accepts Advanced SIMD simd clones when vectorizing using SVE types because the simdlens mig

Re: [PATCH] middle-end: Use rtx_equal_p in notice_stack_pointer_modification_1 [PR117359]

On 11/1/24 10:44 AM, Uros Bizjak wrote: On Fri, Nov 1, 2024 at 3:51 PM Jeff Law wrote: On 11/1/24 8:45 AM, Uros Bizjak wrote: On Fri, Nov 1, 2024 at 2:18 PM Jeff Law wrote: On 11/1/24 5:34 AM, Uros Bizjak wrote: Stack pointer modifications in asm are currently not flagged in crtl->sp

Re: [PATCH] Optimize incoming integer argument promotion

On 11/1/24 4:32 PM, H.J. Lu wrote: For targets, like x86, which define TARGET_PROMOTE_PROTOTYPES to return true, all integer arguments smaller than int are passed as int: [hjl@gnu-tgl-3 pr14907]$ cat x.c extern int baz (char c1); int foo (char c1) { return baz (c1); } [hjl@gnu-tgl-3 pr149

[PATCH v2 0/4] aarch64, vect: Extend simdclone support to vector-length agnostic SVE

Following a few bugfixes in the if-convert pass which were previously found to degrade performance in the proposed SVE libmvec autovectorization of conditional calls to math functions, this patch-series carries on the work initially presented by Andre Vieira and last discussed at: - https://patch

Re: [RISC-V] Reorder the ready queue to avoid extraneous vsetvls

On 10/30/24 7:06 PM, Jeff Law wrote: So this patch is a very conservative approach to eliminate more vsetvl instructions. As we know, scheduling can scramble the instruction stream based on a variety of factors and can easily result in an instruction sequence where we ping-pong between dif

Re: [PATCH v4 1/8] Introduce TARGET_CLONES_ATTR_SEPARATOR for RISC-V

On 11/1/24 2:58 PM, Yangyu Chen wrote: Some architectures may use ',' in the attribute string, but it is not used as the separator for different targets. To avoid conflict, we introduce a new macro TARGET_CLONES_ATTR_SEPARATOR to separate different clones. As an example, according to RISC-V C

Re: [PATCH] RISC-V: zero_extend(not) -> xor optimization [PR112398]

On 11/2/24 2:58 AM, Alexey Merzlyakov wrote: This patch adds optimization of the following patterns:   (zero_extend:M (subreg:N (not:O==M (X:Q==M ->   (xor:M (zero_extend:M (subreg:N (X:M)), 0x))     ... where mask takes 0x bits of N mode bitsize For the cases when X:M does

Re: [PATCH] c: Implement C2y N3356, if declarations [PR117019]

+ Joseph On Mon, Nov 04, 2024 at 06:26:47PM -0500, Marek Polacek wrote: > Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk? > > -- >8 -- > This patch implements C2y N3356, if declarations as described at > . > > This feature

Re: [COMMITTED] [gcc12] [gcc13] [gcc14] PR tree-optimization/117398 - Don't call invert on VARYING.

On 11/4/24 10:00, Andrew MacLeod wrote: The invert() range operation is not supported on values of either VARYING or UNDEFINED.  Primarily this is because UNDEFINED has no type, which makes it impossible to perform invert() twice on a value, and produce that same value.  There were also times

[PATCH] c: Implement C2y N3356, if declarations [PR117019]

Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk? -- >8 -- This patch implements C2y N3356, if declarations as described at . This feature is cognate with C++17 Selection statements with initializer

Re: Bootstrap issue due to translated messages in selftest [PR117361] – was: [pushed: r15-4760] diagnostics: support multiple output formats simultaneously [PR116613]

On Mon, 2024-11-04 at 11:41 +0100, Tobias Burnus wrote: > Hi David > > David Malcolm wrote: > > On Fri, 2024-11-01 at 07:36 +0100, Tobias Burnus wrote: > > > Or you do the same as forhttps://gcc.gnu.org/PR115203 ; namely, > > > your commit > > > https://gcc.gnu.org/r15-866-g2dbb1c124c1e585dc413132

Re: [PATCH] c: minor fixes related to arrays of unspecified size [PR116284,PR117391]

On Sat, 2 Nov 2024, Martin Uecker wrote: > c: minor fixes related to arrays of unspecified size > > The patch for PR117145 and PR117245 also fixed PR100420 and PR116284 > which are bugs related to arrays of unspecified. Those are now > represented > as variable size arrays w

Re: [PATCH 1/3] Write LF_BCLASS records in CodeView struct definitions

On 11/2/24 4:36 PM, Mark Harmstone wrote: When writing the CodeView type definition for a struct, translate DW_TAG_inheritance DIEs into LF_BCLASS records, to record which other structs this one inherits from. gcc/ * dwarf2codeview.cc (enum cv_leaf_type): Add LF_BCLASS. (struc

Re: [PATCH] simulate-thread tests: Silence gdb debuginfod warning

On 11/4/24 3:32 PM, H.J. Lu wrote: On Mon, Nov 4, 2024 at 10:01 PM Jeff Law wrote: On 10/31/24 6:59 PM, H.J. Lu wrote: On Fri, Nov 1, 2024 at 8:32 AM Sam James wrote: "H.J. Lu" writes: When gdb defaults to use debuginfod, gdb warns guality tests: Spawning: gdb -nx -nw -quiet -batc

Re: [PATCH] libstdc++: Remove workaround for modules issue [PR113814]

On Mon, 4 Nov 2024 at 22:46, Nathaniel Shead wrote: > > Thought I should probably clean this up before closing off the PR. > Regtested on x86_64-pc-linux-gnu with no regressions, OK for trunk? OK, thanks. > > -- >8 -- > > The modules bug requiring this workaround was fixed with commit > r15-486

[PATCH] libstdc++: Remove workaround for modules issue [PR113814]

Thought I should probably clean this up before closing off the PR. Regtested on x86_64-pc-linux-gnu with no regressions, OK for trunk? -- >8 -- The modules bug requiring this workaround was fixed with commit r15-4862-g815e48e3d42231. PR testsuite/113710 PR c++/113814 libstdc++-v

[PATCH] c++/modules: Handle location exhaustion in write_location [PR105443]

This patch is missing a testcase because I wasn't able to easily construct one that reliably exhausts all location_t values and then causes an error. Bootstrapped and regtested on x86_64-pc-linux-gnu, OK for trunk? -- >8 -- The 'location_t' type currently only stores a limited number of distinct

[PATCH] simulate-thread tests: Silence gdb debuginfod warning

On Mon, Nov 4, 2024 at 10:01 PM Jeff Law wrote: > > > > On 10/31/24 6:59 PM, H.J. Lu wrote: > > On Fri, Nov 1, 2024 at 8:32 AM Sam James wrote: > >> > >> "H.J. Lu" writes: > >> > >>> When gdb defaults to use debuginfod, gdb warns guality tests: > >>> > >>> Spawning: gdb -nx -nw -quiet -batch -x

Re: [PATCH 00/15] Support for 64-bit location_t

On Mon, Nov 04, 2024 at 10:58:14AM +0100, Richard Biener wrote: > > Regarding memory usage implications of this change. It does make a lot of > > data structures larger. Here is what it does on x86-64. The base sizes of > > some > > types change as follows: > > > > location_t: From 4

Re: [PATCH] [testsuite] disable PIE on ia32 on more tests

On Oct 29, 2024, at 4:15 PM, Alexandre Oliva wrote: > > Multiple tests fail on ia32 with -fPIE enabled by default because of > different call sequences required by the call-saved PIC register > (no-callee-saved-*.c), uses of the constant pool instead of computing > constants (pr100865-*.c), and u

Re: [PATCH] [testsuite] fix pr70321.c PIC expectations

On Oct 29, 2024, at 4:08 PM, Alexandre Oliva wrote: > > When we select a non-bx get_pc_thunk, we get an extra mov to set up > the PIC register before the abort call. Expect that mov or a > get_pc_thunk.bx call. > > Regstrapped on x86_64-linux-gnu; also tested on i686-linux-gnu with > -fPIE. Ok

Re: [PATCH #6/7] ifcombine across noncontiguous blocks

On Nov 3, 2024, Richard Biener wrote: > On Sat, Nov 2, 2024 at 8:39 AM Alexandre Oliva wrote: >> I suppose we could get away without resetting flow info, but even if >> guarding conditions become stricter, resetting flow info makes sense so >> that they're recomputed to reflect the guard chang

Re: [PATCH] Add fancy pointer support in std::map/set

On 04/11/2024 19:45, Jonathan Wakely wrote: On Mon, 4 Nov 2024 at 18:30, François Dumont wrote: On 21/10/2024 06:56, François Dumont wrote: On 17/10/2024 23:11, Jonathan Wakely wrote: On Thu, 17 Oct 2024 at 21:39, Jonathan Wakely wrote: On Thu, 17 Oct 2024 at 20:52, François Dumont

Re: [PATCH][Backport][GCC13] RISC-V: Fix missing boolean_expression in zmmul extension

On 10/22/24 12:33 AM, Kito Cheng wrote: LGTM :) But this doesn't fix a correctness issue, just a performance concern. That doesn't seem appropriate for a release branch where our focus is supposed to be regressions & correctness fixes. Jeff

Re: [PATCH v2 2/2] RISC-V: Disable by pieces for vector setmem length > UNITS_PER_WORD

On 11/4/24 6:09 AM, Craig Blackmore wrote: For fast unaligned access targets, by pieces uses up to UNITS_PER_WORD size pieces resulting in more store instructions than needed. For example gcc.target/riscv/rvv/base/setmem-2.c:f1 built with `-O3 -march=rv64gcv -mtune=thead-c906`: ``` f1:

Re: [PATCH v2 1/2] RISC-V: Make vectorized memset handle more cases

On 11/4/24 6:09 AM, Craig Blackmore wrote: `expand_vec_setmem` only generated vectorized memset if it fitted into a single vector store of at least (TARGET_MIN_VLEN / 8) bytes. Also, without dynamic LMUL the operation was always TARGET_MAX_LMUL even if it would have fitted a smaller LMUL. Al

Re: [PATCH] middle-end/117433 - ICE with gimple BLKmode reg copy

On 11/4/24 3:48 AM, Richard Biener wrote: When we end up expanding a SSA name copy with BLKmode regs which can happen for vectors, possibly wrapped in a NOP-conversion or a PAREN_EXPR and we are not optimizing we can end up with two BLKmode MEMs that expand_gimple_stmt_1 doesn't properly handl

Re: [PATCH 00/15] Support for 64-bit location_t

On 11/4/24 2:58 AM, Richard Biener wrote: All GENERIC decls (tree_decl_minimal) will grow by 8 bytes (and we have 4 bytes unused padding). On the GIMPLE side it's probably a "hooray - more space for flags!". It does feel a bit backwards because the savings we got by making the TREE_BLOCK p

Re: [PATCH] testsuite: arm: Use effective-target for memset-inline* tests

On 2024-11-04 14:37, Richard Earnshaw (lists) wrote: On 04/11/2024 12:28, Torbjorn SVENSSON wrote: On 2024-11-04 12:44, Richard Earnshaw (lists) wrote: On 01/11/2024 19:18, Torbjorn SVENSSON wrote: On 2024-11-01 19:40, Richard Earnshaw (lists) wrote: On 24/10/2024 09:50, Torbjörn SVENS

Re: [PATCH] testsuite: arm: Use effective-target for pr68620 and pr78041 tests

On 2024-11-04 17:03, Richard Earnshaw (lists) wrote: On 31/10/2024 18:26, Torbjörn SVENSSON wrote: Ok for trunk and releases/gcc-14? -- Tests uses neon, so add effective-target arm_neon. gcc/testsuite/ChangeLog: * gcc.target/arm/pr68620.c: Use effective-target arm_neon. *

Re: [PATCH] testsuite: arm: Use effective-target for attr-neon* tests

On 2024-11-04 16:47, Richard Earnshaw (lists) wrote: On 20/10/2024 16:51, Torbjörn SVENSSON wrote: Ok for trunk and releases/gcc-14? -- The tests assume that a neon fpu is avialable and fails it not, so explicitly require it. diff --git a/gcc/testsuite/gcc.target/arm/attr-neon2.c b/gcc/

[pushed: r15-4934] diagnostics: cleanups to opts-diagnostic.cc

No functional change intended. Successfully bootstrapped & regrtested on x86_64-pc-linux-gnu. Pushed to trunk as r15-4934-g196b13f72f3549. gcc/ChangeLog: * opts-diagnostic.cc: Apply renamings throughout for clarity: from "name" and "format_name" to "scheme_name", from "m_format"

[pushed: r15-4935] diagnostics: update leading comment for class diagnostic_context

No functional change intended. Pushed to trunk as r15-4935-gb8ac365db7fac9. gcc/ChangeLog: * diagnostic.h (class diagnostic_context): Update leading comment. Signed-off-by: David Malcolm --- gcc/diagnostic.h | 35 +-- 1 file changed, 33 insertions(+), 2

Re: [PATCH] testsuite: arm: Force hard ABI for pr51534.c test

On 2024-11-04 16:51, Richard Earnshaw (lists) wrote: On 31/10/2024 18:24, Torbjörn SVENSSON wrote: Ok for trunk and releases/gcc-14? -- The test case is written in a way that it should be using hard float ABI, but the use of -mfloat-abi=hard could be overriden by dg-add-options arm_neon. En

Re: [PATCH] testsuite: arm: Relax cbranch tests to accept inverted branches

On 2024-11-01 19:30, Richard Earnshaw (lists) wrote: On 19/10/2024 18:23, Torbjörn SVENSSON wrote: Ok for trunk and releases/gcc-14? -- Similar to PR113502, but for non-aarch64 test. The test started to fail after r14-7243-gafac1bd3365. gcc/testsuite/ChangeLog: * gcc.target/arm/ve

Re: [PATCH] testsuite: arm: Use effective-target for data-intrinsics-assembly test

On 2024-11-01 19:32, Richard Earnshaw (lists) wrote: On 19/10/2024 19:11, Torbjörn SVENSSON wrote: Ok for trunk and releases/gcc-14? -- The expected assembler in the test case assumes -marm, so explicily require it. gcc/testsuite/ChangeLog: * gcc.target/arm/acle/data-intrinsics-as

Re: [PATCH] testsuite: arm: Update expected asm in armv8_2-fp16-neon-2.c

On 2024-11-01 19:47, Richard Earnshaw (lists) wrote: On 24/10/2024 20:12, Torbjörn SVENSSON wrote: Ok for trunk? -- With the changes in r15-1579-g792f97b44ff, the test_vmul_n_16x8 function does not contain any vdup.16 q* r* instruction with -mfloat-abi=softfp. The differnce between r15-157

Re: [PATCH] Add fancy pointer support in std::map/set

On Mon, 4 Nov 2024 at 18:30, François Dumont wrote: > > > On 21/10/2024 06:56, François Dumont wrote: > > > On 17/10/2024 23:11, Jonathan Wakely wrote: > > > > On Thu, 17 Oct 2024 at 21:39, Jonathan Wakely wrote: >> >> >> >> On Thu, 17 Oct 2024 at 20:52, François Dumont wrote: >>> >>> Here is an

Re: [PATCH 0/1] PowerPC vector pair support

I posted an update to this patch to add functions to swap the even and odd elements. https://gcc.gnu.org/pipermail/gcc-patches/2024-November/667451.html -- Michael Meissner, IBM PO Box 98, Ayer, Massachusetts, USA, 01432 email: meiss...@linux.ibm.com

[PATCH, V2] PowerPC vector pair support

This is version 2 of the patch to add functions to allow high performance libraries to write their code so that they can do streaming math functions using the Power10 load vector pair and store vector pair instructions. This patch adds 2 functions to swap the even and odd elements. This is from f

Re: [PATCH 1/1] Unify registered_pp_pragmas and registered_pragmas

On 11/3/24 12:26 PM, Paul Iannetta wrote: On Fri, Nov 01, 2024 at 11:45:07AM -0400, Jason Merrill wrote: On 10/31/24 6:43 AM, Paul Iannetta wrote: gcc/c-family/ChangeLog: * c-pragma.cc (struct pragma_pp_data): Use (struct internal_pragma_handler); (c_register_pragma_1): Always

Re: [PATCH] Add fancy pointer support in std::map/set

On 21/10/2024 06:56, François Dumont wrote: On 17/10/2024 23:11, Jonathan Wakely wrote: On Thu, 17 Oct 2024 at 21:39, Jonathan Wakely wrote: On Thu, 17 Oct 2024 at 20:52, François Dumont wrote: Here is an updated version that compiles, I think, all your feedb

Re: [PATCH] testsuite: arm: Use check-function-bodies in fp16-aapcs-* tests

On Tue, Oct 22, 2024 at 07:18:55PM +0200, Torbjorn SVENSSON wrote: > > > On 2024-10-22 13:36, Richard Earnshaw (lists) wrote: > > On 20/10/2024 16:48, Torbj�rn SVENSSON wrote: > > > Ok for trunk and releases/gcc-14? > > > > > > -- > > > > > > Converted the tests to use check-function-bodies

Some recent dmarc failure bounces

Hi all, The gcc-patches list recently saw a couple of bounces of emails that didn't pass dmarc policy (with p=reject) with spf and dkim failing. All people who got unsubscribed because of this have been resubscribed again. To prevent getting email on the list that don't pass a strict dmarc polic

[COMMITTED 30/38] ada: Avoid unused with warning with Extend_System

From: Viljar Indus When the Extend_System pragma is used then we are supposed to check the extended system for referenced entities. Otherwise we would get an incorrect unused with warning. This was previously done on body files but it should also be done specs as well. gcc/ada/ChangeLog:

[COMMITTED 21/38] ada: CheriBSD: add SIGPROT handler

From: Daniel King gcc/ada/ChangeLog: * libgnarl/s-intman__cheribsd.adb: Add SIGPROT to interrupt list. Tested on x86_64-pc-linux-gnu, committed on master. --- gcc/ada/libgnarl/s-intman__cheribsd.adb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/ada/libgnarl/s

[COMMITTED 14/38] ada: Fix alignment of pthread_mutex_t

From: Daniel King On most targets the alignment of unsigned long is the same as pointer alignment, but on CHERI targets pointers have larger alignment (16 bytes compared to 8 bytes). pthread_mutex_t needs the same alignment as System.Address to account for CHERI targets. gcc/ada/ChangeLog:

[COMMITTED 33/38] ada: Improve performance of Unbounded_Wide_Wide_String

From: Nicolas Roche Improve performance of iteration using Element function. Improve performance of Append. gcc/ada/ChangeLog: * libgnat/a-stzunb__shared.adb: Restructure code to inline only the most common cases. Remove whenever possible runtime checks. * libgnat/a-stzu

[COMMITTED 34/38] ada: Improve Unbounded_Wide_String performance

From: Nicolas Roche Improve performance of iteration using Element function. Improve performance of Append. gcc/ada/ChangeLog: * libgnat/a-stwiun__shared.adb: Restructure code to inline only the most common cases. Remove whenever possible runtime checks. * libgnat/a-stwi

[COMMITTED 31/38] ada: Initial implementation of Extended_Access aspect (FE portion only)

From: Steve Baird The Extended_Access aspect can be specified to be True for certain access-to-unconstrained-array-subtype types. Such extended access types can designate objects that a normal general access type (with the same designated subtype) cannot, such as a slice of an aliased array objec

[COMMITTED 38/38] ada: Move special case for null string literal from frontend to backend

From: Piotr Trojanek Previously the lower bound of string literals indexed by non-static integer types was artificially set to 1 in the frontend. This was to avoid an overflow in calculation of a null string size by the GCC backend, which was causing an excessively large binary object file. Howe

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