On 25/05/2025 12:48, Daniel Stone wrote:
> On Sun, 25 May 2025 at 06:16, Krzysztof Kozlowski
> wrote:
>> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
>> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
>> @@ -
Lists should have fixed constraints, because binding must be specific in
respect to hardware. Add missing constraints to number of iommus in
Mediatek media devices.
Signed-off-by: Krzysztof Kozlowski
---
.../bindings/display/mediatek/mediatek,ovl-2l.yaml | 5 ++---
.../devicetree
On 23/05/2025 18:09, Dan Carpenter wrote:
> The devm_drm_panel_alloc() function returns error pointers, it doesn't
> return NULL. Update the check to match.
>
> Fixes: 4fca6849864d ("drm/panel: Add Novatek NT37801 panel driver")
> Signed-off-by: Dan Carpenter
Re
quot;
> [drivers/gpu/drm/panel/panel-novatek-nt37801.ko] undefined!
>
> Fixes: 4fca6849864d ("drm/panel: Add Novatek NT37801 panel driver")
Indeed, I wrote the driver first without DSC and forgot about it later.
Reviewed-by: Krzysztof Kozlowski
Best regards,
Krzysztof
On 23/05/2025 09:02, Abel Vesa wrote:
>>> static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer,
>>> - struct dpu_plane_state *pstate, const struct msm_format *format)
>>> + struct dpu_plane_state *pstate,
>>> +
On 16/05/2025 11:58, Heiko Stübner wrote:
> Am Donnerstag, 15. Mai 2025, 17:54:20 Mitteleuropäische Sommerzeit schrieb
> Krzysztof Kozlowski:
>> On 15/05/2025 14:35, long.yunj...@zte.com.cn wrote:
>>> From: Yumeng Fang
>>>
>>> In the probe path, dev_e
gt; Signed-off-by: Frank Li
> Reviewed-by: Stefan Agner
> ---
> Change from v1 to v2
> - add Reviewed-by: Stefan Agner review tag
> - add interrupt
Thanks for doing the conversions and for review from Stefan and
Alexander.
Reviewed-by: Krzysztof Kozlowski
Best regards,
Krzysztof
On 20/05/2025 23:23, Dmitry Baryshkov wrote:
>>
>> There is no checkpatch --strict warning here exactly for the reason I
>> was saying. For readability there should be no empty line after because
>> such statements are expected to be together. I don't mind of course
>> adding one, so I will impleme
> - Split register block in its constituent subblocks, and only require
> the ones that the kernel would ever use (Nicolas Frattaroli)
> - Group supplies (Rob Herring)
> - Explain the way in which the top core is special (Rob Herring)
>
> v4:
> - Change required node name
On 20/05/2025 22:06, Dmitry Baryshkov wrote:
> On Tue, May 20, 2025 at 01:13:26PM +0200, Krzysztof Kozlowski wrote:
>> Driver unconditionally saves current state on first init in
>> dsi_pll_10nm_init(), but does not save the VCO rate, only some of the
>> divider register
On 03/05/2025 00:44, Dmitry Baryshkov wrote:
> On Wed, Apr 30, 2025 at 03:00:45PM +0200, Krzysztof Kozlowski wrote:
>> Add bitfields for PHY_CMN_CTRL_0 registers to avoid hard-coding bit
>> masks and shifts and make the code a bit more readable.
>>
>> Signed-
L was not configured configure it to minimum rate to avoid glitches
and configuring entire in clock hierarchy to 0 Hz.
Suggested-by: Dmitry Baryshkov
Link:
https://lore.kernel.org/r/sz4kbwy5nwsebgf64ia7uq4ee7wbsa5uy3xmlqwcstsbntzcov@ew3dcyjdzmi2/
Signed-off-by: Krzysztof Kozlowski
---
Not tested on
ing PHY, while specifying two lets the driver
> choose one PHY for output. This rule also applies to extcon, which
> provides the cable state for the corresponding PHY.
>
> Signed-off-by: Chaoyi Chen
> ---
>
Reviewed-by: Krzysztof Kozlowski
Best regards,
Krzysztof
On Mon, May 19, 2025 at 03:43:37PM GMT, Tomeu Vizoso wrote:
> +#endif
> diff --git a/drivers/accel/rocket/rocket_device.c
> b/drivers/accel/rocket/rocket_device.c
> new file mode 100644
> index
> ..bb469ac87d36249157f4ba9d9f7106ad558309e4
> --- /dev/null
>
> - Split register block in its constituent subblocks, and only require
> the ones that the kernel would ever use (Nicolas Frattaroli)
> - Group supplies (Rob Herring)
> - Explain the way in which the top core is special (Rob Herring)
>
> v4:
> - Change required node name
On Tue, May 20, 2025 at 10:47:18AM GMT, Chaoyi Chen wrote:
> + interrupts:
> +maxItems: 1
> +
> + phys:
> +minItems: 1
> +items:
> + - description: DP output to the DP PHY device 0
> + - description: DP output to the DP PHY deivce 1
Typo here.
> +description: |
> +
On 17/05/2025 02:08, Jessica Zhang wrote:
>
>
> On 4/30/2025 6:00 AM, Krzysztof Kozlowski wrote:
>> Hi,
>>
>> Dependency / Rabased on top of
>> ==
>> https://lore.kernel.org/all/20241214-dpu-drop-features-v1-0-988f0662c...@linar
On 05/05/2025 23:28, Abhinav Kumar wrote:
>>> static int dsi_clk_init(struct msm_dsi_host *msm_host)
>>> {
Dmitry,
Please kindly trim the replies from unnecessary context. It makes it
much easier to find new content.
>>> struct platform_device *pdev = msm_host->pdev;
>>> @@ -370,6 +411,4
On 19/05/2025 10:27, Tomeu Vizoso wrote:
> On Mon, May 19, 2025 at 8:08 AM Krzysztof Kozlowski wrote:
>>
>> On 16/05/2025 18:53, Tomeu Vizoso wrote:
>>> See Chapter 36 "RKNN" from the RK3588 TRM (Part 1).
>>>
>>> This is a derivative of NVID
On Mon, May 19, 2025 at 02:56:03PM GMT, Chaoyi Chen wrote:
> Hi Krzysztof,
>
> On 2025/5/19 14:16, Krzysztof Kozlowski wrote:
> > On 19/05/2025 03:26, Chaoyi Chen wrote:
> > > +maintainers:
> > > + - Andy Yan
> > > + - Heiko Stuebner
&g
different sources.
>
> Reviewed-by: Krzysztof Kozlowski
>
No blank line between tags, wrong order of tags.
> Signed-off-by: Nancy Lin
If you are the author, what does this SoB mean? When was this patch
written, by whom and when was the review given?
Can you start using b4?
Y
On Thu, May 15, 2025 at 05:34:16PM GMT, paul-pl.chen wrote:
> From: Paul-pl Chen
>
> Add mediate,outproc.yaml to support OUTPROC for MT8196.
> MediaTek display overlap output processor, namely OVL_OUTPROC
> or OUTPROC,handles the post-stage of pixel processing in the
> overlapping procedure.
>
>
On 19/05/2025 03:26, Chaoyi Chen wrote:
> +maintainers:
> + - Andy Yan
> + - Heiko Stuebner
> + - Sandy Huang
> +
> +allOf:
> + - $ref: /schemas/sound/dai-common.yaml#
> +
> +properties:
> + compatible:
> +items:
> + - const: rockchip,rk3399-cdn-dp
> +
> + reg:
> +maxItems: 1
On 16/05/2025 18:53, Tomeu Vizoso wrote:
> See Chapter 36 "RKNN" from the RK3588 TRM (Part 1).
>
> This is a derivative of NVIDIA's NVDLA, but with its own front-end
> processor.
>
> The IP is divided in three cores, programmed independently. The first
> core though is special, requiring to be po
On 16/05/2025 18:53, Tomeu Vizoso wrote:
> Add the bindings for the Neural Processing Unit IP from Rockchip.
>
> v2:
> - Adapt to new node structure (one node per core, each with its own
> IOMMU)
> - Several misc. fixes from Sebastian Reichel
>
> v3:
> - Split register block in its constituent
On 15/05/2025 14:35, long.yunj...@zte.com.cn wrote:
> From: Yumeng Fang
>
> In the probe path, dev_err() can be replaced with dev_err_probe()
That's not probe path. I am not sure if you really understand this code.
> which will check if error code is -EPROBE_DEFER and prints the
> error name. I
On Wed, Apr 23, 2025 at 12:31:29AM GMT, Danila Tikhonov wrote:
> description:
> - Qualcomm SC7180/SC7280 SoC Peripheral Authentication Service loads and
> boots
> - firmware on the Qualcomm DSP Hexagon cores.
> + Qualcomm SC7180/SC7280/SM7150 SoC Peripheral Authentication Service loads
> and
On Wed, Apr 23, 2025 at 12:31:30AM GMT, Danila Tikhonov wrote:
> Add DSP Peripheral Authentication Service support for the SM7150
> platform.
>
> Signed-off-by: Danila Tikhonov
> ---
> drivers/remoteproc/qcom_q6v5_pas.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/remotep
> .../devicetree/bindings/clock/qcom,gpucc.yaml | 29 +++
> 1 file changed, 17 insertions(+), 12 deletions(-)
>
Reviewed-by: Krzysztof Kozlowski
Best regards,
Krzysztof
On Wed, Apr 23, 2025 at 12:31:27AM GMT, Danila Tikhonov wrote:
> Document the SM7150 SMMU block.
>
> Signed-off-by: Danila Tikhonov
> ---
> Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 3 +++
> 1 file changed, 3 insertions(+)
>
Reviewed-by: Krzysztof Koz
On Wed, Apr 23, 2025 at 12:31:25AM GMT, Danila Tikhonov wrote:
> Update the documentation for clock rpmh driver on SM7150 SoCs.
>
> Signed-off-by: Danila Tikhonov
> ---
> .../bindings/clock/qcom,rpmhcc.yaml | 53 ++-
> 1 file changed, 29 insertions(+), 24 deletions(-)
>
On Wed, Apr 23, 2025 at 12:31:24AM GMT, Danila Tikhonov wrote:
> Add the SM7150 CCI device string compatible.
>
> Signed-off-by: Danila Tikhonov
> ---
> Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml | 2 ++
> 1 file changed, 2 insertions(+)
Reviewed-by: Krzyszto
ee/bindings/display/msm/gmu.yaml | 34
> ++
> 1 file changed, 34 insertions(+)
Reviewed-by: Krzysztof Kozlowski
Best regards,
Krzysztof
On 09/05/2025 09:34, Chaoyi Chen wrote:
> Hi Krzysztof,
>
> On 2025/5/9 15:11, Krzysztof Kozlowski wrote:
>> On 09/05/2025 09:02, Chaoyi Chen wrote:
>>> +
>>> + clock-names:
>>> +items:
>>> + - const: core-clk
>>> + - c
On 09/05/2025 09:02, Chaoyi Chen wrote:
> +
> + clock-names:
> +items:
> + - const: core-clk
> + - const: pclk
> + - const: spdif
> + - const: grf
> +
> + extcon:
> +$ref: /schemas/types.yaml#/definitions/phandle-array
> +description:
> + Phandle to the extcon
On 08/05/2025 18:19, Akhil P Oommen wrote:
> From: Jie Zhang
>
> Enable GPU for qcs8300-ride platform and provide path for zap
> shader.
>
> Signed-off-by: Jie Zhang
> Signed-off-by: Akhil P Oommen
> Reviewed-by: Dmitry Baryshkov
Is this also real review or you took it from entirely differen
On 08/05/2025 18:19, Akhil P Oommen wrote:
> From: Jie Zhang
>
> Document Adreno 623 GMU in the dt-binding specification.
>
> Signed-off-by: Jie Zhang
> Signed-off-by: Akhil P Oommen
> Reviewed-by: Krzysztof Kozlowski
Drop. You changed patch significantly, like 90%!
&g
Add driver for the Novatek NT37801 or NT37810 AMOLED DSI 1440x3200
panel in CMD mode, used on Qualcomm MTP8750 board (SM8750).
Reviewed-by: Neil Armstrong
Reviewed-by: Linus Walleij
Signed-off-by: Krzysztof Kozlowski
---
MAINTAINERS | 6 +
drivers/gpu/drm
Add bindings for the Novatek NT37801 or NT37810 AMOLED DSI panel.
Sources, like downstream DTS, schematics and hardware manuals, use two
model names (NT37801 and NT37810), so choose one and hope it is correct.
Reviewed-by: Linus Walleij
Signed-off-by: Krzysztof Kozlowski
---
.../bindings
board (SM8750).
Best regards,
Krzysztof
---
Krzysztof Kozlowski (2):
dt-bindings: display: panel: Add Novatek NT37801
drm/panel: Add Novatek NT37801 panel driver
.../bindings/display/panel/novatek,nt37801.yaml| 69 +
MAINTAINERS| 6
On 08/05/2025 14:54, Linus Walleij wrote:
> (...)
>> +static int novatek_nt37801_on(struct novatek_nt37801 *ctx)
>> +{
>> + struct mipi_dsi_device *dsi = ctx->dsi;
>> + struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi };
>> +
>> + dsi->mode_flags |= MIPI_DSI_MODE_LPM;
>> +
>>
On Wed, May 07, 2025 at 03:19:19PM GMT, Chris Morgan wrote:
> From: Chris Morgan
>
> I've spoken with Ryan and he agreed to let me take over this series to
> get the display engine working on the Allwinner H616. I've taken his
> previous patch series for Display Engine 3.3 and combined it with th
On 08/05/2025 08:43, Chaoyi Chen wrote:
> From: Chaoyi Chen
>
> Convert cdn-dp-rockchip.txt to yaml.
>
> Tested with:
>
> 1. make ARCH=arm64 dt_binding_check
> DT_SCHEMA_FILES=Documentation/devicetree/bindings/display/rockchip/rockchip,cdn-dp.yaml
>
> 2. make ARCH=arm64 dtbs_check
> DT_SCHEM
On 23/04/2025 04:46, Abhinav Kumar wrote:
> Hi Krzysztof
>
> On 12/3/2024 12:04 AM, Krzysztof Kozlowski wrote:
>> On 03/12/2024 04:31, Abhinav Kumar wrote:
>>> On some chipsets the display port controller can support more
>>
>> Which chipsets?
>>
>
On 05/05/2025 15:58, Neil Armstrong wrote:
>> +dsi->lanes = 4;
>> +dsi->format = MIPI_DSI_FMT_RGB888;
>> +dsi->mode_flags = MIPI_DSI_MODE_NO_EOT_PACKET |
>> MIPI_DSI_CLOCK_NON_CONTINUOUS;
>> +
>> +drm_panel_init(&ctx->panel, dev, &novatek_nt37801_panel_funcs,
>> +
Add driver for the Novatek NT37801 or NT37810 AMOLED DSI panel, used on
Qualcomm MTP8750 board (SM8750).
Best regards,
Krzysztof
---
Krzysztof Kozlowski (2):
dt-bindings: display: panel: Add Novatek NT37801
drm/panel: Add Novatek NT37801 panel driver
.../bindings/display/panel
Add driver for the Novatek NT37801 or NT37810 AMOLED DSI 1440x3200
panel in CMD mode, used on Qualcomm MTP8750 board (SM8750).
Signed-off-by: Krzysztof Kozlowski
---
MAINTAINERS | 6 +
drivers/gpu/drm/panel/Kconfig | 10 +
drivers/gpu/drm
Add bindings for the Novatek NT37801 or NT37810 AMOLED DSI panel.
Sources, like downstream DTS, schematics and hardware manuals, use two
model names (NT37801 and NT37810), so choose one and hope it is correct.
Signed-off-by: Krzysztof Kozlowski
---
.../bindings/display/panel/novatek,nt37801
On 03/05/2025 00:52, Dmitry Baryshkov wrote:
> On Wed, Apr 30, 2025 at 03:00:49PM +0200, Krzysztof Kozlowski wrote:
>> Add support for DSI on Qualcomm SM8750 SoC with notable difference:
>>
>> DSI PHY PLLs, the parents of pixel and byte clocks, cannot be used as
>>
On 03/05/2025 00:44, Dmitry Baryshkov wrote:
> On Wed, Apr 30, 2025 at 03:00:45PM +0200, Krzysztof Kozlowski wrote:
>> Add bitfields for PHY_CMN_CTRL_0 registers to avoid hard-coding bit
>> masks and shifts and make the code a bit more readable.
>>
>> Signed-
On 03/05/2025 00:42, Dmitry Baryshkov wrote:
> On Wed, Apr 30, 2025 at 03:00:36PM +0200, Krzysztof Kozlowski wrote:
>> On SM8750 the setting rate of pixel and byte clocks, while the parent
>> DSI PHY PLL, fails with:
>>
>> disp_cc_mdss_byte0_clk_src: rcg didn
Resetting mixers should also include resetting active fetch pipes.
Fixes: ae4d721ce100 ("drm/msm/dpu: add an API to reset the encoder related hw
blocks")
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Krzysztof Kozlowski
---
Changes in v3:
1. New patch, split from previous big
On 30/04/2025 15:00, Krzysztof Kozlowski wrote:
>
> @@ -361,21 +373,46 @@ static int dsi_pll_7nm_lock_status(struct dsi_pll_7nm
> *pll)
>
> static void dsi_pll_disable_pll_bias(struct dsi_pll_7nm *pll)
> {
> - u32 data = readl(pll->phy->base +
v12.0 DPU on SM8750 comes with 10-bit color alpha. Add register
differences and new implementations of setup_alpha_out(),
setup_border_color() and setup_blend_config().
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Krzysztof Kozlowski
---
Changes in v4:
1. Lowercase hex, use spaces for define
Add support for the Qualcomm SM8750 platform.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Krzysztof Kozlowski
---
drivers/gpu/drm/msm/msm_mdss.c | 33 +
drivers/gpu/drm/msm/msm_mdss.h | 1 +
2 files changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/msm
: Krzysztof Kozlowski
---
Changes in v4:
1. Lowercase hex
2. Add Dmitry's tag
Changes in v3:
1. New patch, split from previous big DPU v12.0.
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 18 +++-
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 6 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_
v12.0 DPU on SM8750 comes with new CTL_PIPE_ACTIVE register for
selective activation of pipes, which replaces earlier
dpu_hw_ctl_setup_blendstage() code path for newer devices.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Krzysztof Kozlowski
---
Changes in v4:
1. Lowercase hex
2. Add Dmitry&#
responsible for reparenting clocks with proper
procedure: see dsi_clk_init_6g_v2_9().
Signed-off-by: Krzysztof Kozlowski
---
Changes in v5:
1. Only reparent byte and pixel clocks while PLLs is prepared. Setting
rate works fine with earlier DISP CC patch for enabling their parents
during
Add DPU version v12.0 support for the Qualcomm SM8750 platform.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Krzysztof Kozlowski
---
Changes in v2:
1. Add CDM
---
.../drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h| 496 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
L was not configured configure it to minimum rate to avoid glitches
and configuring entire in clock hierarchy to 0 Hz.
Signed-off-by: Krzysztof Kozlowski
---
Changes in v5:
1. New patch
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/dr
MDSS/MDP v12 comes with new bits in flush registers (e.g.
MDP_CTL_0_FLUSH) for Layer Mixer 6 and 7.
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Jessica Zhang
Signed-off-by: Krzysztof Kozlowski
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 6 ++
1 file changed, 6 insertions(+)
diff
The set_active_pipes() callback configures CTL_FETCH_PIPE_ACTIVE and
newer DPU v12.0 comes with CTL_PIPE_ACTIVE, thus rename it to
set_active_fetch_pipes() to better match the purpose.
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Jessica Zhang
Signed-off-by: Krzysztof Kozlowski
---
Changes in
but keep them commented
out to avoid conflict.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Krzysztof Kozlowski
---
Changes in v2:
1. Fix pll freq check for clock inverters
16000ULL -> 16300ULL
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 +
drivers/gpu/drm/msm/
Drop comments about SoC before each 'struct dpu_lm_sub_blks' for given
SoC because it's duplicating the actual name of structure.
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Jessica Zhang
Signed-off-by: Krzysztof Kozlowski
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 8 -
.recalc_rate() did not show up on existing
devices, but only after re-ordering the code for SM8750.
Signed-off-by: Krzysztof Kozlowski
---
Changes in v5:
1. New patch
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 +
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 59
Before blend setup, all existing blend stages are cleared, so shall be
active fetch pipes.
Fixes: b3652e87c03c ("drm/msm/disp/dpu1: add support to program fetch active in
ctl path")
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Krzysztof Kozlowski
---
Changes in v3:
1. New patch,
.
Signed-off-by: Krzysztof Kozlowski
---
Changes in v5:
1. New patch
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
index
Add bitfields for PHY_CMN_CTRL_0 registers to avoid hard-coding bit
masks and shifts and make the code a bit more readable.
Signed-off-by: Krzysztof Kozlowski
---
Changes in v5:
1. New patch
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 9 ++---
drivers/gpu/drm/msm
Add MDSS/MDP display subsystem for Qualcomm SM8750 SoC, next generation
with two revisions up of the IP block comparing to SM8650.
Reviewed-by: Rob Herring (Arm)
Signed-off-by: Krzysztof Kozlowski
---
Changes in v3:
1. Properly described interconnects
2. Use only one compatible and contains
Add IDs for new blocks present in MDSS/MDP v12 for LM, DSC, PINGPONG and
MERGE_3D blocks.
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Jessica Zhang
Signed-off-by: Krzysztof Kozlowski
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a
Resetting entire CTL path should also include resetting active fetch
pipes.
Fixes: e1a950eec256 ("drm/msm/dpu: add reset_intf_cfg operation for dpu_hw_ctl")
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Krzysztof Kozlowski
---
Changes in v3:
1. New patch, split from previous big
Baryshkov
Signed-off-by: Krzysztof Kozlowski
---
Changes in v3:
1. Extend commit msg
---
Documentation/devicetree/bindings/display/msm/dp-controller.yaml | 4
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
b/Documentation
Add DPU for Qualcomm SM8750 SoC which has several differences, new
blocks and changes in registers, making it incompatible with SM8650.
Acked-by: Rob Herring (Arm)
Signed-off-by: Krzysztof Kozlowski
---
Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml | 1 +
1 file changed, 1
S_PARENT_ENABLE to ensure the parent is
enabled during rate changes.
Signed-off-by: Krzysztof Kozlowski
---
Patch is independent and can go via separate tree. Including here for
complete picture of clock debugging issues.
Changes in v5:
1. New patch
---
drivers/clk/qcom/dispcc-sm8750.c | 4 ++--
Add DSI PHY v7.0 for Qualcomm SM8750 SoC which is quite different from
previous (SM8650) generation.
Acked-by: Rob Herring (Arm)
Signed-off-by: Krzysztof Kozlowski
---
Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a
mpatible with SM8650.
Reviewed-by: Rob Herring (Arm)
Signed-off-by: Krzysztof Kozlowski
---
.../bindings/display/msm/dsi-controller-main.yaml | 54 --
1 file changed, 49 insertions(+), 5 deletions(-)
diff --git
a/Documentation/devicetree/bindings/display/msm/dsi-con
Drop SSPP_VIG4 comments
- DPU: Add CDM
- Link to v1:
https://lore.kernel.org/r/20250109-b4-sm8750-display-v1-0-b3f15faf4...@linaro.org
Best regards,
Krzysztof
---
Krzysztof Kozlowski (24):
dt-bindings: display/msm: dsi-phy-7nm: Add SM8750
dt-bindings: display/msm: dsi-controller-main:
> 1 file changed, 65 insertions(+)
Reviewed-by: Krzysztof Kozlowski
Best regards,
Krzysztof
On 28/04/2025 20:13, barnabas.cze...@mainlining.org wrote:
>>
>>> +
>>> +required:
>>> + - compatible
>>> + - reg
>>> + - reset-gpios
>>
>> No supplies? This looks really incomplete.
> It works without supplies because BL is enabling them and there is no
> qpnp-lcdb driver yet.
If something en
On Sun, Apr 27, 2025 at 11:11:11AM GMT, Barnabás Czémán wrote:
> Document BOE TD4320 6.3" 2340x1080 panel
> found in Xiaomi Redmi Note 7 smartphone.
>
> Signed-off-by: Barnabás Czémán
> ---
> .../bindings/display/panel/boe,td4320.yaml | 55
> ++
> 1 file changed, 55
On Thu, Apr 24, 2025 at 05:07:40PM GMT, Kory Maincent wrote:
> Add the data-lanes property to specify the number of DSI lanes used by the
> panel. This allows configuring the panel for either two, three or four
> lanes.
That's the property of DSI controller, not the panel. I do not
understand why
On Thu, Apr 24, 2025 at 05:07:39PM GMT, Kory Maincent wrote:
> Faced a binding error check while adding the data-lanes property in the
> ilitek,ili9881c binding. See the next patch for the binding changes.
> Here is the error:
> Documentation/devicetree/bindings/display/panel/ilitek,ili9881c.exampl
On 24/04/2025 12:54, Jayesh Choudhary wrote:
> For TI SoC J784S4, the display pipeline looks like:
> TIDSS -> CDNS-DSI -> SN65DSI86 -> DisplayConnector -> DisplaySink
> This requires HPD to detect connection form the connector.
> By default, the HPD is disabled for eDP. So enable it conditionally
>
On Thu, Apr 24, 2025 at 09:08:49AM GMT, Jianeng Ceng wrote:
> Ponyta is a custom label Chromebook based on MT8186. It is a
> self-developed project of Huaqin and has no fixed OEM.
>
> Signed-off-by: Jianeng Ceng
> ---
Acked-by: Krzysztof Kozlowski
---
This is an automated in
On 22/04/2025 22:17, Danila Tikhonov wrote:
> This patch series adds support for the Qualcomm Snapdragon 730/730G/732G
> (SM7150) platform along with the Google Pixel 4a (sunfish) device. Since
> the most critical drivers were submitted and applied in separate patch
> series, this series is largely
include/dt-bindings/clock/qcom,gcc-msm8917.h | 19
> +++
> 2 files changed, 27 insertions(+), 3 deletions(-)
Reviewed-by: Krzysztof Kozlowski
Best regards,
Krzysztof
../bindings/opp/opp-v2-qcom-adreno.yaml | 96
> ++
> MAINTAINERS | 1 +
> 2 files changed, 97 insertions(+)
Reviewed-by: Krzysztof Kozlowski
Best regards,
Krzysztof
On 17/04/2025 13:12, Konrad Dybcio wrote:
> On 4/17/25 8:03 AM, Krzysztof Kozlowski wrote:
>> On Thu, Apr 17, 2025 at 02:16:31AM GMT, Dmitry Baryshkov wrote:
>>> From: Dmitry Baryshkov
>>>
>>> Describe DisplayPort controller present on Qualcomm SAR2130P pla
osts and single DisplayPort
> controller.
>
> Signed-off-by: Dmitry Baryshkov
> Reviewed-by: Krzysztof Kozlowski
> Signed-off-by: Dmitry Baryshkov
All three possible identies...
Best regards,
Krzysztof
On Thu, Apr 17, 2025 at 02:16:31AM GMT, Dmitry Baryshkov wrote:
> From: Dmitry Baryshkov
>
> Describe DisplayPort controller present on Qualcomm SAR2130P platform.
>
> Signed-off-by: Dmitry Baryshkov
Addresses do not match. You re-authored the commit, so now everywhere is
mess.
Best regards,
On 17/04/2025 07:39, Ayushi Makhija wrote:
> From: Ayushi Makhija
>
> Document DSI controller and phy on SA8775P platform.
>
> Signed-off-by: Ayushi Makhija
Reviewed-by: Krzysztof Kozlowski
Best regards,
Krzysztof
On 15/04/2025 07:58, Marcus Folkesson wrote:
> This series add support for the ST7571 LCD Controller.
> It is a 4 gray scale dot matrix LCD controller that supports several
> interfaces such as SPI, I2C and a 8bit parallell port.
> The controlelr supports both monochrome and grayscale displays.
>
On 15/04/2025 07:58, Marcus Folkesson wrote:
> Sitronix ST7571 is a dot matrix LCD controller supporting
> both 4bit grayscale and monochrome LCDs.
>
> Signed-off-by: Marcus Folkesson
> ---
Reviewed-by: Krzysztof Kozlowski
Best regards,
Krzysztof
On 15/04/2025 07:58, Marcus Folkesson wrote:
> +title: Sitronix ST7571 Display Controller
> +
> +maintainers:
> + - Marcus Folkesson
> +
> +description:
> + Sitronix ST7571 is a driver and controller for 4-level gray
> + scale and monochrome dot matrix LCD panels.
> +
> +allOf:
> + - $ref: pan
On 08/04/2025 12:38, Ayushi Makhija wrote:
>>> +properties:
>>> + compatible:
>>> +items:
>>
>> contains
>>
>>> + - const: qcom,sa8775p-dsi-ctrl
>>> + - const: qcom,mdss-dsi-ctrl
>>
>> Drop fallback
>>
>
> Hi Krzysztof,
>
> I couldn't understand the meaning of
On Wed, Apr 09, 2025 at 11:00:32PM GMT, Nipun Gupta wrote:
> The AMD PKI accelerator driver provides a accel interface to interact
> with the device for offloading and accelerating asymmetric crypto
> operations.
>
For me this is clearly a crypto driver and you are supposed to:
1. Cc crypto maint
On Wed, Apr 09, 2025 at 11:00:31PM GMT, Nipun Gupta wrote:
> Add binding documentation for AMD PKI accelerator supported for AMD
> versal-net SoC.
>
A nit, subject: drop second/last, redundant "device tree for". The
"dt-bindings" prefix is already stating that these are bindings.
See also:
https:/
On 09/04/2025 17:24, Dmitry Baryshkov wrote:
> On 09/04/2025 09:07, Krzysztof Kozlowski wrote:
>> On 08/04/2025 22:26, Dmitry Baryshkov wrote:
>>>>>>>>> + - const: qcom,sa8775p-dsi-ctrl
>>>>>>>>> +
rence, a SoC-specific compatible string
> 'renesas,r9a09g057-du' is added for the RZ/V2H(P) SoC.
>
> Signed-off-by: Lad Prabhakar
Reviewed-by: Krzysztof Kozlowski
Best regards,
Krzysztof
gt; Signed-off-by: Rob Herring (Arm)
> ---
> .../devicetree/bindings/display/rockchip/rockchip-vop.yaml | 6 --
> 1 file changed, 6 deletions(-)
Reviewed-by: Krzysztof Kozlowski
Best regards,
Krzysztof
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