On 05/05/2025 23:28, Abhinav Kumar wrote:
>>> static int dsi_clk_init(struct msm_dsi_host *msm_host)
>>> {
Dmitry,
Please kindly trim the replies from unnecessary context. It makes it
much easier to find new content.
>>> struct platform_device *pdev = msm_host->pdev;
>>> @@ -370,6 +411,46 @@ int dsi_link_clk_set_rate_6g(struct msm_dsi_host
>>> *msm_host)
>>> return 0;
>>> }
>>>
>>> +int dsi_link_clk_set_rate_6g_v2_9(struct msm_dsi_host *msm_host)
>>> +{
>>> + struct device *dev = &msm_host->pdev->dev;
>>> + int ret;
>>> +
>>> + /*
>>> + * DSI PHY PLLs have to be enabled to allow reparenting to them and
>>> + * setting the rates of pixel/byte clocks.
>>> + */
>>
>> According to the docs this should be handled by the
>> CLK_OPS_PARENT_ENABLE flag. Please correct me if I'm wrong.
>>
>
> I am also interested to know that if we are indeed setting
> CLK_OPS_PARENT_ENABLE flag, do we need this logic in the dsi driver.
>
> If CLK_OPS_PARENT_ENABLE flag is not working as expected, shouldnt this
> be something fixed on the clk fwk side?
>
You are both right - CLK_OPS_PARENT_ENABLE handles this and I just did
not test that exact case (fixed dispcc driver, here dropping
clk_prepare_enable).
Best regards,
Krzysztof
