On Sat, 26 Apr 2025 at 10:56, Linus Torvalds
wrote:
>
> On Fri, 25 Apr 2025 at 16:12, Dave Airlie wrote:
> >
> > Weekly drm fixes, mostly amdgpu, with some exynos cleanups and a
> > couple of minor fixes, seems a bit quiet, but probably some lag from
> > Easter holidays.
>
> Hmm. Is freedesktop.o
In preparation for making the kmalloc family of allocators type aware,
we need to make sure that the returned type from the allocation matches
the type of the variable being assigned. (Before, the allocator would
always return "void *", which can be implicitly cast to any pointer type.)
The assign
In preparation for making the kmalloc family of allocators type aware,
we need to make sure that the returned type from the allocation matches
the type of the variable being assigned. (Before, the allocator would
always return "void *", which can be implicitly cast to any pointer type.)
The assign
In preparation for making the kmalloc family of allocators type aware,
we need to make sure that the returned type from the allocation matches
the type of the variable being assigned. (Before, the allocator would
always return "void *", which can be implicitly cast to any pointer type.)
The assign
In preparation for making the kmalloc family of allocators type aware,
we need to make sure that the returned type from the allocation matches
the type of the variable being assigned. (Before, the allocator would
always return "void *", which can be implicitly cast to any pointer type.)
The assign
On Sat, Apr 12, 2025 at 09:00:47AM +0200, Thierry Reding wrote:
> From: Thierry Reding
>
> Recent generations of Tegra have moved the display components outside of
> host1x, leading to a device that has no CRTCs attached and hence doesn't
> support any of the modesetting functionality. When this
On Sun, Apr 20, 2025 at 05:12:43PM +0200, Luca Weiss wrote:
> Document two interconnect paths found on the MDSS on MSM8953.
>
> Acked-by: Rob Herring (Arm)
> Signed-off-by: Luca Weiss
> ---
> There's also some interconnect paths defined in the mdp5 schema, both
> drivers accept it. Newer mdss sc
From: Dmitry Baryshkov
Since SmartDMA planes provide two rectangles, it is possible to use them
to drive two different DRM planes, first plane getting the rect_0,
another one using rect_1 of the same SSPP. The sharing algorithm is
pretty simple, it requires that each of the planes can be driven b
On Thu, Apr 24, 2025 at 05:07:43PM +0200, Kory Maincent wrote:
> Add support for Saef Technology Limited SFTO340XC LCD panel.
>
> Signed-off-by: Kory Maincent
> ---
> drivers/gpu/drm/panel/panel-ilitek-ili9881c.c | 232
> ++
> 1 file changed, 232 insertions(+)
>
Review
On Thu, Apr 24, 2025 at 05:07:41PM +0200, Kory Maincent wrote:
> Enable support for two-lane configuration which is done by setting the
> LANSEL_SW_EN and LANSEL_SW bits in the Pad Control register.
>
> Use the data-lanes device tree parameter to configure the number of lanes.
> The default config
Hi Andy,
Responding to Mauro's cover-letter of v4 at:
https://lore.kernel.org/cover.1745453655.git.mchehab+hua...@kernel.org/
, which did not CC'd to you.
On Thu, 24 Apr 2025 08:16:20 +0800, Mauro Carvalho Chehab wrote:
> As reported by Andy, the Kernel build system runs kernel-doc script f
On Thu, 13 Mar 2025 11:43:15 + Alessandro Carminati
wrote:
> Some unit tests intentionally trigger warning backtraces by passing bad
> parameters to kernel API functions. Such unit tests typically check the
> return value from such calls, not the existence of the warning backtrace.
I've had
On Fri, Apr 25, 2025 at 02:01:25PM +0300, Tomi Valkeinen wrote:
> Add X403, a 3 plane 10 bits per component non-subsampled YCbCr format.
>
> Signed-off-by: Tomi Valkeinen
> ---
> drivers/gpu/drm/drm_fourcc.c | 3 +++
> include/uapi/drm/drm_fourcc.h | 9 +
> 2 files changed, 12 insertion
On Fri, Apr 25, 2025 at 01:26:58PM +0300, Cristian Ciocaltea wrote:
> Improve consistency throughout drm_hdmi_state_helper_test.c by replacing
> the two occurrences of '[_]MHz' substring with 'mhz'.
>
> As a bonus, this also helps getting rid of checkpatch.pl complaint:
>
> CHECK: Avoid CamelCa
On Fri, 25 Apr 2025 at 16:12, Dave Airlie wrote:
>
> Weekly drm fixes, mostly amdgpu, with some exynos cleanups and a
> couple of minor fixes, seems a bit quiet, but probably some lag from
> Easter holidays.
Hmm. Is freedesktop.org feeling a bit under the weather?
I'm getting
remote: GitLab i
On Fri, Apr 25, 2025 at 09:48:50PM +0200, David Hildenbrand wrote:
> On 25.04.25 21:31, Peter Xu wrote:
> > On Fri, Apr 25, 2025 at 10:17:06AM +0200, David Hildenbrand wrote:
> > > ... by factoring it out from track_pfn_remap().
> > >
> > > For PMDs/PUDs, actually check the full range, and trigger
Hi Linus,
Weekly drm fixes, mostly amdgpu, with some exynos cleanups and a
couple of minor fixes, seems a bit quiet, but probably some lag from
Easter holidays.
Dave.
drm-fixes-2025-04-26:
drm fixes for 6.15-rc4
amdgpu:
- P2P DMA fixes
- Display reset fixes
- DCN 3.5 fixes
- ACPI EDID fix
- LTT
On 4/25/2025 2:51 AM, Dmitry Baryshkov wrote:
From: Dmitry Baryshkov
LVDS support in MDP4 driver makes use of drm_connector directly. However
LCDC encoder and LVDS connector are wrappers around drm_panel. Switch
them to use drm_panel_bridge/drm_bridge_connector. This allows using
standard in
On Fri, Apr 25, 2025 at 01:01:10PM -0700, Abhinav Kumar wrote:
>
>
> On 4/25/2025 2:27 AM, Dmitry Baryshkov wrote:
> > On Fri, 25 Apr 2025 at 00:00, Abhinav Kumar
> > wrote:
> > >
> > >
> > >
> > > On 4/24/2025 3:23 AM, Dmitry Baryshkov wrote:
> > > > On Wed, Apr 23, 2025 at 07:04:16PM -0700
As seen in some recent failures, SLPC num_waiters value is < 0.
This happens because the inc/dec are not balanced. We should skip
decrement for the same conditions as the increment. Currently, we
do that for power saving profile mode. This patch also ensures that
num_waiters is incremented in the c
On 3/7/2025 9:38 PM, Dmitry Baryshkov wrote:
From: Dmitry Baryshkov
It is easy to skip or ignore the fact that the default SSPP feature
masks for SDM845+ don't include the SmartDMA bit (both during
development and during the review stage). Rename SSPP feature masks to
make it more explicit t
On 4/25/25 10:22 PM, barnabas.cze...@mainlining.org wrote:
> On 2025-04-25 21:26, Konrad Dybcio wrote:
>> On 4/25/25 5:13 PM, barnabas.cze...@mainlining.org wrote:
>>> On 2025-04-25 11:57, Konrad Dybcio wrote:
On 4/23/25 4:46 PM, barnabas.cze...@mainlining.org wrote:
> On 2025-04-23 16:03,
On Thu, Apr 24, 2025 at 08:16:23AM +0800 Mauro Carvalho Chehab wrote:
> As reported by Andy, kernel-doc.py is creating a __pycache__
> directory at build time.
>
> Disable creation of __pycache__ for the libraries used by
> kernel-doc.py, when excecuted via the build system or via
> scripts/find-u
Match what is declared as DPP color caps with hw caps. DCN401 has MPC
shaper+3D+blnd LUTs that are movable before and after blending (get from
plane or stream), but no DPP shaper+3D+blend LUTs.
Signed-off-by: Melissa Wen
---
.../gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c | 4 ++--
Color gamut_remap state log may be not avaiable for some hw versions, so
prevent null pointer dereference by checking it there is a function to
collect data for this hw version.
Signed-off-by: Melissa Wen
---
.../amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 26 +--
.../amd/display
On 3/7/2025 9:38 PM, Dmitry Baryshkov wrote:
From: Dmitry Baryshkov
Reworking of the catalog dropped the SmartDMA feature bit on the SC8180X
platform. Renable SmartDMA support on this SoC.
Fixes: 460c410f02e4 ("drm/msm/dpu: duplicate sdm845 catalog entries")
Signed-off-by: Dmitry Baryshkov
On 25.04.25 22:23, Peter Xu wrote:
On Fri, Apr 25, 2025 at 10:17:09AM +0200, David Hildenbrand wrote:
Let's use our new interface. In remap_pfn_range(), we'll now decide
whether we have to track (full VMA covered) or only sanitize the pgprot
(partial VMA covered).
Remember what we have to untra
On 3/7/2025 9:38 PM, Dmitry Baryshkov wrote:
From: Abhinav Kumar
In order to support more versatile configuration of the display pipes on
SM8550, enable SmartDMA for this platform.
Signed-off-by: Dmitry Baryshkov
With authorship fixed,
Reviewed-by: Jessica Zhang
---
.../gpu/drm/msm
On Thu, Apr 24, 2025 at 06:55:50PM -0700, Abhinav Kumar wrote:
>
>
> On 4/23/2025 10:52 AM, Dmitry Baryshkov wrote:
> > From: Dmitry Baryshkov
> >
> > The MSM DisplayPort driver implements several HDMI codec functions
> > in the driver, e.g. it manually manages HDMI codec device registration,
>
On 3/7/2025 9:38 PM, Dmitry Baryshkov wrote:
From: Abhinav Kumar
In order to support more versatile configuration of the display pipes on
SC8280XP, enable SmartDMA for this platform.
Signed-off-by: Dmitry Baryshkov
Hi Dmitry,
Seems like Abhinav's signed-off-by is missing for the patches
On Fri, Apr 25, 2025 at 10:17:09AM +0200, David Hildenbrand wrote:
> Let's use our new interface. In remap_pfn_range(), we'll now decide
> whether we have to track (full VMA covered) or only sanitize the pgprot
> (partial VMA covered).
>
> Remember what we have to untrack by linking it from the VM
On 2025-04-25 21:26, Konrad Dybcio wrote:
On 4/25/25 5:13 PM, barnabas.cze...@mainlining.org wrote:
On 2025-04-25 11:57, Konrad Dybcio wrote:
On 4/23/25 4:46 PM, barnabas.cze...@mainlining.org wrote:
On 2025-04-23 16:03, Konrad Dybcio wrote:
On 4/21/25 10:18 PM, Barnabás Czémán wrote:
From:
On Fri, Apr 25, 2025 at 11:34:18AM -0700, Jessica Zhang wrote:
>
>
> On 3/7/2025 9:38 PM, Dmitry Baryshkov wrote:
> > From: Abhinav Kumar
> >
> > In order to support more versatile configuration of the display pipes on
> > SC8280XP, enable SmartDMA for this platform.
> >
> > Signed-off-by: Dmi
On 4/25/2025 11:53 AM, Dmitry Baryshkov wrote:
On Fri, Apr 25, 2025 at 11:26:20AM -0700, Jessica Zhang wrote:
On 3/7/2025 9:38 PM, Dmitry Baryshkov wrote:
From: Dmitry Baryshkov
Reworking of the catalog dropped the SmartDMA feature bit on the SM8150
platform. Renable SmartDMA support on
On 4/25/2025 12:30 PM, Abhinav Kumar wrote:
On 4/25/2025 12:00 PM, Dmitry Baryshkov wrote:
On Fri, Apr 25, 2025 at 11:34:18AM -0700, Jessica Zhang wrote:
On 3/7/2025 9:38 PM, Dmitry Baryshkov wrote:
From: Abhinav Kumar
In order to support more versatile configuration of the display
p
On 25.04.25 22:00, Peter Xu wrote:
On Fri, Apr 25, 2025 at 10:17:08AM +0200, David Hildenbrand wrote:
Let's use the new, cleaner interface.
Signed-off-by: David Hildenbrand
---
mm/memremap.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/mm/memremap.c b/mm/memre
On Thu, Apr 17, 2025 at 04:10:35AM +0200, Aleksandrs Vinarskis wrote:
> DisplayPort requires per-segment link training when LTTPR are switched
> to non-transparent mode, starting with LTTPR closest to the source.
> Only when each segment is trained individually, source can link train
> to sink.
>
On 4/25/2025 2:27 AM, Dmitry Baryshkov wrote:
On Fri, 25 Apr 2025 at 00:00, Abhinav Kumar wrote:
On 4/24/2025 3:23 AM, Dmitry Baryshkov wrote:
On Wed, Apr 23, 2025 at 07:04:16PM -0700, Abhinav Kumar wrote:
On 2/26/2025 6:25 PM, Dmitry Baryshkov wrote:
LVDS support in MDP4 driver make
On Fri, Apr 25, 2025 at 10:17:08AM +0200, David Hildenbrand wrote:
> Let's use the new, cleaner interface.
>
> Signed-off-by: David Hildenbrand
> ---
> mm/memremap.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/mm/memremap.c b/mm/memremap.c
> index 2aebc1b192
Add missing DTN logs for DCN401 to improve debugging tools. There is no
DPP gamut_remap log: from `ddp_set_gamut_remap = NULL`, there is no DPP
gamut_remap. Also, log doesn't say anything yet about the position of
MPC shaper+3dlut+blndlut, that can be set before or after blending in
this hw versio
- track_pfn_insert(vma, &pgprot, pfn);
+ if (pfnmap_sanitize_pgprot(pfn_t_to_pfn(pfn), PAGE_SIZE, &pgprot))
+ return VM_FAULT_FALLBACK;
Would "pgtable" leak if it fails? If it's PAGE_SIZE, IIUC it won't ever
trigger, though.
Missed that comment. I can document that pgpr
On 4/25/2025 2:51 AM, Dmitry Baryshkov wrote:
From: Dmitry Baryshkov
The LVDS/LCDC controller uses pixel clock coming from the multimedia
controller (mmcc) rather than using the PLL directly. Stop using LVDS
PLL directly and register it as a clock provider. Use lcdc_clk as a
pixel clock for
In order to support more versatile configuration of the display pipes on
SM8550, enable SmartDMA for this platform.
Signed-off-by: Dmitry Baryshkov
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/
From: Dmitry Baryshkov
Reworking of the catalog dropped the SmartDMA feature bit on the SM8150
platform. Renable SmartDMA support on this SoC.
Fixes: 460c410f02e4 ("drm/msm/dpu: duplicate sdm845 catalog entries")
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0
From: Dmitry Baryshkov
It is easy to skip or ignore the fact that the default SSPP feature
masks for SDM845+ don't include the SmartDMA bit (both during
development and during the review stage). Rename SSPP feature masks to
make it more explicit that using non-SmartDMA masks should not be an
exce
From: Dmitry Baryshkov
Reworking of the catalog dropped the SmartDMA feature bit on the SC8180X
platform. Renable SmartDMA support on this SoC.
Fixes: 460c410f02e4 ("drm/msm/dpu: duplicate sdm845 catalog entries")
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_
In order to support more versatile configuration of the display pipes on
SC8280XP, enable SmartDMA for this platform.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/
It is easy to skip or ignore the fact that the default SSPP feature
masks for SDM845+ don't include the SmartDMA bit (both during
development and during the review stage).
Enable SmartDMA on SC8180X, SC8280XP, SM8150 and SM8550. Then rename
SSPP feature masks to make it more explicit that using no
On 25.04.25 21:31, Peter Xu wrote:
On Fri, Apr 25, 2025 at 10:17:06AM +0200, David Hildenbrand wrote:
... by factoring it out from track_pfn_remap().
For PMDs/PUDs, actually check the full range, and trigger a fallback
if we run into this "different memory types / cachemodes" scenario.
The cu
On Thu, Apr 24, 2025 at 11:58 PM Maxime Ripard wrote:
> On Thu, Apr 24, 2025 at 05:13:47PM -0700, John Stultz wrote:
> > On Thu, Apr 24, 2025 at 1:34 AM Maxime Ripard wrote:
> > > I appreciate this is kind of bikeshed-color territory, but I think "cma"
> > > would be a better option here. There's
On 4/25/2025 12:10 PM, Dmitry Baryshkov wrote:
On Thu, Apr 24, 2025 at 06:55:50PM -0700, Abhinav Kumar wrote:
On 4/23/2025 10:52 AM, Dmitry Baryshkov wrote:
From: Dmitry Baryshkov
The MSM DisplayPort driver implements several HDMI codec functions
in the driver, e.g. it manually manages H
On 4/11/25 09:34, Kuan-Wei Chiu wrote:
In either case, instead of packing the cascade into one function, make good
use of it.
In the latter case, __builtin_constant_p() isn't necessary as it puts the
onus on the architecture to separate out const and non-const cases, if it
matters -- which it d
On Tue, Apr 22, 2025 at 09:47:34AM +0200, Michal Wilczynski wrote:
>
>
> On 4/19/25 21:09, Drew Fustini wrote:
> > On Wed, Feb 19, 2025 at 03:02:38PM +0100, Michal Wilczynski wrote:
> >> T-HEAD TH1520 SoC requires to put the GPU out of the reset state as part
> >> of the power-up sequence.
> >>
>
On Fri, Apr 25, 2025 at 10:17:06AM +0200, David Hildenbrand wrote:
> ... by factoring it out from track_pfn_remap().
>
> For PMDs/PUDs, actually check the full range, and trigger a fallback
> if we run into this "different memory types / cachemodes" scenario.
The current patch looks like to still
On 4/25/2025 12:00 PM, Dmitry Baryshkov wrote:
On Fri, Apr 25, 2025 at 11:34:18AM -0700, Jessica Zhang wrote:
On 3/7/2025 9:38 PM, Dmitry Baryshkov wrote:
From: Abhinav Kumar
In order to support more versatile configuration of the display pipes on
SC8280XP, enable SmartDMA for this platf
On 4/25/25 5:13 PM, barnabas.cze...@mainlining.org wrote:
> On 2025-04-25 11:57, Konrad Dybcio wrote:
>> On 4/23/25 4:46 PM, barnabas.cze...@mainlining.org wrote:
>>> On 2025-04-23 16:03, Konrad Dybcio wrote:
On 4/21/25 10:18 PM, Barnabás Czémán wrote:
> From: Dang Huynh
>
> Add i
On Thu, Apr 17, 2025 at 04:10:34AM +0200, Aleksandrs Vinarskis wrote:
> Per-segment link training requires knowing the number of LTTPRs
> (if any) present. Store the count during LTTPRs' initialization.
>
> Signed-off-by: Aleksandrs Vinarskis
> ---
> drivers/gpu/drm/msm/dp/dp_display.c | 17
On Thu, Apr 24, 2025 at 10:28:58PM +0200, Konrad Dybcio wrote:
> On 4/23/25 5:23 PM, Dmitry Baryshkov wrote:
> > On 23/04/2025 17:55, Rob Clark wrote:
> >> On Tue, Apr 22, 2025 at 4:57 PM Konrad Dybcio
> >> wrote:
> >>>
> >>> On 4/21/25 10:13 PM, Rob Clark wrote:
> On Fri, Apr 18, 2025 at 9:0
On Fri, Apr 25, 2025 at 11:26:20AM -0700, Jessica Zhang wrote:
>
>
> On 3/7/2025 9:38 PM, Dmitry Baryshkov wrote:
> > From: Dmitry Baryshkov
> >
> > Reworking of the catalog dropped the SmartDMA feature bit on the SM8150
> > platform. Renable SmartDMA support on this SoC.
> >
> > Fixes: 460c41
On Tuesday, 25 February 2025 08:55:47 Central European Summer Time Tomeu Vizoso
wrote:
> Add the bindings for the Neural Processing Unit IP from Rockchip.
>
> v2:
> - Adapt to new node structure (one node per core, each with its own
> IOMMU)
> - Several misc. fixes from Sebastian Reichel
>
> S
On 3/7/2025 9:38 PM, Dmitry Baryshkov wrote:
From: Dmitry Baryshkov
Reworking of the catalog dropped the SmartDMA feature bit on the SM8150
platform. Renable SmartDMA support on this SoC.
Fixes: 460c410f02e4 ("drm/msm/dpu: duplicate sdm845 catalog entries")
Hi Dmitry,
The code LGTM, but
On Tuesday, 25 February 2025 08:55:50 Central European Summer Time Tomeu Vizoso
wrote:
> This initial version supports the NPU as shipped in the RK3588 SoC and
> described in the first part of its TRM, in Chapter 36.
>
> This NPU contains 3 independent cores that the driver can submit jobs
> to.
On 24/04/2025 07:08, Gregory Greenman wrote:
> Hello,
>
> I'm new to DRM developmentand ran into something in the Panfrost (but
> also Panthor) driver I'm curious about.
>
> In drivers/gpu/drm/panfrost/panfrost_gem.c, there's this line: obj-
>>base.map_wc = !pfdev->coherent;
>
> From what I can
On 4/25/2025 3:36 AM, Jacek Lawrynowicz wrote:
From: Karol Wachowski
The mutex unlock for vdev->submitted_jobs_lock was incorrectly placed
after unlocking file_priv->lock. Change order of unlocks to avoid potential
This should read "before unlocking", right?
race conditions.
Fixes: 5bbccad
On 4/25/2025 3:33 AM, Jacek Lawrynowicz wrote:
Fix deadlocks in ivpu_cmdq_create_ioctl() and ivpu_cmdq_destroy_ioctl()
related to runtime suspend.
Runtime suspend acquires file_priv->lock mutex by calling
ivpu_cmdq_reset_all_contexts(). The same lock is acquired in the cmdq
ioctls. If one of the
On April 25, 2025, 2:32 a.m. UTC Joel Fernandes wrote:
> Hello, Danilo,
>
> On April 24, 2025, 8:17 p.m. UTC Danilo Krummrich wrote:
> > On Thu, Apr 24, 2025 at 03:54:48PM -0400, Joel Fernandes wrote:
> > > On Wed, Apr 23, 2025 at 05:02:58PM +0200, Danilo Krummrich wrote:
> > > > On Wed, Apr 23,
On 4/25/2025 3:28 AM, Jacek Lawrynowicz wrote:
Increase JMS message state dump command timeout to 100 ms. On some
platforms, the FW may take a bit longer than 50 ms to dump its state
to the log buffer and we don't want to miss any debug info during TDR.
Fixes: 5e162f872d7a ("accel/ivpu: Add FW s
On 24/04/2025 16:10, Harry Wentland wrote:
On 2025-04-22 10:58, Melissa Wen wrote:
This reverts commit 272e6aab14bbf98d7a06b2b1cd6308a02d4a10a1.
Applying degamma curve to the cursor by default breaks Linux userspace
expectation.
On Linux, AMD display manager enables cursor degamma ROM just
On 2025-04-25 11:57, Konrad Dybcio wrote:
On 4/23/25 4:46 PM, barnabas.cze...@mainlining.org wrote:
On 2025-04-23 16:03, Konrad Dybcio wrote:
On 4/21/25 10:18 PM, Barnabás Czémán wrote:
From: Dang Huynh
Add initial support for MSM8937 SoC.
Signed-off-by: Dang Huynh
Co-developed-by: Barnabá
MEI GSC interrupt comes from i915. It has top half and bottom half.
Top half is called from i915 interrupt handler. It should be in
irq disabled context.
With RT kernel, by default i915 IRQ handler is in threaded IRQ. MEI GSC
top half might be in threaded IRQ context. generic_handle_irq_safe API
c
+ Thomas, AFAICT you are handling drm-misc-fixes this round - are you
okay to take this patch with Christian's rb?
Regards,
Tvrtko
On 23/04/2025 13:57, Christian König wrote:
On 4/22/25 17:10, Tvrtko Ursulin wrote:
On 22/04/2025 10:20, Koenig, Christian wrote:
[AMD Official Use Only - A
On 25/04/2025 15:30, Boris Brezillon wrote:
> On Fri, 25 Apr 2025 14:34:53 +0100
> Steven Price wrote:
>
>> On 17/03/2025 13:06, Thomas Zimmermann wrote:
>>> Instead of testing import_attach for imported GEM buffers, invoke
>>> drm_gem_is_imported() to do the test. The helper tests the dma_buf
>>
On Thu, Apr 24, 2025 at 11:07:33AM +0800, Wayne Lin wrote:
> [Why]
> Notice few problems under I2C-write-over-Aux with
> Write_Status_Update_Request flag set cases:
>
> - I2C-write-over-Aux request with
> Write_Status_Update_Request flag set won't get sent
> upon the reply of I2C_ACK|AUX_ACK f
On Fri, 25 Apr 2025 14:34:53 +0100
Steven Price wrote:
> On 17/03/2025 13:06, Thomas Zimmermann wrote:
> > Instead of testing import_attach for imported GEM buffers, invoke
> > drm_gem_is_imported() to do the test. The helper tests the dma_buf
> > itself while import_attach is just an artifact of
On Fri, Apr 25, 2025 at 11:48:31AM +0300, Jani Nikula wrote:
> On Thu, 24 Apr 2025, "Paul E. McKenney" wrote:
> > The i915_oa_stream_destroy() function directly accesses the
> > ratelimit_state structure's ->missed field, which work, but which also
> > makes it more difficult to change this field.
The client mask has been reduced from 8 bits on V3D 4.1 to 7 bits
on V3D 7.1, so the ranges for each client are not compatible.
On V3D 7.1, the CSD client can also report MMU errors.
Therefore, add its AXI ID to the IDs list.
Fixes: 0ad5bc1ce463 ("drm/v3d: fix up register addresses for V3D 7.x")
In the case of MMU errors caused by the TFU unit, the
client that causes the MMU error is expected to be reported.
But in the case of MMU TFU errors, a non existing client was
being reported. This happened because the client calculation
was taking into account more than the bits 0-7 from the
axi_id
ace xe_hmm with gpusvm
config: alpha-kismet-CONFIG_DRM_GPUSVM-CONFIG_DRM_XE-0-0
(https://download.01.org/0day-ci/archive/20250425/202504252124.jqdkibsg-...@intel.com/config)
reproduce:
(https://download.01.org/0day-ci/archive/20250425/202504252124.jqdkibsg-...@intel.com/reproduce)
If you fix the
On 3/26/25 20:47, Alex Hung wrote:
> It is to be used to enable HDR by allowing userpace to create and pass
> 3D LUTs to kernel and hardware.
>
> new drm_colorop_type: DRM_COLOROP_3D_LUT.
>
> Signed-off-by: Alex Hung
> ---
> v8:
> - Fix typo in subject (Simon Ser)
> - Update documentation f
Hi,
On Fri, 4 Apr 2025 at 16:31, Jens Wiklander wrote:
>
> Update the header files describing the secure world ABI, both with and
> without FF-A. The ABI is extended to deal with protected memory, but as
> usual backward compatible.
>
> Signed-off-by: Jens Wiklander
> ---
> drivers/tee/optee/op
On 17/03/2025 13:06, Thomas Zimmermann wrote:
> Instead of testing import_attach for imported GEM buffers, invoke
> drm_gem_is_imported() to do the test. The helper tests the dma_buf
> itself while import_attach is just an artifact of the import. Prepares
> to make import_attach optional.
>
> Sign
Hi,
On 20/04/2025 21:01, Aradhya Bhatia wrote:
Hi Tomi,
On 14/04/25 16:41, Tomi Valkeinen wrote:
The driver currently expects the pixel clock and the HS clock to be
compatible, but the DPHY PLL doesn't give very finely grained rates.
This often leads to the situation where the pipeline just fa
On 2025-04-25 20:04:43 [+0800], Junxiao Chang wrote:
> --- a/drivers/gpu/drm/i915/gt/intel_gsc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gsc.c
> @@ -284,7 +284,8 @@ static void gsc_irq_handler(struct intel_gt *gt, unsigned
> int intf_id)
> if (gt->gsc.intf[intf_id].irq < 0)
> ret
El 10/4/25 a las 14:31, Maíra Canal escribió:
Hi Chema,
On 09/04/25 12:55, Jose Maria Casanova Crespo wrote:
The client that causes an MMU error is expected to be reported.
But in the case of MMU TFU errors, a non existing client
"In the case of MMU errors caused by the TFU unit, [...]"
Mes
El 10/4/25 a las 14:40, Maíra Canal escribió:
Hi Chema,
On 09/04/25 12:55, Jose Maria Casanova Crespo wrote:
The client mask has been reduced from 8 bits on V3D 4.1 to 7 bits
on V3d 7.1, so the ranges for each client are not compatible.
s/V3d/V3D
Fixed.
A new CSD client can now report MMU
MEI GSC interrupt comes from i915. It has top half and bottom half.
Top half is called from i915 interrupt handler. It should be in
irq disabled context.
With RT kernel, by default i915 IRQ handler is in threaded IRQ. MEI GSC
top half might be in threaded IRQ context. generic_handle_irq_safe API
c
On Fri, 25 Apr 2025 14:01:23 +0300
Tomi Valkeinen wrote:
> Add greyscale Y8 format.
>
> Acked-by: Dmitry Baryshkov
> Signed-off-by: Tomi Valkeinen
> ---
> drivers/gpu/drm/drm_fourcc.c | 1 +
> include/uapi/drm/drm_fourcc.h | 10 ++
> 2 files changed, 11 insertions(+)
>
> diff --git
Hi,
On 20/04/2025 21:10, Aradhya Bhatia wrote:
Hi,
On 14/04/25 16:41, Tomi Valkeinen wrote:
The driver does all the calculations and programming with video timings
(hftp, hbp, etc.) instead of the modeline values (hsync_start, ...).
Thus it makes sense to use struct videomode instead of struct
On 2025/4/25 16:55, Jani Nikula wrote:
>> } else if (!strncmp(this_opt, "noscale", 7)) {
>> noscale = 1;
> A further cleanup could be to replace all of the strncmp's with
> str_has_prefix(this_opt, "...") to avoid this class of errors
> altogether. It also returns
Hello Krzysztof,
On 25/04/25 11:04, Krzysztof Kozlowski wrote:
On 24/04/2025 12:54, Jayesh Choudhary wrote:
For TI SoC J784S4, the display pipeline looks like:
TIDSS -> CDNS-DSI -> SN65DSI86 -> DisplayConnector -> DisplaySink
This requires HPD to detect connection form the connector.
By default
On 15/04/2025 23:10, Aradhya Bhatia wrote:
Hi Tomi,
On 14/04/25 16:41, Tomi Valkeinen wrote:
The driver tries to calculate the value for REG_WAKEUP_TIME. However,
the calculation itself is not correct, and to add on it, the resulting
value is almost always larger than the field's size, so the a
Add X403, a 3 plane 10 bits per component non-subsampled YCbCr format.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/drm_fourcc.c | 3 +++
include/uapi/drm/drm_fourcc.h | 9 +
2 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
Use drm helpers, drm_format_info_plane_width(),
drm_format_info_plane_height() and drm_format_info_min_pitch() to
calculate sizes for the DMA.
This cleans up the code, but also makes it possible to support more
complex formats (like XV15, XV20).
Reviewed-by: Laurent Pinchart
Signed-off-by: Tomi
Add greyscale Y8 format.
Acked-by: Dmitry Baryshkov
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/drm_fourcc.c | 1 +
include/uapi/drm/drm_fourcc.h | 10 ++
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index e101d1b99a
Add Y10_P32, a 10 bit greyscale format, with 3 pixels packed into
32-bit container.
The fourcc for the format is 'YPA4', which comes from Y - Y only, P -
packed, A - 10 (as in 0xA), 4 - 4 bytes.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/drm_fourcc.c | 3 +++
include/uapi/drm/drm_fourcc
Add support for XVUY2101010 format.
Reviewed-by: Laurent Pinchart
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/xlnx/zynqmp_disp.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c
b/drivers/gpu/drm/xlnx/zynqmp_disp.c
index b7cc7a7581ad..f548f37575
Add support for Y8 and Y10_P32 formats. We also need to add new csc
matrices for the y-only formats.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/xlnx/zynqmp_disp.c | 26 +-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xlnx/zynqmp_dis
Add support for XV15 & XV20 formats.
Reviewed-by: Laurent Pinchart
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/xlnx/zynqmp_disp.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c
b/drivers/gpu/drm/xlnx/zynqmp_disp.c
index b9883ea2d03e..1d
Add support for X403 format.
Reviewed-by: Laurent Pinchart
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/xlnx/zynqmp_disp.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c
b/drivers/gpu/drm/xlnx/zynqmp_disp.c
index fe111fa8cc13..b7cc7a7581ad 1006
Add XVUY2101010, a 10 bits per component YCbCr format in a 32 bit
container.
Reviewed-by: Laurent Pinchart
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/drm_fourcc.c | 1 +
include/uapi/drm/drm_fourcc.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/dr
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