On 24/04/2025 07:08, Gregory Greenman wrote: > Hello, > > I'm new to DRM developmentand ran into something in the Panfrost (but > also Panthor) driver I'm curious about. > > In drivers/gpu/drm/panfrost/panfrost_gem.c, there's this line: obj- >>base.map_wc = !pfdev->coherent; > > From what I can tell, this means when the CPU isn't coherent, it uses > write-combining mapping. > > I'm wondering why this approach instead of something like the > dma_sync_single_* functions at the appropriate places?
Because this memory is mapped into user space - and user space doesn't (want to) deal with coherency. So if the GPU is coherent with the CPU we can use cached memory (on the CPU) and everything is fine. If we don't have coherency then we fall back to a write-combining mapping on the CPU. If you've looked at the "kbase" kernel driver for the proprietary "DDK driver" from Arm then you'll see a different approach where ioctls are exported to user space to allow user space to perform the coherency management (using the dma_sync_single_* functions). But the benefits are minor and it comes with it's own set of problems (user space can deliberately make the memory incoherent and the kernel has to protect itself from that). There's also overhead calling into the kernel for this, so kbase also provides coherent (i.e. write-combining assuming the hardware isn't coherent) memory. Steve > Thanks, > > Gregory >
