From: Duke Zhai
1. Use HPET timer to replace 8254 timer
2.Fix Bug Microcode version cannot show correctly at BIOS setup
3.Enable capsule at linux build
4.Update FspWrapper UPD table for BIOS setup options
Duke Zhai (4):
AMD/AmdPlatformPkg: Use HpetTimerDxe to replace 8254Timer.
AMD/AmdPlatfo
From: Duke Zhai
BZ #:4718
As the new EDK2 no supports 8254 timer, so used HpetTimer to replace it.
Cc: Abner Chang
Cc: Igniculus Fu
Reviewed-by: Ken Yao
Reviewed-by: Eric Xing
Signed-off-by: Duke Zhai
---
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Project.dsc | 2 --
Platform/AMD/VanGoghBo
From: Duke Zhai
BZ #:4719
Microcode not load correct cause BIOS setup not show microcode version, modify
Microcode binary's instance to fixed this issue.
Cc: Abner Chang
Cc: Igniculus Fu
Reviewed-by: Ken Yao
Reviewed-by: Eric Xing
Signed-off-by: Duke Zhai
---
.../AMD/VanGoghBoard/Chachani
From: Duke Zhai
BZ #:4720
Linux build script include capsule build.
Fix winodws capsule build issue.
Cc: Abner Chang
Cc: Igniculus Fu
Reviewed-by: Ken Yao
Reviewed-by: Eric Xing
Signed-off-by: Duke Zhai
---
.../ChachaniBoardPkg/GenCapsule.bat | 2 +-
.../VanGoghBoard/ChachaniBoa
From: Duke Zhai
BZ #:4728
1.Remove useless options like I2C enable
2.Add new option:SocVoltage
Cc: Abner Chang
Cc: Igniculus Fu
Reviewed-by: Ken Yao
Reviewed-by: Eric Xing
Signed-off-by: Duke Zhai
---
.../edk2/Fsp2WrapperPkg/Include/FspmUpd.h | 71 ++-
.../FspWrapperPla
Ali, please also create PR in BaseTools repo.
Reviewed-by: Yuwei Chen
> -Original Message-
> From: S, Ashraf Ali
> Sent: Wednesday, February 28, 2024 5:57 PM
> To: devel@edk2.groups.io
> Cc: S, Ashraf Ali ; Rebecca Cran
> ; Liming Gao ; Feng, Bob
> C ; Chen, Christine ;
> Chaganty, Ranga
This patch set is the part 2 of enable LoongArch virtual machine and is
a continuation of the first patch series v8 submitted at:
https://edk2.groups.io/g/devel/message/114526.
Patch1-Patch4: Reorder some INF files located in UefiCpuPkg
alphabetically.
Patch5-Patch14: Added Timer, CpuMmuLib, CpuM
Some of the order is not in alphabetical, reorder.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4726
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Gerd Hoffmann
Signed-off-by: Chao Li
---
UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --
Some of the order is not in alphabetical, reorder.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4726
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Gerd Hoffmann
Signed-off-by: Chao Li
---
.../DxeCpuExceptionHandlerLib.inf | 20 +--
.../PeiCpuExceptionHandlerLib.inf
Some of the order is not in alphabetical, reorder.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4726
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Gerd Hoffmann
Signed-off-by: Chao Li
---
UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf | 28 +--
UefiCpuPkg/Library/MpInitLib/PeiMpInitLib
Some of the order is not in alphabetical, reorder.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4726
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Gerd Hoffmann
Signed-off-by: Chao Li
---
UefiCpuPkg/CpuDxe/CpuDxe.inf | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a
Add the LoongArch64 CPU Timer instance to CpuTimerLib, using CPUCFG 0x4
and 0x5 for Stable Counter frequency.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Gerd Hoffmann
Signed-off-by: Chao Li
---
.../Library/CpuTimerLib/BaseCpuTimerLib.inf | 15 +-
Added LoongArch exception handler into CpuExceptionHandlerLib.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Gerd Hoffmann
Signed-off-by: Chao Li
Co-authored-by: Baoqi Zhang
---
.../DxeCpuExceptionHandlerLib.inf | 23 +-
.../LoongArch/Dx
Add a new header file CpuMmuLib.h, whitch is referenced from
ArmPkg/Include/Library/ArmMmuLib.h. Currently, only support for
LoongArch64 is added, and more architectures can be accommodated in the
future.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Ger
Added PcdCpuExceptionVectorBaseAddress use for storing the CPU exception
vector base address. This PCD can be be populated at build time or
changed at runtime.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Gerd Hoffmann
Signed-off-by: Chao Li
---
Uefi
Added PcdCpuMmuIsEnabled to instruct that the CPU MMU is enabled.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Gerd Hoffmann
Signed-off-by: Chao Li
---
UefiCpuPkg/UefiCpuPkg.dec | 5 +
1 file changed, 5 insertions(+)
diff --git a/UefiCpuPkg/Uefi
Add a new base library named CpuMmuLib and add a LoongArch64 instance
with in the library.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Gerd Hoffmann
Signed-off-by: Chao Li
Co-authored-by: Baoqi Zhang
Co-authored-by: Dongyan Qian
Co-authored-by: Xia
This file provide the CPU MMU configure and initialize interface, it
will consumes by CpuMmuLib to configure or initialize the MMU.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Gerd Hoffmann
Cc: Leif Lindholm
Cc: Ard Biesheuvel
Cc: Sami Mujawar
Cc:
Add a new base library named CpuMmuInitLib and add a LoongArch64
instance with in the library.
It is the consumer of the CpuMmuLib.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Gerd Hoffmann
Signed-off-by: Chao Li
Co-authored-by: Baoqi Zhang
Co-autho
Added LoongArch multiprocessor initialization instance into MpInitLib.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Gerd Hoffmann
Signed-off-by: Chao Li
---
UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf | 21 +-
.../Library/MpInitLib/LoongArch64/Dx
Added LoongArch64 CPU driver into CpuDxe.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Gerd Hoffmann
Signed-off-by: Chao Li
Co-authored-by: Baoqi Zhang
Co-authored-by: Dongyan Qian
---
UefiCpuPkg/CpuDxe/CpuDxe.inf | 23 +-
UefiCpuPkg/
Add a CPU timer driver named StableTimerDxe, which proviedes
EFI_TIMER_ARCH_PROTOCOL for LoongArch.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Cc: Bibo Mao
Cc: Dongyan Qian
Signed-off-by: Chao Li
Co-authored
This Library is used to collect APs resources, but is currently NULL
for OvmfPkg, because it is not used by the LoongArch virtual machine.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Cc: Bibo Mao
Cc: Dongyan Qi
Add a serial port hook library in LoongArchVirt named
Fdt16550SerialProtHookLib, this library is referenced from ArmVirtPkg.
LoongArch QEMU virtual machine uses register of LOONGARCH_CSR_KS1 to
transfer serial port base addres from the PEI phase to the DXE phase.
BZ: https://bugzilla.tianocore.or
Add a early serial port output library into LoongArchVirt that named
EarlyFdtSerialPortLib16550, this library is referenced from
MdeModulePkg.
This library is used in the PEI phase. Since the serial port address can
not be saved in memory of the LoongArch QEMU virtual machine in the PEI
phase, the
This library is provides real time clock for LoongArch virtual machine.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Cc: Bibo Mao
Cc: Dongyan Qian
Signed-off-by: Chao Li
Co-authored-by: Baoqi Zhang
Co-authore
Add NorFlashQemuLib for LoongArch, it is referenced from ArmVirtPkg.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Cc: Bibo Mao
Cc: Dongyan Qian
Signed-off-by: Chao Li
Co-authored-by: Xianglai Li
Co-authored-b
This library for PEI phase, and obtains the QemuFwCfg base address by
directly parsing the FDT, reads and writes the data in QemuFwCfg by
operating on the QemuFwCfg base address.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Ger
This library provides interface related to restart and shudown the
LoongArch64 virtual machine.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Cc: Bibo Mao
Cc: Dongyan Qian
Signed-off-by: Chao Li
Co-authored-by:
Add SEC code for LoongArch virtual machine.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Cc: Bibo Mao
Cc: Dongyan Qian
Signed-off-by: Chao Li
Co-authored-by: Xianglai Li
Co-authored-by: Bibo Mao
Reviewed-by:
Platfrom PEI module for LoongArch platfrom initialization.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Cc: Bibo Mao
Cc: Dongyan Qian
Signed-off-by: Chao Li
Co-authored-by: Xianglai Li
Co-authored-by: Bibo Ma
Add infrastructure files to build edk2 for LoongArch QEMU virtual
machine.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Cc: Bibo Mao
Cc: Dongyan Qian
Signed-off-by: Chao Li
Co-authored-by: Xianglai Li
Co-auth
Add self introduction file for LoongArch virtual machine.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Cc: Bibo Mao
Cc: Dongyan Qian
Signed-off-by: Chao Li
Reviewed-by: Bibo Mao
---
OvmfPkg/LoongArchVirt/Rea
Thank you Laszlo.
Is ler...@redhat.com still reachable for now ? 😊
-Original Message-
From: devel@edk2.groups.io On Behalf Of gaoliming via
groups.io
Sent: Monday, March 11, 2024 8:22 AM
To: devel@edk2.groups.io; pedro.falc...@gmail.com; ler...@redhat.com
Cc: Kinney, Michael D ; 'Andrew
Thanks for the review.
I have triggered the PR under basetools :
https://github.com/tianocore/edk2-basetools/pull/122
Thanks.,
S, Ashraf Ali
-Original Message-
From: devel@edk2.groups.io On Behalf Of Yuwei Chen
Sent: Monday, March 11, 2024 1:22 PM
To: S, Ashraf Ali ; devel@edk2.groups.
Changes since V4:
- Addressed the comments shared by Levi for V3.
Changes since V3:
- Rebase on top of latest upstream branch.
Changes since V2:
- Removed author's signed-off on the patches, which is owned by another author.
Changes since V1:
- Corrected memory map in the DSDT file.
This patch
The reference design platform currently lacks the CPPC (Collaborative
Processor Performance Control) performance limited register as defined
by the ACPI 6.x specification. There is a typo in the macro definition
where the 'fastchannel address of the performance limited register' is
mentioned instea
From: Vivek Gautam
On RD-N2 and previous generation platforms, the base address was within
32-bit region. However, on upcoming platforms, the SMMUv3 base address
is beyond 32-bit address region. So, update the datatype of SMMUv3 base
PCD.
Signed-off-by: Prabin CA
---
Platform/ARM/SgiPkg/SgiPla
In preparation of adding the next generation of reference design
platform that have different memory map, refactor the
PcdSystemMemoryBase and PcdSystemMemorySize PCD definitions from the
common PCD definitions file into the various platform generation
specific memory map PCD definitions file.
Sig
Introducing a flag called PCIE_ENABLE, which can be set to TRUE or
FALSE from the respective .dsc files to enable or disable the
PCIe support. As not all reference design platforms have PCIe support
enabled, this flag is introduced.
Signed-off-by: Prabin CA
---
Platform/ARM/SgiPkg/SgiPlatform.de
From: Shriram K
RD-Fremont is the next platform in the Arm's reference design platform
series. This platform includes 32 CPUs but the fixed virtual platform
(FVP) simulates 16 CPUs of the platform. There is one CPU per cluster in
the system and so the FVP simulates 16 clusters. In preparation for
The RD-Fremont fixed virtual platform simulates 16 CPUs and 8GB of RAM.
Add initial support for this platform by adding the required platform
build configuration files. This platform has considerable differences in
its memory map compared to its predecessors. So add a corresponding
memory map file
Extend the SMBIOS support for RD-Fremont platform. RD-Fremont is a
16 core platform with Poseidon CPU. Each of the CPUs include
64KB L1 Data cache, 64KB L1 Instruction cache and 2MB L2 cache.
The platform also includes system level cache of 32MB and 8GB of RAM.
Signed-off-by: Prabin CA
---
Platf
RD-Fremont platform supports two LPI states, LPI1 (Standby WFI) and LPI3
(Power-down). The cluster supports LPI2 (Power-down) state. The LPI
implementation also supports combined power state for core and cluster.
Signed-off-by: Prabin CA
---
Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf
Enable ACPI CPPC mechanism for RD-Fremont as defined by the ACPI
specification. The implementation uses AMU registers accessible as
Fixed-feature Hardware (FFixedHW) for monitoring the performance.
Non-secure SCMI fastchannels are used to communicate with LCP to set the
desired performance. In addi
Hi Levi,
The patches to use dynamic tables are under development and so the PCIe support
will follow after your patches.
Thanks,
Prabin CA
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Hi Levi,
Thank you for taking the time to review these patches and providing corrections.
For RD platforms, We don't have any performance limited register. During CPPC
testing with Linux as the OS, we've observed that Linux utilizes only the
performance set level channel and does not utilize the
Reviewed-by: Nickle Wang
Regards,
Nickle
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Mike
> Maslenkin via groups.io
> Sent: Sunday, March 10, 2024 6:42 PM
> To: devel@edk2.groups.io
> Cc: Mike Maslenkin ; Abner Chang
> ; Igor Kulchytskyy ; Nickle Wang
>
> Subject:
Reviewed-by: Nickle Wang
Regards,
Nickle
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Mike
> Maslenkin via groups.io
> Sent: Sunday, March 10, 2024 6:42 PM
> To: devel@edk2.groups.io
> Cc: Mike Maslenkin ; Abner Chang
> ; Igor Kulchytskyy ; Nickle Wang
>
> Subject:
Reviewed-by: Nickle Wang
Regards,
Nickle
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Mike
> Maslenkin via groups.io
> Sent: Sunday, March 10, 2024 6:42 PM
> To: devel@edk2.groups.io
> Cc: Mike Maslenkin ; Abner Chang
> ; Igor Kulchytskyy ; Nickle Wang
>
> Subject:
Reviewed-by: Nickle Wang
Regards,
Nickle
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Mike
> Maslenkin via groups.io
> Sent: Sunday, March 10, 2024 6:42 PM
> To: devel@edk2.groups.io
> Cc: Mike Maslenkin ; Abner Chang
> ; Igor Kulchytskyy ; Nickle Wang
>
> Subject:
On Sat, 9 Mar 2024 at 20:06, Oliver Smith-Denny
wrote:
>
> Currently, there are multiple issues when page or pool guards are
> allocated for runtime memory regions that are aligned to
> non-EFI_PAGE_SIZE alignments. Multiple other issues have been fixed
> for these same systems (notably ARM64 whic
On Wed, 28 Feb 2024 at 03:28, Zhiguang Liu wrote:
>
> To support unregister MMI handler inside MMI handler itself,
> get next node before MMI handler is executed, since LIST_ENTRY that
> Link points to may be freed if unregister MMI handler in MMI handler
> itself.
>
> Cc: Liming Gao
> Cc: Jiaxin
On Wed, 17 Jan 2024 at 22:36, Jeremy Linton wrote:
>
> The rpi's config.txt controls which uart (pl011, or miniuart) is
> selected as the console. TFA and edk2 follow its lead, but if the
> miniuart is selected as the primary and the machine is booted in ACPI
> mode the baud/etc is never configure
Hello Abdul,
I think the FADT patch will change too much with the modifications currently
ongoing on the Arm/Arch common namespace objects. So it might not be worth
reviewing it for now.
The other patches will also have to be rebased/modified, but with less
modifications,
Regards,
Pierre
On 3/4
Hello Abdul,
On 3/4/24 16:43, Abdul Lateef Attar wrote:
From: Abdul Lateef Attar
Adds generic ACPI HPET table generator library.
Register/Deregister HPET table.
Update the HPET table during boot as per specification.
Cc: Sami Mujawar
Cc: Pierre Gondois
Signed-off-by: Abdul Lateef Attar
---
Hello Abdul,
On 3/4/24 16:43, Abdul Lateef Attar wrote:
From: Abdul Lateef Attar
Adds generic ACPI WSMT table generator library.
Register/Deregister WSMT table.
Update the WSMT table during boot as per specification.
Cc: Sami Mujawar
Cc: Pierre Gondois
Signed-off-by: Abdul Lateef Attar
---
Hello Abdul,
On 3/4/24 16:43, Abdul Lateef Attar wrote:
From: Abdul Lateef Attar
Adds generic ACPI SSDT HPET table generator library.
Register/Deregister HPET table.
Adds ACPI namespace object for HPET device.
Adds Address space for HPET device.
Cc: Sami Mujawar
Cc: Pierre Gondois
Signed-of
(follow-up)
On 3/11/24 15:16, Pierre Gondois wrote:
Hello Abdul,
On 3/4/24 16:43, Abdul Lateef Attar wrote:
From: Abdul Lateef Attar
Adds generic ACPI SSDT HPET table generator library.
Register/Deregister HPET table.
Adds ACPI namespace object for HPET device.
Adds Address space for HPET de
On Wed, 17 Jan 2024 at 22:36, Jeremy Linton wrote:
>
> This includes a change to always initialize the PL011 to the
> configured baud (which should be 115200 for the SBSA UART), which
> fixes linux's assumption that SBSA UARTs are pre-programmed for
> 115200. This in turn (re)enables the PL011 whe
Reviewed-by: levi.yun
From: devel@edk2.groups.io on behalf of Prabin CA via
groups.io
Sent: 11 March 2024 13:14
To: devel@edk2.groups.io
Cc: Ard Biesheuvel; Leif Lindholm; Sami Mujawar; Thomas Abraham
Subject: [edk2-devel] [edk2-platforms][PATCH v5 1/9]
Reviewed-by: levi.yun
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groups.io
Sent: 11 March 2024 13:14
To: devel@edk2.groups.io
Cc: Ard Biesheuvel; Leif Lindholm; Sami Mujawar; Thomas Abraham
Subject: [edk2-devel] [edk2-platforms][PATCH v5 2/9]
Reviewed-by: levi.yun
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groups.io
Sent: 11 March 2024 13:14
To: devel@edk2.groups.io
Cc: Ard Biesheuvel; Leif Lindholm; Sami Mujawar; Thomas Abraham
Subject: [edk2-devel] [edk2-platforms][PATCH v5 3/9]
Reviewed-by: levi.yun
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Sent: 11 March 2024 13:14
To: devel@edk2.groups.io
Cc: Ard Biesheuvel; Leif Lindholm; Sami Mujawar; Thomas Abraham
Subject: [edk2-devel] [edk2-platforms][PATCH v5 4/9]
Reviewed-by: levi.yun
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Sent: 11 March 2024 13:14
To: devel@edk2.groups.io
Cc: Ard Biesheuvel; Leif Lindholm; Sami Mujawar; Thomas Abraham
Subject: [edk2-devel] [edk2-platforms][PATCH v5 5/9]
Reviewed-by: levi.yun
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Sent: 11 March 2024 13:14
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Cc: Ard Biesheuvel; Leif Lindholm; Sami Mujawar; Thomas Abraham
Subject: [edk2-devel] [edk2-platforms][PATCH v5 6/9]
Reviewed-by: levi.yun
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Sent: 11 March 2024 13:14
To: devel@edk2.groups.io
Cc: Ard Biesheuvel; Leif Lindholm; Sami Mujawar; Thomas Abraham
Subject: [edk2-devel] [edk2-platforms][PATCH v5 8/9]
Reviewed-by: levi.yun
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Sent: 11 March 2024 13:14
To: devel@edk2.groups.io
Cc: Ard Biesheuvel; Leif Lindholm; Sami Mujawar; Thomas Abraham
Subject: [edk2-devel] [edk2-platforms][PATCH v5 7/9]
Hi Sunil,
> How do we plan creating further patches? I am fine with any approach you
> suggest but don't want to duplicate effort. I think it would be helpful
> to know whether someone is already working on it.
[SAMI] I am working on a patch series that moves the common objects from Arm
Namespac
Reviewed-by: levi.yun
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Sent: 11 March 2024 13:14
To: devel@edk2.groups.io
Cc: Ard Biesheuvel; Leif Lindholm; Sami Mujawar; Thomas Abraham
Subject: [edk2-devel] [edk2-platforms][PATCH v5 9/9]
wt., 20 lut 2024 o 11:35 Gahan Saraiya napisał(a):
>
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4689
>
> Bug 4689 - GetInfo() of Adapter Information Protocol
> should have a provision for IHV to return no data for
> UEFI Spec compliance 2.9 [mantis #1866]
>
> Cc: Marcin Wojtas
> Cc: Le
Thank you all for your support. :)
-Dat
-Original Message-
From: Cheng, Gao
Sent: Sunday, March 10, 2024 9:46 PM
To: Wu, Hao A ; Dat Mach ; gaoliming
; devel@edk2.groups.io
Cc: Ni, Ray
Subject: RE: [PATCH] MdeModulePkg/Xhci: Skip another size round up for TRB
address translation
Exte
On 3/1/24 12:45, Leif Lindholm wrote:
Thank you.
OK, that's logically consistent.
So we'd need an ArmLibNull in MdePkg until ArmLib itself migrates there
(ideally subsumed into BaseLib).
From what Jiewen said, it doesn't seem that creating an ArmLibNull
in the MdePkg is necessary (unless I
Hello Sami, Leif,
Just a ping in case the patch-set was forgotten,
Regards,
Pierre
On 2/14/24 14:26, Ard Biesheuvel wrote:
On Wed, 14 Feb 2024 at 13:42, PierreGondois wrote:
Following the discussion at:
https://edk2.groups.io/g/devel/message/115378
remove ArmCortexA5x.h and ArmCortexA9.h fil
Hello Sami, Leif,
Just a ping in case the patch-set was forgotten,
Regards,
Pierre
On 2/14/24 14:26, Ard Biesheuvel wrote:
On Wed, 14 Feb 2024 at 13:44, wrote:
From: Pierre Gondois
Following the discussion at:
https://edk2.groups.io/g/devel/message/115378
Remove:
- the ArmVExpressLibSec m
On Mon, Mar 11, 2024 at 3:04 AM Ni, Ray wrote:
>
> This is a good idea to have a CREDITS file in edk2 repo.
>
> Pedro, would you mind initiating one?
Laszlo told me (in private) that he doesn't want a CREDITS entry for
him, git log is enough.
So unless you have other people in mind, let's drop t
On 3/4/2024 2:38 PM, Oliver Smith-Denny wrote:
On 3/4/2024 11:24 AM, Oliver Smith-Denny wrote:
On 3/4/2024 10:54 AM, Ard Biesheuvel wrote:
On Mon, 4 Mar 2024 at 18:49, Oliver Smith-Denny
wrote:
Hi Ard,
On 3/1/2024 3:58 AM, Ard Biesheuvel wrote:
Hi Oliver,
On Tue, 27 Feb 2024 at 21:27, Oli
On 3/11/24 11:29, Zeng, Star wrote:
> Thank you Laszlo.
>
> Is ler...@redhat.com still reachable for now ? 😊
March 14th is my last day at Red Hat; my email access will be revoked on
that day.
Laszlo
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On 3/11/24 18:49, Pedro Falcato wrote:
> On Mon, Mar 11, 2024 at 3:04 AM Ni, Ray wrote:
>>
>> This is a good idea to have a CREDITS file in edk2 repo.
>>
>> Pedro, would you mind initiating one?
>
> Laszlo told me (in private) that he doesn't want a CREDITS entry for
> him, git log is enough.
>
Hi Chinni,
Switching from TopOfCar to SizeOfFspMemory doesn't address my previous
feedback. Please also give this patch a better title. Adding new FSP-T Arch
UPDs or something like that. Look forward to a V5 patch.
Thanks,
Nate
-Original Message-
From: Duggapu, Chinni B
Sent: Wednesd
ImagePropertiesRecordLib is currently creating Image Records that
are not accurate. It is setting the CodeSegmentSize to be the size
of the raw data in the image file, however, when the image is
loaded into memory, the raw data size is aligned to the
section alignment. This caused the memory attrib
*Reminder: Tools, CI, Code base construction meeting series*
*When:*
Monday, March 11, 2024
4:30pm to 5:30pm
(UTC-07:00) America/Los Angeles
*Where:*
https://teams.microsoft.com/l/meetup-join/19%3ameeting_ZDI2ZDg4NmMtMjI1My00MzI5LWFmYjAtMGQyNjUzNTBjZGYw%40thread.v2/0?context=%7b%22Tid%22%3a%2272f
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Not enough content requested here Tools and CI Meeting - vNext - Date TBD ·
tianocore/edk2 · Discussion #5366 (github.com) (
https://github.com/tianocore/edk2/discussions/5366 )
Cancelling the meeting for the week.
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*Reminder: TianoCore Bug Triage - APAC / NAMO*
*When:*
Tuesday, March 12, 2024
6:30pm to 7:30pm
(UTC-07:00) America/Los Angeles
*Where:*
https://teams.microsoft.com/l/meetup-join/19%3ameeting_OTk1YzJhN2UtOGQwNi00NjY4LWEwMTktY2JiODRlYTY1NmY0%40thread.v2/0?context=%7b%22Tid%22%3a%2246c98d88-e344-4e
From: Duke Zhai
BZ #:4728
1.Use HPET timer to replace 8254 timer
2.Fix Bug Microcode version cannot show correctly at BIOS setup
3.Enable capsule at linux build
4.Update FspWrapper UPD table for BIOS setup options
Cc: Ken Yao
Cc: Igniculus Fu
Reviewed-by: Abner Chang
Reviewed-by: Eric Xing
https://bugzilla.tianocore.org/show_bug.cgi?id=4556
Based on XHCI spec 4.8.3, software should do the
reset endpoint while USB Transaction occur.
Also add the error code for USB Transaction error
since UEFI spec don't have the related definition.
Cc: Hao A Wu
Cc: Ray Ni
Cc: Liming Gao
On Mon, Mar 11, 2024 at 07:35:28AM -0700, Sami Mujawar wrote:
> Hi Sunil,
>
> > How do we plan creating further patches? I am fine with any approach you
> > suggest but don't want to duplicate effort. I think it would be helpful
> > to know whether someone is already working on it.
> [SAMI] I am
Reviewed-by: Jiewen Yao
> -Original Message-
> From: Xu, Min M
> Sent: Tuesday, February 27, 2024 2:49 PM
> To: Sun, CepingX ; devel@edk2.groups.io
> Cc: Liming Gao ; Kinney, Michael D
> ; Aktas, Erdem ; James
> Bottomley ; Yao, Jiewen ; Tom
> Lendacky ; Michael Roth
> ; Gerd Hoffmann ;
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