Hi Levi, Thank you for taking the time to review these patches and providing corrections.
For RD platforms, We don't have any performance limited register. During CPPC testing with Linux as the OS, we've observed that Linux utilizes only the performance set level channel and does not utilize the performance limit set channels. Even when we attempt to set the performance limit from Linux sysfs, the kernel handles this internally without forwarding any limit set requests to the platform firmware. Consequently, as these registers are optional, we are not using these channels. Looking ahead to potential future implementations, it's anticipated that the performance limited register will come into play. That's why we've included the performance limited register. if you have any suggestions, please do share. The decision to use the fast channel address was influenced by potentially misleading information found in the FFH specification v1.2, under chapter 'B.2.2 Performance Controls', where the performance limited register address was indicated as the next address after the 'Desired Performance Register'. We've now updated the _CPC object with a value address of 0 for the performance limited register (we will make the similar changes for older platforms as well and post as a new series). Please do let us know if you have any suggestions on using any specific register for the performance limited register. Your input would be greatly appreciated. Thanks, Prabin CA -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#116623): https://edk2.groups.io/g/devel/message/116623 Mute This Topic: https://groups.io/mt/104668523/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
