The reference design platform currently lacks the CPPC (Collaborative
Processor Performance Control) performance limited register as defined
by the ACPI 6.x specification. There is a typo in the macro definition
where the 'fastchannel address of the performance limited register' is
mentioned instead of the 'performance limited register address'.
Correcting this typo. However, it's important to retain the reference to
the performance limited register in the macro for future use, as it will
prove useful once functionalities such as power metering devices are
enabled.
Signed-off-by: Prabin CA <prabin...@arm.com>
---
Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
index 033d398fdb63..3e24f569c95a 100644
--- a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
+++ b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
@@ -469,8 +469,7 @@ typedef struct {
@param [in] DesiredPerfReg Fastchannel address for desired performance
register.
- @param [in] PerfLimitedReg Fastchannel address for performance limited
- register.
+ @param [in] PerfLimitedReg Address for performance limited register.
@param [in] GranularityMHz Granularity of the performance scale.
@param [in] HighestPerf Highest performance in linear scale.
@param [in] NominalPerf Nominal performance in linear scale.
--
2.34.1
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