Sort ApicIdOrderTable by following special rules:
1. Make sure BSP is the first entry.
2. For APs, big core first, then small core.
With this implementation, BIOS can present cores in order
of relative performance in MADT. Linux OS would schedule
cores by the order that they are presented in the M
Add a new field CoreType in EFI_CPU_ID_ORDER_MAP
and get CoreType for all cores.
Signed-off-by: Dun Tan
Cc: Ray Ni
Cc: Jason Lou
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Liming Gao
Cc: Eric Dong
---
Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c | 50
+++
This global variable mForceX2ApicId is not assigned
to any value in code and will be initialized to 0 when
the driver is loaded. So remove the global variable
and related code that will not be executed.
Signed-off-by: Dun Tan
Cc: Ray Ni
Cc: Jason Lou
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Limi
This patch set is to sort ApicIdOrderTable by following special rules:
1. Make sure BSP is the first entry.
2. For APs, big core first, then small core.
With this implementation, BIOS can present cores in order of relative
performance in MADT.
Linux OS would schedule cores by the order that they
Change AcpiProcessorUid in CpuApicIdOrderTable to
the index in MpService regardless of disabled core.
Let's take a simple example:
There are 2 enabled cores and 1 disabled core.
APICID Index in MpService
0x_0
0x_0010(disbaled) 1
0x_0040
Hi Michael,
Thanks for the tool recommendation.
However, the tools are useful for x86, arm, and IPF platforms. I'm working on a
RISC-V platform.
I wanted to compile the tools for RISC-V, but the link is not found:
https://edk.tianocore.org/files/documents/16/347/file_347.dat/EDK%20Build_0_2.pd
On Sat, Mar 30, 2024 at 06:10 AM, Andrew Fish wrote:
>
> You can make a ReadOnly file system out of contents on an FV (Firmware
> Volume):
> https://github.com/tianocore/edk2/tree/master/MdeModulePkg/Universal/FvSimpleFileSystemDxe
>
> FV is defined in the PI Spec as a layout for flash that con
Hi Liming,
Could you please help review and merge it? Thanks.
Best,
Aaron
-Original Message-
From: Liu, Zhiguang
Sent: Monday, April 1, 2024 10:06 AM
To: Li, Aaron ; devel@edk2.groups.io
Cc: Bi, Dandan ; Liming Gao ;
Liu, Yun Y ; Yao, Jiewen ; Ni, Ray
; Kinney, Michael D
Subject: RE
Reviewed-by: Zhiguang Liu
> -Original Message-
> From: Li, Aaron
> Sent: Tuesday, March 26, 2024 3:58 PM
> To: devel@edk2.groups.io
> Cc: Liu, Zhiguang ; Bi, Dandan
> ; Liming Gao ; Liu, Yun Y
> ; Yao, Jiewen ; Ni, Ray
> ; Kinney, Michael D
> Subject: [PATCH v2 1/1] MdeModulePkg/AcpiTab
Appreciate your efforts in optimization of unit test, for this patch set:
Looks good to me.
Reviewed-by: Yi Li
-Original Message-
From: devel@edk2.groups.io On Behalf Of Chris Ruffin via
groups.io
Sent: Sunday, March 31, 2024 6:00 AM
To: devel@edk2.groups.io
Cc: Chris Ruffin
Subject:
[AMD Official Use Only - General]
Hi Mike,
Just letting you know that I merged this patch set to clean up the backlogs. I
believe your comment was addressed in V5. Just let me know if you still find
any improper code.
Thanks
Abner
> -Original Message-
> From: devel@edk2.groups.io On Be
[AMD Official Use Only - General]
Acked-by: Abner Chang
> -Original Message-
> From: Abdul Lateef Attar
> Sent: Saturday, March 30, 2024 1:23 PM
> To: devel@edk2.groups.io
> Cc: Attar, AbdulLateef (Abdul Lateef) ; Chang,
> Abner ; Michael D Kinney
> ; Liming Gao ;
> Zhiguang Liu
> Subj
*Reminder: Tools, CI, Code base construction meeting series*
*When:*
Monday, April 1, 2024
4:30pm to 5:30pm
(UTC-07:00) America/Los Angeles
*Where:*
https://teams.microsoft.com/l/meetup-join/19%3ameeting_ZDI2ZDg4NmMtMjI1My00MzI5LWFmYjAtMGQyNjUzNTBjZGYw%40thread.v2/0?context=%7b%22Tid%22%3a%2272f9
Merged as 344be33d497d..b64443f7b8c3
Thanks.
Regards,
Sami Mujawar
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Hi Prabin,
I am going to drop patch 7/9 that adds the SMBIOS support, and merge the
remaining series.
Please fix patch 7/9 and send it as a separate patch that adds SMBIOS
support for RD-Fremont.
Regards,
Sami Mujawar
On 11/03/2024 01:14 pm, Prabin CA wrote:
Changes since V4:
- Addressed
Hi Prabin,
Thank you for this patch.
These changes look good to me.
Reviewed-by: Sami Mujawar
Regards,
Sami Mujawar
On 11/03/2024 01:14 pm, Prabin CA wrote:
Enable ACPI CPPC mechanism for RD-Fremont as defined by the ACPI
specification. The implementation uses AMU registers accessible as
F
Hi Prabin,
Thank you for this patch.
These changes look good to me.
Reviewed-by: Sami Mujawar
Regards,
Sami Mujawar
On 11/03/2024 01:14 pm, Prabin CA wrote:
RD-Fremont platform supports two LPI states, LPI1 (Standby WFI) and LPI3
(Power-down). The cluster supports LPI2 (Power-down) state.
Hi Prabin,
Thank you for this patch.
These changes look good to me.
Reviewed-by: Sami Mujawar
Regards,
Sami Mujawar
On 11/03/2024 01:14 pm, Prabin CA wrote:
The RD-Fremont fixed virtual platform simulates 16 CPUs and 8GB of RAM.
Add initial support for this platform by adding the required
Hi Prabin,
Thank you for this patch.
These changes look good to me.
Reviewed-by: Sami Mujawar
Regards,
Sami Mujawar
On 11/03/2024 01:14 pm, Prabin CA wrote:
From: Shriram K
RD-Fremont is the next platform in the Arm's reference design platform
series. This platform includes 32 CPUs but t
Hi Prabin,
Thank you for this patch.
These changes look good to me.
Reviewed-by: Sami Mujawar
Regards,
Sami Mujawar
On 11/03/2024 01:14 pm, Prabin CA wrote:
In preparation of adding the next generation of reference design
platform that have different memory map, refactor the
PcdSystemMemor
Hi Prabin,
Thank you for this patch.
Minor, EDKII does not have u32 and u64 types, otherwise these changes
look good to me.
I will reword the commit message before merging.
Reviewed-by: Sami Mujawar
Regards,
Sami Mujawar
On 11/03/2024 01:14 pm, Prabin CA wrote:
From: Vivek Gautam
On
Hi Prabin,
Thank you for this patch.
These changes look good to me.
Reviewed-by: Sami Mujawar
Regards,
Sami Mujawar
On 11/03/2024 01:14 pm, Prabin CA wrote:
The reference design platform currently lacks the CPPC (Collaborative
Processor Performance Control) performance limited register as
I am going to fix this locally before merging.
With that,
Reviewed-by: Sami Mujawar
Regards,
Sami Mujawar
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Hi Prabin,
Thank you for this patch.
This patch does not cleanly apply on the latest edk2-platforms master
branch. Can you check, please?
Regards,
Sami Mujawar
On 11/03/2024 01:14 pm, Prabin CA wrote:
Extend the SMBIOS support for RD-Fremont platform. RD-Fremont is a
16 core platform with
Hi Prabin,
Thank you for this patch.
On Mon, Mar 11, 2024 at 06:14 AM, Prabin CA wrote:
>
> #define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS =
> \
> - ((14 + (FixedPcdGet32 (PcdChipCount) * 2)) + =
> \
> + ((13 + (FixedPcdGet32 (PcdChipCount) * 2)) + =
> \
> + (FeaturePcdGet (PcdPcieEnable)) + =
> \
Merged patches 1 to 4 as 7c26299112f3..344be33d497d.
Thanks.
Regards,
Sami Mujawar
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Hi Prabin,
To me the RD-V2 support appears to be incomplete (or the required information
is not clear).
Therefore, instead of stalling the entire series, I am going to drop patch 5/6
and 6/6 and merge the remaining patches.
Please reply back to my queries for patch 5/6 and send a separate patch
Hi Prabin,
Thank you for this patch.
On Fri, Mar 1, 2024 at 08:30 AM, Prabin CA wrote:
>
> Add RD-V2 platform identification values including the part number
> and configuration number. This information will be used in populating
> the SMBIOS tables.
In the cover letter you mention the followin
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