Hi Chengwen,
Thanks for the review and feedback. Please find my reply in-line.
Thanks,
Amit Shukla
> -Original Message-
> From: fengchengwen
> Sent: Saturday, October 7, 2023 2:31 PM
> To: Amit Prakash Shukla ; Kevin Laatz
> ; Bruce Richardson
> Cc: dev@dpdk.org; Jerin Jacob Kollanukka
> -Original Message-
> From: fengchengwen
> Sent: Saturday, October 7, 2023 3:03 PM
> To: Amit Prakash Shukla ; Kevin Laatz
> ; Bruce Richardson
> Cc: dev@dpdk.org; Jerin Jacob Kollanukkaran ;
> m...@smartsharesystems.com; conor.wa...@intel.com; Vamsi Krishna
> Attunuru ; g.si...@nxp.co
https://bugs.dpdk.org/show_bug.cgi?id=1281
Thomas Monjalon (tho...@monjalon.net) changed:
What|Removed |Added
CC||tho...@monjalon.net
E
Hi,
> -Original Message-
> From: Dariusz Sosnowski
> Sent: Friday, August 25, 2023 9:44 PM
> To: Matan Azrad ; Slava Ovsiienko
> ; Ori Kam ; Suanming Mou
>
> Cc: dev@dpdk.org; sta...@dpdk.org
> Subject: [PATCH] net/mlx5: fix jump ipool entry size
>
> In mlx5 PMD, MLX5_IPOOL_JUMP ipool c
> RTE_FLOW_ITEM_TYPE_IB_BTH matches an InfiniBand base transport header.
> We extend the match on the acknowledgment bit (BTH_A).
>
> Signed-off-by: Itamar Gozlan
Series-acked-by: Matan Azrad
> ---
> drivers/net/mlx5/hws/mlx5dr_definer.c | 12 ++--
> drivers/net/mlx5/hws/mlx5dr_defin
From: Yuying Zhang
This patchset add rte flow support for cpfl driver.
It depends on the following patch set:
http://patchwork.dpdk.org/project/dpdk/cover/20230912173039.1612287-1-beilei.x...@intel.com/
Wenjing Qiao (2):
net/cpfl: parse flow offloading hint from JSON
net/cpfl: build action m
From: Wenjing Qiao
Add devargs "flow_parser" to specify the path of a JSON
configure file. The cpfl PMD use the JSON configuration file
to translate rte_flow tokens into low level hardware
representation.
Example:
-a ca:00.0,flow_parser="refpkg.json"
jansson library is used to parse JSON sy
From: Wenjing Qiao
Build rules that maps from an rte_flow action vxlan_encap or
vxlan_decap to hardware representations.
Signed-off-by: Wenjing Qiao
Acked-by: Qi Zhang
---
drivers/net/cpfl/cpfl_flow_parser.c | 538 +++-
drivers/net/cpfl/cpfl_flow_parser.h | 100 ++
From: Yuying Zhang
Set up the rte_flow backend skeleton. Introduce the framework
to support different engines as rte_flow backend. Bridge rte_flow
driver API to flow engines.
Signed-off-by: Yuying Zhang
Acked-by: Qi Zhang
---
drivers/net/cpfl/cpfl_ethdev.c | 53 ++
drivers/net/cpfl/cpfl_
From: Yuying Zhang
Set up a dedicate vport with 4 pairs of control queues for flow offloading.
Signed-off-by: Yuying Zhang
Acked-by: Qi Zhang
---
drivers/net/cpfl/cpfl_controlq.c | 801 +++
drivers/net/cpfl/cpfl_controlq.h | 75 +++
drivers/net/cpfl/cpfl_ethdev.c
From: Yuying Zhang
Add low level helper functions for CPFL PMD to create / delete
rules on IPU's Flexible Packet Processor(FXP).
Signed-off-by: Yuying Zhang
Acked-by: Qi Zhang
---
drivers/net/cpfl/cpfl_actions.h | 858
drivers/net/cpfl/cpfl_rules.c | 127 +++
From: Yuying Zhang
Add a new module that implements FXP rule creation / destroying.
Signed-off-by: Yuying Zhang
Acked-by: Qi Zhang
---
drivers/net/cpfl/cpfl_ethdev.c | 31
drivers/net/cpfl/cpfl_ethdev.h | 6 +
drivers/net/cpfl/cpfl_fxp_rule.c | 263 +++
[AMD Official Use Only - General]
> -Original Message-
> From: David Marchand
> Sent: Friday, October 6, 2023 1:57 PM
> To: Tummala, Sivaprasad
> Cc: david.h...@intel.com; anatoly.bura...@intel.com; Yigit, Ferruh
> ; tho...@monjalon.net; dev@dpdk.org; Tyler Retzlaff
>
> Subject: Re: [PA
From: Yuying Zhang
Adapt FXP implementation to a flow engine
Signed-off-by: Yuying Zhang
Acked-by: Qi Zhang
---
doc/guides/nics/cpfl.rst| 18 +-
doc/guides/rel_notes/release_23_11.rst | 1 +
drivers/net/cpfl/cpfl_ethdev.h | 27 ++
drivers/net/cpfl/cpfl_flow_engin
From: Yuying Zhang
Add flow ops support for representor, so representor can
create, destroy, validate and flush rules.
Signed-off-by: Yuying Zhang
Acked-by: Qi Zhang
---
drivers/net/cpfl/cpfl_flow_engine_fxp.c | 74 +
drivers/net/cpfl/cpfl_representor.c | 29 ++
From: Yuying Zhang
Support RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT action for forwarding
packet to APF/CPF/VF representors.
Signed-off-by: Yuying Zhang
Acked-by: Qi Zhang
---
drivers/net/cpfl/cpfl_flow_engine_fxp.c | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --gi
On 9/29/2023 12:24 PM, Thomas Monjalon wrote:
>29/09/2023 11:46, Ferruh Yigit:
>> On 9/29/2023 10:21 AM, Christian Koue Muf wrote:
>> > On 9/21/2023 4:05 PM, Ferruh Yigit wrote:
>> >> On 9/20/2023 2:17 PM, Thomas Monjalon wrote:
>> >>> Hello,
>> >>>
>> >>> 19/09/2023 11:06, Christian Koue Muf:
>> >
From: Yuying Zhang
This patchset add rte flow support for cpfl driver.
It depends on the following patch set:
http://patchwork.dpdk.org/project/dpdk/cover/20230912173039.1612287-1-beilei.x...@intel.com/
Wenjing Qiao (2):
net/cpfl: parse flow offloading hint from JSON
net/cpfl: build action m
From: Wenjing Qiao
Add devargs "flow_parser" to specify the path of a JSON
configure file. The cpfl PMD use the JSON configuration file
to translate rte_flow tokens into low level hardware
representation.
Example:
-a ca:00.0,flow_parser="refpkg.json"
jansson library is used to parse JSON sy
From: Wenjing Qiao
Build rules that maps from an rte_flow action vxlan_encap or
vxlan_decap to hardware representations.
Signed-off-by: Wenjing Qiao
Acked-by: Qi Zhang
---
drivers/net/cpfl/cpfl_flow_parser.c | 538 +++-
drivers/net/cpfl/cpfl_flow_parser.h | 100 ++
From: Yuying Zhang
Set up the rte_flow backend skeleton. Introduce the framework
to support different engines as rte_flow backend. Bridge rte_flow
driver API to flow engines.
Signed-off-by: Yuying Zhang
Acked-by: Qi Zhang
---
drivers/net/cpfl/cpfl_ethdev.c | 53 ++
drivers/net/cpfl/cpfl_
From: Yuying Zhang
Set up a dedicate vport with 4 pairs of control queues for flow offloading.
Signed-off-by: Yuying Zhang
Acked-by: Qi Zhang
---
drivers/net/cpfl/cpfl_controlq.c | 801 +++
drivers/net/cpfl/cpfl_controlq.h | 75 +++
drivers/net/cpfl/cpfl_ethdev.c
From: Yuying Zhang
Add low level helper functions for CPFL PMD to create / delete
rules on IPU's Flexible Packet Processor(FXP).
Signed-off-by: Yuying Zhang
Acked-by: Qi Zhang
---
drivers/net/cpfl/cpfl_actions.h | 858
drivers/net/cpfl/cpfl_rules.c | 127 +++
From: Yuying Zhang
Add a new module that implements FXP rule creation / destroying.
Signed-off-by: Yuying Zhang
Acked-by: Qi Zhang
---
drivers/net/cpfl/cpfl_ethdev.c | 31
drivers/net/cpfl/cpfl_ethdev.h | 6 +
drivers/net/cpfl/cpfl_fxp_rule.c | 263 +++
From: Yuying Zhang
Adapt FXP implementation to a flow engine
Signed-off-by: Yuying Zhang
Acked-by: Qi Zhang
---
doc/guides/nics/cpfl.rst| 18 +-
doc/guides/rel_notes/release_23_11.rst | 1 +
drivers/net/cpfl/cpfl_ethdev.h | 27 ++
drivers/net/cpfl/cpfl_flow_engin
From: Yuying Zhang
Add flow ops support for representor, so representor can
create, destroy, validate and flush rules.
Signed-off-by: Yuying Zhang
Acked-by: Qi Zhang
---
drivers/net/cpfl/cpfl_flow_engine_fxp.c | 74 +
drivers/net/cpfl/cpfl_representor.c | 29 ++
From: Yuying Zhang
Support RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT action for forwarding
packet to APF/CPF/VF representors.
Signed-off-by: Yuying Zhang
Acked-by: Qi Zhang
---
drivers/net/cpfl/cpfl_flow_engine_fxp.c | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --gi
Hi,
> -Original Message-
> From: Ori Kam
> Sent: Tuesday, September 26, 2023 13:38
> To: cristian.dumitre...@intel.com; Aman Singh
> ; Yuying Zhang ;
> NBU-Contact-Thomas Monjalon (EXTERNAL) ;
> Ferruh Yigit ; Andrew Rybchenko
>
> Cc: dev@dpdk.org; Ori Kam ; Raslan Darawsheh
>
> Subject
Hi Trevor,
Now the port Rx mq_mode had been set to RTE_ETH_MQ_RX_RSS
by default, but some hw and/or virtual interface does not
support the RSS and offload mode presupposed, e.g., some
virtio interfaces in the cloud don't support
RSS and the error msg may like:
virtio_dev_configure(): RSS suppor
Hi Amit,
Rethink again, I suggest use auto-free to denote this feature.
So we could re-define as:
RTE_DMA_CAPA_M2D_AUTO_FREE
RTE_DMA_OP_FLAG_AUTO_FREE
struct rte_dma_auto_free_param {
union {
struct {
struct rte_mempool *pool;
} m2d;
};
u
Hi,
> -Original Message-
> From: Jiawei(Jonny) Wang
> Sent: Friday, September 22, 2023 9:50 AM
> To: Slava Ovsiienko
> Cc: dev@dpdk.org; Raslan Darawsheh
> Subject: [PATCH] net/mlx5: adds the checking for Tx queue affinity
>
> MLX5 PMD updates the TIS index based on the tx queue affini
02.10.2023 09:53, Trevor Tao пишет:
Now the port Rx offload mode is set to RTE_ETH_RX_OFFLOAD_CHECKSUM
by default, but some hw and/or virtual interface does not support
the offload mode presupposed, e.g., some virtio interfaces in
the cloud may only partly support RTE_ETH_RX_OFFLOAD_UDP_CKSUM/
RT
On 10/8/2023 8:08 AM, Chaoyong He wrote:
> The initial logic do not give a value to the out parameter in the
> abnormal logic, which cause an local variable uninitialized problem.
>
> Fixes: 3d6811281392 ("net/nfp: add infrastructure for conntrack flow merge")
> Cc: chaoyong...@corigine.com
>
> S
On 10/6/2023 7:31 PM, David Christensen wrote:
>
>
> On 9/29/23 6:48 AM, Ferruh Yigit wrote:
>> On 6/7/2023 7:47 PM, Ferruh Yigit wrote:
>>> On 5/16/2023 10:55 AM, Ferruh Yigit wrote:
On 5/16/2023 2:28 AM, Stephen Hemminger wrote:
> On Tue, 16 May 2023 00:35:56 +0100
> Ferruh Yigit
On 10/8/2023 7:46 AM, Dengdui Huang wrote:
> This series fix help string and add a new command.
>
> v3->v4
> help string add '\n' at last.
>
> v2->v3
> add 'mcast_addr add|remove' to help string and
> update the new command description.
>
> v1->v2
> update order on help string.
>
> Dengdui Huan
On 10/9/2023 8:57 AM, Christian Koue Muf wrote:
> On 9/29/2023 12:24 PM, Thomas Monjalon wrote:
>> 29/09/2023 11:46, Ferruh Yigit:
>>> On 9/29/2023 10:21 AM, Christian Koue Muf wrote:
On 9/21/2023 4:05 PM, Ferruh Yigit wrote:
> On 9/20/2023 2:17 PM, Thomas Monjalon wrote:
>> Hello,
>>>
The aarch32 with gcc13 fails with:
Compiler for C supports arguments -march=armv8-a: NO
../config/arm/meson.build:714:12: ERROR: Problem encountered: No
suitable armv8 march version found.
This is because we test -march=armv8-a alone (without the -mpfu option),
which is no longer supported in gc
Hi Ferruh and Thomas,
Can you take a look at this series? They've been over a year on
disscussion.
在 2023/8/2 11:15, Huisong Li 写道:
This patchset fix some bugs and support attaching and detaching port
in primary and secondary.
---
-v6: adjust rte_eth_dev_is_used position based on alphabet
Multi-process applications operate on shared hugepage memory but each
process has its own ASan shadow region which is not synchronized with
the other processes. This causes issues when different processes try to
use the same memory because they have their own view of which addresses
are valid.
Fix
On 10/4/23 16:51, David Marchand wrote:
- did you test with --in-memory mode? with --no-huge?
Please see v2 of the patch. I added checks for these options. They imply
no multi-process support so mapping is skipped for those cases.
- I did not look at the patch, but I wonder if there is a risk
Hi,
> -Original Message-
> From: Haifei Luo
> Sent: Sunday, October 8, 2023 6:10 AM
> To: dev@dpdk.org
> Cc: Ori Kam ; Slava Ovsiienko ;
> Raslan Darawsheh ; Xueming(Steven) Li
> ; Haifei Luo
> Subject: [PATCH v4 0/5] support item NSH matching
>
> NSH can be matched using the existed it
Hi Chengwen,
Ack, I will make the changes in next version of the patch.
Thanks,
Amit Shukla
> -Original Message-
> From: fengchengwen
> Sent: Monday, October 9, 2023 2:29 PM
> To: Amit Prakash Shukla ; Kevin Laatz
> ; Bruce Richardson
> Cc: dev@dpdk.org; Jerin Jacob Kollanukkaran ;
> m
This series adds offload support to auto free buffer in dma library
and adds a test support in dmadev_autotest to validate the functionality.
v4:
- Resolved review comments.
v3:
- Removed unwanted comment from code.
v2:
- Resolved review comments.
- Fixed compilation issue.
v1:
- Implementation
This changeset adds support in DMA library to auto free DMA buffer by
hardware. On a supported hardware, application can pass on the mempool
information as part of vchan config.
Signed-off-by: Amit Prakash Shukla
Acked-by: Morten Brørup
Acked-by: Anoob Joseph
---
lib/dmadev/rte_dmadev.h | 43 +
Add a test case to validate the functionality of drivers' dma
buffer offload auto free. As part of dmadev_autotest, test case
will be executed only if the driver supports buffer offload auto
free and if the test is exported by env variable DPDK_ADD_DMA_TEST.
Signed-off-by: Amit Prakash Shukla
Ack
When the packets is sent in packed mode, and the packets data and
virtio-header are divided into two desc, set the next flag of virtio-header desc
Bugzilla ID: 1295
Fixes: 892dc798fa9c ("net/virtio: implement Tx path for packed queues")
Signed-off-by: liufengjiang.0426
---
drivers/net/virtio/vi
On 10/5/2023 10:04 AM, Mcnamara, John wrote:
> Release status meeting minutes 2023-10-05
> =
>
> Agenda:
> * Release Dates
> * Subtrees
> * Roadmaps
> * LTS
> * Defects
> * Opens
>
> Participants:
> * AMD
> * Intel
> * Marvell
> * Nvidia
> * Red Hat
>
>
amd-pstate introduces a new CPU frequency control mechanism for AMD
EPYC processors using the ACPI Collaborative Performance Power Control
feature for a finer grained frequency management.
Patch to add support for amd-pstate driver.
Signed-off-by: Sivaprasad Tummala
Acked-by: Anatoly Burakov
--
This patch series fixes SM2 algorithm implementation to
support digest message as input along with plain message
as today.
v4:
- code rebase on next-crypto
Gowrishankar Muthukrishnan (7):
crypto/openssl: include SM2 in asymmetric capabilities
cryptodev: add hash algorithms in asymmetric capa
Include SM2 algorithm in the asymmetric capabilities supported
by OpenSSL PMD.
Fixes: 3b7d638fb11f ("crypto/openssl: support asymmetric SM2")
Signed-off-by: Gowrishankar Muthukrishnan
Acked-by: Arkadiusz Kusztal
---
drivers/crypto/openssl/rte_openssl_pmd_ops.c | 14 ++
1 file chang
Most of the asymmetric operations start with hash of the input.
But a PMD might also support only plain input (eg openssl).
Add a new field in asymmetric capability to declare support
for hash operations that PMD can support for the asymmetric
operations. Application can skip computing hash if PMD
SM2 curve could use generic EC xform as it is yet another EC.
This would also require SM2 curve ID enumerated
along with other curves, as listed in:
https://www.iana.org/assignments/tls-parameters/tls-parameters.xhtml
Signed-off-by: Gowrishankar Muthukrishnan
Acked-by: Arkadiusz Kusztal
---
app
Set EC private and public keys into xform so that, it can be
maintained per session.
Signed-off-by: Gowrishankar Muthukrishnan
Acked-by: Ciara Power
---
app/test/test_cryptodev_asym.c | 60 ++--
drivers/common/cnxk/roc_ae.h | 18 ++
drivers/comm
Elliptic curve based asymmetric operations use cryptographically
secure random number in its computation. If PMD supports RNG
for such ops, the application could skip computing on its own.
This patch adds new field in asymmetric capability to declare
this capability.
Signed-off-by: Gowrishankar Mu
Add SM2 asymmetric algorithm support in cnxk PMD.
Signed-off-by: Gowrishankar Muthukrishnan
---
doc/guides/cryptodevs/features/cn10k.ini | 1 +
doc/guides/rel_notes/release_23_11.rst| 4 +
drivers/common/cnxk/hw/cpt.h | 2 +-
drivers/common/cnxk/roc_ae.c
Check asymmetric capabilities such as SM3 hash support and
internal RNG and accordingly choose op params for SM2 test.
Signed-off-by: Gowrishankar Muthukrishnan
Acked-by: Arkadiusz Kusztal
---
app/test/test_cryptodev_asym.c | 77 +++---
app/test/test_cryptodev_sm2_te
[AMD Official Use Only - General]
> -Original Message-
> From: David Marchand
> Sent: Friday, October 6, 2023 2:33 PM
> To: david.h...@intel.com; anatoly.bura...@intel.com
> Cc: Yigit, Ferruh ; dev@dpdk.org; Tummala, Sivaprasad
>
> Subject: Re: [PATCH v2 1/2] power: refactor uncore power
Add a new CPUID flag to indicate support for monitorx instruction
on AMD EPYC processors.
Signed-off-by: Sivaprasad Tummala
Acked-by: Anatoly Burakov
---
lib/eal/x86/include/rte_cpuflags.h | 1 +
lib/eal/x86/rte_cpuflags.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/lib/eal/
current x86 power monitor implementation fails on platforms
with only monitor supported and not power_pause.
Signed-off-by: Sivaprasad Tummala
Acked-by: Anatoly Burakov
---
lib/eal/x86/rte_power_intrinsics.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/lib/eal/x86/
mwaitx allows EPYC processors to enter a implementation dependent
power/performance optimized state (C1 state) for a specific period
or until a store to the monitored address range.
Signed-off-by: Sivaprasad Tummala
Acked-by: Anatoly Burakov
---
lib/eal/x86/rte_power_intrinsics.c | 108
On Sat, Oct 07, 2023 at 03:36:34PM +0800, Jieqiang Wang wrote:
> __mm_cmpeq_epi16 returns 0x if the corresponding 16-bit elements are
> equal. In original SSE2 implementation for function compare_signatures,
> it utilizes _mm_movemask_epi8 to create mask from the MSB of each 8-bit
> element, wh
amd-pstate introduces a new CPU frequency control mechanism for AMD
EPYC processors using the ACPI Collaborative Performance Power Control
feature for a finer grained frequency management.
Patch to add support for amd-pstate driver.
Signed-off-by: Sivaprasad Tummala
Acked-by: Anatoly Burakov
--
On Thu, 5 Oct 2023 23:17:28 +
Sam Andrew wrote:
> +
> +static int
> +hn_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
> +{
> + struct hn_data *hv = dev->data->dev_private;
> + unsigned int orig_mtu = dev->data->mtu;
> + uint32_t rndis_mtu;
> + int ret = 0;
> + int i;
27/09/2023 17:08, Paul Szczepanek:
> Add a test that runs a zero copy burst enqueue and dequeue on a ring
> of raw pointers and compressed pointers at different burst sizes to
> showcase performance benefits of newly added pointer compression APIs
>
> To reuse existing code, some refactoring was d
27/09/2023 17:08, Paul Szczepanek:
> Add a new utility header for compressing pointers. Pointers are
> compressed by taking advantage of their locality. Instead of
> storing the full address only an offset from a known base is stored.
You probably need to insert some explanations from the cover le
Add RTE_FLOW_ITEM_TYPE_PTYPE to allow matching on
L2/L3/L4 and tunnel information as defined in mbuf.
To match on RTE_PTYPE_L4_TCP and RTE_PTYPE_INNER_L4_UDP:
flow pattern_template 0 create pattern_template_id 1
ingress template ptype packet_type mask 0x0f000f00 / end
flow queue 0 create 0
Recheck-request: iol-unit-amd64-testing
Failed for service_autotest on windows. I'm doing a retest to see if it's
reproducible.
Add RTE_FLOW_ITEM_TYPE_PTYPE to allow matching on
L2/L3/L4 and tunnel information as defined in mbuf.
To match on RTE_PTYPE_L4_TCP and RTE_PTYPE_INNER_L4_UDP:
flow pattern_template 0 create pattern_template_id 1
ingress template ptype packet_type mask 0x0f000f00 / end
flow queue 0 create 0
From: Sunil Kumar Kori
This patch adds RSS key for CNXK platforms. CNXK platform uses
48 bytes long key for hash calculations.
For the same patch also updates help mesaages to provide range
information for supporting NICs/platforms.
Also CNXK uses reta size as 64 so to get correct offset to ret
From: Sunil Kumar Kori
This patch adds RSS key for CNXK platforms. CNXK platform uses
48 bytes long key for hash calculations.
For the same patch also updates help mesaages to provide range
information for supporting NICs/platforms.
Also CNXK uses reta size as 64 so to get correct offset to ret
The packet type matching provides quick way of finding out
L2/L3/L4 protocols in a given packet. That helps with
optimized flow rules matching, eliminating the need of
stacking all the packet headers in the matching criteria.
Signed-off-by: Alexander Kozyrev
---
drivers/net/mlx5/hws/mlx5dr_defin
Expand packet type matching with support of the
Fragmented IP (Internet Protocol) packet type.
Signed-off-by: Alexander Kozyrev
---
drivers/net/mlx5/hws/mlx5dr_definer.c | 74 +++
drivers/net/mlx5/hws/mlx5dr_definer.h | 2 +
2 files changed, 56 insertions(+), 20 deletion
From: Michael Baum
Add limitations for ptype item support in "mlx5.rst" file.
Signed-off-by: Michael Baum
---
doc/guides/nics/features/mlx5.ini | 1 +
doc/guides/nics/mlx5.rst | 19 +++
2 files changed, 20 insertions(+)
diff --git a/doc/guides/nics/features/mlx5.ini
Add support for RTE_FLOW_ITEM_TYPE_PTYPE in mlx5 PMD.
Alexander Kozyrev (3):
net/mlx5: add support for ptype match in hardware steering
net/mlx5/hws: add support for fragmented ptype match
net/mlx5/hws: fix integrity bits level
Michael Baum (2):
doc: add PMD ptype item limitations
net/m
From: Michael Baum
This patch changes the integrity item behavior for HW steering.
Old behavior: the "ipv4_csum_ok" checks only IPv4 checksum and "l3_ok"
checks everything is ok including IPv4 checksum.
New behavior: the "l3_ok" checks everything is ok excluding IPv4
checksum.
This change enab
The level field in the integrity item is not taken into account
in the current implementation of hardware steering.
Use this value instead of trying to find out the encapsulation
level according to the protocol items involved.
Fixes: c55c2bf35333 ("net/mlx5/hws: add definer layer")
Signed-off-by:
Hi Stephen,
From: Stephen Hemminger
Sent: Monday, October 9, 2023 8:18 AM
> On Thu, 5 Oct 2023 23:17:28 +
> Sam Andrew wrote:
> > +
> > +static int
> > +hn_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) {
> > + struct hn_data *hv = dev->data->dev_private;
> > + unsigned int orig_m
On 2023-10-06 10:46, David Marchand wrote:
Hello Mattias,
On Thu, Oct 5, 2023 at 12:09 PM Mattias Rönnblom wrote:
+
+deps += ['eventdev']
diff --git a/lib/dispatcher/rte_dispatcher.c b/lib/dispatcher/rte_dispatcher.c
new file mode 100644
index 00..0e69db2b9b
--- /dev/null
+++ b/lib/dis
On 2023-10-06 10:52, David Marchand wrote:
On Thu, Oct 5, 2023 at 1:26 PM Mattias Rönnblom wrote:
[snip]
+#define RETURN_ON_ERROR(rc) \
+ do {\
+ if (rc != TEST_SUCCESS) \
+ return rc; \
+
On 2023-10-06 11:03, Thomas Monjalon wrote:
06/10/2023 10:46, David Marchand:
On Thu, Oct 5, 2023 at 12:09 PM Mattias Rönnblom wrote:
+static int
+evd_lookup_handler_idx(struct rte_dispatcher_lcore *lcore,
+ const struct rte_event *event)
Wrt DPDK coding tyle, indent is
The purpose of the dispatcher library is to decouple different parts
of an eventdev-based application (e.g., processing pipeline stages),
sharing the same underlying event device.
The dispatcher replaces the conditional logic (often, a switch
statement) that typically follows an event device deque
The purpose of the dispatcher library is to help reduce coupling in an
Eventdev-based DPDK application.
In addition, the dispatcher also provides a convenient and flexible
way for the application to use service cores for application-level
processing.
Signed-off-by: Mattias Rönnblom
Tested-by: Pe
Provide programming guide for the dispatcher library.
Signed-off-by: Mattias Rönnblom
--
PATCH v6:
o Eliminate unneeded white space in code blocks. (David Marchand)
PATCH v5:
o Update guide to match API changes related to dispatcher ids.
PATCH v3:
o Adapt guide to the dispatcher API name c
Add unit tests for the dispatcher.
--
PATCH v6:
o Register test as "fast". (David Marchand)
o Use single tab as indentation for continuation lines in multiple-line
function prototypes. (David Marchand)
o Add Signed-off-by line. (David Marchand)
o Use DPDK atomics wrapper API instead of C11
> Subject: [PATCH v4 0/7] cryptodev: support digest message in SM2
>
> This patch series fixes SM2 algorithm implementation to
> support digest message as input along with plain message
> as today.
>
> v4:
> - code rebase on next-crypto
>
Added release notes for API changes introduced in 4/7 p
On Wed, Oct 4, 2023 at 11:13 AM Aaron Conole wrote:
> Patrick Robb writes:
>
> > Thanks, this should help greatly going forward in the community lab.
> >
> > As it relates to our arm64 unit testing, I will give it a few days (or
> longer if needed) for next branches to rebase off of
> > main and
> Subject: [PATCH v2 0/5] add TLS record processing security offload
>
> Add Transport Layer Security (TLS) and Datagram Transport Layer Security
> (DTLS). The protocols provide communications privacy for L4 protocols
> such as TCP & UDP.
>
> TLS (and DTLS) protocol is composed of two layers,
> 1
> Subject: [PATCH v3 1/2] security: add fallback security processing and Rx
> inject
>
> Add alternate datapath API for security processing which would do Rx
> injection (similar to loopback) after successful security processing.
>
> With inline protocol offload, variable part of the session con
Members Attending
-
Aaron Conole
Bruce Richardson
Hemant Agrawal
Honappa Nagarahalli
Jerin Jacob
Kevin Traynor
Konstantin Ananyev
Maxime Coquelin
Stephen Hemminger
Thomas Monjalon
NOTE: The technical board meetings are on every second Wednesday at 3 pm UTC.
Meetings are public, a
> -Original Message-
> From: Zhang, Yuying
> Sent: Monday, October 9, 2023 12:00 PM
> To: Zhang, Yuying ; dev@dpdk.org; Zhang, Qi Z
> ; Wu, Jingjing ; Xing, Beilei
>
> Subject: [PATCH v10 0/9] add rte flow support for cpfl
>
> From: Yuying Zhang
>
> This patchset add rte flow suppor
Acked-by: Chengwen Feng
On 2023/10/9 20:02, Amit Prakash Shukla wrote:
This changeset adds support in DMA library to auto free DMA buffer by
hardware. On a supported hardware, application can pass on the mempool
information as part of vchan config.
Signed-off-by: Amit Prakash Shukla
Acked-by:
> -Original Message-
> From: Zhang, Yuying
> Sent: Thursday, September 28, 2023 1:05 PM
> To: Zhang, Yuying ; dev@dpdk.org; Zhang, Qi Z
> ; Wu, Jingjing ; Xing, Beilei
>
> Cc: sta...@dpdk.org
> Subject: [PATCH v1] net/idpf: fix incorrect status calculation
>
> From: Yuying Zhang
>
>
When the packets is sent in packed mode, and the packets data and
virtio-header are divided into two desc, set the next flag of
virtio-header desc
>> Fix the warning that a single line of commit log exceeds 75 chars
Bugzilla ID: 1295
Fixes: 892dc798fa9c ("net/virtio: implement Tx path for packed
Hi, Thomas,
Kindly ping for review.
Thanks,
Jie Hai
On 2023/7/4 17:04, Jie Hai wrote:
This patch set supports telemetry cmd to list rings and dump information
of a ring by its name.
v1->v2:
1. Add space after "switch".
2. Fix wrong strlen parameter.
v2->v3:
1. Remove prefix "rte_" for static
> -Original Message-
> From: Juraj Linkeš
> Sent: Monday, October 9, 2023 5:53 PM
> To: tho...@monjalon.net; Honnappa Nagarahalli ;
> bruce.richard...@intel.com; Ruifeng Wang
> Cc: dev@dpdk.org; Juraj Linkeš
> Subject: [PATCH v2] config/arm: update aarch32 build with gcc13
>
> The aarch
On Mon, Oct 9, 2023 at 10:06 PM wrote:
>
> From: Sunil Kumar Kori
>
> This patch adds RSS key for CNXK platforms. CNXK platform uses
> 48 bytes long key for hash calculations.
>
> For the same patch also updates help mesaages to provide range
> information for supporting NICs/platforms.
>
> Also
From: Zerun Fu
The former logic of initializing the array of physical port
representors is according to 'nfp_idx', but referencing based
on 'port_id'. This is a potential bug and will cause segment
fault when these two values are not equal. Fix it by using the
'port_id' as index at all time.
Fix
From: James Hershaw
The pointer to the beginning of the MAC stats counters for port 1 are
incorrectly set as the pointer to the beginning of the port 0 MAC stats
counters, plus the size of the MAC stats counters multiplied by the port
number.
This patch corrects this by setting the multiplier as
From: Long Wu
When sending a jumbo packet on NFDk the packet must be split between
multiple descriptors. The first descriptor contains the packet header
and is limited to NFDK_DESC_TX_DMA_LEN_HEAD bytes. If the packet is
large, one or more payload descriptors, without a packet header, and
a size
This patch series fix two converity issue 403098 and 403100.
Long Wu (2):
net/nfp: fix checking return value
net/nfp: fix illegal memory accesses
drivers/net/nfp/nfpcore/nfp6000_pcie.c | 8 +---
drivers/net/nfp/nfpcore/nfp_rtsym.c| 2 +-
2 files changed, 6 insertions(+), 4 deletions(
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