From: Michael Baum <michae...@nvidia.com>
This patch changes the integrity item behavior for HW steering.
Old behavior: the "ipv4_csum_ok" checks only IPv4 checksum and "l3_ok"
checks everything is ok including IPv4 checksum.
New behavior: the "l3_ok" checks everything is ok excluding IPv4
checksum.
This change enables matching "l3_ok" in IPv6 packets since for IPv6
packets "ipv4_csum_ok" is always miss.
For SW steering the old behavior is kept as same as for L4 ok.
Signed-off-by: Michael Baum <michae...@nvidia.com>
---
doc/guides/nics/mlx5.rst | 19 ++++++++++++-------
drivers/net/mlx5/hws/mlx5dr_definer.c | 6 ++----
2 files changed, 14 insertions(+), 11 deletions(-)
diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
index 26cf310e8e..ddec84a9bb 100644
--- a/doc/guides/nics/mlx5.rst
+++ b/doc/guides/nics/mlx5.rst
@@ -667,18 +667,23 @@ Limitations
- Integrity:
- - Integrity offload is enabled starting from **ConnectX-6 Dx**.
- Verification bits provided by the hardware are ``l3_ok``,
``ipv4_csum_ok``, ``l4_ok``, ``l4_csum_ok``.
- ``level`` value 0 references outer headers.
- Negative integrity item verification is not supported.
- - Multiple integrity items not supported in a single flow rule.
- - Flow rule items supplied by application must explicitly specify network
headers referred by integrity item.
- For example, if integrity item mask sets ``l4_ok`` or ``l4_csum_ok`` bits,
reference to L4 network header,
- TCP or UDP, must be in the rule pattern as well::
+ - With SW steering (``dv_flow_en=1``)
+ - Integrity offload is enabled starting from **ConnectX-6 Dx**.
+ - Multiple integrity items not supported in a single flow rule.
+ - Flow rule items supplied by application must explicitly specify network
headers referred by integrity item.
+ For example, if integrity item mask sets ``l4_ok`` or ``l4_csum_ok``
bits, reference to L4 network header,
+ TCP or UDP, must be in the rule pattern as well::
- flow create 0 ingress pattern integrity level is 0 value mask l3_ok
value spec l3_ok / eth / ipv6 / end …
+ flow create 0 ingress pattern integrity level is 0 value mask l3_ok
value spec l3_ok / eth / ipv6 / end …
- flow create 0 ingress pattern integrity level is 0 value mask l4_ok
value spec l4_ok / eth / ipv4 proto is udp / end …
+ flow create 0 ingress pattern integrity level is 0 value mask l4_ok
value spec l4_ok / eth / ipv4 proto is udp / end …
+
+ - With HW steering (``dv_flow_en=2``)
+ - The ``l3_ok`` field represents all L3 checks, but nothing about whether
IPv4 checksum ok.
+ - The ``l4_ok`` field represents all L4 checks including L4 checksum ok.
- Connection tracking:
diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c
b/drivers/net/mlx5/hws/mlx5dr_definer.c
index b2c0655790..84d15a41df 100644
--- a/drivers/net/mlx5/hws/mlx5dr_definer.c
+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c
@@ -384,10 +384,8 @@ mlx5dr_definer_integrity_set(struct mlx5dr_definer_fc *fc,
uint32_t ok1_bits = 0;
if (v->l3_ok)
- ok1_bits |= inner ? BIT(MLX5DR_DEFINER_OKS1_SECOND_L3_OK) |
-
BIT(MLX5DR_DEFINER_OKS1_SECOND_IPV4_CSUM_OK) :
- BIT(MLX5DR_DEFINER_OKS1_FIRST_L3_OK) |
- BIT(MLX5DR_DEFINER_OKS1_FIRST_IPV4_CSUM_OK);
+ ok1_bits |= inner ? BIT(MLX5DR_DEFINER_OKS1_SECOND_L3_OK) :
+ BIT(MLX5DR_DEFINER_OKS1_FIRST_L3_OK);
if (v->ipv4_csum_ok)
ok1_bits |= inner ?
BIT(MLX5DR_DEFINER_OKS1_SECOND_IPV4_CSUM_OK) :
--
2.18.2
