[PATCH] D50448: [CGObjCGNU] Rename GetSelector helper method to fix -Woverloaded-virtual warning (PR38210)

RKSimon created this revision. RKSimon added a reviewer: theraven. As suggested by @theraven on PR38210, this patch fixes the gcc -Woverloaded-virtual warnings by renaming the extra CGObjCGNU::GetSelector method to CGObjCGNU::GetTypedSelector Repository: rC Clang https://reviews.llvm.org/D5

[PATCH] D50448: [CGObjCGNU] Rename GetSelector helper method to fix -Woverloaded-virtual warning (PR38210)

This revision was automatically updated to reflect the committed changes. Closed by commit rL339264: [CGObjCGNU] Rename GetSelector helper method to fix -Woverloaded-virtual… (authored by RKSimon, committed by ). Herald added a subscriber: llvm-commits. Changed prior to commit: https://reviews.

[PATCH] D46863: [X86] Use __builtin_convertvector to implement some of the packed integer to packed flow conversion intrinsics.

RKSimon added reviewers: efriedma, hfinkel. RKSimon added a comment. I'm all for keeping the scalar/vector behaviour the same but I'm concerned about constant folding not taking into account runtime rounding mode: e,.g. SelectionDAG::getNode - we don't check the return status of convertFromAPIn

[PATCH] D47125: [X86] Remove masking from pternlog llvm intrinsics and use a select instruction instead.

RKSimon accepted this revision. RKSimon added a comment. This revision is now accepted and ready to land. LGTM - I'd love to see constexpr arguments someday in C/C++ to avoid all of these macro shenanigans... Repository: rC Clang https://reviews.llvm.org/D47125 ___

[PATCH] D47174: [X86] Move 128-bit f16c intrinsics to __emmintrin_f16c.h include from emmintrin.h. Move 256-bit f16c intrinsics back to f16cintrin.h

RKSimon added a comment. Aren't all the instructions from the same CPUID bit? It seems odd to split them across multiple files. Repository: rC Clang https://reviews.llvm.org/D47174 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://l

[PATCH] D47174: [X86] Move 128-bit f16c intrinsics to __emmintrin_f16c.h include from emmintrin.h. Move 256-bit f16c intrinsics back to f16cintrin.h

RKSimon added a comment. In https://reviews.llvm.org/D47174#1108329, @craig.topper wrote: > It is odd, but they really are split in the icc include files. So they got > split a while back in clang to match the Intel Intrinsic Guide documentation. OK - if that means we're matching latest icc/gc

[PATCH] D47401: [X86] Rewrite the max and min reduction intrinsics to make better use of other functions and to reduce width to 256 and 128 bits were possible.

RKSimon added inline comments. Comment at: cfe/trunk/lib/Headers/avx512fintrin.h:9855 + __v8di __t6 = (__v8di)_mm512_##op(__t4, __t5); \ + return __t6[0]; Would it be dumb to allow VLX capable CPUs to use 128/256 variants of the VPMAXUQ etc ? Or is it better

[PATCH] D38683: [X86][AVX512] lowering broadcastm intrinsic - clang part

RKSimon added inline comments. Comment at: test/CodeGen/avx512cdintrin.c:106 + // CHECK: insertelement <16 x i32> %{{.*}}, i32 %{{.*}} + return _mm512_broadcastmw_epi32(_mm512_cmpeq_epi32_mask ( a, b)); } Any reason why you can't use the actual insertion indi

[PATCH] D38781: [X86] Add CLWB intrinsic. clang part

RKSimon added inline comments. Comment at: lib/Headers/clwbintrin.h:34 + +static __inline__ void __DEFAULT_FN_ATTRS +_mm_clwb(void const *__m) { Worth adding the doxygen description? You can probably just copy+paste+modify the _mm_clflush documentation. ==

[PATCH] D38781: [X86] Add CLWB intrinsic. clang part

RKSimon accepted this revision. RKSimon added a comment. This revision is now accepted and ready to land. LGTM - one minor Comment at: lib/Headers/clwbintrin.h:42 +/// +/// \param __p +///A pointer to the memory location used to identify the cache line to be ---

[PATCH] D38813: [X86] Add skeleton support for "knm" cpu - clang side

RKSimon accepted this revision. RKSimon added a comment. This revision is now accepted and ready to land. LGTM Comment at: lib/Basic/Targets/X86.cpp:232 + case CK_KNM: case CK_KNL: Worth adding a TODO comment for the missing features? https://reviews.ll

[PATCH] D51771: [X86] Modify addcarry/subborrow builtins to emit an 2 result and intrinsic and an store instruction.

RKSimon accepted this revision. RKSimon added a comment. This revision is now accepted and ready to land. LGTM Repository: rC Clang https://reviews.llvm.org/D51771 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-

[PATCH] D51805: [X86] Custom emit __builtin_rdtscp so we can emit an explicit store for the out parameter

RKSimon accepted this revision. RKSimon added a comment. This revision is now accepted and ready to land. LGTM - The lack of existing tests is worrying. https://reviews.llvm.org/D51805 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http

[PATCH] D42530: Clang permits assignment to vector/extvector elements in a const method

RKSimon added a comment. @avt77 Close this now that https://reviews.llvm.org/rL324721 has landed? https://reviews.llvm.org/D42530 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D33406: PR28129 expand vector oparation to an IR constant.

RKSimon closed this revision. RKSimon added a comment. https://reviews.llvm.org/rL305551 https://reviews.llvm.org/D33406 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D41520: smmintrin.h documentation fixes and updates

RKSimon accepted this revision. RKSimon added a comment. This revision is now accepted and ready to land. LGTM https://reviews.llvm.org/D41520 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe

[PATCH] D41518: pmmintrin.h documentation fixes and updates

RKSimon accepted this revision. RKSimon added a comment. This revision is now accepted and ready to land. LGTM https://reviews.llvm.org/D41518 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe

[PATCH] D41523: xmmintrin.h documentation fixes and updates

RKSimon added a comment. Sort of related - should we enable -Wdocumentation (it's currently -Wall and -Weverything might be too much) on the respective clang builtin tests? Doesn't have to be part of this patch. Comment at: lib/Headers/xmmintrin.h:1927 /// -/// This intr

[PATCH] D41507: avxintrin.h documentation fixes and updates

RKSimon accepted this revision. RKSimon added a comment. This revision is now accepted and ready to land. LGTM https://reviews.llvm.org/D41507 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe

[PATCH] D41517: mmintrin.h documentation fixes and updates

RKSimon added inline comments. Comment at: lib/Headers/mmintrin.h:1292 /// -/// This intrinsic corresponds to the VXORPS / XORPS instruction. +/// This intrinsic corresponds to the XOR instruction. /// craig.topper wrote: > kromanova wrote: > > craig.topper

[PATCH] D41517: mmintrin.h documentation fixes and updates

RKSimon added a comment. Any more comments? https://reviews.llvm.org/D41517 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D41517: mmintrin.h documentation fixes and updates

RKSimon accepted this revision. RKSimon added a comment. This revision is now accepted and ready to land. LGTM - thanks https://reviews.llvm.org/D41517 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/lis

[PATCH] D41168: [X86] Lowering X86 avx512 sqrt intrinsics to IR

RKSimon requested changes to this revision. RKSimon added a comment. This revision now requires changes to proceed. In https://reviews.llvm.org/D41168#1118624, @tkrupa wrote: > Mask scalar case is closed and doesn't have any effects on this revision. > Besides, I resolved issues connected to low

[PATCH] D41168: [X86] Lowering X86 avx512 sqrt intrinsics to IR

RKSimon added inline comments. Comment at: test/CodeGen/sse2-builtins.c:1199 // CHECK-LABEL: test_mm_sqrt_sd - // CHECK: call <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double> %{{.*}}) - // CHECK: extractelement <2 x double> %{{.*}}, i32 0 - // CHECK: insertelement <2 x doub

[PATCH] D47693: [X86] Use target independent masked expandload and compressstore intrinsics to implement expandload/compressstore builtins.

RKSimon accepted this revision. RKSimon added a comment. This revision is now accepted and ready to land. We're going to need more codegen tests on the llvm side - test coverage (fast-isel and intrinsics) isn't great. But LGTM on the clang side. Repository: rC Clang https://reviews.llvm.org/

[PATCH] D41168: [X86] Lowering X86 avx512 sqrt intrinsics to IR

RKSimon added a comment. LGTM as well Repository: rL LLVM https://reviews.llvm.org/D41168 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D47401: [X86] Rewrite the max and min reduction intrinsics to make better use of other functions and to reduce width to 256 and 128 bits were possible.

RKSimon added a comment. Is there any llvm side fast isel tests for these? Comment at: cfe/trunk/lib/Headers/avx512fintrin.h:9855 + __v8di __t6 = (__v8di)_mm512_##op(__t4, __t5); \ + return __t6[0]; craig.topper wrote: > RKSimon wrote: > > Would it be dumb

[PATCH] D47401: [X86] Rewrite the max and min reduction intrinsics to make better use of other functions and to reduce width to 256 and 128 bits were possible.

RKSimon accepted this revision. RKSimon added a comment. This revision is now accepted and ready to land. OK, if the llvm side tests are incoming I'm happy with this patch https://reviews.llvm.org/D47401 ___ cfe-commits mailing list cfe-commits@list

[PATCH] D48346: [X86] Rewrite the add/mul/or/and reduction intrinsics to make better use of other intrinsics and remove undef shuffle indices.

RKSimon added inline comments. Comment at: test/CodeGen/avx512-reduceIntrin.c:1 // RUN: %clang_cc1 -ffreestanding %s -O2 -triple=x86_64-apple-darwin -target-cpu skylake-avx512 -emit-llvm -o - -Wall -Werror | FileCheck %s We're using -O2 here but most codegen

[PATCH] D48346: [X86] Rewrite the add/mul/or/and reduction intrinsics to make better use of other intrinsics and remove undef shuffle indices.

RKSimon accepted this revision. RKSimon added a comment. This revision is now accepted and ready to land. LGTM (with suitable IR fast-isel tests in llvm) https://reviews.llvm.org/D48346 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://

[PATCH] D48487: [X86][AVX512] Lowering _mm512_[max|min]_p[s|d] to native IR

RKSimon added a comment. I haven't used the AVX512 versions, but I do know plenty of cases that rely on the 'use the second op if there is a NAN or both zeros' special cases in the SSE version of these FMIN/FMAX intrinsics. The Intel docs state: > If the values being compared are both 0.0s (of

[PATCH] D52967: Extend shelf-life by 70 years

RKSimon resigned from this revision. RKSimon added reviewers: rsmith, bruno, rtrieu. RKSimon added a comment. Sorry I'm not the right person to review this - adding some other potentials Repository: rC Clang https://reviews.llvm.org/D52967 ___ cf

[PATCH] D56530: [X86] Add versions of the avx512 gather intrinsics that take the mask as a vXi1 vector instead of a scalar (clang side)

RKSimon accepted this revision. RKSimon added a comment. This revision is now accepted and ready to land. LGTM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D56530/new/ https://reviews.llvm.org/D56530 ___ cfe-commits mailing list cfe-commits

[PATCH] D56965: [X86] Remove the cvtuqq2ps256/cvtqq2ps256 mask builtins. Replace with uitofp/sitofp and select.

RKSimon added a comment. Just to confirm, this isn't driven by RC in any way? cvtsi642ps isn't so I don't expect it to be, but just to be sure.. Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D56965/new/ https://reviews.llvm.org/D56965 _

[PATCH] D56965: [X86] Remove the cvtuqq2ps256/cvtqq2ps256 mask builtins. Replace with uitofp/sitofp and select.

RKSimon accepted this revision. RKSimon added a comment. This revision is now accepted and ready to land. OK - LGTM, thanks Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D56965/new/ https://reviews.llvm.org/D56965 ___

[PATCH] D56998: [X86] Custom codegen 512-bit cvt(u)qq2tops, cvt(u)qqtopd, and cvt(u)dqtops intrinsics.

RKSimon accepted this revision. RKSimon added a comment. This revision is now accepted and ready to land. LGTM Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D56998/new/ https://reviews.llvm.org/D56998 ___ cfe-commits

[PATCH] D58675: [clang] Adds `-ftime-trace` option to clang that produces Chrome `chrome://tracing` compatible JSON profiling output dumps

RKSimon added a comment. Ideally I think you need more clang/frontend experts reviewers - many of us on the reviewers list tend to work mainly in llvm. Test cases would be good as well - even if its just basic sanity tests for command line args etc. Comment at: clang/lib/Sem

[PATCH] D58675: [clang] Adds `-ftime-trace` option to clang that produces Chrome `chrome://tracing` compatible JSON profiling output dumps

RKSimon added inline comments. Comment at: clang/lib/Sema/SemaTemplateInstantiateDecl.cpp:23 #include "clang/Sema/Lookup.h" +#include "clang/Sema/SemaInternal.h" #include "clang/Sema/Template.h" anton-afanasyev wrote: > RKSimon wrote: > > nfc change? > What do

[PATCH] D58675: [clang] Adds `-ftime-trace` option to clang that produces Chrome `chrome://tracing` compatible JSON profiling output dumps

RKSimon added a comment. @rsmith Any suggestions for good reviewers for this please? CHANGES SINCE LAST ACTION https://reviews.llvm.org/D58675/new/ https://reviews.llvm.org/D58675 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://li

[PATCH] D59287: [X86] Only define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 in 64-bit mode.

RKSimon added a comment. I agree that its not great, but I don't think we're going to do much better - and matching gcc behaviours does make sense here. Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D59287/new/ https://reviews.llvm.org/D59287 _

[PATCH] D59557: Fix CodeGen/arm64-microsoft-status-reg.cpp test

RKSimon added a comment. I thought we weren't supposed to reference asm codegen in clang tests? (PR24580) Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D59557/new/ https://reviews.llvm.org/D59557 ___ cfe-commits maili

[PATCH] D59567: [X86] Add __popcntd and __popcntq to ia32intrin.h to match gcc and icc. Remove popcnt feature flag from _popcnt32/_popcnt64 and move to ia32intrin.h to match gcc

RKSimon added a comment. IIRC we don't use libcalls for popcnt - we just expand Comment at: clang/lib/Headers/ia32intrin.h:35 +/// +/// This intrinsic corresponds to the POPCNT instruction. +/// Change this as we don't require POPCNT any more? CHANGES SINCE

[PATCH] D59533: [X86] Add __crc32b/__crc32w/__crc32d/__crc32q intrinsics to match gcc and icc.

RKSimon accepted this revision. RKSimon added a comment. This revision is now accepted and ready to land. LGTM with one minor (doxygen desciptions) Comment at: lib/Headers/ia32intrin.h:58 +static __inline__ unsigned int __attribute__((__always_inline__, __nodebug__, __target

[PATCH] D59567: [X86] Add __popcntd and __popcntq to ia32intrin.h to match gcc and icc. Remove popcnt feature flag from _popcnt32/_popcnt64 and move to ia32intrin.h to match gcc

RKSimon accepted this revision. RKSimon added a comment. This revision is now accepted and ready to land. LGTM with some minor typos Comment at: lib/Headers/ia32intrin.h:36 + * This intrinsic corresponds to the POPCNT instruction or a + * a sequence of arithmetic and logic

[PATCH] D59682: [X86] Add BSR/BSF/BSWAP intrinsics to ia32intrin.h to match gcc.

RKSimon added inline comments. Comment at: lib/Headers/ia32intrin.h:31 +static __inline__ int __attribute__((__always_inline__, __nodebug__)) +__bsfd(int __A) { Ideally we'd have doxygen comments. Comment at: test/CodeGen/bitscan-builtins.c:2

[PATCH] D59682: [X86] Add BSR/BSF/BSWAP intrinsics to ia32intrin.h to match gcc.

RKSimon accepted this revision. RKSimon added a comment. This revision is now accepted and ready to land. LGTM - cheers Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D59682/new/ https://reviews.llvm.org/D59682 ___ cfe

[PATCH] D59744: Fix i386 ABI "__m64" type bug

RKSimon added inline comments. Comment at: test/CodeGen/x86_32-mmx-linux.c:2 +// RUN: %clang_cc1 -w -O2 -fblocks -triple i386-pc-linux-gnu -target-cpu pentium4 -emit-llvm -o %t %s +// RUN: FileCheck < %t %s + Test on more triples and add the test file to trunk w

[PATCH] D60674: [X86] Restore the pavg intrinsics.

RKSimon accepted this revision. RKSimon added a comment. This revision is now accepted and ready to land. LGTM - there's too many different optimizations and canonicalizations that can occur on such a pattern to be able to match all of the permutations. We can probably add some InstCombine optim

[PATCH] D59744: Fix i386 ABI "__m64" type bug

RKSimon added inline comments. Comment at: test/CodeGen/x86_32-m64-darwin.c:1 +// RUN: %clang_cc1 -w -fblocks -triple i386-apple-darwin9 -target-cpu yonah -target-feature +mmx -emit-llvm -O2 -o - %s | FileCheck %s + You should be able to merge all of these tripl

[PATCH] D59744: Fix i386 ABI "__m64" type bug

RKSimon added a comment. One last style comment from me but we need somebody better with the different ABIs to finally approve this. Comment at: lib/CodeGen/TargetInfo.cpp:1416 + return ABIArgInfo::getDirect(llvm::Type::getX86_MMXTy(getVMContext())); +} +

[PATCH] D60552: [X86] Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake

RKSimon added inline comments. Comment at: lib/Headers/avx512bf16intrin.h:23 + +static __inline__ __m512bh __DEFAULT_FN_ATTRS512 +_mm512_cvtne2ps_pbh(__m512 __A, __m512 __B) { All of these need proper doxygen based descriptions - see xmmintrin.h etc. for example

[PATCH] D58404: [clang-format] Add basic support for formatting C# files

RKSimon added inline comments. Comment at: lib/Format/FormatTokenLexer.cpp:249 + Identifier->ColumnWidth += Question->ColumnWidth; + Identifier->Type = Identifier->Type; + Tokens.erase(Tokens.end() - 1); @MyDeveloperDay Should this be ``` Identifier->Type = Qu

[PATCH] D60937: [clangd] Fix code completion of macros defined in the preamble region of the main file.

RKSimon added a comment. @sammccall I'm sorry but I had to revert this to fix the buildbots: http://lab.llvm.org:8011/builders/llvm-clang-lld-x86_64-scei-ps4-ubuntu-fast/builds/47684/ Repository: rCTE Clang Tools Extra CHANGES SINCE LAST ACTION https://reviews.llvm.org/D60937/new/ https:/

[PATCH] D61281: [clang-format] Fixed self assignment

RKSimon added a reviewer: RKSimon. RKSimon added a comment. In D61281#1485833 , @MyDeveloperDay wrote: > Did this cause some issue? Does this fix something if so can we add a test, > because maybe the line isn't needed > > I would think we'd want to keep

[PATCH] D61472: [X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.

RKSimon added a comment. Where did all the clang diffs come from? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D61472/new/ https://reviews.llvm.org/D61472 ___ cfe-commits mailing list cfe-commits@lists

[PATCH] D60934: [clang] adding explicit(bool) from c++2a

RKSimon added inline comments. Comment at: cfe/trunk/lib/Parse/ParseDecl.cpp:3939 + "both or neither of isAlreadyConsumed and " + "RangeEnd needs to be set"); +DS.SetRangeEnd(isAlreadyConsumed ? RangeEnd

[PATCH] D52392: [X86] For lzcnt/tzcnt intrinsics use cttz/ctlz intrinsics with zero_undef flag set to false.

RKSimon added a comment. Are there other targets that would benefit from this and if so should we provide a more generic intrinsic? Repository: rC Clang https://reviews.llvm.org/D52392 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http

[PATCH] D52392: [X86] For lzcnt/tzcnt intrinsics use cttz/ctlz intrinsics with zero_undef flag set to false.

RKSimon accepted this revision. RKSimon added a comment. This revision is now accepted and ready to land. LGTM, thanks for checking. Please update the *-intrinsics-fast-isel.ll llvm test cases to match the *-builtins.c changes. Repository: rC Clang https://reviews.llvm.org/D52392 ___

[PATCH] D52665: [X86] Add more of the icc unaligned load/store to/from 128 bit vector intrinsics

RKSimon added a comment. Just to confirm - does icc provide the si64 intrinsics on 32-bit builds? https://reviews.llvm.org/D52665 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D52665: [X86] Add more of the icc unaligned load/store to/from 128 bit vector intrinsics

RKSimon accepted this revision. RKSimon added a comment. This revision is now accepted and ready to land. Thanks for checking - LGTM with the equivalent updates to sse2-intrinsics-fast-isel.ll https://reviews.llvm.org/D52665 ___ cfe-commits mailing

[PATCH] D37448: Fix cast assertion on MS inline assembly with vector spills (PR34021)

RKSimon created this revision. I can add the other test cases from PR34021 if required? Repository: rL LLVM https://reviews.llvm.org/D37448 Files: lib/CodeGen/CGStmt.cpp test/CodeGen/pr34021.c Index: test/CodeGen/pr34021.c ===

[PATCH] D37449: [X86][AVX512] _mm512_stream_load_si512 should take a void const* argument (PR33977)

RKSimon created this revision. Based off the Intel Intrinsics guide, we should expect a void const* argument. Prevents 'passing 'const void *' to parameter of type 'void *' discards qualifiers' warnings. Repository: rL LLVM https://reviews.llvm.org/D37449 Files: lib/Headers/avx512fintrin

[PATCH] D37449: [X86][AVX512] _mm512_stream_load_si512 should take a void const* argument (PR33977)

This revision was automatically updated to reflect the committed changes. Closed by commit rL312523: [X86][AVX512] _mm512_stream_load_si512 should take a void const* argument… (authored by RKSimon). Changed prior to commit: https://reviews.llvm.org/D37449?vs=113786&id=113819#toc Repository:

[PATCH] D37448: Fix cast assertion on MS inline assembly with vector spills (PR34021)

RKSimon added a comment. In https://reviews.llvm.org/D37448#861019, @erichkeane wrote: > I apologize for the lack of detail for this comment, but I didn't seem to > capture this at the time. When I investigated this initially, I came up with > this solution and it was insufficient. I don't re

[PATCH] D37413: [X86][MS-InlineAsm] Extended support for variables / identifiers on memory / immediate expressions

RKSimon added a reviewer: RKSimon. RKSimon added a comment. Tests? Comment at: lib/Sema/SemaStmtAsm.cpp:71 +if (!Piece.isOperand()) + continue; This all looks like a clang-format NFC change - just commit it? Comment at: lib/Sema/Se

[PATCH] D37668: [X86][intrinsics] lower _mm[256|512]_mask[z]_set1_epi[8|16|32|64] intrinsic to IR

RKSimon added a comment. As with https://reviews.llvm.org/D37562, strip the builtins from include/clang/Basic/BuiltinsX86.def https://reviews.llvm.org/D37668 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mail

[PATCH] D37448: Fix cast assertion on MS inline assembly with vector spills (PR34021)

RKSimon updated this revision to Diff 114569. RKSimon added a comment. Added checks to test case Repository: rL LLVM https://reviews.llvm.org/D37448 Files: lib/CodeGen/CGStmt.cpp test/CodeGen/pr34021.c Index: test/CodeGen/pr34021.c ==

[PATCH] D37448: Fix cast assertion on MS inline assembly with vector spills (PR34021)

RKSimon added a comment. In https://reviews.llvm.org/D37448#866700, @rnk wrote: > lgtm > > I was hoping for a test case that didn't require assertions, but this is > enough to land the fix. My mistake, I should be able to remove that as well - I'll do it as part of the commit. Thanks. Repos

[PATCH] D37448: Fix cast assertion on MS inline assembly with vector spills (PR34021)

This revision was automatically updated to reflect the committed changes. Closed by commit rL313019: [MS-InlineAsm] Fix cast assertion with vector spills (PR34021) (authored by RKSimon). Changed prior to commit: https://reviews.llvm.org/D37448?vs=114569&id=114794#toc Repository: rL LLVM htt

[PATCH] D37668: [X86][intrinsics] lower _mm[256|512]_mask[z]_set1_epi[8|16|32|64] intrinsic to IR

RKSimon added a comment. some very minor whitespace/indentation issues please can you confirm @craig.topper's query about __builtin_ia32_pbroadcastq512_mem_mask Comment at: lib/Headers/avx512vlintrin.h:5727 +static __inline__ __m128i __DEFAULT_FN_ATTRS + _mm_mask_set1_epi32(

[PATCH] D37892: [X86] Use native shuffle vector for the perm2f128 intrinsics

RKSimon added a comment. _mm256_permute2x128_si256 ? https://reviews.llvm.org/D37892 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D37892: [X86] Use native shuffle vector for the perm2f128 intrinsics

RKSimon added a comment. Also, there currently isn't any testing of the zero vector case. https://reviews.llvm.org/D37892 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D37892: [X86] Use native shuffle vector for the perm2f128 intrinsics

RKSimon accepted this revision. RKSimon added a comment. This revision is now accepted and ready to land. LGTM - please can you update the avx-intrinsics-fast-isel.ll/avxs-intrinsics-fast-isel.ll cases to match the *-builtins.c as well (either now or if/when you add the intrinsics to autoupgrad

[PATCH] D37941: [X86] Move even more of our CPU to feature mapping switch to use fallthroughs

RKSimon accepted this revision. RKSimon added a comment. This revision is now accepted and ready to land. LGTM, there are a couple of other fall-throughs that could still be done. Comment at: lib/Basic/Targets/X86.cpp:141 setFeatureEnabledImpl(Features, "sse2", true);

[PATCH] D37938: [X86] Remove unnecessary extra encodings from the CPU name enum in clang

RKSimon accepted this revision. RKSimon added a comment. This revision is now accepted and ready to land. LGTM https://reviews.llvm.org/D37938 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe

[PATCH] D62282: [X86] Add ENQCMD intrinsics.

RKSimon accepted this revision. RKSimon added a comment. In D62282#1528631 , @tianqing wrote: > Added doxygen comments of intrinsics in enqcmdintrin.h. Thanks, LGTM as well. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D62282/new/ https://revi

[PATCH] D62363: [X86] Enable intrinsics that convert float and bf16 data to each other

RKSimon accepted this revision. RKSimon added a comment. Yup, doxygen LGTM - cheers Comment at: lib/Headers/avx512bf16intrin.h:33 + +/// Convert One BF16 Data to One Single Data. +/// Single Float Data CHANGES SINCE LAST ACTION https://reviews.llvm.org/D623

[PATCH] D63018: [X86] Attempt to make the Intel core CPU inheritance a little more readable and maintainable

RKSimon accepted this revision. RKSimon added a comment. This revision is now accepted and ready to land. LGTM - the goto is unfortunate but more maintainable and less confusing then the current state of things Comment at: clang/lib/Basic/Targets/X86.cpp:157 +setFeatureEna

[PATCH] D63473: Support -fclang-abi-compat=8.0 to keep old ABI behavior

RKSimon added inline comments. Comment at: test/CodeGen/x86_32-m64.c:6 // RUN: %clang_cc1 -w -O2 -fblocks -triple i386-pc-win32 -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,WIN32 +// RUN: %clang_cc1 -w -O2 -fblocks -triple i386-pc-linux-gnu -target-cpu pentium4 -em

[PATCH] D59744: Fix i386 ABI "__m64" type bug

RKSimon added a comment. I've raised https://bugs.llvm.org/show_bug.cgi?id=42319 which suggests the creation of a EMMS insertion pass. Repository: rL LLVM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D59744/new/ https://reviews.llvm.org/D59744

[PATCH] D64416: [AArch64] Add support for Transactional Memory Extension (TME)

RKSimon added a comment. @chill This is failing on buildbots with EXPENSIVE_CHECKS enabled: http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/18684/steps/test-check-all/logs/stdio Repository: rL LLVM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D64416/ne

[PATCH] D64416: [AArch64] Add support for Transactional Memory Extension (TME)

RKSimon added inline comments. Comment at: llvm/test/CodeGen/AArch64/tme-tcancel.ll:1 +; RUN: llc %s -o - | FileCheck %s + Would it make sense to add -verify-machineinstrs to all these Codegen/AArch64/tme-*.ll tests? CHANGES SINCE LAST ACTION https://reviews

[PATCH] D65110: [NewPM] Run avx*-builtins.c tests under the new pass manager only

RKSimon added inline comments. Comment at: clang/test/CodeGen/avx512vlbw-builtins.c:904 + // CHECK: [[TMP:%.*]] = bitcast [[SRCTY:<.*>]] [[SEL]] to [[DSTTY:<.*>]] + // CHECK: [[SEL:%.*]] = bitcast [[DSTTY]] [[TMP]] to [[SRCTY]] // CHECK: select <16 x i1> %{{.*}}, <16 x i8> [

[PATCH] D64638: [CrossTU] Fix plist macro expansion if macro in other file.

RKSimon added a comment. @balazske This is causing buildbot failures - revert? Repository: rL LLVM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D64638/new/ https://reviews.llvm.org/D64638 ___ cfe-commits mailing list cfe-commits@lists.ll

[PATCH] D25845: [CUDA] Ignore implicit target attributes during function template instantiation.

RKSimon added inline comments. Herald added subscribers: llvm-commits, sanjoy.google, bixia. Herald added a project: LLVM. Comment at: cfe/trunk/lib/Sema/SemaDecl.cpp:8416 +// in the CheckFunctionTemplateSpecialization() call below. +if (getLangOpts().CUDA & !isFunctionTe

[PATCH] D63538: [CFG] Add a new function to get the proper condition of a CFGBlock

RKSimon added a comment. @Szelethus This is causing problems on windows buildbots http://lab.llvm.org:8011/builders/llvm-clang-lld-x86_64-scei-ps4-windows10pro-fast - revert? Repository: rL LLVM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D63538/new/ https://reviews.llvm.org/D6353

[PATCH] D63538: [CFG] Add a new function to get the proper condition of a CFGBlock

RKSimon added a comment. In D63538#1571454 , @Szelethus wrote: > In D63538#1571451 , @Szelethus wrote: > > > Since the followup patches test this roughly anyways, and the fact that the > > AST's lifetime ends right

[PATCH] D61637: [Syntax] Introduce syntax trees

RKSimon added a comment. @ilya-biryukov We're seeing buildbot failures in SyntaxTests.exe : http://lab.llvm.org:8011/builders/llvm-clang-lld-x86_64-scei-ps4-ubuntu-fast/builds/50927 http://lab.llvm.org:8011/builders/llvm-clang-lld-x86_64-scei-ps4-windows10pro-fast/builds/26822 Failing Tests (1):

[PATCH] D61637: [Syntax] Introduce syntax trees

RKSimon reopened this revision. RKSimon added a comment. This revision is now accepted and ready to land. @ilya-biryukov I'm sorry but I've reverted this at rL365465 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D

[PATCH] D64389: [NFC] [X86] Fix scan-build complaining

RKSimon accepted this revision. RKSimon added a comment. This revision is now accepted and ready to land. LGTM - cheers Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D64389/new/ https://reviews.llvm.org/D64389

[PATCH] D62232: [Clang][Driver] recheck for nullptr

RKSimon added a comment. According to the coverage report we don't have any coverage of TC == null at all - not sure if its (a) possible to add tests or (b) if we can ever have a non-null TC - so should we just assert? http://lab.llvm.org:8080/coverage/coverage-reports/clang/coverage/Users/buil

[PATCH] D62282: [X86] Add ENQCMD intrinsics.

RKSimon added inline comments. Comment at: lib/Headers/enqcmdintrin.h:21 + +static __inline__ int _DEFAULT_FN_ATTRS +_enqcmd (void *__dst, const void *__src) Please add doxygen comments describing the intrinsics Repository: rC Clang CHANGES SINCE LAST ACTION

[PATCH] D62363: [X86] Enable intrinsics that convert float and bf16 data to each other

RKSimon added inline comments. Comment at: lib/Headers/avx512bf16intrin.h:52 +/// +/// \headerfile +/// \headerfile Comment at: lib/Headers/avx512bf16intrin.h:54 +/// +/// This intrinsic is lowered to LLVM IR. +/// Please can

[PATCH] D62367: [X86] VP2INTERSECT clang

RKSimon added inline comments. Comment at: lib/Headers/avx512vlvp2intersectintrin.h:39 + +static __inline__ void __DEFAULT_FN_ATTRS256 +_mm256_2intersect_epi32(__m256i __a, __m256i __b, __mmask8 *__m0, __mmask8 *__m1) { craig.topper wrote: > xiangzhangllvm wrote

[PATCH] D55879: [X86][SSE] Auto upgrade PADDUS/PSUBUS intrinsics to UADD_SAT/USUB_SAT generic intrinsics (clang)

RKSimon created this revision. RKSimon added reviewers: craig.topper, spatel, nikic, tkrupa. Herald added a subscriber: llvm-commits. Sibling patch to D55855 , this emits UADD_SAT/USUB_SAT generic intrinsics for the SSE saturated math intrinsics instead of expand

[PATCH] D55879: [X86][SSE] Auto upgrade PADDUS/PSUBUS intrinsics to UADD_SAT/USUB_SAT generic intrinsics (clang)

This revision was automatically updated to reflect the committed changes. Closed by commit rC349631: [X86][SSE] Auto upgrade PADDUS/PSUBUS intrinsics to UADD_SAT/USUB_SAT generic… (authored by RKSimon, committed by ). Changed prior to commit: https://reviews.llvm.org/D55879?vs=178839&id=178880#

[PATCH] D55890: [X86][SSE] Auto upgrade PADDS/PSUBS intrinsics to SADD_SAT/SSUB_SAT generic intrinsics (clang)

RKSimon created this revision. RKSimon added reviewers: craig.topper, spatel, nikic, tkrupa. Herald added a subscriber: llvm-commits. This emits SADD_SAT/SSUB_SAT generic intrinsics for the SSE saturated math intrinsics. I'm still working on the llvm sibling patch (auto upgrade etc.) as there's

[PATCH] D55890: [X86][SSE] Auto upgrade PADDS/PSUBS intrinsics to SADD_SAT/SSUB_SAT generic intrinsics (clang)

RKSimon updated this revision to Diff 178946. RKSimon added a comment. Use ArrayRef Repository: rL LLVM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D55890/new/ https://reviews.llvm.org/D55890 Files: lib/CodeGen/CGBuiltin.cpp test/CodeGen/avx2-builtins.c test/CodeGen/avx512bw-

[PATCH] D55890: [X86][SSE] Auto upgrade PADDS/PSUBS intrinsics to SADD_SAT/SSUB_SAT generic intrinsics (clang)

This revision was automatically updated to reflect the committed changes. Closed by commit rL349743: [X86][SSE] Auto upgrade PADDS/PSUBS intrinsics to SADD_SAT/SSUB_SAT generic… (authored by RKSimon, committed by ). Changed prior to commit: https://reviews.llvm.org/D55890?vs=178946&id=179036#to

[PATCH] D55937: [X86] Auto upgrade XOP/AVX512 rotation intrinsics to generic funnel shift intrinsics (clang)

RKSimon created this revision. RKSimon added reviewers: spatel, craig.topper. Herald added a subscriber: llvm-commits. This emits FSHL/FSHR generic intrinsics for the XOP VPROT and AVX512 VPROL/VPROR rotation intrinsics. Repository: rL LLVM https://reviews.llvm.org/D55937 Files: lib/CodeG

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