> From: Paul Koning
>>> core memory details such as destructive read weren't visible to the
>>> CPU
> DATAIP/DATAO on the Unibus doesn't depend on the destructive read
> property.
Yes, the CPU can't tell what the memory is doing.
> The reason it existed is that it allo
On 12/17/18 9:51 AM, Guy Sotomayor Jr wrote:
> Except it is *much* more expensive than MRAM. 32x8 NVSRAM is $18.50 in qty 1
> from Digikey.
> A 64Kx16 MRAM is $11.84 in qty 1 from Digikey. MRAM requires no additional
> circuitry so that
> also reduces the overall cost (and has unlimited write
> On Dec 17, 2018, at 10:52 AM, Noel Chiappa via cctalk
> wrote:
>
>> From: Paul Koning
>
>> For that matter, core memory details such as destructive read weren't
>> visible to the CPU
>
> Umm, not quite. If you'd said 'core memory details such as destructive read
> weren't visible to the _
> On Dec 17, 2018, at 1:52 PM, Noel Chiappa via cctalk
> wrote:
>
>> From: Paul Koning
>
>> For that matter, core memory details such as destructive read weren't
>> visible to the CPU
>
> Umm, not quite. If you'd said 'core memory details such as destructive read
> weren't visible to the _p
> From: Paul Koning
> For that matter, core memory details such as destructive read weren't
> visible to the CPU
Umm, not quite. If you'd said 'core memory details such as destructive read
weren't visible to the _program_', you'd have been 100% correct.
But as I suspect you know, jus
I've seen a lot of talk about memory technologies, but as far as I can see,
no one has offered any complete solutions.
One already exists, thanks to the efforts of Steve Lafferty, Vince
Slyngstad, and others.
http://so-much-stuff.com/pdp8/32KOmnibus/32KOmnibus.php
Yes, it uses a battery. FPGAs a
> On Dec 17, 2018, at 12:51 PM, Guy Sotomayor Jr via cctalk
> wrote:
>
>
>
>> On Dec 16, 2018, at 10:40 PM, Chuck Guzis via cctalk
>> wrote:
>>
>> On 12/16/18 11:21 AM, Paul Koning wrote:
>>
>>> If you simply want non-volatile memory, the obvious answer is SRAM with
>>> battery backup
> On Dec 16, 2018, at 10:40 PM, Chuck Guzis via cctalk
> wrote:
>
> On 12/16/18 11:21 AM, Paul Koning wrote:
>
>> If you simply want non-volatile memory, the obvious answer is SRAM with
>> battery backup and a small FPGA to do the interfacing.
>
> I proposed nvRAM - CMOS SRAM backed by cel
> On Dec 16, 2018, at 10:49 PM, Rod G8DGR via cctech
> wrote:
>
>
> I’m trying to make a look and feel reproduction PDP-8/e.
> So the memory characteristics need to be as close as possible.
>
> An original ( and I do have one) and the copy when placed side by side
> should run in sync.
On Sunday (12/16/2018 at 10:40PM -0800), Chuck Guzis via cctalk wrote:
> On 12/16/18 11:21 AM, Paul Koning wrote:
>
> > If you simply want non-volatile memory, the obvious answer is SRAM with
> > battery backup and a small FPGA to do the interfacing.
>
> I proposed nvRAM - CMOS SRAM backed by ce
> On Dec 16, 2018, at 10:07 PM, ben via cctalk wrote:
>
> On 12/16/2018 8:00 PM, allison via cctech wrote:
>
>> In the end, current generation CMOS ram is the easy out, battery is
>> small, cost is small, and
>> produces much less of the heat that is killer to systems. The only
>> reason t
On 12/16/18 11:21 AM, Paul Koning wrote:
> If you simply want non-volatile memory, the obvious answer is SRAM with
> battery backup and a small FPGA to do the interfacing.
I proposed nvRAM - CMOS SRAM backed by cell-for-cell flash. Loads SRAM
from flash on power-up and stores into flash at powe
> On Dec 16, 2018, at 8:21 PM, allison via cctech wrote:
>
> On 12/15/2018 03:51 PM, Jon Elson via cctech wrote:
>> On 12/15/2018 02:45 PM, Anders Nelson via cctalk wrote:
>>> Serial flash has an endurance between 10K-100K writes per cell so I
>>> think
>>> that would break down quickly. Wear-l
On 12/15/2018 09:32 PM, Charles Anthony via cctech wrote:
> On Sat, Dec 15, 2018 at 6:15 PM Rod G8DGR via cctalk
> wrote:
>
>> All very interesting.. 1201 alarm while I deal will all of the information
>> Rod
>>
>>
> 1202 coming up...
>
> I don't know specifically about the various memory types be
I put focal in it...I leave focal in it... then I turn on the power it
talks focal to a tty!
( for grains want copy of focal 11 for the 11/20 too...)
But definitely want to see focal on a little omnibus 8! Just like that
famous night in 1979..
Life is good Ed#
In
On 12/15/2018 03:51 PM, Jon Elson via cctech wrote:
> On 12/15/2018 02:45 PM, Anders Nelson via cctalk wrote:
>> Serial flash has an endurance between 10K-100K writes per cell so I
>> think
>> that would break down quickly. Wear-leveling on a serial device would be
>> very slow...
>>
>>
> If you in
On 12/16/2018 10:07 PM, ben via cctech wrote:
> On 12/16/2018 8:00 PM, allison via cctech wrote:
>
>> In the end, current generation CMOS ram is the easy out, battery is
>> small, cost is small, and
>> produces much less of the heat that is killer to systems. The only
>> reason to do that is cor
On 12/16/2018 8:00 PM, allison via cctech wrote:
In the end, current generation CMOS ram is the easy out, battery is
small, cost is small, and
produces much less of the heat that is killer to systems. The only
reason to do that is core
cost big if you can find it for your machine. I can cost
Sent from Mail for Windows 10
From: ben via cctech
Sent: 17 December 2018 03:08
To: cct...@classiccmp.org
Subject: Re: Core memory emulator using non volatile ram.
On 12/16/2018 8:00 PM, allison via cctech wrote:
> In the end, current generation CMOS ram is the easy out, battery is
>
On Sun, 16 Dec 2018, Jon Elson via cctalk wrote:
made, but if they are still being made they might not be too bad. I'm not
sure 3D-printed housings would be strong enough for this, but maybe if ABS
PLA is actually a stiffer plastic than ABS. That being said, PETG might
be a better choice du
> On Dec 15, 2018, at 1:55 PM, Chuck Guzis via cctalk
> wrote:
>
> On 12/15/18 10:01 AM, Guy Sotomayor Jr via cctalk wrote:
>> FRAM or MRAM. I make extensive use of them in my projects.
>>
>> Everspin has a few (all SMT and 3.3v). As I recall they run ~$20/ea for 4Mb
>> (512K x 8 or 256K
Sent from Mail for Windows 10
From: Jon Elson via cctech
Sent: 16 December 2018 16:43
To: Rod G8DGR; gene...@ezwind.net; discuss...@ezwind.net:On-Topic Posts
Subject: Re: Core memory emulator using non volatile ram.
On 12/15/2018 11:19 PM, Rod G8DGR via cctech wrote:
>
>
> However I
On 12/15/2018 11:19 PM, Rod G8DGR via cctech wrote:
However I began to think would it be possible to create a close copy of an 8/e
out of modern parts.
Finally the big one – Omnibus and the connectors its made from. A 3D printing
candidate?
I’m going to autopsy a busted connector and see
Anyone building 8 omnibus batter backed up core replacement currently
that is available off the shelf reasonably for 8 m,e and f? (( Smaller
size board than the 8a would accept for memory as I remember..))
Have a 8 m or f in my den on a shelf... as as I best re
Sent from Mail for Windows 10
From: allison via cctech
Sent: 16 December 2018 03:08
To: cct...@classiccmp.org
Subject: Re: Core memory emulator using non volatile ram.
On 12/15/2018 01:01 PM, Guy Sotomayor Jr via cctech wrote:
> FRAM or MRAM. I make extensive use of them in my proje
> On Dec 15, 2018, at 7:09 PM, allison via cctech wrote:
>
> On 12/15/2018 01:01 PM, Guy Sotomayor Jr via cctech wrote:
>> FRAM or MRAM. I make extensive use of them in my projects.
>>
>> Everspin has a few (all SMT and 3.3v). As I recall they run ~$20/ea for 4Mb
>> (512K x 8 or 256K x 16).
On 12/15/2018 01:01 PM, Guy Sotomayor Jr via cctech wrote:
> FRAM or MRAM. I make extensive use of them in my projects.
>
> Everspin has a few (all SMT and 3.3v). As I recall they run ~$20/ea for 4Mb
> (512K x 8 or 256K x 16).
>
> TTFN - Guy
>
>> On Dec 15, 2018, at 1:22 AM, Rod G8DGR via cctalk
On Sat, Dec 15, 2018 at 6:15 PM Rod G8DGR via cctalk
wrote:
> All very interesting.. 1201 alarm while I deal will all of the information
> Rod
>
>
1202 coming up...
I don't know specifically about the various memory types being bandied
about, but I do know that the destructive read behavior of
On Sat, Dec 15, 2018 at 11:55 AM Chuck Guzis via cctalk <
cctalk@classiccmp.org> wrote:
> On 12/15/18 10:01 AM, Guy Sotomayor Jr via cctalk wrote:
> > FRAM or MRAM. I make extensive use of them in my projects.
> >
> > Everspin has a few (all SMT and 3.3v). As I recall they run ~$20/ea for
> 4Mb
On 12/15/18 1:30 PM, Warner Losh via cctalk wrote:
> True. Lessening the pain still doesn't make it right :). MRAM or FRAM does
> sound a lot simpler to use...
How about nvRAM? Faster, with high capacity. Stores into flash
(every CMOS RAM cell is paired with a flash cell) when the supply drops
On Sat, Dec 15, 2018, 2:25 PM Guy Sotomayor Jr
> > On Dec 15, 2018, at 1:18 PM, Warner Losh via cctalk <
> cctalk@classiccmp.org> wrote:
> >
> > On Sat, Dec 15, 2018, 1:51 PM Jon Elson via cctalk <
> cctalk@classiccmp.org
> > wrote:
> >
> >> On 12/15/2018 02:45 PM, Anders Nelson via cctalk wrote:
> On Dec 15, 2018, at 1:18 PM, Warner Losh via cctalk
> wrote:
>
> On Sat, Dec 15, 2018, 1:51 PM Jon Elson via cctalk wrote:
>
>> On 12/15/2018 02:45 PM, Anders Nelson via cctalk wrote:
>>> Serial flash has an endurance between 10K-100K writes per cell so I think
>>> that would break down qu
On Sat, Dec 15, 2018, 1:51 PM Jon Elson via cctalk On 12/15/2018 02:45 PM, Anders Nelson via cctalk wrote:
> > Serial flash has an endurance between 10K-100K writes per cell so I think
> > that would break down quickly. Wear-leveling on a serial device would be
> > very slow...
> >
> >
> If you in
> On Dec 15, 2018, at 12:51 PM, Jon Elson via cctalk
> wrote:
>
> On 12/15/2018 02:45 PM, Anders Nelson via cctalk wrote:
>> Serial flash has an endurance between 10K-100K writes per cell so I think
>> that would break down quickly. Wear-leveling on a serial device would be
>> very slow...
>>
On 12/15/2018 02:45 PM, Anders Nelson via cctalk wrote:
Serial flash has an endurance between 10K-100K writes per cell so I think
that would break down quickly. Wear-leveling on a serial device would be
very slow...
If you intend to use it as main core memory on an old CPU,
it will perform VER
Serial flash has an endurance between 10K-100K writes per cell so I think
that would break down quickly. Wear-leveling on a serial device would be
very slow...
On Sat, Dec 15, 2018, 3:33 PM Gerhard Kreuzer via cctalk <
cctalk@classiccmp.org wrote:
> Hi Rod,
>
> take some microcontroller and some
Hi Rod,
take some microcontroller and some serial flash memory.
With best regards
Gerhard
-Ursprüngliche Nachricht-
Von: cctalk [mailto:cctalk-boun...@classiccmp.org] Im Auftrag von
cctalk-requ...@classiccmp.org
Gesendet: Samstag, 15. Dezember 2018 19:00
An: cctalk@classiccmp.org
Betref
If you want the real deal you can always make a driver out of a bunch of
H-bridge ICs and an old core plane. I'll skip suggesting you weave your own
core...
On Sat, Dec 15, 2018, 2:01 PM systems_glitch via cctalk <
cctalk@classiccmp.org wrote:
> Chuck,
>
> FRAM is destructive read on the die, fro
Chuck,
FRAM is destructive read on the die, from what I understand. It's just that
the onboard controller takes care of it for you, much like a core subsystem.
Thanks,
Jonathan
On Sat, Dec 15, 2018 at 1:55 PM Chuck Guzis via cctalk <
cctalk@classiccmp.org> wrote:
> On 12/15/18 10:01 AM, Guy Sot
On 12/15/18 10:01 AM, Guy Sotomayor Jr via cctalk wrote:
> FRAM or MRAM. I make extensive use of them in my projects.
>
> Everspin has a few (all SMT and 3.3v). As I recall they run ~$20/ea for 4Mb
> (512K x 8 or 256K x 16).
As neither MRAM nor FRAM requires a write-after-read refresh, I fail
FRAM or MRAM. I make extensive use of them in my projects.
Everspin has a few (all SMT and 3.3v). As I recall they run ~$20/ea for 4Mb
(512K x 8 or 256K x 16).
TTFN - Guy
> On Dec 15, 2018, at 1:22 AM, Rod G8DGR via cctalk
> wrote:
>
> I have an idea to produce an MM-8 clone using RAM tha
On 12/15/2018 03:22 AM, Rod G8DGR via cctalk wrote:
I have an idea to produce an MM-8 clone using RAM that acts like core when
turned off.
Can anybody suggest a chip that will do this?
Any CMOS SRAM chips can do this, with a backup battery. I
used a IS62WV6416DBLL in a project a while ago.
1201.. 1201 .. Processing large amount of data...
Rod
Sent from Mail for Windows 10
From: Bob Rosenbloom via cctalk
Sent: 15 December 2018 16:45
To: cctalk@classiccmp.org
Subject: Re: Core memory emulator using non volatile ram.
On 12/15/2018 1:22 AM, Rod G8DGR via cctalk wrote:
> I have
All very interesting.. 1201 alarm while I deal will all of the information
Rod
Sent from Mail for Windows 10
From: systems_glitch via cctalk
Sent: 15 December 2018 16:40
To: Anders Nelson; General Discussion: On-Topic and Off-Topic Posts
Subject: Re: Core memory emulator using non volatile ram
On 12/15/2018 1:22 AM, Rod G8DGR via cctalk wrote:
I have an idea to produce an MM-8 clone using RAM that acts like core when
turned off.
Can anybody suggest a chip that will do this?
Rod Smallwood
Sent from Mail for Windows 10
I used Everspin MRAM chips for my PDP-8e memory cards. It's ju
n a century
> > of endurance.
> >
> > -Alan
> >
> >
> > On 2018-12-15 05:19, Paul Birkel via cctech wrote:
> > > Perhaps Cypress FM1808 (32Kx8). Obsolete, but available on eBay. SOP
> > > for a bit of extra challenge!
> > >
> > &
vailable on eBay. SOP
> > for a bit of extra challenge!
> >
> > -Original Message-
> > From: cctech [mailto:cctech-boun...@classiccmp.org] On Behalf Of Rod
> > G8DGR via cctech
> > Sent: Saturday, December 15, 2018 4:22 AM
> > To: General Discussion
cctech
Sent: Saturday, December 15, 2018 4:22 AM
To: General Discussion: On-Topic and Off-Topic Posts
Subject: Core memory emulator using non volatile ram.
I have an idea to produce an MM-8 clone using RAM that acts like core
when turned off.
Can anybody suggest a chip that will do this?
Rod
Off-Topic Posts
Subject: Core memory emulator using non volatile ram.
I have an idea to produce an MM-8 clone using RAM that acts like core when
turned off.
Can anybody suggest a chip that will do this?
Rod Smallwood
Sent from Mail for Windows 10
I have an idea to produce an MM-8 clone using RAM that acts like core when
turned off.
Can anybody suggest a chip that will do this?
Rod Smallwood
Sent from Mail for Windows 10
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