On 12/16/18 11:21 AM, Paul Koning wrote: > If you simply want non-volatile memory, the obvious answer is SRAM with > battery backup and a small FPGA to do the interfacing.
I proposed nvRAM - CMOS SRAM backed by cell-for-cell flash. Loads SRAM from flash on power-up and stores into flash at power-down. All that's needed is a capacitor to extend the power-down cycle a bit. Very fast, available in 8 to 32-bit wide architectures, up to 16Mbit per package. Claims to be guaranteed for 1M power cycles and doesn't require a battery. --Chuck
