On 4/9/2025 8:12 PM, Alex Deucher wrote:
On Wed, Apr 9, 2025 at 10:36 AM SRINIVASAN SHANMUGAM
wrote:
On 4/8/2025 9:30 PM, Alex Deucher wrote:
Switch from a bool to an enum and allow more options
for enforce isolation. There are now 3 modes of operation:
- Disabled (0)
- Enabled (serializat
The variable mode_422 is initialized to zero, making if (mode_422)
always false.
Removing this unimplemented code and the redundant check simplifies
the code without affecting functionality.
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Signed-off-by: Rostislav Nesin
---
..
On Wed, Apr 09, 2025 at 07:19:25PM +0530, Lazar, Lijo wrote:
>
>
> On 4/9/2025 7:09 PM, Ce Sun wrote:
> > Checking hive is more readable.
> >
> > The following smatch warning:
> > drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:6820 amdgpu_pci_slot_reset()
> > warn: iterator used outside loop: 'tmp_a
Enable doorbell for JPEG5_0_1 and adjust index for VCN5_0_1.
Signed-off-by: Sathishkumar S
---
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0
On Thu, Apr 10, 2025 at 7:48 AM Arvind Yadav wrote:
>
> This patch is load usermode queue based on FW support for gfx12.
> CP Ucode FW Vesion: [PFP = 2840, ME = 2780, MEC = 2600, MES = 123]
>
> Cc: Alex Deucher
> Cc: Christian Koenig
> Cc: Shashank Sharma
> Cc: Sunil Khatri
> Signed-off-by: Ar
The display backlight on TUXEDO Polaris AMD Gen2 and Gen3 with panels
BOE 2420 and BOE 2423 must be forced to pwn controlled to be able to
control the brightness.
This could already be archived via a module parameter, but this patch adds
a quirk to apply this by default on the mentioned device + p
Am 10.04.25 um 05:52 schrieb SRINIVASAN SHANMUGAM:
>
> On 4/9/2025 7:16 PM, SRINIVASAN SHANMUGAM wrote:
>>
>> On 4/9/2025 7:11 PM, SRINIVASAN SHANMUGAM wrote:
>>>
>>> On 4/9/2025 6:45 PM, SRINIVASAN SHANMUGAM wrote:
On 4/9/2025 4:15 PM, Christian König wrote:
> This reverts commit c2c
Apart from minor comment LGTM. Also lets wait for Alex to review the
series.
Reviewed-by: Sunil Khatri
On 4/10/2025 4:59 PM, Arvind Yadav wrote:
This patch is load usermode queue based on FW support for gfx12.
CP Ucode FW Vesion: [PFP = 2840, ME = 2780, MEC = 2600, MES = 123]
Cc: Alex Deuche
On 4/9/2025 7:26 PM, Dan Carpenter wrote:
> On Wed, Apr 09, 2025 at 07:19:25PM +0530, Lazar, Lijo wrote:
>>
>>
>> On 4/9/2025 7:09 PM, Ce Sun wrote:
>>> Checking hive is more readable.
>>>
>>> The following smatch warning:
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:6820 amdgpu_pci_slot_reset
Enable the cleaner shader for additional GFX11.5.2/11.5.3 series GPUs to
ensure data isolation among GPU tasks. The cleaner shader is tasked with
clearing the Local Data Store (LDS), Vector General Purpose Registers
(VGPRs), and Scalar General Purpose Registers (SGPRs), which helps avoid
data leaka
On Thu, Apr 10, 2025 at 10:57 AM Arvind Yadav wrote:
>
> This patch is load usermode queue based on FW support for gfx11.
> CP Ucode FW version: [PFP = 2530, ME = 2390, MEC = 2600, MES = 120]
>
> v2: Addressed review comments from Alex.
> - Just check the firmware versions directly.
>
> Cc: Al
On Thu, Apr 10, 2025 at 11:56 AM Yadav, Arvind wrote:
>
>
> On 4/10/2025 8:50 PM, Alex Deucher wrote:
> > On Thu, Apr 10, 2025 at 10:57 AM Arvind Yadav wrote:
> >> This patch is load usermode queue based on FW support for gfx11.
> >> CP Ucode FW version: [PFP = 2530, ME = 2390, MEC = 2600, MES =
[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Aurabindo Pillai
--
Regards,
Jay
From: Deucher, Alexander
Sent: Wednesday, April 9, 2025 5:41 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Pillai, Aurabindo
Subject: [PATC
On 4/10/2025 8:50 PM, Alex Deucher wrote:
On Thu, Apr 10, 2025 at 10:57 AM Arvind Yadav wrote:
This patch is load usermode queue based on FW support for gfx11.
CP Ucode FW version: [PFP = 2530, ME = 2390, MEC = 2600, MES = 120]
v2: Addressed review comments from Alex.
- Just check the f
On Tuesday, April 1st, 2025 at 04:42, Alex Hung wrote:
> On 3/29/25 09:48, Simon Ser wrote:
>
> > I would prefer these functions to be introduced together with the
> > patches adding functions to create objects and adding the new fields.
> > That way it's easier to check the symmetry and at no p
This patch is load usermode queue based on FW support for gfx11.
CP Ucode FW version: [PFP = 2530, ME = 2390, MEC = 2600, MES = 120]
v2: Addressed review comments from Alex.
- Just check the firmware versions directly.
v3: Firmware version checks only for Navi3x(by Alex).
Cc: Alex Deucher
Cc
On 4/10/2025 7:01 PM, Alex Deucher wrote:
On Thu, Apr 10, 2025 at 7:48 AM Arvind Yadav wrote:
This patch is load usermode queue based on FW support for gfx12.
CP Ucode FW Vesion: [PFP = 2840, ME = 2780, MEC = 2600, MES = 123]
Cc: Alex Deucher
Cc: Christian Koenig
Cc: Shashank Sharma
Cc: S
This is a quirk we currently manually apply via our installer, but we don't
have this exact device + panel configuration in our archive anymore so I
could only test the qurik moking in other ids.
Werner Sembach (1):
drm/amd/display: Add quirk to force backlight type on some TUXEDO
devices
On Wed, 9 Apr 2025 at 00:29, Christian König wrote:
>
> I mean open coding the limit checks everywhere certainly works, but as far as
> I can see it would be more defensive if we do that inside kvmalloc_array().
No.
If we add some limit to kvmalloc_array(), I guarantee that people will
just the
Op 26-03-2025 om 20:49 schreef Fangzhi Zuo:
From: Aurabindo Pillai
make the drm device available in create_validate_stream_for_sink()
so that drm_err() can be used
Reviewed-by: Alex Hung
Signed-off-by: Aurabindo Pillai
Signed-off-by: Fangzhi Zuo
---
drivers/gpu/drm/amd/display/amdgpu_dm/a
Op 30-09-2024 om 13:59 schreef Arunpravin Paneer Selvam:
Few optimization and fixes for userq fence driver.
v1:(Christian):
- Remove unnecessary comments.
- In drm_exec_init call give num_bo_handles as last parameter it would
making allocation of the array more efficient
- Handle r
Hello Ce Sun,
Commit 8ba904f54148 ("drm/amdgpu: Multi-GPU DPC recovery support")
from Mar 21, 2025 (linux-next), leads to the following Smatch static
checker warning:
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:6820 amdgpu_pci_slot_reset()
warn: iterator used outside loop: 'tmp_ade
On Wed, 2025-04-09 at 14:39 +0200, Boris Brezillon wrote:
> Hi Philipp,
>
> On Wed, 9 Apr 2025 14:06:37 +0200
> Philipp Stanner wrote:
>
> > dma_fence_is_signaled()'s name strongly reads as if this function
> > were
> > intended for checking whether a fence is already signaled. Also the
> > boo
Hello Arvind Yadav,
Commit 70773bef4e09 ("drm/amdgpu: update userqueue BOs and PDs") from
Sep 25, 2024 (linux-next), leads to the following Smatch static
checker warning:
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c:139
amdgpu_gem_update_bo_mapping()
error: we previously assumed 'bo_v
On Wed, Apr 09, 2025 at 08:10:01PM +0800, Ce Sun wrote:
> Fixes smatch warning:
>
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:6820 amdgpu_pci_slot_reset()
> warn: iterator used outside loop: 'tmp_adev'
>
> Fixes: 8ba904f54148 ("drm/amdgpu: Multi-GPU DPC recovery support")
>
Thanks. This doesn
On Wed, 2025-04-09 at 09:52 +0200, Pierre-Eric Pelloux-Prayer wrote:
> Hi,
>
> I've rebased the series on top of drm-next, applied the minor tweaks
> suggested by Tvrtko on v8 and
> the R-b tags. The result can be found on gitlab.fdo:
>
> https://gitlab.freedesktop.org/pepp/linux/-/commits/impro
+Cc Matthew
On Wed, 2025-04-09 at 15:55 +0200, Christian König wrote:
> Am 09.04.25 um 12:28 schrieb Philipp Stanner:
> > On Fri, 2025-03-21 at 16:58 +0100, Christian König wrote:
> > > Sometimes drivers need to be able to submit multiple jobs which
> > > depend on
> > > each other to different sc
On Fri, 2025-03-21 at 16:58 +0100, Christian König wrote:
> Sometimes drivers need to be able to submit multiple jobs which
> depend on
> each other to different schedulers at the same time, but using
> drm_sched_job_add_dependency() can't fail any more after the first
> job is
> initialized.
>
>
On Wed, 2025-04-09 at 15:14 +0200, Christian König wrote:
> Am 09.04.25 um 14:56 schrieb Philipp Stanner:
> > On Wed, 2025-04-09 at 14:51 +0200, Philipp Stanner wrote:
> > > On Wed, 2025-04-09 at 14:39 +0200, Boris Brezillon wrote:
> > > > Hi Philipp,
> > > >
> > > > On Wed, 9 Apr 2025 14:06:37 +
Op 24-03-2025 om 12:51 schreef Dmitry Baryshkov:
From: Dmitry Baryshkov
Switch drm_dp_helper.c to use new set of DPCD read / write helpers.
Reviewed-by: Lyude Paul
Acked-by: Jani Nikula
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/display/drm_dp_helper.c | 296 +
From: Srinivasan Shanmugam
commit 15c2990e0f0108b9c3752d7072a97d45d4283aea upstream.
This commit adds null checks for the 'stream' and 'plane' variables in
the dcn30_apply_idle_power_optimizations function. These variables were
previously assumed to be null at line 922, but they were used later
On Wed, 2025-04-09 at 14:51 +0200, Philipp Stanner wrote:
> On Wed, 2025-04-09 at 14:39 +0200, Boris Brezillon wrote:
> > Hi Philipp,
> >
> > On Wed, 9 Apr 2025 14:06:37 +0200
> > Philipp Stanner wrote:
> >
> > > dma_fence_is_signaled()'s name strongly reads as if this function
> > > were
> > >
On Wed, 2025-04-09 at 16:10 +0200, Christian König wrote:
> Am 09.04.25 um 16:01 schrieb Philipp Stanner:
> > On Wed, 2025-04-09 at 15:14 +0200, Christian König wrote:
> > > Am 09.04.25 um 14:56 schrieb Philipp Stanner:
> > > > On Wed, 2025-04-09 at 14:51 +0200, Philipp Stanner wrote:
> > > > > On
This patch is load usermode queue based on FW support for gfx12.
CP Ucode FW Vesion: [PFP = 2840, ME = 2780, MEC = 3050, MES = 123]
v2: Addressed review comments from Alex
- Just check the firmware versions directly.
Cc: Alex Deucher
Cc: Christian Koenig
Cc: Shashank Sharma
Cc: Sunil Khatri
From: Ville Syrjälä
Decouple .get_format_info() from struct drm_mode_fb_cmd2 and just
pass the pixel format+modifier combo in by hand.
We may want to use .get_format_info() outside of the normal
addfb paths where we won't have a struct drm_mode_fb_cmd2, and
creating a temporary one just for this
From: Ville Syrjälä
Decouple drm_get_format_info() from struct drm_mode_fb_cmd2 and just
pass the pixel format+modifier combo in by hand.
We may want to use drm_get_format_info() outside of the normal
addfb paths where we won't have a struct drm_mode_fb_cmd2, and
creating a temporary one just fo
From: Ville Syrjälä
Pass long the format information from the top to .fb_create()
so that we can avoid redundant (and somewhat expensive) lookups
in the drivers.
Done with cocci (with some manual fixups):
@@
identifier func =~ ".*create.*";
identifier dev, file, mode_cmd;
@@
struct drm_framebuff
From: Ville Syrjälä
Soon all drivers should have the format info already available in the
places where they call drm_helper_mode_fill_fb_struct(). Allow it to
be passed along into drm_helper_mode_fill_fb_struct() instead of doing
yet another redundant lookup.
Start by always passing in NULL and
From: Ville Syrjälä
Plumb the format info from .fb_create() all the way to
drm_helper_mode_fill_fb_struct() to avoid the redundant
lookup.
Cc: Alex Deucher
Cc: amd-gfx@lists.freedesktop.org
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 5 +++--
1 file changed,
Please change this also instead of 'goto free_fence_drv' just return err.
fence_drv = kzalloc(sizeof(*fence_drv), GFP_KERNEL);
if (!fence_drv) {
DRM_ERROR("Failed to allocate memory for fence driver\n");
r = -ENOMEM;
goto free_fence_
On Thu, Apr 10, 2025 at 12:52 PM Arvind Yadav wrote:
>
> This patch is load usermode queue based on FW support for gfx11.
> CP Ucode FW version: [PFP = 2530, ME = 2390, MEC = 2600, MES = 120]
>
> v2: Addressed review comments from Alex.
> - Just check the firmware versions directly.
> v3: Firm
Am 09.04.25 um 19:27 schrieb Linus Torvalds:
> On Wed, 9 Apr 2025 at 00:29, Christian König wrote:
>> I mean open coding the limit checks everywhere certainly works, but as far
>> as I can see it would be more defensive if we do that inside
>> kvmalloc_array().
> No.
>
> If we add some limit to
This patch is load usermode queue based on FW support for gfx12.
CP Ucode FW Vesion: [PFP = 2840, ME = 2780, MEC = 2600, MES = 123]
Cc: Alex Deucher
Cc: Christian Koenig
Cc: Shashank Sharma
Cc: Sunil Khatri
Signed-off-by: Arvind Yadav
---
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 15 +
This patch is load usermode queue based on FW support for gfx11.
CP Ucode FW version: [PFP = 2530, ME = 2390, MEC = 2600, MES = 120]
Cc: Alex Deucher
Cc: Christian Koenig
Cc: Shashank Sharma
Cc: Sunil Khatri
Signed-off-by: Arvind Yadav
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 17
This patch is load usermode queue based on FW support for gfx12.
CP Ucode FW Vesion: [PFP = 2840, ME = 2780, MEC = 2600, MES = 123]
Cc: Alex Deucher
Cc: Christian Koenig
Cc: Shashank Sharma
Cc: Sunil Khatri
Signed-off-by: Arvind Yadav
---
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 15 +
Apart from a minor alignment issue LGTM.
Reviewed-by: Sunil Khatri
On 4/10/2025 4:59 PM, Arvind Yadav wrote:
This patch is load usermode queue based on FW support for gfx11.
CP Ucode FW version: [PFP = 2530, ME = 2390, MEC = 2600, MES = 120]
Cc: Alex Deucher
Cc: Christian Koenig
Cc: Shashank
[AMD Official Use Only - AMD Internal Distribution Only]
Tested on MI210 VF also.
Tested-by: Horace Chen
-Original Message-
From: amd-gfx On Behalf Of Emily Deng
Sent: Thursday, April 10, 2025 2:26 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deng, Emily
Subject: [PATCH] drm/amdgpu: Clear
On 4/9/2025 5:40 PM, Ce Sun wrote:
> Fixes smatch warning:
>
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:6820 amdgpu_pci_slot_reset()
> warn: iterator used outside loop: 'tmp_adev'
>
> Fixes: 8ba904f54148 ("drm/amdgpu: Multi-GPU DPC recovery support")
>
> Signed-off-by: Ce Sun
> ---
> driv
[AMD Official Use Only - AMD Internal Distribution Only]
Hi Lijo,
There is indeed a single device issue, thank you very much
Thanks,
Sun,Ce
From: Lazar, Lijo
Sent: Thursday, April 10, 2025 4:11 PM
To: Sun, Ce(Overlord) ; amd-gfx@lists.freedesktop.org
Am 09.04.25 um 17:04 schrieb Philipp Stanner:
> On Wed, 2025-04-09 at 16:10 +0200, Christian König wrote:
>>> I only see improvement by making things more obvious.
>>>
>>> In any case, how would you call a wrapper that just does
>>> test_bit(IS_SIGNALED, …) ?
>> Broken, that was very intentionally
On 4/7/25 20:20, Wentao Liang wrote:
The function fill_stream_properties_from_drm_display_mode() calls the
function drm_hdmi_avi_infoframe_from_display_mode() and the
function drm_hdmi_vendor_infoframe_from_display_mode(), but does
not check its return value. Log the error messages to prevent
Fix DEBUG_LOCKS_WARN_ON(lock->magic != lock) warning logs.
Signed-off-by: Arunpravin Paneer Selvam
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_
Hi Gergo,
Thanks for the patch. I am sending this patch for testing and I will
update test result next week.
On 4/2/25 11:03, Gergo Koteles wrote:
Since b255ce4388e0, it is possible that the CRTC timing
information for the preferred mode has not yet been
calculated while amdgpu_dm_connector_
[AMD Official Use Only - AMD Internal Distribution Only]
Ping ..
Regards,
Prike
> -Original Message-
> From: Liang, Prike
> Sent: Friday, March 28, 2025 7:52 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Liang, Prike
>
> Subject: [PATCH] drm/amdgpu: remove the
Applied. Thanks!
Alex
On Mon, Apr 7, 2025 at 1:52 AM Alexandre Demers
wrote:
>
> The defines, shifts and masks are already available in dce_6_0_d.h,
> dce_6_0_sh_mask.h.
>
> Signed-off-by: Alexandre Demers
> ---
> drivers/gpu/drm/amd/amdgpu/si.c | 26 +-
> drivers/gpu
From: "jesse.zh...@amd.com"
This patch refactors the SDMA v5.2 queue reset and stop logic to improve
code readability, maintainability, and performance. The key changes include:
1. **Generalized `sdma_v5_2_gfx_stop` Function**:
- Added an `inst_mask` parameter to allow stopping specific
Am 09.04.25 um 14:56 schrieb Philipp Stanner:
> On Wed, 2025-04-09 at 14:51 +0200, Philipp Stanner wrote:
>> On Wed, 2025-04-09 at 14:39 +0200, Boris Brezillon wrote:
>>> Hi Philipp,
>>>
>>> On Wed, 9 Apr 2025 14:06:37 +0200
>>> Philipp Stanner wrote:
>>>
dma_fence_is_signaled()'s name stron
Hello!
The nomination period is currently open for the upcoming election to
the X.Org Foundation Board of Directors. All X.Org Foundation members
are eligible for election to the board.
Nominations for the 2025 election are now open and will remain open
until 23:59 UTC on 16 April 2025.
The Boar
On Mon, Apr 7, 2025 at 4:15 PM Rodrigo Siqueira wrote:
>
> On 04/07, Alex Deucher wrote:
> > On Sun, Apr 6, 2025 at 7:07 PM Rodrigo Siqueira wrote:
> > >
> > > This patchset was inspired and made on top of the below series:
> > >
> > > https://lore.kernel.org/amd-gfx/20250319162225.3775315-1-alex
This patch is load usermode queue based on FW support for gfx11.
CP Ucode FW version: [PFP = 2530, ME = 2390, MEC = 2600, MES = 120]
v2: Addressed review comments from Alex.
- Just check the firmware versions directly.
Cc: Alex Deucher
Cc: Christian Koenig
Cc: Shashank Sharma
Cc: Sunil Kha
On 4/10/2025 12:24 PM, Mario Limonciello wrote:
When an APU exits HW sleep with no active wake sources the Linux kernel will
rapidly assert that the APU can enter back into HW sleep. This happens in a
few ms. Contrasting this to Windows, Windows can take 10s of seconds to
enter back into the resi
When an APU exits HW sleep with no active wake sources the Linux kernel will
rapidly assert that the APU can enter back into HW sleep. This happens in a
few ms. Contrasting this to Windows, Windows can take 10s of seconds to
enter back into the resiliency phase for Modern Standby.
For some situati
These have been announced so add them to the table.
Link:
https://www.amd.com/en/products/processors/laptop/ryzen/ai-300-series/amd-ryzen-ai-7-350.html
Signed-off-by: Mario Limonciello
---
Documentation/gpu/amdgpu/apu-asic-info-table.csv | 1 +
1 file changed, 1 insertion(+)
diff --git a/Docum
On Thu, Apr 10, 2025 at 1:33 PM Mario Limonciello
wrote:
>
> These have been announced so add them to the table.
>
> Link:
> https://www.amd.com/en/products/processors/laptop/ryzen/ai-300-series/amd-ryzen-ai-7-350.html
> Signed-off-by: Mario Limonciello
Acked-by: Alex Deucher
> ---
> Documen
[Public]
> -Original Message-
> From: Arnd Bergmann
> Sent: Monday, April 7, 2025 6:38 AM
> To: Bjorn Helgaas
> Cc: Arnd Bergmann ; Jeff Hugo
> ; Carl Vanderlip ; Oded
> Gabbay ; Takashi Sakamoto ;
> Maarten Lankhorst ; Maxime Ripard
> ; Thomas Zimmermann ; David
> Airlie ; Simona Vetter
Fix lockdep warnings.
[ +0.24] WARNING: CPU: 10 PID: 1909 at drivers/gpu/drm/drm_syncobj.c:456
drm_syncobj_find_fence+0x58c/0x6e0
[ +0.000519] CPU: 10 UID: 1000 PID: 1909 Comm: gnome-shel:cs0 Tainted: G
W OE 6.12.0+ #18
[ +0.08] Tainted: [W]=WARN, [O]=OOT_MODULE, [E]=UNSI
Unmap user queues on suspend and map them on resume.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_devic
If the queues needs to access TMZ surfaces, it must
be set up as secure.
Signed-off-by: Alex Deucher
---
include/uapi/drm/amdgpu_drm.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 8719754c777b4..0ca4b3b961eb3 100644
---
Enable users to create queues at different priority levels.
The highest level is restricted to drm master.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 26 ++-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amd
Handle the queue priority set by the user.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/mes_userqueue.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c
b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c
ind
Enable users to create secure GFX/compute queues.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq
So we can track this when we create user queues.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.h
index fd0542f60433b..e
So that we initialize the MQD as a secure queue.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/mes_userqueue.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c
b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c
index f406a9a29bda5..e175f0
Set up TMZ for queues.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 91d29f482c3ca..b204d0e6e816d 100644
--- a/drivers/gpu/drm/a
Set up TMZ for queues.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
index 2474006b1a340..da67f27d65a33 100644
--- a/drivers/gpu/drm/a
Use this to track the whether we want TMZ for queues.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index b818ad63dc84f..364a65524cfdb 100644
--- a
Allow the user to set a queue priority levels:
0 - normal low - most apps (maps to MES AMD_PRIORITY_LEVEL_NORMAL)
1 - low - background jobs (maps to MES AMD_PRIORITY_LEVEL_LOW)
2 - normal high - apps that need relative high (maps to MES
AMD_PRIORITY_LEVEL_MEDIUM)
3 - high (admin only - for composi
Convert driver priority levels to MES11 priority levels.
At the moment they are the same, but they may not always
be.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 21 +++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/
Reuse the _pad field for flags.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 4 ++--
include/uapi/drm/amdgpu_drm.h | 5 -
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c
b/drivers
Convert driver priority levels to MES11 priority levels.
At the moment they are the same, but they may not always
be.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 21 +++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/
On Thu, Apr 10, 2025 at 10:18 AM Srinivasan Shanmugam
wrote:
>
> Enable the cleaner shader for additional GFX11.5.2/11.5.3 series GPUs to
> ensure data isolation among GPU tasks. The cleaner shader is tasked with
> clearing the Local Data Store (LDS), Vector General Purpose Registers
> (VGPRs), an
This will be used to stop/start user queue scheduling for
example when switching between kernel and user queues when
enforce isolation is enabled.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 66
If userq creation fails, we need to properly unwind and free the
user queue fence driver.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c
b/drivers/gpu/drm/amd/amdg
Add helpers to unmap and map user queues on suspend and
resume.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 39 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.h | 3 ++
2 files changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgp
Enforce isolation serializes access to the GFX IP. User
queues are isolated in the MES scheduler, but we still
need to serialize between kernel queues and user queues.
For enforce isolation, group KGD user queues with KFD user
queues.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/a
Move some userq fence handling code into amdgpu_userq_fence.c.
This matches the other code in that file.
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/amdgpu/amdgpu_userq_fence.c | 26 +++
.../gpu/drm/amd/amdgpu/amdgpu_userq_fence.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu
since we loop through the queues |= the errors.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c
index 4
Split out the queue map from the mqd create call and split
out the queue unmap from the mqd destroy call. This splits
the queue setup and teardown with the actual enablement
in the firmware.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 17 +++--
dr
This is unused so remove it.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/mes_userqueue.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c
b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c
index abd32415d7343..e3c3fc160b799 100644
--- a/driv
Rename to map and umap to better align with what is happening
at the firmware level and remove the extra level of indirection
in the MES userq code.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 10 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.h | 8 ++--
d
On Wed, Apr 2, 2025 at 5:28 AM jesse.zh...@amd.com wrote:
>
> Since KFD no longer registers its own callbacks for SDMA resets, and only KGD
> uses the reset mechanism,
> we can simplify the SDMA reset flow by directly calling the ring's
> `stop_queue` and `start_queue` functions.
> This patch re
Hi Ville,
Thank you for the patch.
On Thu, Apr 10, 2025 at 07:32:00PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Decouple .get_format_info() from struct drm_mode_fb_cmd2 and just
> pass the pixel format+modifier combo in by hand.
>
> We may want to use .get_format_info() outside of
Hi Ville,
Thank you for the patch.
On Thu, Apr 10, 2025 at 07:32:01PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Decouple drm_get_format_info() from struct drm_mode_fb_cmd2 and just
> pass the pixel format+modifier combo in by hand.
>
> We may want to use drm_get_format_info() outsi
"aligned" not "aligend"
Signed-off-by: Alexandre Demers
---
drivers/gpu/drm/radeon/atombios.h | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/radeon/atombios.h
b/drivers/gpu/drm/radeon/atombios.h
index 2db40789235c..c4abd1f78410 100644
--- a/drivers/gpu/
Hi Ville,
Thank you for the patch.
On Thu, Apr 10, 2025 at 07:32:03PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Pass long the format information from the top to .fb_create()
> so that we can avoid redundant (and somewhat expensive) lookups
> in the drivers.
>
> Done with cocci (wit
Hi Ville,
Thank you for the patch.
On Thu, Apr 10, 2025 at 07:32:04PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Soon all drivers should have the format info already available in the
> places where they call drm_helper_mode_fill_fb_struct(). Allow it to
> be passed along into drm_hel
[AMD Official Use Only - AMD Internal Distribution Only]
Test-by: Jesse.Zhang , Series is Reviewed-by:
Jesse.Zhang
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Friday, April 11, 2025 2:54 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH
[AMD Official Use Only - AMD Internal Distribution Only]
Hi Jesse,
> -Original Message-
> From: jesse.zh...@amd.com
> Sent: Tuesday, April 8, 2025 2:33 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Koenig, Christian
> ; Huang, Tim ; Lazar,
> Lijo ; Zhang, Jesse(Jie) ;
On Thu, Apr 10, 2025 at 10:27:45PM +0300, Laurent Pinchart wrote:
> Hi Ville,
>
> Thank you for the patch.
>
> On Thu, Apr 10, 2025 at 07:32:00PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Decouple .get_format_info() from struct drm_mode_fb_cmd2 and just
> > pass the pixel form
The structures are large and they do not require continuous
memory so use vzalloc.
Fixes: 70839da63605 ("drm/amd/display: Add new DCN401 sources")
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4126
Cc: Aurabindo Pillai
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/display/dc/dml2/dm
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