From: Harry Wentland
The BT.709 and BT.2020 OETFs are the same, the only difference
being that the BT.2020 variant is defined with more precision
for 10 and 12-bit per color encodings.
Both are used as encoding functions for video content, and are
therefore defined as OETF (opto-electronic trans
[why]
In the mode validation, mst dsc is considered for bw calculation after
common dsc config is determined. Currently it considered common dsc config
is found if max and min target bpp are non zero which is not accurate. Invalid
max and min target bpp values would not get max_kbps and min_kbps ca
cursor plane does not need to have color pipeline.
Signed-off-by: Alex Hung
---
v7:
- Add a commit messages
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
b/drivers/gpu/drm/
On Thu, Mar 20, 2025 at 9:11 AM Denis Arefev wrote:
>
> The user can set any speed value.
> If speed is greater than UINT_MAX/8, division by zero is possible.
>
> Found by Linux Verification Center (linuxtesting.org) with SVACE.
>
> Fixes: 1e866f1fe528 ("drm/amd/pm: Prevent divide by zero")
> Sign
On Mon, Mar 24, 2025 at 3:03 PM Alex Deucher wrote:
>
> On Fri, Mar 21, 2025 at 9:48 PM Alexandre Demers
> wrote:
> >
> > They will be used later when switching away from sid.h/si_enums.h.
> >
> > To prevent redefinition clashes, comment out the ones in sid.h. They will be
> > removed later.
> >
On Mon, Mar 24, 2025 at 2:21 PM Alex Deucher wrote:
>
> On Sat, Mar 22, 2025 at 2:48 PM Alexandre Demers
> wrote:
> >
> > Bring things on a single line and fix spacing.
> >
> > Signed-off-by: Alexandre Demers
> > ---
> > drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 10 +++---
> > drivers/gpu/drm
Break when we get to the end of the supported pipes
rather than continuing the loop.
Reviewed-by: Shaoyun.liu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
b/dr
From: Harry Wentland
The PQ function defines a mapping of code values to nits (cd/m^2).
The max code value maps to 10,000 nits.
Windows DWM's canonical composition color space (CCCS) defaults
to composing SDR contents to 80 nits and uses a float value of
1.0 to represent this. For this reason A
Expose one 1D curve colorop with support for
DRM_COLOROP_1D_CURVE_SRGB_EOTF and program HW to perform
the sRGB transform when the colorop is not in bypass.
With this change the following IGT test passes:
kms_colorop --run plane-XR30-XR30-srgb_eotf
The color pipeline now consists of a single color
From: Harry Wentland
This patch introduces a VKMS color pipeline that includes two
drm_colorops for named transfer functions. For now the only ones
supported are sRGB EOTF, sRGB Inverse EOTF, and a Linear TF.
We will expand this in the future but I don't want to do so
without accompanying IGT tes
From: Harry Wentland
Debugging LUT math is much easier when we can unit test
it. Add kunit functionality to VKMS and add tests for
- get_lut_index
- lerp_u16
Reviewed-by: Louis Chauvet
Signed-off-by: Alex Hung
Signed-off-by: Harry Wentland
Cc: Arthur Grillo
---
v8:
- Update config names (
dynamic-debug has several __sections, each with ,
num_, and it iterates over these with a 2-index for-loop.
These loops are fiddly with the 2 names.
We have only 2 such loops now, but are getting more soon; lets
embed/abstract the fiddlyness in the for_subvec() macro, and avoid
repeating it going
This adds support for a 3D LUT.
The color pipeline now consists of the following colorops:
1. 1D curve colorop
2. Multiplier
3. 3x4 CTM
4. 1D curve colorop
5. 1D LUT
6. 3D LUT
7. 1D curve colorop
8. 1D LUT
Signed-off-by: Alex Hung
---
v8:
- Set initialized to 0 and return when drm_lut3d_size is
[AMD Official Use Only - AMD Internal Distribution Only]
-Original Message-
From: Alex Deucher
Sent: Wednesday, March 26, 2025 11:08 PM
To: Feng, Kenneth
Cc: amd-gfx@lists.freedesktop.org; Wang, Yang(Kevin) ;
Deucher, Alexander ; Wentland, Harry
Subject: Re: [PATCH] drm/amd/display: p
Hi, Alex,
On Thu, Mar 27, 2025 at 8:10 AM Alex Hung wrote:
>
> The following error messages showed up on an APU and a dGPU during testing.
>
> <3> [100.231411] BUG: sleeping function called from invalid context at
> include/linux/sched/mm.h:321
> <3> [100.231414] in_atomic(): 1, irqs_disabled():
From: Harry Wentland
This adds support for the BT.709/BT.2020 transfer functions
on all current 1D curve plane colorops, i.e., on DEGAM, SHAPER,
and BLND blocks.
With this change the following IGT subtests pass:
kms_colorop --run plane-XR30-XR30-bt2020_inv_oetf
kms_colorop --run plane-XR30-XR30-
On 3/27/25 09:58, Linus Torvalds wrote:
> On Wed, 26 Mar 2025 at 15:00, Bert Karwatzki wrote:
>>
>> As Balbir Singh found out this memory comes from amdkfd
>> (kgd2kfd_init_zone_device()) with CONFIG_HSA_AMD_SVM=y. The memory gets
>> placed
>> by devm_request_free_mem_region() which places the me
The following error messages showed up on an APU and a dGPU during testing.
<3> [100.231411] BUG: sleeping function called from invalid context at
include/linux/sched/mm.h:321
<3> [100.231414] in_atomic(): 1, irqs_disabled(): 0, non_block: 0, pid:
1711, name: kms_color
<3> [100.231416] preempt
This adds support for a 3x4 color transformation matrix.
With this change the following IGT tests pass:
kms_colorop --run plane-XR30-XR30-ctm_3x4_50_desat
kms_colorop --run plane-XR30-XR30-ctm_3x4_overdrive
kms_colorop --run plane-XR30-XR30-ctm_3x4_oversaturate
kms_colorop --run plane-XR30-XR30-ct
From: Harry Wentland
While working on the CTM implementation of VKMS I had to ascertain
myself of a few assumptions. One of those is whether drm_fixed.h
treats its numbers using signed-magnitude or twos-complement. It is
twos-complement.
In order to make someone else's day easier I am adding the
It is to be used to enable HDR by allowing userpace to create and pass
3D LUTs to kernel and hardware.
new drm_colorop_type: DRM_COLOROP_3D_LUT.
Signed-off-by: Alex Hung
---
v8:
- Fix typo in subject (Simon Ser)
- Update documentation for DRM_COLOROP_3D_LUT (Simon Ser)
- Delete empty lines (S
Swap the order of matrix and multiplier as designed in hardware.
Signed-off-by: Alex Hung
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 12 ++--
.../drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c| 8
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git
This adds support for a multiplier. This multiplier is
programmed via the HDR Multiplier in DCN.
With this change the following IGT tests pass:
kms_colorop --run plane-XR30-XR30-multiply_125
kms_colorop --run plane-XR30-XR30-multiply_inv_125
The color pipeline now consists of the following coloro
This introduces a new drm_colorop_type: DRM_COLOROP_MULTIPLIER.
It's a simple multiplier to all pixel values. The value is
specified via a S31.32 fixed point provided via the
"MULTIPLIER" property.
Reviewed-by: Simon Ser
Signed-off-by: Alex Hung
---
v7:
- Modify size_property to lut_size_prope
The functions are to clean up color pipeline when a device driver
fails to create its color pipeline.
Signed-off-by: Alex Hung
---
.../amd/display/amdgpu_dm/amdgpu_dm_colorop.c | 3 +-
drivers/gpu/drm/drm_colorop.c | 41 +++
drivers/gpu/drm/vkms/vkms_colorop.c
We've previously introduced DRM_COLOROP_1D_CURVE for
pre-defined 1D curves. But we also have HW that supports
custom curves and userspace needs the ability to pass
custom curves, aka LUTs.
This patch introduces a new colorop type, called
DRM_COLOROP_1D_LUT that provides a SIZE property which
is us
From: Harry Wentland
Not all HW will be able to do bypass on all color
operations. Introduce an 'allow_bypass' boolean for
all colorop init functions and only create the BYPASS
property when it's true.
Signed-off-by: Alex Hung
Signed-off-by: Harry Wentland
---
.../amd/display/amdgpu_dm/amdgpu
From: Harry Wentland
We want to make sure userspace is aware of the 1D LUT
interpolation. While linear interpolation is common it
might not be supported on all HW. Give driver implementers
a way to specify their interpolation.
Reviewed-by: Simon Ser
Signed-off-by: Alex Hung
Signed-off-by: Harr
This patch adds colorops for custom 1D LUTs in the SHAPER and
BLND HW blocks.
With this change the following IGT tests pass:
kms_colorop --run plane-XR30-XR30-srgb_inv_eotf_lut
kms_colorop --run plane-XR30-XR30-srgb_inv_eotf_lut-srgb_eotf_lut
The color pipeline now consists of the following color
From: Harry Wentland
Add a read-only TYPE property. The TYPE specifies the colorop
type, such as enumerated curve, 1D LUT, CTM, 3D LUT, PWL LUT,
etc.
For now we're only introducing an enumerated 1D LUT type to
illustrate the concept.
Reviewed-by: Simon Ser
Reviewed-by: Louis Chauvet
Signed-of
From: Harry Wentland
This patchset enables support for the PQ_125 EOTF and its inverse
on all existing plane 1D curve colorops, i.e., on DEGAM, SHAPER,
and BLND blocks.
With this patchset the following IGT subtests are passing:
kms_colorop --run plane-XR30-XR30-pq_125_eotf
kms_colorop --run plan
Expose a 3rd 1D curve colorop, with support for
DRM_COLOROP_1D_CURVE_SRGB_EOTF and program the BLND block
to perform the sRGB transform when the colorop is not in
bypass
With this change the following IGT test passes:
kms_colorop --run plane-XR30-XR30-srgb_eotf-srgb_inv_eotf-srgb_eotf
The color p
Expose a 2nd curve colorop with support for
DRM_COLOROP_1D_CURVE_SRGB_INV_EOTF and program HW to
perform the sRGB Inverse EOTF on the shaper block
when the colorop is not in bypass.
With this change the follow IGT tests pass:
kms_colorop --run plane-XR30-XR30-srgb_inv_eotf
kms_colorop --run plane-
From: Harry Wentland
Add the default Bypass pipeline and ensure it passes the
kms_colorop test plane-XR30-XR30-bypass.
Signed-off-by: Alex Hung
Signed-off-by: Harry Wentland
---
.../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 19 +++
1 file changed, 19 insertions(+)
diff --gi
From: Harry Wentland
When the plane_color_pipeline bit is set we should ignore
deprecated properties, such as COLOR_RANGE and COLOR_ENCODING.
Signed-off-by: Alex Hung
Signed-off-by: Harry Wentland
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4
1 file changed, 4 insertions(+)
Create a new macro for_each_new_colorop_in_state to access new
drm_colorop_state updated from uapi.
Reviewed-by: Simon Ser
Signed-off-by: Alex Hung
---
include/drm/drm_atomic.h | 20
1 file changed, 20 insertions(+)
diff --git a/include/drm/drm_atomic.h b/include/drm/drm_a
From: Harry Wentland
Drivers will need to know whether an atomic check/commit
originated from a client with DRM_CLIENT_CAP_PLANE_COLOR_PIPELINE
so they can ignore deprecated properties, like COLOR_ENCODING
and COLOR_RANGE.
Pass the plane_color_pipeline bit to drm_atomic_state.
Signed-off-by: Al
From: Harry Wentland
A whole slew of tests for CTM handling that greatly helped in
debugging the CTM code. The extent of tests might seem a bit
silly but they're fast and might someday help save someone
else's day when debugging this.
Reviewed-by: Louis Chauvet
Signed-off-by: Alex Hung
Signed-
From: Harry Wentland
We add two 3x4 matrices into the VKMS color pipeline. The reason
we're adding matrices is so that we can test that application
of a matrix and its inverse yields an output equal to the input
image.
One complication with the matrix implementation has to do with
the fact that
From: Harry Wentland
Certain operations require us to preserve values below 0.0 and
above 1.0 (0x0 and 0x respectively in 16 bpc unorm). One
such operation is a BT709 encoding operation followed by its
decoding operation, or the reverse.
We'll use s32 values as intermediate in and outputs of
From: Harry Wentland
This type is used to support a 3x4 matrix in colorops. A 3x4
matrix uses the last column as a "bias" column. Some HW exposes
support for 3x4. The calculation looks like:
out matrixin
|R| |0 1 2 3 | | R |
|G| = |4 5 6 7 | x | G |
|B| |8 9 10 11| | B
From: Harry Wentland
Two tests are added to VKMS LUT handling:
- linear
- inv_srgb
Reviewed-by: Louis Chauvet
Signed-off-by: Alex Hung
Signed-off-by: Harry Wentland
---
v7:
- Fix checkpatch warnings (Louis Chauvet)
- Adde a commit messages
- Fix code styles by adding and removing spaces
From: Harry Wentland
Add kernel doc for drm_colorop objects.
Signed-off-by: Alex Hung
Signed-off-by: Harry Wentland
---
v8:
- Move this after "drm/colorop: Introduce DRM_CLIENT_CAP_PLANE_COLOR_PIPELINE"
(Simon Ser)
- Update DOC overview (Simon Ser)
v7:
- Add a commit messages
v5:
- Drop
From: Harry Wentland
With the introduction of the pre-blending color pipeline we
can no longer have color operations that don't have a clear
position in the color pipeline. We deprecate all existing
plane properties. For upstream drivers those are:
- COLOR_ENCODING
- COLOR_RANGE
Drivers are ex
From: Harry Wentland
We're adding a new enum COLOR PIPELINE property. This
property will have entries for each COLOR PIPELINE by
referencing the DRM object ID of the first drm_colorop
of the pipeline. 0 disables the entire COLOR PIPELINE.
Userspace can use this to discover the available color
pi
From: Harry Wentland
Print atomic state for drm_colorop in debugfs
Signed-off-by: Alex Hung
Signed-off-by: Harry Wentland
---
v8:
- Add switch statement to print colorop type (Simon Ser)
v7:
- Add a commit messages
- Squash "drm/colorop: Add NEXT to colorop state print" (Simon Ser)
drive
From: Harry Wentland
We'll construct color pipelines out of drm_colorop by
chaining them via the NEXT pointer. NEXT will point to
the next drm_colorop in the pipeline, or by 0 if we're
at the end of the pipeline.
Signed-off-by: Alex Hung
Signed-off-by: Harry Wentland
---
v8:
- Remove null che
From: Harry Wentland
We want to be able to bypass each colorop at all times.
Introduce a new BYPASS boolean property for this.
Reviewed-by: Simon Ser
Reviewed-by: Louis Chauvet
Signed-off-by: Alex Hung
Signed-off-by: Harry Wentland
---
v6:
- clarify that bypass is only valid if BYPASS prop
From: Harry Wentland
This patches introduces a new drm_colorop mode object. This
object represents color transformations and can be used to
define color pipelines.
We also introduce the drm_colorop_state here, as well as
various helpers and state tracking bits.
Reviewed-by: Simon Ser
Signed-of
From: Harry Wentland
Add documentation for color pipeline API.
Signed-off-by: Alex Hung
Signed-off-by: Harry Wentland
---
v8:
- Fix typo "definint" -> "defining"
v7:
- Add a commit messages
v5:
- Don't require BYPASS to succeed (Sebastian)
- use DATA for 1D and 3D LUT types (Sebastian)
From: Harry Wentland
CTM values are defined as signed-magnitude values. Add
a helper that converts from CTM signed-magnitude fixed
point value to the twos-complement value used by
drm_fixed.
Reviewed-by: Louis Chauvet
Signed-off-by: Harry Wentland
---
include/drm/drm_fixed.h | 18
This is an RFC set for a color pipeline API, along with implementations
in VKMS and amdgpu. It is tested with a set of IGT tests that can be
found at [1]. The IGT tests run a pixel-by-pixel comparison with an
allowable delta variation as the goal for these transformations is
perceptual correctness,
From: Aurabindo Pillai
drm_info prints the drm device instance which is helpful when
debugging multi gpu issues
Reviewed-by: Alex Hung
Signed-off-by: Aurabindo Pillai
Signed-off-by: Fangzhi Zuo
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 24 +--
1 file changed, 12 ins
From: Aurabindo Pillai
make the drm device available in create_validate_stream_for_sink()
so that drm_err() can be used
Reviewed-by: Alex Hung
Signed-off-by: Aurabindo Pillai
Signed-off-by: Fangzhi Zuo
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 13 +++--
1 file changed,
From: Dillon Varone
[WHY&HOW]
Core should evaluate support based on the max clocks after considering
downspread.
Reviewed-by: Austin Zheng
Signed-off-by: Dillon Varone
Signed-off-by: Fangzhi Zuo
---
.../dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c | 6 +++---
.../amd/display/dc/dm
From: Dillon Varone
[WHY]
DCN4+ supports a new register based mailbox for sending messages
from host to DMCUB. This mailbox supports 64 byte commands, which makes
it compatible with the same structure as the frame buffer based mailbox.
[HOW]
The intention for reg_inbox0 is to be slot in replacem
From: Robin Chen
Enable replay low refresh rate support.
Reviewed-by: ChunTao Tso
Signed-off-by: Robin Chen
Signed-off-by: Fangzhi Zuo
---
drivers/gpu/drm/amd/display/dc/dc_types.h | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types
From: Austin Zheng
[Why]
Mapping of ODM enum is different for DML2.0 vs DML2.1.
Configs using DML2.1 will incorrectly trigger an assert meant for DML2.0.
[How]
Use if/else to seperate logic between DML2.0 and DML2.1.
Reviewed-by: Aurabindo Pillai
Signed-off-by: Austin Zheng
Signed-off-by: Fan
Summary:
* Improve vrr for replay and psr
* Rewrite drm debug message
* Fix clock issues for dcn32 and dcn401
* Fix mst dsc mode validation issue
Aric Cyr (1):
drm/amd/display: Promote DAL to 3.2.327
Aurabindo Pillai (6):
drm/amd/display: convert DRM_ERROR to drm_err in
hpd_rx_irq_cr
From: Aurabindo Pillai
prefer drm_err instead of DRM_ERROR since the former prints the
associated DRM device, which is helpful when debugging multi-gpu
use cases.
Reviewed-by: Alex Hung
Signed-off-by: Aurabindo Pillai
Signed-off-by: Fangzhi Zuo
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm
From: Joshua Aberback
[Why]
This array was initially defined as size 50. There were array overflow
issues so the size was increased to 100. To ensure such issues are
avoided in the future, the size should be set based on the possible
contents instead of an arbitrary value.
[How]
- upper bound,
From: Dillon Varone
[WHY&HOW]
DCN401 uses a different structure to store the VStartup offset used to
calculate the VUpdate position, so adjust the calculations to use this
value.
Reviewed-by: Aric Cyr
Signed-off-by: Dillon Varone
Signed-off-by: Fangzhi Zuo
---
.../amd/display/dc/hwss/dcn401/
From: Aric Cyr
Summary:
* Improve vrr for replay and psr
* Rewrite drm debug message
* Fix clock issues for dcn32 and dcn401
* Fix mst dsc mode validation issue
Reviewed-by: Aurabindo Pillai
Signed-off-by: Aric Cyr
Signed-off-by: Fangzhi Zuo
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1
From: Aurabindo Pillai
add amdgpu_device pointer to data associated with the work struct
such that hpd handlers has access to the drm device for use with
drm_err()
Reviewed-by: Alex Hung
Signed-off-by: Aurabindo Pillai
Signed-off-by: Fangzhi Zuo
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_d
From: Dillon Varone
[WHY&HOW]
- VUPDATE_NO_LOCK should be used in place of VUPDATE always
- Add VERTICAL_INTERRUPT1 and VERTICAL_INTERRUPT2 definitions
Reviewed-by: Aric Cyr
Signed-off-by: Dillon Varone
Signed-off-by: Fangzhi Zuo
---
.../display/dc/irq/dcn32/irq_service_dcn32.c | 61 +++
From: Aurabindo Pillai
drm_warn prints the drm device instance which is helpful when
debugging multi gpu issues
Reviewed-by: Alex Hung
Signed-off-by: Aurabindo Pillai
Signed-off-by: Fangzhi Zuo
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 26 +--
1 file changed, 13 ins
From: Tom Chung
[Why]
Replay and PSR will cause some video corruption while VRR is enabled.
[How]
Do not enable the Replay and PSR while VRR is active in
amdgpu_dm_enable_self_refresh().
Fixes: d7879340e987 ("drm/amd/display: Disable replay and psr while VRR is
enabled")
Reviewed-by: Sun peng
From: ChunTao Tso
[Why]
Replay need special policy for the scenario Teams,
add a flag to imply apply special policy or not.
[How]
Add a config option intended for future use for video conferencing applications.
Reviewed-by: Aric Cyr
Signed-off-by: ChunTao Tso
Signed-off-by: Fangzhi Zuo
---
From: Aurabindo Pillai
pass in a pointer to amdgpu_device directly to the function.
Reviewed-by: Alex Hung
Signed-off-by: Aurabindo Pillai
Signed-off-by: Fangzhi Zuo
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git
Add the user queue IP support query to the drm_amdgpu_info_device
query.
Cc: marek.ol...@amd.com
Cc: prike.li...@amd.com
Cc: sunil.kha...@amd.com
Cc: yogesh.mohanmarimu...@amd.com
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++-
1 file changed, 2 insertions(+), 1
In reference to memory carved out for APUs,
s/cave out/carve out/
Signed-off-by: Alex Deucher
---
Documentation/gpu/amdgpu/debugfs.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/gpu/amdgpu/debugfs.rst
b/Documentation/gpu/amdgpu/debugfs.rst
index fe7736a0b4
Both patches looks good.
Reviewed-by: Sunil Khatri
Regards
Sunil khatri
On 3/26/2025 9:54 PM, Alex Deucher wrote:
With the ME details fixed, we can now consolidate
this state. Also split out the userq setup into a separate
switch statement so that we can set them per IP version
when the firmw
Applied the series with some minor clarifications per the comments and
my proof reading.
Thanks!
Alex
On Tue, Mar 25, 2025 at 1:27 PM Rodrigo Siqueira wrote:
>
> Hi,
>
> This patchset came from my endeavor to understand better how some of the
> amdgpu components operate; in particular, I was fo
KIQ is replaced with MES on GFX 11 and newer.
Signed-off-by: Alex Deucher
---
Documentation/gpu/amdgpu/driver-core.rst | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/gpu/amdgpu/driver-core.rst
b/Documentation/gpu/amdgpu/driver-core.rst
index 7e3f5d1e9aaf4..8
Am 26.03.25 um 14:55 schrieb Alex Deucher:
> On Wed, Mar 26, 2025 at 4:13 AM Christian König
> wrote:
>> Am 25.03.25 um 16:24 schrieb Srinivasan Shanmugam:
>>> This commit addresses the issue where the cleaner shader was not
>>> correctly executed during gang submissions due to improper handling o
Add a separate switch statement for the userq callback
assignment so that we can assign the callbacks for each
asic as the firmware becomes available.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 20 ++--
1 file changed, 14 insertions(+), 6 deletions(-
With the ME details fixed, we can now consolidate
this state. Also split out the userq setup into a separate
switch statement so that we can set them per IP version
when the firmwares are ready.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 33
[AMD Official Use Only - AMD Internal Distribution Only]
Sounds good. Series is reviewed then.
Reviewed-by: Sunil Khatri
Regards
Sunil khatri
-Original Message-
From: Alex Deucher
Sent: Wednesday, March 26, 2025 9:23 PM
To: Khatri, Sunil
Cc: Deucher, Alexander ;
amd-gfx@lists.freede
On Wed, Mar 26, 2025 at 11:48 AM Khatri, Sunil wrote:
>
> [AMD Official Use Only - AMD Internal Distribution Only]
>
> Gfx11 now we have same values, hence we don't need to differentiate between
> two sets , only one set is needed like below.
For these fixes, I'd like to keep this as is so we ca
[AMD Official Use Only - AMD Internal Distribution Only]
We could clean that up, but if we did so, we should add a second switch
statement for the userq_funcs assignments so we can enable them selectively as
the firmwares become available.
Alex
From: Khatri, Su
[AMD Official Use Only - AMD Internal Distribution Only]
Series LGTM, if num_mec value is correct as per the hw documents.
With the minor changes I suggest in patch 1 series is
Reviewed-by: Sunil Khatri
-Original Message-
From: Alex Deucher
Sent: Wednesday, March 26, 2025 7:28 PM
To: D
[AMD Official Use Only - AMD Internal Distribution Only]
Gfx11 now we have same values, hence we don't need to differentiate between two
sets , only one set is needed like below.
As below
case IP_VERSION(11, 0, 0):
case IP_VERSION(11, 0, 2):
case IP_VERSION(11, 0, 3):
cas
On Wed, Mar 26, 2025 at 4:02 AM Srinivasan Shanmugam
wrote:
>
> Enable the cleaner shader for other GFX10.3.x series of GPUs to provide
> data isolation between GPU workloads. The cleaner shader is responsible
> for clearing the Local Data Store (LDS), Vector General Purpose
> Registers (VGPRs), a
On Wed, Mar 26, 2025 at 1:22 AM Kenneth Feng wrote:
>
> Port the workload profile setting logic into dm before MALL optimization.
>
> Background:
> MALL optimization strategy has changed in the firmware.Previously, firmware
> does not
> care what workload type it is, once there is a request from
The user can set any speed value.
If speed is greater than UINT_MAX/8, division by zero is possible.
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Fixes: c52dcf49195d ("drm/amd/pp: Avoid divide-by-zero in
fan_ctrl_set_fan_speed_rpm")
Signed-off-by: Denis Arefev
---
drivers/
+ Sunil to review this series
On Mon, Mar 24, 2025 at 3:48 PM Alex Deucher wrote:
>
> ping on this series?
>
> On Thu, Mar 20, 2025 at 4:36 PM Alex Deucher
> wrote:
> >
> > It's not used outside of amdgpu_gfx.c.
> >
> > Signed-off-by: Alex Deucher
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgp
On Wed, Mar 26, 2025 at 4:13 AM Christian König
wrote:
>
> Am 25.03.25 um 16:24 schrieb Srinivasan Shanmugam:
> > This commit addresses the issue where the cleaner shader was not
> > correctly executed during gang submissions due to improper handling of
> > the isolation spearhead.
> >
> > - Enhan
GC12 only has 1 mec.
Fixes: 52cb80c12e8a ("drm/amdgpu: Add gfx v12_0 ip block support (v6)")
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
b/drivers/gpu/drm/amd/am
GC11 only has 1 mec.
Fixes: 3d879e81f0f9 ("drm/amdgpu: add init support for GFX11 (v2)")
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
b/drivers/gpu/drm/amd/amdgpu
Am Mittwoch, dem 26.03.2025 um 12:50 +1100 schrieb Balbir Singh:
> On 3/26/25 10:43, Balbir Singh wrote:
> > On 3/26/25 10:21, Bert Karwatzki wrote:
> > > Am Mittwoch, dem 26.03.2025 um 09:45 +1100 schrieb Balbir Singh:
> > > >
> > > >
> > > > The second region seems to be additional, I suspect tha
Am Mittwoch, dem 26.03.2025 um 21:36 +1100 schrieb Balbir Singh:
> On 3/26/25 21:10, Bert Karwatzki wrote:
> > Am Mittwoch, dem 26.03.2025 um 12:50 +1100 schrieb Balbir Singh:
> > > On 3/26/25 10:43, Balbir Singh wrote:
> > > > On 3/26/25 10:21, Bert Karwatzki wrote:
> > > > > Am Mittwoch, dem 26.0
On Tue, Mar 25, 2025 at 11:53 PM Lijo Lazar wrote:
>
> Fetch VBIOS from shadow ROM when available before trying other methods
> like EFI method.
>
> Signed-off-by: Lijo Lazar
> Fixes: 9c081c11c621 ("drm/amdgpu: Reorder to read EFI exported ROM first")
> Closes: https://gitlab.freedesktop.org/drm/
Signed-off-by: Flora Cui
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index dc2713ec95a5..9e738fae2b74 100644
--- a/drivers/gpu/drm/amd/amdgpu/
On 3/25/25 6:12 PM, Alex Deucher wrote:
While you are at it, can you take a look at
drivers/gpu/drm/amd/amdgpu/isp_v4_1_0.c and
drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.c as well?
Alex
I think it makes more sense to handle that in a separate patch as it is
an unrelated ip block.
On 3/26/25 21:10, Bert Karwatzki wrote:
> Am Mittwoch, dem 26.03.2025 um 12:50 +1100 schrieb Balbir Singh:
>> On 3/26/25 10:43, Balbir Singh wrote:
>>> On 3/26/25 10:21, Bert Karwatzki wrote:
Am Mittwoch, dem 26.03.2025 um 09:45 +1100 schrieb Balbir Singh:
>
>
> The second region s
> > - int valid_class;
> > + int slctd_class;
>
> Nitpick: can you use full words? slctd is difficult to read.
>
yes. done. thx.
[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Candice Li
Sent: Wednesday, March 26, 2025 13:44
To: amd-gfx@lists.freedesktop.org
Cc: Li, Candice
Subject: [PATCH] Remove unnecessary firm
On Mon, Mar 24, 2025 at 9:20 AM Louis Chauvet wrote:
>
>
>
> Le 20/03/2025 à 19:52, Jim Cromie a écrit :
> > Current classmap code protects class'd pr_debugs from unintended
> > changes by "legacy" unclassed queries:
> >
> ># this doesn't disable all of DRM_UT_* categories
> >echo "-p" > /
msleep < 20ms will often sleep for ~20ms (according to
Documentation/timers/timers-howto.rst).
Signed-off-by: James Flowers
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amd
On 3/26/2025 1:43 PM, Asad Kamal wrote:
> Use gpu_metrics_v1_8 for smu_v13_0_6 to fill metrics data
>
> v2: Move exposing caps to separate patch, move smu_v13.0.12 gpu metrics
> 1.8 usage to separate patch (Lijo)
>
> Signed-off-by: Asad Kamal
Patches 5 and 6 are -
Reviewed-by: Lijo Lazar
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