[AMD Official Use Only - AMD Internal Distribution Only]
Series LGTM, if num_mec value is correct as per the hw documents.
With the minor changes I suggest in patch 1 series is
Reviewed-by: Sunil Khatri <sunil.kha...@amd.com>
-----Original Message-----
From: Alex Deucher <alexdeuc...@gmail.com>
Sent: Wednesday, March 26, 2025 7:28 PM
To: Deucher, Alexander <alexander.deuc...@amd.com>; Khatri, Sunil
<sunil.kha...@amd.com>
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/3] drm/amdgpu/gfx: make amdgpu_gfx_me_queue_to_bit()
static
+ Sunil to review this series
On Mon, Mar 24, 2025 at 3:4 PM Alex Deucher <alexdeuc...@gmail.com> wrote:
>
> ping on this series?
>
> On Thu, Mar 20, 2025 at 4:36 PM Alex Deucher <alexander.deuc...@amd.com>
> wrote:
> >
> > It's not used outside of amdgpu_gfx.c.
> >
> > Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 4 ++--
> > drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 2 --
> > 2 files changed, 2 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> > index 72af5e5a894a2..04982b7f33a8a 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> > @@ -74,8 +74,8 @@ bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device
> > *adev,
> > adev->gfx.mec_bitmap[xcc_id].queue_bitmap);
> > }
> >
> > -int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev,
> > - int me, int pipe, int queue)
> > +static int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev,
> > + int me, int pipe, int queue)
> > {
> > int bit = 0;
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> > index 75af4f25a133b..319e6e547c734 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> > @@ -551,8 +551,6 @@ bool amdgpu_gfx_is_high_priority_compute_queue(struct
> > amdgpu_device *adev,
> > struct amdgpu_ring
> > *ring); bool amdgpu_gfx_is_high_priority_graphics_queue(struct
> > amdgpu_device *adev,
> > struct amdgpu_ring
> > *ring); -int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me,
> > - int pipe, int queue);
> > bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me,
> > int pipe, int queue); void
> > amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable);
> > --
> > 2.49.0
> >
