From: Dillon Varone <dillon.var...@amd.com>
[WHY&HOW]
Core should evaluate support based on the max clocks after considering
downspread.
Reviewed-by: Austin Zheng <austin.zh...@amd.com>
Signed-off-by: Dillon Varone <dillon.var...@amd.com>
Signed-off-by: Fangzhi Zuo <jerry....@amd.com>
---
.../dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c | 6 +++---
.../amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_dcn4.c | 4 ++++
.../dc/dml2/dml21/src/inc/dml2_internal_shared_types.h | 6 ++++++
3 files changed, 13 insertions(+), 3 deletions(-)
diff --git
a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
index 5d91f195397a..a27409464616 100644
---
a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
+++
b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
@@ -7299,9 +7299,9 @@ static bool dml_core_mode_support(struct
dml2_core_calcs_mode_support_ex *in_out
mode_lib->ms.FabricClock =
((double)min_clk_table->dram_bw_table.entries[in_out_params->min_clk_index].min_fclk_khz
/ 1000);
mode_lib->ms.MaxDCFCLK = (double)min_clk_table->max_clocks_khz.dcfclk /
1000;
mode_lib->ms.MaxFabricClock =
(double)min_clk_table->max_clocks_khz.fclk / 1000;
- mode_lib->ms.max_dispclk_freq_mhz =
(double)min_clk_table->max_clocks_khz.dispclk / 1000;
+ mode_lib->ms.max_dispclk_freq_mhz =
(double)min_clk_table->max_ss_clocks_khz.dispclk / 1000;
mode_lib->ms.max_dscclk_freq_mhz =
(double)min_clk_table->max_clocks_khz.dscclk / 1000;
- mode_lib->ms.max_dppclk_freq_mhz =
(double)min_clk_table->max_clocks_khz.dppclk / 1000;
+ mode_lib->ms.max_dppclk_freq_mhz =
(double)min_clk_table->max_ss_clocks_khz.dppclk / 1000;
mode_lib->ms.uclk_freq_mhz =
dram_bw_kbps_to_uclk_mhz(min_clk_table->dram_bw_table.entries[in_out_params->min_clk_index].pre_derate_dram_bw_kbps,
&mode_lib->soc.clk_table.dram_config);
mode_lib->ms.dram_bw_mbps =
((double)min_clk_table->dram_bw_table.entries[in_out_params->min_clk_index].pre_derate_dram_bw_kbps
/ 1000);
mode_lib->ms.max_dram_bw_mbps =
((double)min_clk_table->dram_bw_table.entries[min_clk_table->dram_bw_table.num_entries
- 1].pre_derate_dram_bw_kbps / 1000);
@@ -8061,7 +8061,7 @@ static bool dml_core_mode_support(struct
dml2_core_calcs_mode_support_ex *in_out
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.audio_sample_rate,
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.audio_sample_layout);
- if (mode_lib->ms.RequiredDTBCLK[k] >
((double)min_clk_table->max_clocks_khz.dtbclk / 1000)) {
+ if (mode_lib->ms.RequiredDTBCLK[k] >
((double)min_clk_table->max_ss_clocks_khz.dtbclk / 1000)) {
mode_lib->ms.support.DTBCLKRequiredMoreThanSupported = true;
}
} else {
diff --git
a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_dcn4.c
b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_dcn4.c
index f4b1a7d02d42..a265f254152c 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_dcn4.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_dcn4.c
@@ -182,6 +182,10 @@ static bool build_min_clock_table(const struct dml2_soc_bb
*soc_bb, struct dml2_
min_table->max_clocks_khz.dtbclk =
soc_bb->clk_table.dtbclk.clk_values_khz[soc_bb->clk_table.dtbclk.num_clk_values
- 1];
min_table->max_clocks_khz.phyclk =
soc_bb->clk_table.phyclk.clk_values_khz[soc_bb->clk_table.phyclk.num_clk_values
- 1];
+ min_table->max_ss_clocks_khz.dispclk = (unsigned
int)((double)min_table->max_clocks_khz.dispclk / (1.0 +
soc_bb->dcn_downspread_percent / 100.0));
+ min_table->max_ss_clocks_khz.dppclk = (unsigned
int)((double)min_table->max_clocks_khz.dppclk / (1.0 +
soc_bb->dcn_downspread_percent / 100.0));
+ min_table->max_ss_clocks_khz.dtbclk = (unsigned
int)((double)min_table->max_clocks_khz.dtbclk / (1.0 +
soc_bb->dcn_downspread_percent / 100.0));
+
min_table->max_clocks_khz.dcfclk =
soc_bb->clk_table.dcfclk.clk_values_khz[soc_bb->clk_table.dcfclk.num_clk_values
- 1];
min_table->max_clocks_khz.fclk =
soc_bb->clk_table.fclk.clk_values_khz[soc_bb->clk_table.fclk.num_clk_values -
1];
diff --git
a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
index d8d01dceacdd..00688b9f1df4 100644
---
a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
+++
b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
@@ -37,6 +37,12 @@ struct dml2_mcg_min_clock_table {
unsigned int dcfclk;
} max_clocks_khz;
+ struct {
+ unsigned int dispclk;
+ unsigned int dppclk;
+ unsigned int dtbclk;
+ } max_ss_clocks_khz;
+
struct {
unsigned int dprefclk;
unsigned int xtalclk;
--
2.43.0
