[U-Boot] [PATCH] i2c: xiic: Add Xilinx AXI I2C driver
Add Xilinx AXI I2C controller driver based on the Linux i2c-xiic driver.
This driver is stripped of all the IRQ handling and uses pure polling,
yet tries to retain most of the structure of the Linux driver to make
backporting of fixes easy.
Note that the IP has a known limitation on 255 bytes read and write,
according to xilinx this is still being worked on [1].
[1]
https://forums.xilinx.com/t5/Embedded-Processor-System-Design/AXI-IIC-V2-0-I2C-Master-Reading-multiple-bytes-from-I2C-slave/m-p/854419/highlight/true#M39387
Signed-off-by: Marek Vasut
Cc: Michal Simek
Cc: Michal Simek
Cc: Heiko Schocher
---
drivers/i2c/Kconfig | 6 +
drivers/i2c/Makefile | 1 +
drivers/i2c/xilinx_xiic.c | 340 ++
3 files changed, 347 insertions(+)
create mode 100644 drivers/i2c/xilinx_xiic.c
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 5eceab9ea8..810d861f32 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -437,6 +437,12 @@ config SYS_I2C_BUS_MAX
help
Define the maximum number of available I2C buses.
+config SYS_I2C_XILINX_XIIC
+ bool "Xilinx AXI I2C driver"
+depends on DM_I2C
+ help
+ Support for Xilinx AXI I2C controller.
+
config SYS_I2C_ZYNQ
bool "Xilinx I2C driver"
depends on ARCH_ZYNQMP || ARCH_ZYNQ
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index da368cc02a..94c68c8ba1 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -38,6 +38,7 @@ obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o
obj-$(CONFIG_SYS_I2C_UNIPHIER) += i2c-uniphier.o
obj-$(CONFIG_SYS_I2C_UNIPHIER_F) += i2c-uniphier-f.o
obj-$(CONFIG_SYS_I2C_ZYNQ) += zynq_i2c.o
+obj-$(CONFIG_SYS_I2C_XILINX_XIIC) += xilinx_xiic.o
obj-$(CONFIG_TEGRA186_BPMP_I2C) += tegra186_bpmp_i2c.o
obj-$(CONFIG_I2C_MUX) += muxes/
diff --git a/drivers/i2c/xilinx_xiic.c b/drivers/i2c/xilinx_xiic.c
new file mode 100644
index 00..180cd14fec
--- /dev/null
+++ b/drivers/i2c/xilinx_xiic.c
@@ -0,0 +1,340 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx AXI I2C driver
+ *
+ * Copyright (C) 2018 Marek Vasut
+ *
+ * Based on Linux 4.14.y i2c-xiic.c
+ * Copyright (c) 2002-2007 Xilinx Inc.
+ * Copyright (c) 2009-2010 Intel Corporation
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct xilinx_xiic_priv {
+ void __iomem*base;
+ struct clk clk;
+};
+
+#define XIIC_MSB_OFFSET 0
+#define XIIC_REG_OFFSET (0x100+XIIC_MSB_OFFSET)
+
+/*
+ * Register offsets in bytes from RegisterBase. Three is added to the
+ * base offset to access LSB (IBM style) of the word
+ */
+#define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET)/* Control Register */
+#define XIIC_SR_REG_OFFSET (0x04+XIIC_REG_OFFSET)/* Status Register*/
+#define XIIC_DTR_REG_OFFSET (0x08+XIIC_REG_OFFSET)/* Data Tx Register */
+#define XIIC_DRR_REG_OFFSET (0x0C+XIIC_REG_OFFSET)/* Data Rx Register */
+#define XIIC_ADR_REG_OFFSET (0x10+XIIC_REG_OFFSET)/* Address Register */
+#define XIIC_TFO_REG_OFFSET (0x14+XIIC_REG_OFFSET)/* Tx FIFO Occupancy */
+#define XIIC_RFO_REG_OFFSET (0x18+XIIC_REG_OFFSET)/* Rx FIFO Occupancy */
+#define XIIC_TBA_REG_OFFSET (0x1C+XIIC_REG_OFFSET)/* 10 Bit Address reg */
+#define XIIC_RFD_REG_OFFSET (0x20+XIIC_REG_OFFSET)/* Rx FIFO Depth reg */
+#define XIIC_GPO_REG_OFFSET (0x24+XIIC_REG_OFFSET)/* Output Register*/
+
+/* Control Register masks */
+#define XIIC_CR_ENABLE_DEVICE_MASK0x01 /* Device enable = 1 */
+#define XIIC_CR_TX_FIFO_RESET_MASK0x02 /* Transmit FIFO reset=1 */
+#define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */
+#define XIIC_CR_DIR_IS_TX_MASK0x08 /* Dir of tx. Txing=1 */
+#define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */
+#define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */
+#define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */
+
+/* Status Register masks */
+#define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */
+#define XIIC_SR_ADDR_AS_SLAVE_MASK0x02 /* 1=when addr as slave */
+#define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy*/
+#define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */
+#define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */
+#define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */
+#define XIIC_SR_RX_FIFO_EMPTY_MASK0x40 /* 1 = Rx FIFO empty */
+#define XIIC_SR_TX_FIFO_EMPTY_MASK0x80 /* 1 = Tx FIFO empty */
+
+/* Interrupt Status Register masksInterrupt occurs when... */
+#define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */
+#define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete */
+#define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty
Re: [U-Boot] [PATCH 1/3] riscv: Add asm/dma-mapping.h for DMA mappings
On Tue, Dec 18, 2018 at 3:15 PM Bin Meng wrote:
>
> On Mon, Dec 17, 2018 at 7:52 PM Anup Patel wrote:
> >
> > From: Anup Patel
> >
> > This patch adds asm/dma-mapping.h for Linux-like DMA mappings
> > APIs required by some of the drivers (such as, Cadance MACB
> > Ethernet driver).
> >
> > Signed-off-by: Anup Patel
> > ---
> > arch/riscv/include/asm/dma-mapping.h | 37
> > 1 file changed, 37 insertions(+)
> > create mode 100644 arch/riscv/include/asm/dma-mapping.h
> >
>
> Reviewed-by: Bin Meng
>
> But please see nits below:
>
> > diff --git a/arch/riscv/include/asm/dma-mapping.h
> > b/arch/riscv/include/asm/dma-mapping.h
> > new file mode 100644
> > index 00..9782b6f168
> > --- /dev/null
> > +++ b/arch/riscv/include/asm/dma-mapping.h
> > @@ -0,0 +1,37 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * Copyright (c) 2018 Western Digital Corporation or its affiliates.
> > + *
> > + * Authors:
> > + * Anup Patel
> > + */
>
> nits: should have one blank line here
OK, will update.
>
> > +#ifndef __ASM_RISCV_DMA_MAPPING_H
> > +#define __ASM_RISCV_DMA_MAPPING_H
> > +
> > +#include
> > +
> > +#definedma_mapping_error(x, y) 0
>
> nits: no between #define and dma_
OK, will update.
>
> > +
> > +static inline void *dma_alloc_coherent(size_t len, unsigned long *handle)
> > +{
> > + *handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, len);
> > + return (void *)*handle;
> > +}
> > +
> > +static inline void dma_free_coherent(void *addr)
> > +{
> > + free(addr);
> > +}
> > +
> > +static inline unsigned long dma_map_single(volatile void *vaddr, size_t
> > len,
> > + enum dma_data_direction dir)
> > +{
> > + return (unsigned long)vaddr;
> > +}
> > +
> > +static inline void dma_unmap_single(volatile void *vaddr, size_t len,
> > + unsigned long paddr)
> > +{
> > +}
> > +
> > +#endif /* __ASM_RISCV_DMA_MAPPING_H */
> > --
>
> Regards,
> Bin
Regards,
Anup
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Re: [U-Boot] [PATCH 2/3] net: macb: Fix clk API usage for RISC-V systems
On Tue, Dec 18, 2018 at 3:15 PM Bin Meng wrote: > > On Mon, Dec 17, 2018 at 7:52 PM Anup Patel wrote: > > > > From: Anup Patel > > > > This patch does following fixes in MACB ethernet driver > > for using it on RISC-V systems (particularly QEMU sifive_u > > machine): > > 1. asm/arch/clk.h is not available on RISC-V port so include > >it only for non-RISC-V systems. > > 2. Don't fail in macb_enable_clk() if clk_enable() returns > >-ENOSYS because we get -ENOSYS for fixed-rate clocks. > > > > Signed-off-by: Anup Patel > > --- > > drivers/net/macb.c | 4 +++- > > 1 file changed, 3 insertions(+), 1 deletion(-) > > > > Reviewed-by: Bin Meng > > But please see comments below: > > > diff --git a/drivers/net/macb.c b/drivers/net/macb.c > > index 94c89c762b..9a06b523cc 100644 > > --- a/drivers/net/macb.c > > +++ b/drivers/net/macb.c > > @@ -38,7 +38,9 @@ > > #include > > #include > > #include > > +#ifndef CONFIG_RISCV > > #include > > +#endif > > #include > > > > #include "macb.h" > > @@ -1066,7 +1068,7 @@ static int macb_enable_clk(struct udevice *dev) > > */ > > #ifndef CONFIG_MACB_ZYNQ > > I suspect this "#ifndef CONFIG_MACB_ZYNQ" can be removed per the > comments below, with the adding check of (ret != -ENOSYS). > > /* > * Zynq clock driver didn't support for enable or disable > * clock. Hence, clk_enable() didn't apply for Zynq > */ > > Someone else who has access to Zynq targets need to confirm. I think let someone with Zynq SOC based board remove this. Regards, Anup ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [linux-sunxi] [PATCH] Revert "sunxi: board: Print error after power initialization fails"
Hi André On Wed, Dec 19, 2018 at 2:46 AM André Przywara wrote: > > On 19/12/2018 00:51, André Przywara wrote: > > On 18/12/2018 12:06, Jagan Teki wrote: > >> On Tue, Dec 18, 2018 at 4:09 PM wrote: > >>> > >>> From: Karl Palsson > >>> > >>> This reverts commit a8011eb84dfac5187cebf00ed8bc981bdb5c1fa1 > >>> > >>> This causes DRAM init failures on (at least) > >>> * allwinner h3 nanopi-duo2 > >>> * allwinner h2+ orangepi zero v1.1 > >>> > >>> Signed-off-by: Karl Palsson > >>> --- > >>> > >>> Ideally, this should get into 2019.01, so that this release is not > >>> broken on those targets. > >> > >> Better to understand the issue here, since I have BPI-M2+ which boots > >> fine w/o this revert. > > > > Could this be a .bss issue? This lies in DRAM and is thus only available > > *after* DRAM init. IIRC we silently rely on not accessing anything in > > .bss before the DRAM is up, see 59d07ee08e85 for instance. > > I don't immediately spot any .bss usage in clock_set_pll1(), though. > > > > Or is the 1GHz CPU clock speed too fast for the DRAM init? If I am not > > mistaken, we run with 24MHz before, so there might be some "natural" > > delay in some setup routines. Some DRAM chips or board layout might be > > more susceptible to this than others, which might explain why it only > > fails on some boards. > > Just did some testing on my OrangePi Zero: if I force the CPU frequency > to 408 MHz, it works, but fails with the standard 1008 MHz. > So this smells that we indeed miss some delays in the DRAM setup code, > which sounds tedious to find. There are a number of delays, but those > are fine as they are timer controlled, so independent from the CPU > frequency. > > For now I think that reverting would be the easiest solution. Somewhat > in contrast to what the commit message says, we don't really change > anything in terms of error *checking*, as the code carries on anyways > (just without increasing the CPU frequency). The only real difference is > the order of CPU clock setup and DRAM init. > > Karl, can you please amend the commit message to mention the CPU > frequency issue? > > > So if the original patch is about bailing out on error early, can't we > > just do *that* before the DRAM init, keeping the CPU clock setup still > > after DRAM? > > Just checked, this works as well, but is a bit pointless. Just reverting > this and meanwhile checking the DRAM init code seems the easier solution. > Definitely have the same impression. Please send the same revert but adjust the commit message Michael > Cheers, > Andre > ___ > U-Boot mailing list > U-Boot@lists.denx.de > https://lists.denx.de/listinfo/u-boot -- | Michael Nazzareno Trimarchi Amarula Solutions BV | | COO - Founder Cruquiuskade 47 | | +31(0)851119172 Amsterdam 1018 AM NL | | [`as] http://www.amarulasolutions.com | ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [linux-sunxi] [PATCH] Revert "sunxi: board: Print error after power initialization fails"
On Wed, Dec 19, 2018 at 01:45:29AM +, André Przywara wrote: > On 19/12/2018 00:51, André Przywara wrote: > > On 18/12/2018 12:06, Jagan Teki wrote: > >> On Tue, Dec 18, 2018 at 4:09 PM wrote: > >>> > >>> From: Karl Palsson > >>> > >>> This reverts commit a8011eb84dfac5187cebf00ed8bc981bdb5c1fa1 > >>> > >>> This causes DRAM init failures on (at least) > >>> * allwinner h3 nanopi-duo2 > >>> * allwinner h2+ orangepi zero v1.1 > >>> > >>> Signed-off-by: Karl Palsson > >>> --- > >>> > >>> Ideally, this should get into 2019.01, so that this release is not > >>> broken on those targets. > >> > >> Better to understand the issue here, since I have BPI-M2+ which boots > >> fine w/o this revert. > > > > Could this be a .bss issue? This lies in DRAM and is thus only available > > *after* DRAM init. IIRC we silently rely on not accessing anything in > > .bss before the DRAM is up, see 59d07ee08e85 for instance. > > I don't immediately spot any .bss usage in clock_set_pll1(), though. > > > > Or is the 1GHz CPU clock speed too fast for the DRAM init? If I am not > > mistaken, we run with 24MHz before, so there might be some "natural" > > delay in some setup routines. Some DRAM chips or board layout might be > > more susceptible to this than others, which might explain why it only > > fails on some boards. > > Just did some testing on my OrangePi Zero: if I force the CPU frequency > to 408 MHz, it works, but fails with the standard 1008 MHz. > So this smells that we indeed miss some delays in the DRAM setup code, > which sounds tedious to find. There are a number of delays, but those > are fine as they are timer controlled, so independent from the CPU > frequency. With latest u-boot, I got it only working when lowering DRAM_CLK to 312MHz (default being 624 MHz(. Even with 336 and 360 MHz it hung just after displaying the 'Trying to boot from FEL' message, while reporting wrong DRAM size (1GiB and 2048MiB). > > For now I think that reverting would be the easiest solution. Somewhat > in contrast to what the commit message says, we don't really change > anything in terms of error *checking*, as the code carries on anyways > (just without increasing the CPU frequency). The only real difference is > the order of CPU clock setup and DRAM init. > > Karl, can you please amend the commit message to mention the CPU > frequency issue? > > > So if the original patch is about bailing out on error early, can't we > > just do *that* before the DRAM init, keeping the CPU clock setup still > > after DRAM? > > Just checked, this works as well, but is a bit pointless. Just reverting > this and meanwhile checking the DRAM init code seems the easier solution. > > Cheers, > Andre > > -- > You received this message because you are subscribed to the Google Groups > "linux-sunxi" group. > To unsubscribe from this group and stop receiving emails from it, send an > email to linux-sunxi+unsubscr...@googlegroups.com. > For more options, visit https://groups.google.com/d/optout. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v6 0/4] Stratix10 FPGA reconfiguration support
On 12/19/2018 05:53 AM, Ang, Chee Hong wrote: > On Tue, 2018-12-18 at 18:47 +0100, Marek Vasut wrote: >> On 12/18/2018 09:54 AM, chee.hong@intel.com wrote: >>> >>> From: "Ang, Chee Hong" >>> >>> Summary of v6 changes: >>> - Patch 1/4 and 4/4 are unchanged >>> - Patch 2/4: >>> - fixed compilation warnings in drivers/fpga/stratix10.c >>> - Patch 3/4: >>> - socfpga_fpga_add() in misc.c >>> - define fpga descriptor structure in misc_arria10.c, misc_gen5.c >>> & >>> misc_s10.c respectively >>> - removed for-loop in socfpga_fpga_add() (only 1 FPGA device >>> added) >>> >>> v5 patchsets: >>> https://lists.denx.de/pipermail/u-boot/2018-November/349670.html >>> >>> Ang, Chee Hong (4): >>> arm: socfpga: stratix10: Add macros for mailbox's arguments >>> arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration >>> Driver >>> arm: socfpga: stratix10: Add Stratix10 FPGA into FPGA device >>> table >>> arm: socfpga: stratix10: Enable Stratix10 FPGA Reconfiguration >>> >>> arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 6 + >>> arch/arm/mach-socfpga/include/mach/misc.h| 4 +- >>> arch/arm/mach-socfpga/misc.c | 26 +- >>> arch/arm/mach-socfpga/misc_arria10.c | 22 +- >>> arch/arm/mach-socfpga/misc_gen5.c| 22 +- >>> arch/arm/mach-socfpga/misc_s10.c | 22 ++ >>> configs/socfpga_stratix10_defconfig | 1 + >>> drivers/fpga/Kconfig | 11 + >>> drivers/fpga/Makefile| 1 + >>> drivers/fpga/altera.c| 6 + >>> drivers/fpga/stratix10.c | 288 >>> +++ >>> include/altera.h | 8 + >>> 12 files changed, 389 insertions(+), 28 deletions(-) >>> create mode 100644 drivers/fpga/stratix10.c >> I take it this fixes the previous stratix 10 build breakage, right ? >> let's see what travis says. > Yes. Actually they are just compilation warnings to me. Your travis's > build settings treat all warning as error. Please let me know about the > travis report. Thanks. +drivers/fpga/stratix10.c: In function 'reconfig_status_polling_resp': +drivers/fpga/stratix10.c:102:9: error: implicit declaration of function 'mbox_get_fpga_config_status' [-Werror=implicit-function-declaration] + ret = mbox_get_fpga_config_status(MBOX_RECONFIG_STATUS); + ^~~ +cc1: all warnings being treated as errors +make[3]: *** [drivers/fpga/stratix10.o] Error 1 +make[2]: *** [drivers/fpga] Error 2 +make[1]: *** [drivers] Error 2 +make: *** [sub-make] Error 2 Seems like a compile error to me. Please at least build the patches before posting them. See my other email. -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v6 4/4] arm: socfpga: stratix10: Enable Stratix10 FPGA Reconfiguration
On 12/19/2018 05:55 AM, Ang, Chee Hong wrote: > On Tue, 2018-12-18 at 18:47 +0100, Marek Vasut wrote: >> On 12/18/2018 09:54 AM, chee.hong@intel.com wrote: >>> >>> From: "Ang, Chee Hong" >>> >>> Enable Stratix10 FPGA reconfiguration support in defconfig. >>> >>> Signed-off-by: Ang, Chee Hong >>> --- >>> configs/socfpga_stratix10_defconfig | 1 + >>> 1 file changed, 1 insertion(+) >>> >>> diff --git a/configs/socfpga_stratix10_defconfig >>> b/configs/socfpga_stratix10_defconfig >>> index 5f3d733..155c406 100644 >>> --- a/configs/socfpga_stratix10_defconfig >>> +++ b/configs/socfpga_stratix10_defconfig >>> @@ -10,6 +10,7 @@ CONFIG_NR_DRAM_BANKS=1 >>> CONFIG_BOOTDELAY=5 >>> CONFIG_SPL_SPI_LOAD=y >>> CONFIG_HUSH_PARSER=y >>> +CONFIG_FPGA_STRATIX10=y >>> CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # " >>> CONFIG_CMD_MEMTEST=y >>> # CONFIG_CMD_FLASH is not set >>> >> Can you send a subsequent patch which uses Kconfig imply to select >> FPGA_STRATIX10 on S10 instead of adding it in defconfig ? > Noted. Will address this in next patchsets. I asked you for an incremental patch, not for reposting the whole patchset (also, please track changelog with new versions of patches). But travis would seem to indicate, again, that the patches break some other target [1]. Can you please at least build test the next version of patches on all systems before posting them ? You can very well just set up the travis CI with your github repo/fork of u-boot repo, push a branch there and wait for travis to build that branch on all supported systems and tell you what the situation is. It saves me time, which I otherwise spend on applying, rejecting and dropping of your patches after they fail to build. [1] https://travis-ci.org/marex/u-boot-socfpga/jobs/469629378#L1142 -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 1/2] mtd/spi: Add JEDEC SFDP support in SPI framework
> -Original Message-
> From: Vignesh R
> Sent: Friday, November 16, 2018 8:56 PM
> To: Rajat Srivastava ; Simon Goldschmidt
> ; U-Boot Mailing List b...@lists.denx.de>
> Cc: Jagan Teki
> Subject: Re: [U-Boot] [PATCH v2 1/2] mtd/spi: Add JEDEC SFDP support in SPI
> framework
>
> On 16-Nov-18 6:29 PM, Rajat Srivastava wrote:
> >> On Fri, Nov 16, 2018 at 11:19 AM Vignesh R wrote:
> >>> On 16/11/18 3:10 PM, Rajat Srivastava wrote:
> > Hi Rajat,
> >
> > On 13/11/18 5:30 PM, Rajat Srivastava wrote:
> >> Add support for JESD216 rev B standard JEDEC Serial Flash
> >> Discoverable Parameters (SFDP) tables to dynamically initialize
> >> flash size, page size and address width of the flash. More
> >> parameters can be added as per requirement.
> >> SFDP parsing is made default but already existing method for
> >> parsing these parameters are not deprecated.
> >> A flag is created to skip SFDP parsing for a particular flash, if
> >> required.
> >>
> >> SFDP data lets us auto-detect the addressing mode supported by
> >> the flash which helps us access the flash using 4-byte address.
> >>
> >> Add a new argument in spi_flash_addr() function to create
> >> commands with 3-byte or 4-byte address depending on the SFDP
> data
> >> read. Add pointer to struct spi_flash in struct spi_slave so that
> >> driver can have access to SFDP data.
> >>
> >> Introduce new structures and functions to read and parse SFDP data.
> >> This is loosely based on Linux SFDP framework.
> >>
> >> Signed-off-by: Rajat Srivastava
> >> ---
> >> Changes in v2:
> >> - Make SFDP parsing the default method.
> >> - Change SPI_FLASH_USE_SFDP flag to SPI_FLASH_USE_SFDP to
> >> provide
> >> an option to skip SFDP parsing for a particular flash.
> >> ---
> >
> > [...]
> >> +static int spi_flash_parse_bfpt(struct spi_flash *flash,
> >> + const struct sfdp_parameter_header
> > *bfpt_header) {
> >> + struct sfdp_bfpt bfpt;
> >> + size_t len;
> >> + int i, err;
> >> + u32 addr;
> >> +
> >> + /* JESD216 Basic Flash Parameter Table length is at least 9
> DWORDs.
> > */
> >> + if (bfpt_header->length < BFPT_DWORD_MAX_JESD216)
> >> + return -EINVAL;
> >> +
> >> + /* Read the Basic Flash Parameter Table. */
> >> + len = min_t(size_t, sizeof(bfpt),
> >> + bfpt_header->length * sizeof(u32));
> >> + addr = SFDP_PARAM_HEADER_PTP(bfpt_header);
> >> + memset(&bfpt, 0, sizeof(bfpt));
> >> + err = spi_flash_read_sfdp(flash, addr, len, &bfpt);
> >> + if (err < 0)
> >> + return err;
> >> +
> >> + /* Fix endianness of the BFPT DWORDs. */
> >> + for (i = 0; i < BFPT_DWORD_MAX; i++)
> >> + bfpt.dwords[i] = le32_to_cpu(bfpt.dwords[i]);
> >> +
> >> + /* Number of address bytes. */
> >> + switch (bfpt.dwords[BFPT_DWORD(1)] &
> > BFPT_DWORD1_ADDRESS_BYTES_MASK) {
> >> + case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY:
> >> + flash->addr_width = 3;
> >> + break;
> >> +
> >> + case BFPT_DWORD1_ADDRESS_BYTES_3_OR_4:
> >> + printf("SF: Flash defaults to 3-Byte mode; enters 4-Byte
> >> ");
> >> + printf("mode on command\n");
> >> + /*
> >> +* By default, 4-byte addressing mode is set.
> >> +* To enforce 3-byte addressing mode, set
> >> + addrwd_3_in_use
> > flag
> >> +* in struct spi_flash for every command.
> >> +*/
> >> + flash->addr_width = 4;
> >> + break;
> >> +
> >> + case BFPT_DWORD1_ADDRESS_BYTES_4_ONLY:
> >> + flash->addr_width = 4;
> >> + break;
> >> +
> >
> > I see your are updating flash->addr_width to 4 bytes here. But I
> > don't see any code in this patch that changes flash->read_cmd (and
> > write/erase
> > cmds) to use 4B addressing opcodes. Also, I dont see any code that
> > bypasses BAR register configuration when CONFIG_SPI_FLASH_BAR is
> > defined and SFDP is available.
>
> We don't have any flash that supports CONFIG_SPI_FLASH_BAR. What
> do
> >> you suggest, shall we skip SFDP parsing in case CONFIG_SPI_FLASH_BAR
> >> is defined?
>
> >>>
> >>> I suggest skipping BAR configuration completely if flash supports
> >>> address width of 4 as per SFDP. BAR configuration is only needed if
> >>> flash does not support 4 byte addressing and flash size is > 16MB
> >>>
> > This patch will most certainly break SPI controller drivers(like
> > cadence_qspi.c) that expect sf layer to provide correct read
> > opcode and address width information, since there will be mismatch
> > wrt opcode used and number of address byte sent.
> > Not sure how thi
Re: [U-Boot] [PATCH 0/3] Ethernet support for QEMU sifive_u machine
Hi Anup, On Wed, Dec 19, 2018 at 2:32 PM Anup Patel wrote: > > On Wed, Dec 19, 2018 at 11:02 AM Bin Meng wrote: > > > > Hi Anup, > > > > On Wed, Dec 19, 2018 at 12:41 PM Anup Patel wrote: > > > > > > On Tue, Dec 18, 2018 at 4:06 PM Bin Meng wrote: > > > > > > > > Hi Anup, > > > > > > > > On Tue, Dec 18, 2018 at 6:33 PM Anup Patel wrote: > > > > > > > > > > On Tue, Dec 18, 2018 at 3:21 PM Bin Meng wrote: > > > > > > > > > > > > Hi Anup, > > > > > > > > > > > > On Mon, Dec 17, 2018 at 7:51 PM Anup Patel > > > > > > wrote: > > > > > > > > > > > > > > This patchset enables Cadance MACB ethernet driver for > > > > > > > QEMU sifive_u machine. The Cadance MACB ethernet driver > > > > > > > works fine for QEMU sifive_u machince in both M-mode and > > > > > > > S-mode with some minor fixes. > > > > > > > > > > > > > > The patches are based upon latest RISC-V U-Boot tree > > > > > > > (git://git.denx.de/u-boot-riscv.git) at commit id > > > > > > > 9deb8d2fcd13d4a40a4e63c396fe4376af46efac > > > > > > > > > > > > > > To try on QEMU, please ensure following patches are > > > > > > > applied to QEMU sources: > > > > > > > https://patchwork.kernel.org/patch/10729579/ > > > > > > > https://patchwork.kernel.org/patch/10729581/ > > > > > > > > > > > > > > > > > > > What "-device " parameter should I tell QEMU to instantiate the > > > > > > MACB? > > > > > > "-device ?" does not give me anything that looks like MACB. Without > > > > > > a > > > > > > proper "-device " parameter, I can boot U-Boot on QEMU sifive_u and > > > > > > see U-Boot driver is probed, but a simple 'ping' test does not work. > > > > > > > > > > Try the following: > > > > > # setenv ipaddr 10.0.2.1 > > > > > # ping 10.0.2.2 > > > > > > > > > > > > > Yes, I have set up all the required network parameters. > > > > > > > > > The above works for me on QEMU. > > > > > > > > My understanding is that we need enable QEMU network via "-netdev " > > > > (either usr, or tap), with a corresponding "-device". I don't know how > > > > to set it up. What's your command line to test this? > > > > > > > > > > "-netdev" or "-device" parameters are not mandatory. By default, virtual > > > NICs are in NAT mode. The QEMU NAT gateway is at IP address > > > 10.0.2.2. We can always ping the NAT gateway when virtual NIC is in > > > NAT mode. > > > > > > Here's how I compile for M-mode: > > > # ARCH=riscv > > > # CROSS_COMPILE=riscv64-unknown-linux-gnu- > > > # make qemu-riscv64_defconfig > > > # make > > > > > > My U-boot log is as follows: > > > > > > anup@anup-ubuntu64:~/Work/riscv-test/u-boot$ qemu-system-riscv64 -M > > > sifive_u -m 256M -display none -serial stdio -kernel ./u-boot > > > > > > > > > U-Boot 2019.01-rc1-00948-ge6b3cdafd0 (Dec 19 2018 - 10:05:50 +0530) > > > > > > CPU: rv64imafdcsu > > > Model: ucbbar,spike-bare,qemu > > > DRAM: 256 MiB > > > In:uart@10013000 > > > Out: uart@10013000 > > > Err: uart@10013000 > > > Net: > > > Warning: ethernet@100900fc (eth0) using random MAC address - > > > f6:1f:8c:13:83:c0 > > > eth0: ethernet@100900fc > > > Hit any key to stop autoboot: 0 > > > > > > Device 0: unknown device > > > ethernet@100900fc: PHY present at 0 > > > ethernet@100900fc: link up, 100Mbps full-duplex (lpa: 0xcde1) > > > BOOTP broadcast 1 > > > DHCP client bound to address 10.0.2.15 (2 ms) > > > Using ethernet@100900fc device > > > TFTP from server 10.0.2.2; our IP address is 10.0.2.15 > > > Filename 'boot.scr.uimg'. > > > Load address: 0x8210 > > > Loading: * > > > TFTP error: 'Access violation' (2) > > > Not retrying... > > > ethernet@100900fc: PHY present at 0 > > > ethernet@100900fc: link up, 100Mbps full-duplex (lpa: 0xcde1) > > > BOOTP broadcast 1 > > > DHCP client bound to address 10.0.2.15 (1 ms) > > > Using ethernet@100900fc device > > > TFTP from server 10.0.2.2; our IP address is 10.0.2.15 > > > Filename 'boot.scr.uimg'. > > > Load address: 0x8100 > > > Loading: * > > > TFTP error: 'Access violation' (2) > > > Not retrying... > > > => ping 10.0.2.2 > > > ethernet@100900fc: PHY present at 0 > > > ethernet@100900fc: link up, 100Mbps full-duplex (lpa: 0xcde1) > > > Using ethernet@100900fc device > > > host 10.0.2.2 is alive > > > => > > > ethernet@100900fc: PHY present at 0 > > > ethernet@100900fc: link up, 100Mbps full-duplex (lpa: 0xcde1) > > > Using ethernet@100900fc device > > > host 10.0.2.2 is alive > > > => qemu-system-riscv64: terminating on signal 2 > > > > > > > I have always been using "qemu-system-riscv64 -nographic -M sifive_u > > -kernel u-boot" to test U-Boot on qemu risc-v. > > With above command, I can "ping 10.0.2.2" and get the exact the same > > result as yours. > > > > However I wanted to connect the tap interface to the emulated network > > controller for testing, that's why I wanted to use "-device" and > > "-netdev", but I don't know which device string I need to tell QEMU. > > After a bit googleing I got the following page: > > https://forums.xilinx.com/t5/Embedded-Processor-System-Design/Zyn
Re: [U-Boot] [PATCH v6 4/4] arm: socfpga: stratix10: Enable Stratix10 FPGA Reconfiguration
On Wed, 2018-12-19 at 09:41 +0100, Marek Vasut wrote: > On 12/19/2018 05:55 AM, Ang, Chee Hong wrote: > > > > On Tue, 2018-12-18 at 18:47 +0100, Marek Vasut wrote: > > > > > > On 12/18/2018 09:54 AM, chee.hong@intel.com wrote: > > > > > > > > > > > > From: "Ang, Chee Hong" > > > > > > > > Enable Stratix10 FPGA reconfiguration support in defconfig. > > > > > > > > Signed-off-by: Ang, Chee Hong > > > > --- > > > > configs/socfpga_stratix10_defconfig | 1 + > > > > 1 file changed, 1 insertion(+) > > > > > > > > diff --git a/configs/socfpga_stratix10_defconfig > > > > b/configs/socfpga_stratix10_defconfig > > > > index 5f3d733..155c406 100644 > > > > --- a/configs/socfpga_stratix10_defconfig > > > > +++ b/configs/socfpga_stratix10_defconfig > > > > @@ -10,6 +10,7 @@ CONFIG_NR_DRAM_BANKS=1 > > > > CONFIG_BOOTDELAY=5 > > > > CONFIG_SPL_SPI_LOAD=y > > > > CONFIG_HUSH_PARSER=y > > > > +CONFIG_FPGA_STRATIX10=y > > > > CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # " > > > > CONFIG_CMD_MEMTEST=y > > > > # CONFIG_CMD_FLASH is not set > > > > > > > Can you send a subsequent patch which uses Kconfig imply to > > > select > > > FPGA_STRATIX10 on S10 instead of adding it in defconfig ? > > Noted. Will address this in next patchsets. > I asked you for an incremental patch, not for reposting the whole > patchset (also, please track changelog with new versions of patches). > > But travis would seem to indicate, again, that the patches break some > other target [1]. Can you please at least build test the next version > of > patches on all systems before posting them ? > > You can very well just set up the travis CI with your github > repo/fork > of u-boot repo, push a branch there and wait for travis to build that > branch on all supported systems and tell you what the situation is. > It > saves me time, which I otherwise spend on applying, rejecting and > dropping of your patches after they fail to build. > > [1] https://travis-ci.org/marex/u-boot-socfpga/jobs/469629378#L1142 Ok. I only test the build for current (S10) target. Some of the code are not tested with other build target. I will setup the travis CI and test it on my side before submitting new patchsets. But 1 of the build error is due to your code base missing the following patch: http://u-boot.10912.n7.nabble.com/PATCH-v2-Add-generic-FPGA-reconfig-ma ilbox-API-for-S10-td343559.html#a343560 All current patch has dependency on the patch mentioned above. You will get build errors without this patch applied before current patchsets. > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] fdt: Add warning about CONFIG_OF_EMBED
Dear Simon and Simon, > Am 05.12.2018 um 14:57 schrieb Simon Glass: > > This option has crept into use with some boards. Add a warning to > > try to prevent this. > > > > As an example: > > https://lists.denx.de/pipermail/u-boot/2017-September/304966.html > > We have just discussed this in another thread. There seem to be ~109 > defconfigs in the tree that enable OF_EMBED. > > I doubt all of them do this for fun, so we might want to collect the > reasons they do so. I do know two: > > - socfpga_stratix10_defconfig needs this to get a correct > u-boot-spl.hex > - I would need it to ensure in SPL, the DTB is in one block with the > other readonly parts. Without OF_EMBED, we have '.text', '.bss', DT. Another use case is imx6: When I want to use SPL's embedded DTB for early init, with OF_SEPARATE I get fdt_blob = (ulong *)&__bss_end; ,which points me to 0x18200060, which is in DDR (and there is either garbage nor DDR is not initialized at all). The above looks like the __bss_end is for u-boot proper. The workaround (for now) is to have OF_EMBED, which assigns gd->fdt_blob = __dtb_dt_spl_begin [1], and this is a correct address. Hence, I'm wondering if shall I assign: gd->fdt_blob = __dtb_dt_spl_begin; in my early SPL code (and do not use fdt_setup() function at all in SPL) ? Moreover, defining board_fdt_blob_setup() for _each_ IMX6 board which would switch to DM_MMC in SPL seems like an no acceptable solution. [1] - ./spl/dts/dt-spl.dtb.S:3:.global __dtb_dt_spl_begin --> Looks like __dtb_dt_spl_begin is exactly for this purpose. > > Regards, > Simon > > > > > Signed-off-by: Simon Glass > > --- > > > > Makefile | 8 > > 1 file changed, 8 insertions(+) > > > > diff --git a/Makefile b/Makefile > > index 0d11ff97971..05896598fe3 100644 > > --- a/Makefile > > +++ b/Makefile > > @@ -947,6 +947,14 @@ ifeq > > ($(CONFIG_LIBATA)$(CONFIG_DM_SCSI)$(CONFIG_MVSATA_IDE),y) @echo > > "Failure to update by the deadline may result in board removal." > > @echo "See doc/driver-model/MIGRATION.txt for more info." @echo > > "" +endif > > +ifeq ($(CONFIG_OF_EMBED),y) > > + @echo "= WARNING > > ==" > > + @echo "CONFIG_OF_EMBED is enabled. This option should only" > > + @echo "be used for debugging purposes. Please use" > > + @echo "CONFIG_OF_SEPARATE for boards in mainline." > > + @echo "See doc/README.fdt-control for more info." > > + @echo > > "" endif > > @# Check that this build does not use CONFIG options that > > we do not @# know about unless they are in Kconfig. All the > > existing CONFIG > > ___ > U-Boot mailing list > U-Boot@lists.denx.de > https://lists.denx.de/listinfo/u-boot Best regards, Lukasz Majewski -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lu...@denx.de pgpdiAe2on9og.pgp Description: OpenPGP digital signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] fighting with unreliable designware-based 1G debug port
i've just been handed an issue regarding a modified version of
u-boot v2015.07 and an unreliable designware MAC i'm hoping someone
can give me some guidance on while i continue to dig through the code
and continue testing.
ARM-based target board has, among other things, an ethernet debug
port that is used for downloading and flashing firmware images while
in u-boot. problem is that, after coming up in u-boot, the debug port
is totally inoperative anywhere from 1/3 to 1/2 of the time
(reportedly no packet traffic at all). if one resets a few times,
eventually the port is operational. there is no apparent pattern, and
no predictable number of retries until the port works.
for the testers, i configured u-boot to include the mdio command to
let them poke around, then went to the DW data sheet, where i found
the following in the GMAC register map:
reg 48: 0x00C0AN Control Register
reg 49: 0x00C4AN Status Register
further down in the data sheet, a couple useful bits from the status
register:
5 ANC Auto-Negotiation Complete
2 LS Link Status
one of the testers, armed with this information and an ability to
poke around the registers, *assures* me that there is a direct
correlation between the debug port working, and those two bits from
the status register both being set to one. both one -- working. both
zero -- dead. given my assumption that those two bits simply display
the current situation (you can't just set them), this suggests that
*something* related to the dwmac is not being initialized properly
when u-boot comes up.
i can also see register:
reg 54: 0x00D8SGMII/RGMII/SMII Control and Status Register
but have yet to dig into that; that's today's project.
there is, AFAICT, a single line change to the v2015.07
designware.c file for this target board, down around line 267
(clearly modifying settings in the AN control register):
... snip ...
#ifdef CONFIG_DW_AXI_BURST_LEN
writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus);
#endif
* Enable Auto-Negotiation and External loopback (same way as
* linux driver does it) to get this driver to work.
*/
> writel(readl((u32)mac_p + 0xc0) | (1<<12) | (1<<14),
(u32)mac_p + 0xc0);
/* Start up the PHY */
ret = phy_startup(priv->phydev);
... snip ...
the line marked ">" is the line added to the source file. from
the data sheet, the two bits being set in the AN control register are:
14ELE loopback enable
12ANE auto-negotiation enable
despite the comment that that line is necessary to get the driver to
work, it is still unreliable as i've already described.
finally, the configuration for this board does *not* include
CONFIG_RESET_PHY_R, so there is no invocation of a board-specific
reset_phy() routine in common/board_r.c:
#ifdef CONFIG_CMD_NET
static int initr_net(void)
{
puts("Net: ");
eth_initialize();
#if defined(CONFIG_RESET_PHY_R)<=== NOT configured
debug("Reset Ethernet PHY\n");
reset_phy();
#endif
return 0;
}
#endif
which makes me wonder if there *should* be a reset_phy() routine
defined for this board (whatever it might need to do).
bottom line: has anyone else had this sort of maddeningly unreliable
behaviour with a designware MAC? have there been any bug fixes since
v2015.07 that might be applicable here? (i'm about to dig into the git
log to see what's happened since then.) does that single line change
to designware.c to set ELE and ANE in the AN control register look
familiar to anyone, as in, has anyone else needed to do something
similar?
totally open to advice here.
rday
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Re: [U-Boot] [PATCH v4 06/10] dm: usb: create a new UCLASS ID for USB gadget devices
On 18/12/2018 13:08, Jagan Teki wrote: On Thu, Nov 29, 2018 at 3:30 PM Jean-Jacques Hiblot wrote: UCLASS_USB_DEV_GENERIC was meant for USB devices connected to host controllers, not gadget devices. Adding a new UCLASS for gadget devices alone. Also move the generic DM code for USB gadgets in a separate file for clarity. Signed-off-by: Jean-Jacques Hiblot --- Changes in v4: None Changes in v3: None Changes in v2: None board/sunxi/board.c | 2 +- drivers/usb/dwc3/dwc3-generic.c | 2 +- drivers/usb/gadget/ether.c | 2 +- drivers/usb/gadget/udc/Makefile | 4 +++ drivers/usb/gadget/udc/udc-core.c | 41 -- drivers/usb/gadget/udc/udc-uclass.c | 58 + drivers/usb/musb-new/omap2430.c | 2 +- drivers/usb/musb-new/sunxi.c| 2 +- include/dm/uclass-id.h | 1 + 9 files changed, 68 insertions(+), 46 deletions(-) create mode 100644 drivers/usb/gadget/udc/udc-uclass.c diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 64ccbc7..9b36cc7 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -663,7 +663,7 @@ int g_dnl_board_usb_cable_connected(void) struct phy phy; int ret; - ret = uclass_get_device(UCLASS_USB_DEV_GENERIC, 0, &dev); + ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, &dev); This is breaking sunxi boards which uses gadget mode. U-Boot 2019.01-rc2 (Dec 18 2018 - 17:31:53 +0530) Allwinner Technology CPU: Allwinner H3 (SUN8I 1680) Model: Banana Pi BPI-M2-Plus DRAM: 1 GiB Error binding driver 'sunxi-musb': -96 Some drivers failed to bind Can you try with DM_USB_GADGET enabled ? JJ Error binding driver 'generic_simple_bus': -96 Some drivers failed to bind initcall sequence 7dfd127c failed at call 4a00c3a3 (err=-96) ### ERROR ### Please RESET the board ### ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 06/10] dm: usb: create a new UCLASS ID for USB gadget devices
On 19/12/2018 11:31, Jean-Jacques Hiblot wrote: On 18/12/2018 13:08, Jagan Teki wrote: On Thu, Nov 29, 2018 at 3:30 PM Jean-Jacques Hiblot wrote: UCLASS_USB_DEV_GENERIC was meant for USB devices connected to host controllers, not gadget devices. Adding a new UCLASS for gadget devices alone. Also move the generic DM code for USB gadgets in a separate file for clarity. Signed-off-by: Jean-Jacques Hiblot --- Changes in v4: None Changes in v3: None Changes in v2: None board/sunxi/board.c | 2 +- drivers/usb/dwc3/dwc3-generic.c | 2 +- drivers/usb/gadget/ether.c | 2 +- drivers/usb/gadget/udc/Makefile | 4 +++ drivers/usb/gadget/udc/udc-core.c | 41 -- drivers/usb/gadget/udc/udc-uclass.c | 58 + drivers/usb/musb-new/omap2430.c | 2 +- drivers/usb/musb-new/sunxi.c | 2 +- include/dm/uclass-id.h | 1 + 9 files changed, 68 insertions(+), 46 deletions(-) create mode 100644 drivers/usb/gadget/udc/udc-uclass.c diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 64ccbc7..9b36cc7 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -663,7 +663,7 @@ int g_dnl_board_usb_cable_connected(void) struct phy phy; int ret; - ret = uclass_get_device(UCLASS_USB_DEV_GENERIC, 0, &dev); + ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, &dev); This is breaking sunxi boards which uses gadget mode. U-Boot 2019.01-rc2 (Dec 18 2018 - 17:31:53 +0530) Allwinner Technology CPU: Allwinner H3 (SUN8I 1680) Model: Banana Pi BPI-M2-Plus DRAM: 1 GiB Error binding driver 'sunxi-musb': -96 Some drivers failed to bind Can you try with DM_USB_GADGET enabled ? The reasoning is that UCLASS_DRIVER(usb_gadget_generic) is defined if and only if DM_USB_GADGET is enabled. JJ Error binding driver 'generic_simple_bus': -96 Some drivers failed to bind initcall sequence 7dfd127c failed at call 4a00c3a3 (err=-96) ### ERROR ### Please RESET the board ### ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] USB: musb-new: omap2430: Add hooks for Peripheral support.
On 17/12/2018 21:34, Adam Ford wrote:
Borrowing from the updates to ti-musb.c, this glue layer checks
to see if the MUSB controller is gadget or host. Going under
the assumpution there is only one MUSB controller, this only builds
either the host probe or the gadget probe. OTG would be preferred,
but it doesn't appear to be working yet.
You can support both host and periph mode at the same time:
Create a new driver (a MISC UCLASS for ex) compatible with ti,omap3-musb.
Provide a bind function. In this function check the value of dr_mode and
bind the appropriate child driver (host or peripheral).
This is how it is done in ti-musb.c.
JJ
Signed-off-by: Adam Ford
diff --git a/drivers/usb/musb-new/omap2430.c b/drivers/usb/musb-new/omap2430.c
index b6e1320538..780d21c693 100644
--- a/drivers/usb/musb-new/omap2430.c
+++ b/drivers/usb/musb-new/omap2430.c
@@ -203,7 +203,7 @@ static int omap2430_musb_ofdata_to_platdata(struct udevice
*dev)
return 0;
}
-#ifdef CONFIG_USB_MUSB_HOST
+#ifndef CONFIG_USB_MUSB_GADGET
static int omap2430_musb_probe(struct udevice *dev)
{
struct musb_host_data *host = dev_get_priv(dev);
@@ -241,7 +241,7 @@ static int omap2430_musb_remove(struct udevice *dev)
#if CONFIG_IS_ENABLED(OF_CONTROL)
static int omap2430_musb_host_ofdata_to_platdata(struct udevice *dev)
{
- struct ti_musb_platdata *platdata = dev_get_platdata(dev);
+ struct omap2430_musb_platdata *platdata = dev_get_platdata(dev);
const void *fdt = gd->fdt_blob;
int node = dev_of_offset(dev);
int ret;
@@ -272,6 +272,83 @@ U_BOOT_DRIVER(omap2430_musb) = {
.priv_auto_alloc_size = sizeof(struct musb_host_data),
};
+#else
+
+struct omap2430_musb_peripheral {
+ struct musb *periph;
+};
+
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+static int omap2430_musb_peripheral_ofdata_to_platdata(struct udevice *dev)
+{
+ struct ti_musb_platdata *platdata = dev_get_platdata(dev);
+ const void *fdt = gd->fdt_blob;
+ int node = dev_of_offset(dev);
+ int ret;
+
+ ret = omap2430_musb_ofdata_to_platdata(dev);
+ if (ret) {
+ pr_err("platdata dt parse error\n");
+ return ret;
+ }
+ platdata->plat.mode = MUSB_PERIPHERAL;
+
+ return 0;
+}
+#endif
+
+int dm_usb_gadget_handle_interrupts(struct udevice *dev)
+{
+ struct omap2430_musb_peripheral *priv = dev_get_priv(dev);
+
+ priv->periph->isr(0, priv->periph);
+
+ return 0;
+}
+
+static int omap2430_musb_peripheral_probe(struct udevice *dev)
+{
+ struct omap2430_musb_peripheral *priv = dev_get_priv(dev);
+ struct omap2430_musb_platdata *platdata = dev_get_platdata(dev);
+ struct omap_musb_board_data *otg_board_data;
+ int ret;
+
+ otg_board_data = &platdata->otg_board_data;
+ priv->periph = musb_init_controller(&platdata->plat,
+ (struct device *)otg_board_data,
+ platdata->base);
+ if (!priv->periph)
+ return -EIO;
+
+ /* ti_musb_set_phy_power(dev, 1); */
+ musb_gadget_setup(priv->periph);
+ return usb_add_gadget_udc((struct device *)dev, &priv->periph->g);
+}
+
+static int omap2430_musb_peripheral_remove(struct udevice *dev)
+{
+ struct omap2430_musb_peripheral *priv = dev_get_priv(dev);
+
+ usb_del_gadget_udc(&priv->periph->g);
+ /* ti_musb_set_phy_power(dev, 0); */
+
+ return 0;
+}
+
+U_BOOT_DRIVER(omap2430_musb_peripheral) = {
+ .name = "ti-musb-peripheral",
+ .id = UCLASS_USB_GADGET_GENERIC,
+ .of_match = omap2430_musb_ids,
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+ .ofdata_to_platdata = omap2430_musb_peripheral_ofdata_to_platdata,
+#endif
+ .probe = omap2430_musb_peripheral_probe,
+ .remove = omap2430_musb_peripheral_remove,
+ .ops= &musb_usb_ops,
+ .platdata_auto_alloc_size = sizeof(struct omap2430_musb_platdata),
+ .priv_auto_alloc_size = sizeof(struct omap2430_musb_peripheral),
+ .flags = DM_FLAG_PRE_RELOC,
+};
#endif
#endif /* CONFIG_IS_ENABLED(DM_USB) */
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[U-Boot] [PATCH 8/9] clk: uniphier: add NAND 200MHz clock
The Denali NAND controller IP needs three clocks:
- clk: controller core clock
- clk_x: bus interface clock
- ecc_clk: clock at which ECC circuitry is run
Currently, only the first one (50MHz) is provided. The rest of the
two clock ports must be connected to the 200MHz clock line. Add this.
Signed-off-by: Masahiro Yamada
---
drivers/clk/uniphier/clk-uniphier-sys.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c
b/drivers/clk/uniphier/clk-uniphier-sys.c
index 9e087b6..487b43e 100644
--- a/drivers/clk/uniphier/clk-uniphier-sys.c
+++ b/drivers/clk/uniphier/clk-uniphier-sys.c
@@ -6,13 +6,12 @@
#include "clk-uniphier.h"
-/* Denali driver requires clk_x rate (clk: 50MHz, clk_x & ecc_clk: 200MHz) */
#define UNIPHIER_LD4_SYS_CLK_NAND(_id) \
- UNIPHIER_CLK_RATE(128, 2), \
+ UNIPHIER_CLK_RATE(128, 5000), \
UNIPHIER_CLK_GATE((_id), 128, 0x2104, 2)
#define UNIPHIER_LD11_SYS_CLK_NAND(_id)
\
- UNIPHIER_CLK_RATE(128, 2), \
+ UNIPHIER_CLK_RATE(128, 5000), \
UNIPHIER_CLK_GATE((_id), 128, 0x210c, 0)
const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = {
@@ -20,6 +19,7 @@ const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] =
{
defined(CONFIG_ARCH_UNIPHIER_PRO4) || defined(CONFIG_ARCH_UNIPHIER_PRO5)
||\
defined(CONFIG_ARCH_UNIPHIER_PXS2) || defined(CONFIG_ARCH_UNIPHIER_LD6B)
UNIPHIER_LD4_SYS_CLK_NAND(2),
+ UNIPHIER_CLK_RATE(3, 2),
UNIPHIER_CLK_GATE_SIMPLE(6, 0x2104, 12),/* ether (Pro4, PXs2) */
UNIPHIER_CLK_GATE_SIMPLE(7, 0x2104, 5), /* ether-gb (Pro4) */
UNIPHIER_CLK_GATE_SIMPLE(8, 0x2104, 10),/* stdmac */
@@ -36,6 +36,7 @@ const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] =
{
const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
#if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20)
UNIPHIER_LD11_SYS_CLK_NAND(2),
+ UNIPHIER_CLK_RATE(3, 2),
UNIPHIER_CLK_GATE_SIMPLE(6, 0x210c, 6), /* ether */
UNIPHIER_CLK_GATE_SIMPLE(8, 0x210c, 8), /* stdmac */
UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 14), /* usb30 (LD20) */
@@ -48,6 +49,7 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] =
{
const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = {
#if defined(CONFIG_ARCH_UNIPHIER_PXS3)
UNIPHIER_LD11_SYS_CLK_NAND(2),
+ UNIPHIER_CLK_RATE(3, 2),
UNIPHIER_CLK_GATE_SIMPLE(6, 0x210c, 9), /* ether0 */
UNIPHIER_CLK_GATE_SIMPLE(7, 0x210c, 10),/* ether1 */
UNIPHIER_CLK_GATE_SIMPLE(12, 0x210c, 4),/* usb30 (gio0) */
--
2.7.4
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[U-Boot] [PATCH 7/9] mtd: rawnand: denali: fix a race condition when DMA is kicked
Based on Linux commit cf51e4b9c34407bf0c3d9b582b7837e047e1df47 Add the register read-back, commenting why this is necessary. Signed-off-by: Masahiro Yamada --- drivers/mtd/nand/raw/denali.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/mtd/nand/raw/denali.c b/drivers/mtd/nand/raw/denali.c index bbfa3b6..e0eb133 100644 --- a/drivers/mtd/nand/raw/denali.c +++ b/drivers/mtd/nand/raw/denali.c @@ -587,6 +587,12 @@ static int denali_dma_xfer(struct denali_nand_info *denali, void *buf, } iowrite32(DMA_ENABLE__FLAG, denali->reg + DMA_ENABLE); + /* +* The ->setup_dma() hook kicks DMA by using the data/command +* interface, which belongs to a different AXI port from the +* register interface. Read back the register to avoid a race. +*/ + ioread32(denali->reg + DMA_ENABLE); denali_reset_irq(denali); denali->setup_dma(denali, dma_addr, page, write); -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 6/9] mtd: rawnand: denali: optimize timing parameters for data interface
Based on Linux commit 1dfac31a5a63ac04a9b5fbc3f5105a586560f191
This commit improves the ->setup_data_interface() hook.
The denali_setup_data_interface() needs the frequency of clk_x
and the ratio of clk_x / clk.
The latter is currently hardcoded in the driver, like this:
#define DENALI_CLK_X_MULT 6
The IP datasheet requires that clk_x / clk be 4, 5, or 6. I just
chose 6 because it is the most defensive value, but it is not optimal.
By getting the clock rate of both "clk" and "clk_x", the driver can
compute the timing values more precisely.
To not break the existing platforms, the fallback value, 50 MHz is
provided. It is true for all upstreamed platforms.
Signed-off-by: Masahiro Yamada
---
drivers/mtd/nand/raw/denali.c| 47
drivers/mtd/nand/raw/denali.h| 1 +
drivers/mtd/nand/raw/denali_dt.c | 2 ++
3 files changed, 26 insertions(+), 24 deletions(-)
diff --git a/drivers/mtd/nand/raw/denali.c b/drivers/mtd/nand/raw/denali.c
index d1cac06..bbfa3b6 100644
--- a/drivers/mtd/nand/raw/denali.c
+++ b/drivers/mtd/nand/raw/denali.c
@@ -69,14 +69,6 @@ static int dma_mapping_error(void *dev, dma_addr_t addr)
#define DENALI_INVALID_BANK-1
#define DENALI_NR_BANKS4
-/*
- * The bus interface clock, clk_x, is phase aligned with the core clock. The
- * clk_x is an integral multiple N of the core clk. The value N is configured
- * at IP delivery time, and its available value is 4, 5, or 6. We need to
align
- * to the largest value to make it work with any possible configuration.
- */
-#define DENALI_CLK_X_MULT 6
-
static inline struct denali_nand_info *mtd_to_denali(struct mtd_info *mtd)
{
return container_of(mtd_to_nand(mtd), struct denali_nand_info, nand);
@@ -946,7 +938,7 @@ static int denali_setup_data_interface(struct mtd_info
*mtd, int chipnr,
{
struct denali_nand_info *denali = mtd_to_denali(mtd);
const struct nand_sdr_timings *timings;
- unsigned long t_clk;
+ unsigned long t_x, mult_x;
int acc_clks, re_2_we, re_2_re, we_2_re, addr_2_data;
int rdwr_en_lo, rdwr_en_hi, rdwr_en_lo_hi, cs_setup;
int addr_2_data_mask;
@@ -957,15 +949,24 @@ static int denali_setup_data_interface(struct mtd_info
*mtd, int chipnr,
return PTR_ERR(timings);
/* clk_x period in picoseconds */
- t_clk = DIV_ROUND_DOWN_ULL(1ULL, denali->clk_x_rate);
- if (!t_clk)
+ t_x = DIV_ROUND_DOWN_ULL(1ULL, denali->clk_x_rate);
+ if (!t_x)
+ return -EINVAL;
+
+ /*
+* The bus interface clock, clk_x, is phase aligned with the core clock.
+* The clk_x is an integral multiple N of the core clk. The value N is
+* configured at IP delivery time, and its available value is 4, 5, 6.
+*/
+ mult_x = DIV_ROUND_CLOSEST_ULL(denali->clk_x_rate, denali->clk_rate);
+ if (mult_x < 4 || mult_x > 6)
return -EINVAL;
if (chipnr == NAND_DATA_IFACE_CHECK_ONLY)
return 0;
/* tREA -> ACC_CLKS */
- acc_clks = DIV_ROUND_UP(timings->tREA_max, t_clk);
+ acc_clks = DIV_ROUND_UP(timings->tREA_max, t_x);
acc_clks = min_t(int, acc_clks, ACC_CLKS__VALUE);
tmp = ioread32(denali->reg + ACC_CLKS);
@@ -974,7 +975,7 @@ static int denali_setup_data_interface(struct mtd_info
*mtd, int chipnr,
iowrite32(tmp, denali->reg + ACC_CLKS);
/* tRWH -> RE_2_WE */
- re_2_we = DIV_ROUND_UP(timings->tRHW_min, t_clk);
+ re_2_we = DIV_ROUND_UP(timings->tRHW_min, t_x);
re_2_we = min_t(int, re_2_we, RE_2_WE__VALUE);
tmp = ioread32(denali->reg + RE_2_WE);
@@ -983,7 +984,7 @@ static int denali_setup_data_interface(struct mtd_info
*mtd, int chipnr,
iowrite32(tmp, denali->reg + RE_2_WE);
/* tRHZ -> RE_2_RE */
- re_2_re = DIV_ROUND_UP(timings->tRHZ_max, t_clk);
+ re_2_re = DIV_ROUND_UP(timings->tRHZ_max, t_x);
re_2_re = min_t(int, re_2_re, RE_2_RE__VALUE);
tmp = ioread32(denali->reg + RE_2_RE);
@@ -997,8 +998,7 @@ static int denali_setup_data_interface(struct mtd_info
*mtd, int chipnr,
* With WE_2_RE properly set, the Denali controller automatically takes
* care of the delay; the driver need not set NAND_WAIT_TCCS.
*/
- we_2_re = DIV_ROUND_UP(max(timings->tCCS_min, timings->tWHR_min),
- t_clk);
+ we_2_re = DIV_ROUND_UP(max(timings->tCCS_min, timings->tWHR_min), t_x);
we_2_re = min_t(int, we_2_re, TWHR2_AND_WE_2_RE__WE_2_RE);
tmp = ioread32(denali->reg + TWHR2_AND_WE_2_RE);
@@ -1013,7 +1013,7 @@ static int denali_setup_data_interface(struct mtd_info
*mtd, int chipnr,
if (denali->revision < 0x0501)
addr_2_data_mask >>= 1;
- addr_2_data = DIV_ROUND_UP(timings->tADL_min, t_clk);
+ addr_2_data = DIV_ROUND_UP(timings->tADL_
[U-Boot] [PATCH 1/9] ARM: uniphier: do not modify bootcmd environment variable at run-time
Some users might want to modify 'bootcmd' at compile-time by editing
include/configs/uniphier.h, but overwriting it at run-time makes it
impossible.
Instead, set 'bootdev' at run-time, which contains the boot device the
system is booting from, then indirectly reference it from 'bootcmd'.
It is up to users whether to override 'bootcmd'.
Signed-off-by: Masahiro Yamada
---
arch/arm/mach-uniphier/board_late_init.c | 8
configs/uniphier_ld4_sld8_defconfig | 1 +
configs/uniphier_v7_defconfig| 1 +
configs/uniphier_v8_defconfig| 1 +
include/configs/uniphier.h | 4
5 files changed, 11 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-uniphier/board_late_init.c
b/arch/arm/mach-uniphier/board_late_init.c
index 1b871c6..972dbe8 100644
--- a/arch/arm/mach-uniphier/board_late_init.c
+++ b/arch/arm/mach-uniphier/board_late_init.c
@@ -66,20 +66,20 @@ int board_late_init(void)
switch (uniphier_boot_device_raw()) {
case BOOT_DEVICE_MMC1:
printf("eMMC Boot");
- env_set("bootcmd", "run bootcmd_mmc0; run distro_bootcmd");
+ env_set("bootdev", "emmc");
break;
case BOOT_DEVICE_NAND:
printf("NAND Boot");
- env_set("bootcmd", "run bootcmd_ubifs0; run distro_bootcmd");
+ env_set("bootdev", "nand");
nand_denali_wp_disable();
break;
case BOOT_DEVICE_NOR:
printf("NOR Boot");
- env_set("bootcmd", "run tftpboot; run distro_bootcmd");
+ env_set("bootdev", "nor");
break;
case BOOT_DEVICE_USB:
printf("USB Boot");
- env_set("bootcmd", "run bootcmd_usb0; run distro_bootcmd");
+ env_set("bootdev", "usb");
break;
default:
printf("Unknown");
diff --git a/configs/uniphier_ld4_sld8_defconfig
b/configs/uniphier_ld4_sld8_defconfig
index 6b9e22a..bede166 100644
--- a/configs/uniphier_ld4_sld8_defconfig
+++ b/configs/uniphier_ld4_sld8_defconfig
@@ -9,6 +9,7 @@ CONFIG_ARCH_UNIPHIER_LD4_SLD8=y
CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_NR_DRAM_BANKS=3
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_BOOTCOMMAND="run ${bootdev}boot"
CONFIG_LOGLEVEL=6
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_NOR_SUPPORT=y
diff --git a/configs/uniphier_v7_defconfig b/configs/uniphier_v7_defconfig
index 4c06f27..be4ab7c 100644
--- a/configs/uniphier_v7_defconfig
+++ b/configs/uniphier_v7_defconfig
@@ -8,6 +8,7 @@ CONFIG_SPL=y
CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_NR_DRAM_BANKS=3
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_BOOTCOMMAND="run ${bootdev}boot"
CONFIG_LOGLEVEL=6
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_NOR_SUPPORT=y
diff --git a/configs/uniphier_v8_defconfig b/configs/uniphier_v8_defconfig
index f8f9bdf..6f7c269 100644
--- a/configs/uniphier_v8_defconfig
+++ b/configs/uniphier_v8_defconfig
@@ -7,6 +7,7 @@ CONFIG_ARCH_UNIPHIER_V8_MULTI=y
CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_NR_DRAM_BANKS=3
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_BOOTCOMMAND="run ${bootdev}boot"
CONFIG_LOGLEVEL=6
CONFIG_CMD_CONFIG=y
CONFIG_CMD_IMLS=y
diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index 70f8712..7d14c31 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -171,6 +171,10 @@
"initrd_high=0x\0" \
"scriptaddr=0x8500\0" \
"nor_base=0x4200\0" \
+ "emmcboot=mmcsetn && run bootcmd_mmc${mmc_first_dev}\0" \
+ "nandboot=run bootcmd_ubifs0\0" \
+ "norboot=run tftpboot\0" \
+ "usbboot=run bootcmd_usb0\0" \
"sramupdate=setexpr tmp_addr $nor_base + 0x5 &&"\
"tftpboot $tmp_addr $second_image && " \
"setexpr tmp_addr $nor_base + 0x7 && " \
--
2.7.4
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[U-Boot] [PATCH 5/9] mtd: rawnand: denali_dt: add more clocks based on IP datasheet
Based on Linux commit 6f1fe97bec349a1fd6c5a8c7c5998d759fe721d5
Currently, denali_dt.c requires a single anonymous clock, but
the Denali User's Guide requires three clocks for this IP:
- clk: controller core clock
- clk_x: bus interface clock
- ecc_clk: clock at which ECC circuitry is run
This commit supports these named clocks to represent the real hardware.
For the backward compatibility, the driver still accepts a single clock
just as before. The clk_x_rate is taken from the clock driver again if
the named clock "clk_x" is available. This will happen only for future
DT, hence the existing DT files are not affected.
Signed-off-by: Masahiro Yamada
---
drivers/mtd/nand/raw/denali_dt.c | 38 +++---
1 file changed, 35 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/nand/raw/denali_dt.c b/drivers/mtd/nand/raw/denali_dt.c
index 65a7797..f9eadb4 100644
--- a/drivers/mtd/nand/raw/denali_dt.c
+++ b/drivers/mtd/nand/raw/denali_dt.c
@@ -62,7 +62,7 @@ static int denali_dt_probe(struct udevice *dev)
{
struct denali_nand_info *denali = dev_get_priv(dev);
const struct denali_dt_data *data;
- struct clk clk;
+ struct clk clk, clk_x, clk_ecc;
struct resource res;
int ret;
@@ -87,15 +87,47 @@ static int denali_dt_probe(struct udevice *dev)
denali->host = devm_ioremap(dev, res.start, resource_size(&res));
- ret = clk_get_by_index(dev, 0, &clk);
+ ret = clk_get_by_name(dev, "nand", &clk);
+ if (ret)
+ ret = clk_get_by_index(dev, 0, &clk);
if (ret)
return ret;
+ ret = clk_get_by_name(dev, "nand_x", &clk_x);
+ if (ret)
+ clk_x.dev = NULL;
+
+ ret = clk_get_by_name(dev, "ecc", &clk_ecc);
+ if (ret)
+ clk_ecc.dev = NULL;
+
ret = clk_enable(&clk);
if (ret)
return ret;
- denali->clk_x_rate = clk_get_rate(&clk);
+ if (clk_x.dev) {
+ ret = clk_enable(&clk_x);
+ if (ret)
+ return ret;
+ }
+
+ if (clk_ecc.dev) {
+ ret = clk_enable(&clk_ecc);
+ if (ret)
+ return ret;
+ }
+
+ if (clk_x.dev) {
+ denali->clk_x_rate = clk_get_rate(&clk_x);
+ } else {
+ /*
+* Hardcode the clock rates for the backward compatibility.
+* This works for both SOCFPGA and UniPhier.
+*/
+ dev_notice(dev,
+ "necessary clock is missing. default clock rates are
used.\n");
+ denali->clk_x_rate = 2;
+ }
return denali_init(denali);
}
--
2.7.4
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[U-Boot] [PATCH 4/9] linux/kernel.h: import DIV_ROUND_CLOSEST_ULL from Linux
Copied from Linux v4.20-rc7.
Signed-off-by: Masahiro Yamada
---
include/linux/kernel.h | 12
1 file changed, 12 insertions(+)
diff --git a/include/linux/kernel.h b/include/linux/kernel.h
index bd88483..a85c15d 100644
--- a/include/linux/kernel.h
+++ b/include/linux/kernel.h
@@ -102,6 +102,18 @@
(((__x) - ((__d) / 2)) / (__d));\
} \
)
+/*
+ * Same as above but for u64 dividends. divisor must be a 32-bit
+ * number.
+ */
+#define DIV_ROUND_CLOSEST_ULL(x, divisor)( \
+{ \
+ typeof(divisor) __d = divisor; \
+ unsigned long long _tmp = (x) + (__d) / 2; \
+ do_div(_tmp, __d); \
+ _tmp; \
+} \
+)
/*
* Multiplies an integer by a fraction, while avoiding unnecessary
--
2.7.4
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[U-Boot] [PATCH 3/9] ARM: uniphier: add CONFIG_PREBOOT
For more boot-flow flexibility,
Signed-off-by: Masahiro Yamada
---
include/configs/uniphier.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index 1e509ce..95d6452 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -124,6 +124,8 @@
"third_image=u-boot.bin\0"
#endif
+#define CONFIG_PREBOOT "env exist ${bootdev}preboot && run
${bootdev}preboot"
+
#define CONFIG_ROOTPATH"/nfs/root/path"
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs $bootargs root=/dev/nfs rw " \
--
2.7.4
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[U-Boot] [PATCH 0/9] ARM: dts: uniphier: updates for v2019.01
Masahiro Yamada (9): ARM: uniphier: do not modify bootcmd environment variable at run-time ARM: uniphier: allow to source boot script before distro-boot ARM: uniphier: add CONFIG_PREBOOT linux/kernel.h: import DIV_ROUND_CLOSEST_ULL from Linux mtd: rawnand: denali_dt: add more clocks based on IP datasheet mtd: rawnand: denali: optimize timing parameters for data interface mtd: rawnand: denali: fix a race condition when DMA is kicked clk: uniphier: add NAND 200MHz clock ARM: uniphier: dts: sync with Linux 4.20-rc7 arch/arm/dts/uniphier-ld11.dtsi | 52 +- arch/arm/dts/uniphier-ld20-global.dts| 4 + arch/arm/dts/uniphier-ld20-ref.dts | 4 + arch/arm/dts/uniphier-ld20.dtsi | 242 +++- arch/arm/dts/uniphier-ld4.dtsi | 14 +- arch/arm/dts/uniphier-pinctrl.dtsi | 20 +++ arch/arm/dts/uniphier-pro4-ace.dts | 8 +- arch/arm/dts/uniphier-pro4-sanji.dts | 8 +- arch/arm/dts/uniphier-pro4.dtsi | 143 - arch/arm/dts/uniphier-pro5.dtsi | 25 ++- arch/arm/dts/uniphier-pxs2.dtsi | 207 +++- arch/arm/dts/uniphier-pxs3.dtsi | 267 ++- arch/arm/dts/uniphier-sld8.dtsi | 14 +- arch/arm/mach-uniphier/board_late_init.c | 8 +- configs/uniphier_ld4_sld8_defconfig | 1 + configs/uniphier_v7_defconfig| 1 + configs/uniphier_v8_defconfig| 1 + drivers/clk/uniphier/clk-uniphier-sys.c | 8 +- drivers/mtd/nand/raw/denali.c| 53 +++--- drivers/mtd/nand/raw/denali.h| 1 + drivers/mtd/nand/raw/denali_dt.c | 40 - include/configs/uniphier.h | 26 +++ include/linux/kernel.h | 12 ++ 23 files changed, 1109 insertions(+), 50 deletions(-) -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 9/9] ARM: uniphier: dts: sync with Linux 4.20-rc7
Currently, the DWC3 USB node is out of sync because the bindings
for the UniPhier DWC3 PHY diverged between Linux and U-Boot.
Signed-off-by: Masahiro Yamada
---
arch/arm/dts/uniphier-ld11.dtsi | 52 ++-
arch/arm/dts/uniphier-ld20-global.dts | 4 +
arch/arm/dts/uniphier-ld20-ref.dts| 4 +
arch/arm/dts/uniphier-ld20.dtsi | 242 +-
arch/arm/dts/uniphier-ld4.dtsi| 14 +-
arch/arm/dts/uniphier-pinctrl.dtsi| 20 +++
arch/arm/dts/uniphier-pro4-ace.dts| 8 +-
arch/arm/dts/uniphier-pro4-sanji.dts | 8 +-
arch/arm/dts/uniphier-pro4.dtsi | 143 +-
arch/arm/dts/uniphier-pro5.dtsi | 25 +++-
arch/arm/dts/uniphier-pxs2.dtsi | 207 +-
arch/arm/dts/uniphier-pxs3.dtsi | 267 +-
arch/arm/dts/uniphier-sld8.dtsi | 14 +-
13 files changed, 992 insertions(+), 16 deletions(-)
diff --git a/arch/arm/dts/uniphier-ld11.dtsi b/arch/arm/dts/uniphier-ld11.dtsi
index d63b56e..31ba52b 100644
--- a/arch/arm/dts/uniphier-ld11.dtsi
+++ b/arch/arm/dts/uniphier-ld11.dtsi
@@ -116,6 +116,28 @@
#size-cells = <1>;
ranges = <0 0 0 0x>;
+ spi0: spi@54006000 {
+ compatible = "socionext,uniphier-scssi";
+ status = "disabled";
+ reg = <0x54006000 0x100>;
+ interrupts = <0 39 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi0>;
+ clocks = <&peri_clk 11>;
+ resets = <&peri_rst 11>;
+ };
+
+ spi1: spi@54006100 {
+ compatible = "socionext,uniphier-scssi";
+ status = "disabled";
+ reg = <0x54006100 0x100>;
+ interrupts = <0 216 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1>;
+ clocks = <&peri_clk 11>;
+ resets = <&peri_rst 11>;
+ };
+
serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
status = "disabled";
@@ -432,6 +454,8 @@
<&mio_clk 12>;
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
<&mio_rst 12>;
+ phy-names = "usb";
+ phys = <&usb_phy0>;
has-transaction-translator;
};
@@ -446,6 +470,8 @@
<&mio_clk 13>;
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
<&mio_rst 13>;
+ phy-names = "usb";
+ phys = <&usb_phy1>;
has-transaction-translator;
};
@@ -460,6 +486,8 @@
<&mio_clk 14>;
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
<&mio_rst 14>;
+ phy-names = "usb";
+ phys = <&usb_phy2>;
has-transaction-translator;
};
@@ -488,6 +516,27 @@
pinctrl: pinctrl {
compatible = "socionext,uniphier-ld11-pinctrl";
};
+
+ usb-phy {
+ compatible = "socionext,uniphier-ld11-usb2-phy";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb_phy0: phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ usb_phy1: phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+
+ usb_phy2: phy@2 {
+ reg = <2>;
+ #phy-cells = <0>;
+ };
+ };
};
soc-glue@5f90 {
@@ -571,7 +620,8 @@
interrupts = <0 65 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
- clocks = <&sys_clk 2>;
+ clock-names = "nand", "nand_x", "ecc";
+ clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
resets = <&sys_rst 2>;
};
};
diff --git a/arch/arm/dts/uniphier-ld20-global.dts
b/arch/arm/dts/uniphier-ld20-global.dts
index 1a5e7c2..9ca692e 100644
-
[U-Boot] [PATCH 2/9] ARM: uniphier: allow to source boot script before distro-boot
Some users might need additional setups before booting the kernel.
If there is found a file 'boot.scr', run it before invoking the
distro boot command.
Signed-off-by: Masahiro Yamada
---
configs/uniphier_ld4_sld8_defconfig | 2 +-
configs/uniphier_v7_defconfig | 2 +-
configs/uniphier_v8_defconfig | 2 +-
include/configs/uniphier.h | 20
4 files changed, 23 insertions(+), 3 deletions(-)
diff --git a/configs/uniphier_ld4_sld8_defconfig
b/configs/uniphier_ld4_sld8_defconfig
index bede166..98a0017 100644
--- a/configs/uniphier_ld4_sld8_defconfig
+++ b/configs/uniphier_ld4_sld8_defconfig
@@ -9,7 +9,7 @@ CONFIG_ARCH_UNIPHIER_LD4_SLD8=y
CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_NR_DRAM_BANKS=3
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
-CONFIG_BOOTCOMMAND="run ${bootdev}boot"
+CONFIG_BOOTCOMMAND="run ${bootdev}script; run ${bootdev}boot"
CONFIG_LOGLEVEL=6
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_NOR_SUPPORT=y
diff --git a/configs/uniphier_v7_defconfig b/configs/uniphier_v7_defconfig
index be4ab7c..bba8e18 100644
--- a/configs/uniphier_v7_defconfig
+++ b/configs/uniphier_v7_defconfig
@@ -8,7 +8,7 @@ CONFIG_SPL=y
CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_NR_DRAM_BANKS=3
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
-CONFIG_BOOTCOMMAND="run ${bootdev}boot"
+CONFIG_BOOTCOMMAND="run ${bootdev}script; run ${bootdev}boot"
CONFIG_LOGLEVEL=6
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_NOR_SUPPORT=y
diff --git a/configs/uniphier_v8_defconfig b/configs/uniphier_v8_defconfig
index 6f7c269..df6c511 100644
--- a/configs/uniphier_v8_defconfig
+++ b/configs/uniphier_v8_defconfig
@@ -7,7 +7,7 @@ CONFIG_ARCH_UNIPHIER_V8_MULTI=y
CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_NR_DRAM_BANKS=3
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
-CONFIG_BOOTCOMMAND="run ${bootdev}boot"
+CONFIG_BOOTCOMMAND="run ${bootdev}script; run ${bootdev}boot"
CONFIG_LOGLEVEL=6
CONFIG_CMD_CONFIG=y
CONFIG_CMD_IMLS=y
diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index 7d14c31..1e509ce 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -169,12 +169,32 @@
#defineCONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"initrd_high=0x\0" \
+ "script=boot.scr\0" \
"scriptaddr=0x8500\0" \
"nor_base=0x4200\0" \
"emmcboot=mmcsetn && run bootcmd_mmc${mmc_first_dev}\0" \
"nandboot=run bootcmd_ubifs0\0" \
"norboot=run tftpboot\0" \
"usbboot=run bootcmd_usb0\0" \
+ "emmcscript=setenv devtype mmc && " \
+ "mmcsetn && " \
+ "setenv devnum ${mmc_first_dev} && " \
+ "run loadscript_fat\0" \
+ "nandscript=echo Running ${script} from ubi ... && " \
+ "ubi part UBI && " \
+ "ubifsmount ubi0:boot && " \
+ "ubifsload ${loadaddr} ${script} && " \
+ "source\0" \
+ "norscript=echo Running ${script} from tftp ... && " \
+ "tftpboot ${script} &&" \
+ "source\0" \
+ "usbscript=usb start && " \
+ "setenv devtype usb && " \
+ "setenv devnum 0 && " \
+ "run loadscript_fat\0" \
+ "loadscript_fat=echo Running ${script} from ${devtype}${devnum} ... &&
" \
+ "load ${devtype} ${devnum}:1 ${loadaddr} ${script} && " \
+ "source\0" \
"sramupdate=setexpr tmp_addr $nor_base + 0x5 &&"\
"tftpboot $tmp_addr $second_image && " \
"setexpr tmp_addr $nor_base + 0x7 && " \
--
2.7.4
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v6 4/4] arm: socfpga: stratix10: Enable Stratix10 FPGA Reconfiguration
On 12/19/2018 10:48 AM, Ang, Chee Hong wrote: > On Wed, 2018-12-19 at 09:41 +0100, Marek Vasut wrote: >> On 12/19/2018 05:55 AM, Ang, Chee Hong wrote: >>> >>> On Tue, 2018-12-18 at 18:47 +0100, Marek Vasut wrote: On 12/18/2018 09:54 AM, chee.hong@intel.com wrote: > > > From: "Ang, Chee Hong" > > Enable Stratix10 FPGA reconfiguration support in defconfig. > > Signed-off-by: Ang, Chee Hong > --- > configs/socfpga_stratix10_defconfig | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/configs/socfpga_stratix10_defconfig > b/configs/socfpga_stratix10_defconfig > index 5f3d733..155c406 100644 > --- a/configs/socfpga_stratix10_defconfig > +++ b/configs/socfpga_stratix10_defconfig > @@ -10,6 +10,7 @@ CONFIG_NR_DRAM_BANKS=1 > CONFIG_BOOTDELAY=5 > CONFIG_SPL_SPI_LOAD=y > CONFIG_HUSH_PARSER=y > +CONFIG_FPGA_STRATIX10=y > CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # " > CONFIG_CMD_MEMTEST=y > # CONFIG_CMD_FLASH is not set > Can you send a subsequent patch which uses Kconfig imply to select FPGA_STRATIX10 on S10 instead of adding it in defconfig ? >>> Noted. Will address this in next patchsets. >> I asked you for an incremental patch, not for reposting the whole >> patchset (also, please track changelog with new versions of patches). >> >> But travis would seem to indicate, again, that the patches break some >> other target [1]. Can you please at least build test the next version >> of >> patches on all systems before posting them ? >> >> You can very well just set up the travis CI with your github >> repo/fork >> of u-boot repo, push a branch there and wait for travis to build that >> branch on all supported systems and tell you what the situation is. >> It >> saves me time, which I otherwise spend on applying, rejecting and >> dropping of your patches after they fail to build. >> >> [1] https://travis-ci.org/marex/u-boot-socfpga/jobs/469629378#L1142 > > Ok. I only test the build for current (S10) target. Some of the code > are not tested with other build target. I will setup the travis CI and > test it on my side before submitting new patchsets. > But 1 of the build error is due to your code base missing the following > patch: > http://u-boot.10912.n7.nabble.com/PATCH-v2-Add-generic-FPGA-reconfig-ma > ilbox-API-for-S10-td343559.html#a343560 > All current patch has dependency on the patch mentioned above. > You will get build errors without this patch applied before current > patchsets. Then please submit the complete series, the dependency is not mentioned anywhere. And yes, please do keep testing. -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] i2c: xiic: Add Xilinx AXI I2C driver
Hello Marek,
Am 19.12.2018 um 09:07 schrieb Marek Vasut:
Add Xilinx AXI I2C controller driver based on the Linux i2c-xiic driver.
This driver is stripped of all the IRQ handling and uses pure polling,
yet tries to retain most of the structure of the Linux driver to make
backporting of fixes easy.
Note that the IP has a known limitation on 255 bytes read and write,
according to xilinx this is still being worked on [1].
[1]
https://forums.xilinx.com/t5/Embedded-Processor-System-Design/AXI-IIC-V2-0-I2C-Master-Reading-multiple-bytes-from-I2C-slave/m-p/854419/highlight/true#M39387
Signed-off-by: Marek Vasut
Cc: Michal Simek
Cc: Michal Simek
Cc: Heiko Schocher
---
drivers/i2c/Kconfig | 6 +
drivers/i2c/Makefile | 1 +
drivers/i2c/xilinx_xiic.c | 340 ++
3 files changed, 347 insertions(+)
create mode 100644 drivers/i2c/xilinx_xiic.c
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 5eceab9ea8..810d861f32 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -437,6 +437,12 @@ config SYS_I2C_BUS_MAX
help
Define the maximum number of available I2C buses.
+config SYS_I2C_XILINX_XIIC
+ bool "Xilinx AXI I2C driver"
+depends on DM_I2C
seems some formating problem ...
+ help
+ Support for Xilinx AXI I2C controller.
+
config SYS_I2C_ZYNQ
bool "Xilinx I2C driver"
depends on ARCH_ZYNQMP || ARCH_ZYNQ
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index da368cc02a..94c68c8ba1 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -38,6 +38,7 @@ obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o
obj-$(CONFIG_SYS_I2C_UNIPHIER) += i2c-uniphier.o
obj-$(CONFIG_SYS_I2C_UNIPHIER_F) += i2c-uniphier-f.o
obj-$(CONFIG_SYS_I2C_ZYNQ) += zynq_i2c.o
+obj-$(CONFIG_SYS_I2C_XILINX_XIIC) += xilinx_xiic.o
please sort in alphabetical order.
obj-$(CONFIG_TEGRA186_BPMP_I2C) += tegra186_bpmp_i2c.o
obj-$(CONFIG_I2C_MUX) += muxes/
diff --git a/drivers/i2c/xilinx_xiic.c b/drivers/i2c/xilinx_xiic.c
new file mode 100644
index 00..180cd14fec
--- /dev/null
+++ b/drivers/i2c/xilinx_xiic.c
@@ -0,0 +1,340 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx AXI I2C driver
+ *
+ * Copyright (C) 2018 Marek Vasut
+ *
+ * Based on Linux 4.14.y i2c-xiic.c
+ * Copyright (c) 2002-2007 Xilinx Inc.
+ * Copyright (c) 2009-2010 Intel Corporation
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct xilinx_xiic_priv {
+ void __iomem*base;
+ struct clk clk;
+};
+
+#define XIIC_MSB_OFFSET 0
+#define XIIC_REG_OFFSET (0x100+XIIC_MSB_OFFSET)
+
+/*
+ * Register offsets in bytes from RegisterBase. Three is added to the
+ * base offset to access LSB (IBM style) of the word
+ */
+#define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET)/* Control Register */
+#define XIIC_SR_REG_OFFSET (0x04+XIIC_REG_OFFSET)/* Status Register*/
+#define XIIC_DTR_REG_OFFSET (0x08+XIIC_REG_OFFSET)/* Data Tx Register */
+#define XIIC_DRR_REG_OFFSET (0x0C+XIIC_REG_OFFSET)/* Data Rx Register */
+#define XIIC_ADR_REG_OFFSET (0x10+XIIC_REG_OFFSET)/* Address Register */
+#define XIIC_TFO_REG_OFFSET (0x14+XIIC_REG_OFFSET)/* Tx FIFO Occupancy */
+#define XIIC_RFO_REG_OFFSET (0x18+XIIC_REG_OFFSET)/* Rx FIFO Occupancy */
+#define XIIC_TBA_REG_OFFSET (0x1C+XIIC_REG_OFFSET)/* 10 Bit Address reg */
+#define XIIC_RFD_REG_OFFSET (0x20+XIIC_REG_OFFSET)/* Rx FIFO Depth reg */
+#define XIIC_GPO_REG_OFFSET (0x24+XIIC_REG_OFFSET)/* Output Register*/
A struct would be much more nicer, but as you said it is taken from
linux code ... I am fine with it.
+
+/* Control Register masks */
+#define XIIC_CR_ENABLE_DEVICE_MASK0x01 /* Device enable = 1 */
+#define XIIC_CR_TX_FIFO_RESET_MASK0x02 /* Transmit FIFO reset=1 */
+#define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */
+#define XIIC_CR_DIR_IS_TX_MASK0x08 /* Dir of tx. Txing=1 */
+#define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */
+#define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */
+#define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */
+
+/* Status Register masks */
+#define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */
+#define XIIC_SR_ADDR_AS_SLAVE_MASK0x02 /* 1=when addr as slave */
+#define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy*/
+#define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */
+#define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */
+#define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */
+#define XIIC_SR_RX_FIFO_EMPTY_MASK0x40 /* 1 = Rx FIFO empty */
+#define XIIC_SR_TX_FIFO_EMPTY_MASK0x80 /* 1 = Tx FIFO empty */
+
+/* Interrupt Status Register masksInter
[U-Boot] [PATCH V2] i2c: xiic: Add Xilinx AXI I2C driver
Add Xilinx AXI I2C controller driver based on the Linux i2c-xiic driver.
This driver is stripped of all the IRQ handling and uses pure polling,
yet tries to retain most of the structure of the Linux driver to make
backporting of fixes easy.
Note that the IP has a known limitation on 255 bytes read and write,
according to xilinx this is still being worked on [1].
[1]
https://forums.xilinx.com/t5/Embedded-Processor-System-Design/AXI-IIC-V2-0-I2C-Master-Reading-multiple-bytes-from-I2C-slave/m-p/854419/highlight/true#M39387
Signed-off-by: Marek Vasut
Cc: Michal Simek
Cc: Michal Simek
Cc: Heiko Schocher
---
V2: - Sort Makefile
- Fix formatting in Kconfig
---
drivers/i2c/Kconfig | 6 +
drivers/i2c/Makefile | 1 +
drivers/i2c/xilinx_xiic.c | 340 ++
3 files changed, 347 insertions(+)
create mode 100644 drivers/i2c/xilinx_xiic.c
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 1ef22e6bcd..536617115a 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -450,6 +450,12 @@ config SYS_I2C_BUS_MAX
help
Define the maximum number of available I2C buses.
+config SYS_I2C_XILINX_XIIC
+ bool "Xilinx AXI I2C driver"
+ depends on DM_I2C
+ help
+ Support for Xilinx AXI I2C controller.
+
config SYS_I2C_ZYNQ
bool "Xilinx I2C driver"
depends on ARCH_ZYNQMP || ARCH_ZYNQ
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index d3637bcd8d..ec2d1964c3 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o
obj-$(CONFIG_SYS_I2C_UNIPHIER) += i2c-uniphier.o
obj-$(CONFIG_SYS_I2C_UNIPHIER_F) += i2c-uniphier-f.o
obj-$(CONFIG_SYS_I2C_VERSATILE) += i2c-versatile.o
+obj-$(CONFIG_SYS_I2C_XILINX_XIIC) += xilinx_xiic.o
obj-$(CONFIG_SYS_I2C_ZYNQ) += zynq_i2c.o
obj-$(CONFIG_TEGRA186_BPMP_I2C) += tegra186_bpmp_i2c.o
diff --git a/drivers/i2c/xilinx_xiic.c b/drivers/i2c/xilinx_xiic.c
new file mode 100644
index 00..83114ed510
--- /dev/null
+++ b/drivers/i2c/xilinx_xiic.c
@@ -0,0 +1,340 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx AXI I2C driver
+ *
+ * Copyright (C) 2018 Marek Vasut
+ *
+ * Based on Linux 4.14.y i2c-xiic.c
+ * Copyright (c) 2002-2007 Xilinx Inc.
+ * Copyright (c) 2009-2010 Intel Corporation
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct xilinx_xiic_priv {
+ void __iomem*base;
+ struct clk clk;
+};
+
+#define XIIC_MSB_OFFSET 0
+#define XIIC_REG_OFFSET (0x100+XIIC_MSB_OFFSET)
+
+/*
+ * Register offsets in bytes from RegisterBase. Three is added to the
+ * base offset to access LSB (IBM style) of the word
+ */
+#define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET)/* Control Register */
+#define XIIC_SR_REG_OFFSET (0x04+XIIC_REG_OFFSET)/* Status Register*/
+#define XIIC_DTR_REG_OFFSET (0x08+XIIC_REG_OFFSET)/* Data Tx Register */
+#define XIIC_DRR_REG_OFFSET (0x0C+XIIC_REG_OFFSET)/* Data Rx Register */
+#define XIIC_ADR_REG_OFFSET (0x10+XIIC_REG_OFFSET)/* Address Register */
+#define XIIC_TFO_REG_OFFSET (0x14+XIIC_REG_OFFSET)/* Tx FIFO Occupancy */
+#define XIIC_RFO_REG_OFFSET (0x18+XIIC_REG_OFFSET)/* Rx FIFO Occupancy */
+#define XIIC_TBA_REG_OFFSET (0x1C+XIIC_REG_OFFSET)/* 10 Bit Address reg */
+#define XIIC_RFD_REG_OFFSET (0x20+XIIC_REG_OFFSET)/* Rx FIFO Depth reg */
+#define XIIC_GPO_REG_OFFSET (0x24+XIIC_REG_OFFSET)/* Output Register*/
+
+/* Control Register masks */
+#define XIIC_CR_ENABLE_DEVICE_MASK0x01 /* Device enable = 1 */
+#define XIIC_CR_TX_FIFO_RESET_MASK0x02 /* Transmit FIFO reset=1 */
+#define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */
+#define XIIC_CR_DIR_IS_TX_MASK0x08 /* Dir of tx. Txing=1 */
+#define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */
+#define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */
+#define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */
+
+/* Status Register masks */
+#define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */
+#define XIIC_SR_ADDR_AS_SLAVE_MASK0x02 /* 1=when addr as slave */
+#define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy*/
+#define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */
+#define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */
+#define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */
+#define XIIC_SR_RX_FIFO_EMPTY_MASK0x40 /* 1 = Rx FIFO empty */
+#define XIIC_SR_TX_FIFO_EMPTY_MASK0x80 /* 1 = Tx FIFO empty */
+
+/* Interrupt Status Register masksInterrupt occurs when... */
+#define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */
+#define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete */
Re: [U-Boot] [PATCH] i2c: xiic: Add Xilinx AXI I2C driver
On 12/19/2018 12:15 PM, Heiko Schocher wrote:
> Hello Marek,
Hi,
> Am 19.12.2018 um 09:07 schrieb Marek Vasut:
>> Add Xilinx AXI I2C controller driver based on the Linux i2c-xiic driver.
>> This driver is stripped of all the IRQ handling and uses pure polling,
>> yet tries to retain most of the structure of the Linux driver to make
>> backporting of fixes easy.
>>
>> Note that the IP has a known limitation on 255 bytes read and write,
>> according to xilinx this is still being worked on [1].
>>
>> [1]
>> https://forums.xilinx.com/t5/Embedded-Processor-System-Design/AXI-IIC-V2-0-I2C-Master-Reading-multiple-bytes-from-I2C-slave/m-p/854419/highlight/true#M39387
>>
>>
>> Signed-off-by: Marek Vasut
>> Cc: Michal Simek
>> Cc: Michal Simek
>> Cc: Heiko Schocher
>> ---
>> drivers/i2c/Kconfig | 6 +
>> drivers/i2c/Makefile | 1 +
>> drivers/i2c/xilinx_xiic.c | 340 ++
>> 3 files changed, 347 insertions(+)
>> create mode 100644 drivers/i2c/xilinx_xiic.c
>>
>> diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
>> index 5eceab9ea8..810d861f32 100644
>> --- a/drivers/i2c/Kconfig
>> +++ b/drivers/i2c/Kconfig
>> @@ -437,6 +437,12 @@ config SYS_I2C_BUS_MAX
>> help
>> Define the maximum number of available I2C buses.
>> +config SYS_I2C_XILINX_XIIC
>> + bool "Xilinx AXI I2C driver"
>> + depends on DM_I2C
>
> seems some formating problem ...
Fixed
>> + help
>> + Support for Xilinx AXI I2C controller.
>> +
>> config SYS_I2C_ZYNQ
>> bool "Xilinx I2C driver"
>> depends on ARCH_ZYNQMP || ARCH_ZYNQ
>> diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
>> index da368cc02a..94c68c8ba1 100644
>> --- a/drivers/i2c/Makefile
>> +++ b/drivers/i2c/Makefile
>> @@ -38,6 +38,7 @@ obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o
>> obj-$(CONFIG_SYS_I2C_UNIPHIER) += i2c-uniphier.o
>> obj-$(CONFIG_SYS_I2C_UNIPHIER_F) += i2c-uniphier-f.o
>> obj-$(CONFIG_SYS_I2C_ZYNQ) += zynq_i2c.o
>> +obj-$(CONFIG_SYS_I2C_XILINX_XIIC) += xilinx_xiic.o
>
> please sort in alphabetical order.
Fixed
>> obj-$(CONFIG_TEGRA186_BPMP_I2C) += tegra186_bpmp_i2c.o
>> obj-$(CONFIG_I2C_MUX) += muxes/
>> diff --git a/drivers/i2c/xilinx_xiic.c b/drivers/i2c/xilinx_xiic.c
>> new file mode 100644
>> index 00..180cd14fec
>> --- /dev/null
>> +++ b/drivers/i2c/xilinx_xiic.c
>> @@ -0,0 +1,340 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Xilinx AXI I2C driver
>> + *
>> + * Copyright (C) 2018 Marek Vasut
>> + *
>> + * Based on Linux 4.14.y i2c-xiic.c
>> + * Copyright (c) 2002-2007 Xilinx Inc.
>> + * Copyright (c) 2009-2010 Intel Corporation
>> + */
>> +
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +
>> +struct xilinx_xiic_priv {
>> + void __iomem *base;
>> + struct clk clk;
>> +};
>> +
>> +#define XIIC_MSB_OFFSET 0
>> +#define XIIC_REG_OFFSET (0x100+XIIC_MSB_OFFSET)
>> +
>> +/*
>> + * Register offsets in bytes from RegisterBase. Three is added to the
>> + * base offset to access LSB (IBM style) of the word
>> + */
>> +#define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control
>> Register */
>> +#define XIIC_SR_REG_OFFSET (0x04+XIIC_REG_OFFSET) /* Status
>> Register */
>> +#define XIIC_DTR_REG_OFFSET (0x08+XIIC_REG_OFFSET) /* Data Tx
>> Register */
>> +#define XIIC_DRR_REG_OFFSET (0x0C+XIIC_REG_OFFSET) /* Data Rx
>> Register */
>> +#define XIIC_ADR_REG_OFFSET (0x10+XIIC_REG_OFFSET) /* Address
>> Register */
>> +#define XIIC_TFO_REG_OFFSET (0x14+XIIC_REG_OFFSET) /* Tx FIFO
>> Occupancy */
>> +#define XIIC_RFO_REG_OFFSET (0x18+XIIC_REG_OFFSET) /* Rx FIFO
>> Occupancy */
>> +#define XIIC_TBA_REG_OFFSET (0x1C+XIIC_REG_OFFSET) /* 10 Bit
>> Address reg */
>> +#define XIIC_RFD_REG_OFFSET (0x20+XIIC_REG_OFFSET) /* Rx FIFO
>> Depth reg */
>> +#define XIIC_GPO_REG_OFFSET (0x24+XIIC_REG_OFFSET) /* Output
>> Register */
>
> A struct would be much more nicer, but as you said it is taken from
> linux code ... I am fine with it.
Actually, struct is not a good idea. Once you get a slight variance in
the register layout, the struct approach breaks down horribly. Using
macros for registers seems much better in most cases.
>> +
>> +/* Control Register masks */
>> +#define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable =
>> 1 */
>> +#define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO
>> reset=1 */
>> +#define XIIC_CR_MSMS_MASK 0x04 /* Master starts
>> Txing=1 */
>> +#define XIIC_CR_DIR_IS_TX_MASK 0x08 /* Dir of tx.
>> Txing=1 */
>> +#define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack =
>> 1 */
>> +#define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start =
>> 1 */
>> +#define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled
>> = 1 */
>> +
>> +/* Status Register masks */
>> +#define XIIC_SR_GEN_CALL_MASK
Re: [U-Boot] [linux-sunxi] CONFIG_DM_USB breakage on sunxi boards with musb?
On Wed, Dec 19, 2018 at 01:26:18PM +0530, Jagan Teki wrote: > On Wed, Dec 19, 2018 at 1:23 PM Priit Laes wrote: > > > > Heya! > > > > I ran into following error when trying to fel-boot > > A20 OLinuxino Lime2 eMMC board with latest u-boot: > > > > [snip] > > U-Boot 2019.01-rc2-5-gbf60dae9dd (Dec 19 2018 - 09:47:08 +0200) > > Allwinner Technology > > > > CPU: Allwinner A20 (SUN7I) > > Model: Olimex A20-OLinuXino-LIME2-eMMC > > I2C: ready > > DRAM: 1 GiB > > Error binding driver 'sunxi-musb': -96 > > Some drivers failed to bind > > Error binding driver 'generic_simple_bus': -96 > > Some drivers failed to bind > > initcall sequence 7efbdfc8 failed at call 4a00d07b (err=-96) > > ### ERROR ### Please RESET the board ### > > [/snip] > > > > > > Could it be caused by a side effect of the upcoming CONFIG_DM_USB > > changes? > > No, board file change wrt this commit 0131162439508801b9f8a330fa731f04273c9337 > > Need to figure out. Yup, bisecting points to the same commit and reverting fixes the issue. 0131162439508801b9f8a330fa731f04273c9337 is the first bad commit commit 0131162439508801b9f8a330fa731f04273c9337 Author: Jean-Jacques Hiblot Date: Thu Nov 29 10:52:46 2018 +0100 dm: usb: create a new UCLASS ID for USB gadget devices UCLASS_USB_DEV_GENERIC was meant for USB devices connected to host controllers, not gadget devices. Adding a new UCLASS for gadget devices alone. Also move the generic DM code for USB gadgets in a separate file for clarity. Signed-off-by: Jean-Jacques Hiblot :04 04 5223a6058a0c4a1e877f32355c947d4a607fef1b d3f89658db63ec26d887163740cf5d974dd2c0e5 M board :04 04 67c4404917ada478595b408d7747a6f5c17c0c99 8c67ea39df65e4e982d9b9eeb984d66678a33fc8 M drivers :04 04 89243fd62729e128489d80e206db4fa9b946dc99 16783bd1f210ae3454255cb1c4eaa05fe7eaa6ed M include $ git bisect log git bisect start # bad: [058701534ffde8032649ba8421a0428959519b79] WIP git bisect bad 058701534ffde8032649ba8421a0428959519b79 # bad: [d94604d558cda9f89722c967d6f8d6269a2db21c] Merge tag 'fsl-qoriq-for-v2019.01-rc2' of git://git.denx.de/u-boot-fsl-qoriq git bisect bad d94604d558cda9f89722c967d6f8d6269a2db21c # good: [c49aff3e66b930aa06936afee401cf5e19377958] Merge branch 'master' of git://git.denx.de/u-boot-sunxi git bisect good c49aff3e66b930aa06936afee401cf5e19377958 # bad: [7ff485c68b7e5573e5a4a877066e98398283a24f] Merge branch 'master' of git://git.denx.de/u-boot-i2c git bisect bad 7ff485c68b7e5573e5a4a877066e98398283a24f # good: [19f8c4dfb6e744a31da59bdd23b24d144152f1dc] cmd: i2c: Fix help output of i2c command. git bisect good 19f8c4dfb6e744a31da59bdd23b24d144152f1dc # bad: [b491afa0f3c0df88027b08f18934cc034c40d659] configs: enable DM_USB and DM_USB_DEV for all DRA7 platforms git bisect bad b491afa0f3c0df88027b08f18934cc034c40d659 # bad: [93991cf1969077108ae36e90acb3cd25a6a449ac] dwc3-generic: Add select_dr_mode operation git bisect bad 93991cf1969077108ae36e90acb3cd25a6a449ac # good: [20bebd866690bb09dd1c1cb8ac674c3b17b63c6d] dwc3_generic: do not probe the USB device driver when it's bound git bisect good 20bebd866690bb09dd1c1cb8ac674c3b17b63c6d # bad: [0131162439508801b9f8a330fa731f04273c9337] dm: usb: create a new UCLASS ID for USB gadget devices git bisect bad 0131162439508801b9f8a330fa731f04273c9337 # good: [d648a50c0a27452a5439e7982b23b97c64820430] dwc3: move phy operation to core.c git bisect good d648a50c0a27452a5439e7982b23b97c64820430 # first bad commit: [0131162439508801b9f8a330fa731f04273c9337] dm: usb: create a new UCLASS ID for USB gadget devices > > -- > You received this message because you are subscribed to the Google Groups > "linux-sunxi" group. > To unsubscribe from this group and stop receiving emails from it, send an > email to linux-sunxi+unsubscr...@googlegroups.com. > For more options, visit https://groups.google.com/d/optout. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [linux-sunxi] CONFIG_DM_USB breakage on sunxi boards with musb?
On 19/12/2018 12:37, Priit Laes wrote: On Wed, Dec 19, 2018 at 01:26:18PM +0530, Jagan Teki wrote: On Wed, Dec 19, 2018 at 1:23 PM Priit Laes wrote: Heya! I ran into following error when trying to fel-boot A20 OLinuxino Lime2 eMMC board with latest u-boot: [snip] U-Boot 2019.01-rc2-5-gbf60dae9dd (Dec 19 2018 - 09:47:08 +0200) Allwinner Technology CPU: Allwinner A20 (SUN7I) Model: Olimex A20-OLinuXino-LIME2-eMMC I2C: ready DRAM: 1 GiB Error binding driver 'sunxi-musb': -96 Some drivers failed to bind Error binding driver 'generic_simple_bus': -96 Some drivers failed to bind initcall sequence 7efbdfc8 failed at call 4a00d07b (err=-96) ### ERROR ### Please RESET the board ### [/snip] Could it be caused by a side effect of the upcoming CONFIG_DM_USB changes? No, board file change wrt this commit 0131162439508801b9f8a330fa731f04273c9337 Need to figure out. Yup, bisecting points to the same commit and reverting fixes the issue. Can you try with DM_USB_GADGET enabled? 0131162439508801b9f8a330fa731f04273c9337 is the first bad commit commit 0131162439508801b9f8a330fa731f04273c9337 Author: Jean-Jacques Hiblot Date: Thu Nov 29 10:52:46 2018 +0100 dm: usb: create a new UCLASS ID for USB gadget devices UCLASS_USB_DEV_GENERIC was meant for USB devices connected to host controllers, not gadget devices. Adding a new UCLASS for gadget devices alone. Also move the generic DM code for USB gadgets in a separate file for clarity. Signed-off-by: Jean-Jacques Hiblot :04 04 5223a6058a0c4a1e877f32355c947d4a607fef1b d3f89658db63ec26d887163740cf5d974dd2c0e5 M board :04 04 67c4404917ada478595b408d7747a6f5c17c0c99 8c67ea39df65e4e982d9b9eeb984d66678a33fc8 M drivers :04 04 89243fd62729e128489d80e206db4fa9b946dc99 16783bd1f210ae3454255cb1c4eaa05fe7eaa6ed M include $ git bisect log git bisect start # bad: [058701534ffde8032649ba8421a0428959519b79] WIP git bisect bad 058701534ffde8032649ba8421a0428959519b79 # bad: [d94604d558cda9f89722c967d6f8d6269a2db21c] Merge tag 'fsl-qoriq-for-v2019.01-rc2' of git://git.denx.de/u-boot-fsl-qoriq git bisect bad d94604d558cda9f89722c967d6f8d6269a2db21c # good: [c49aff3e66b930aa06936afee401cf5e19377958] Merge branch 'master' of git://git.denx.de/u-boot-sunxi git bisect good c49aff3e66b930aa06936afee401cf5e19377958 # bad: [7ff485c68b7e5573e5a4a877066e98398283a24f] Merge branch 'master' of git://git.denx.de/u-boot-i2c git bisect bad 7ff485c68b7e5573e5a4a877066e98398283a24f # good: [19f8c4dfb6e744a31da59bdd23b24d144152f1dc] cmd: i2c: Fix help output of i2c command. git bisect good 19f8c4dfb6e744a31da59bdd23b24d144152f1dc # bad: [b491afa0f3c0df88027b08f18934cc034c40d659] configs: enable DM_USB and DM_USB_DEV for all DRA7 platforms git bisect bad b491afa0f3c0df88027b08f18934cc034c40d659 # bad: [93991cf1969077108ae36e90acb3cd25a6a449ac] dwc3-generic: Add select_dr_mode operation git bisect bad 93991cf1969077108ae36e90acb3cd25a6a449ac # good: [20bebd866690bb09dd1c1cb8ac674c3b17b63c6d] dwc3_generic: do not probe the USB device driver when it's bound git bisect good 20bebd866690bb09dd1c1cb8ac674c3b17b63c6d # bad: [0131162439508801b9f8a330fa731f04273c9337] dm: usb: create a new UCLASS ID for USB gadget devices git bisect bad 0131162439508801b9f8a330fa731f04273c9337 # good: [d648a50c0a27452a5439e7982b23b97c64820430] dwc3: move phy operation to core.c git bisect good d648a50c0a27452a5439e7982b23b97c64820430 # first bad commit: [0131162439508801b9f8a330fa731f04273c9337] dm: usb: create a new UCLASS ID for USB gadget devices -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 8/8] cmd: env: add "-e" option for handling UEFI variables
On 12/19/18 2:49 AM, AKASHI Takahiro wrote: > Heinrich, > > On Tue, Dec 18, 2018 at 07:07:02AM +0100, Heinrich Schuchardt wrote: >> On 12/18/18 6:05 AM, AKASHI Takahiro wrote: >>> "env [print|set] -e" allows for handling uefi variables without >>> knowing details about mapping to corresponding u-boot variables. >>> >>> Signed-off-by: AKASHI Takahiro >> >> Hello Takahiro, >> >> in several patch series you are implementing multiple interactive >> commands that concern >> >> - handling of EFI variables >> - executing EFI binaries >> - managing boot sequence >> >> I very much appreciate your effort to provide an independent UEFI shell >> implementation. What I am worried about is that your current patches >> make it part of the monolithic U-Boot binary. > > First of all, in v3, CONFIG_CMD_EFISHELL was introduced after Alex's > comment on v2. So you can disable efishell command if you don't want it. > > Are you still worried? > >> This design has multiple drawbacks: >> >> The memory size available for U-Boot is very limited for many devices. >> We already had to disable EFI_LOADER for some boards due to this >> limitations. Hence we want to keep everything out of the U-Boot binary >> that does not serve the primary goal of loading and executing the next >> binary. > > I don't know your point here. If EFI_LOADER is disabled, efishell > will never be compiled in. > >> The UEFI forum has published a UEFI Shell specification which is very >> extensive. We still have a lot of deficiencies in U-Boot's UEFI API >> implementation. By merging in parts of an UEFI shell implementation our >> project looses focus. > > What is "our project?" What is "focus?" > I'm just asking as I want to share that information with you. > >> There is an EDK2 implementation of said >> specification. If we fix the remaining bugs of the EFI API >> implementation in U-Boot we could simply run the EDK2 shell which >> provides all that is needed for interactive work. >> >> With you monolithic approach your UEFI shell implementation can neither >> be used with other UEFI API implementations than U-Boot nor can it be >> tested against other API implementations. > > Let me explain my stance. > My efishell is basically something like a pursuit as well as > a debug/test tool which was and is still quite useful for me. > Without it, I would have completed (most of) my efi-related work so far. > So I believe that it will also be useful for other people who may want > to get involved and play with u-boot's efi environment. On SD-Cards U-Boot is installed between the MBR and the first partition. On other devices it is put into a very small ROM. Both ways the maximum size is rather limited. U-Boot provides all that is needed to load and execute an EFI binary. So you can put your efishell as file into the EFI partition like you would install the EDK2 shell. The only hardshift this approach brings is that you have to implement your own printf because UEFI does not offer formatted output. But this can be copied from lib/efi_selftest/efi_selftest_console.c. The same decision I took for booting from iSCSI. I did not try to put an iSCSI driver into U-Boot instead I use iPXE as an executable that is loaded from the EFI partition. > > I have never intended to fully implement a shell which is to be compliant > with UEFI specification while I'm trying to mimick some command > interfaces for convenience. UEFI shell, as you know, provides plenty > of "protocols" on which some UEFI applications, including UEFI SCT, > reply. I will never implement it with my efishell. > > I hope that my efishell is a quick and easy way of learning more about > u-boot's uefi environment. I will be even happier if more people > get involved there. > >> Due to these considerations I suggest that you build your UEFI shell >> implementation as a separate UEFI binary (like helloworld.efi). You may >> offer an embedding of the binary (like the bootefi hello command) into >> the finally linked U-Boot binary via a configuration variable. Please, >> put the shell implementation into a separate directory. You may want to >> designate yourself as maintainer (in file MAINTAINERS). > > Yeah, your suggestion is reasonable and I have thought of it before. > There are, however, several reasons that I haven't done so; particularly, > efishell is implemented not only with boottime services but also > other helper functions, say, from device path utilities. Exporting them > as libraries is possible but I don't think that it would be so valuable. > > Even if efishell is a separate application, it will not contribute to > reduce the total footprint if it is embedded along with u-boot binary. That is why CONFIG_CMD_BOOTEFI_HELLO - which embeds helloworld.efi into the U-Boot binary - is default no. Same I would do for efishell.efi. Best regards Heinrich > > Thanks, > -Takahiro Akashi > >> Best regards >> >> Heinrich >> >> >>> --- >>> cmd/nvedit.c | 61 +++
[U-Boot] [PATCH v2 0/3] Ethernet support for QEMU sifive_u machine
This patchset enables Cadance MACB ethernet driver for QEMU sifive_u machine. The Cadance MACB ethernet driver works fine for QEMU sifive_u machince in both M-mode and S-mode with some minor fixes. The patches are based upon latest RISC-V U-Boot tree (git://git.denx.de/u-boot-riscv.git) at commit id 9deb8d2fcd13d4a40a4e63c396fe4376af46efac To try on QEMU, please ensure following patches are applied to QEMU sources: https://patchwork.kernel.org/patch/10729579/ https://patchwork.kernel.org/patch/10729581/ Changes since v1: - Minor nit changes in PATCH1 Anup Patel (3): riscv: Add asm/dma-mapping.h for DMA mappings net: macb: Fix clk API usage for RISC-V systems riscv: qemu: Imply MACB ethernet for emulation arch/riscv/include/asm/dma-mapping.h | 38 board/emulation/qemu-riscv/Kconfig | 4 +++ drivers/net/macb.c | 4 ++- 3 files changed, 45 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/include/asm/dma-mapping.h -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 1/3] riscv: Add asm/dma-mapping.h for DMA mappings
From: Anup Patel
This patch adds asm/dma-mapping.h for Linux-like DMA mappings
APIs required by some of the drivers (such as, Cadance MACB
Ethernet driver).
Signed-off-by: Anup Patel
Reviewed-by: Bin Meng
---
arch/riscv/include/asm/dma-mapping.h | 38
1 file changed, 38 insertions(+)
create mode 100644 arch/riscv/include/asm/dma-mapping.h
diff --git a/arch/riscv/include/asm/dma-mapping.h
b/arch/riscv/include/asm/dma-mapping.h
new file mode 100644
index 00..3d930c90ec
--- /dev/null
+++ b/arch/riscv/include/asm/dma-mapping.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2018 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ * Anup Patel
+ */
+
+#ifndef __ASM_RISCV_DMA_MAPPING_H
+#define __ASM_RISCV_DMA_MAPPING_H
+
+#include
+
+#define dma_mapping_error(x, y)0
+
+static inline void *dma_alloc_coherent(size_t len, unsigned long *handle)
+{
+ *handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, len);
+ return (void *)*handle;
+}
+
+static inline void dma_free_coherent(void *addr)
+{
+ free(addr);
+}
+
+static inline unsigned long dma_map_single(volatile void *vaddr, size_t len,
+ enum dma_data_direction dir)
+{
+ return (unsigned long)vaddr;
+}
+
+static inline void dma_unmap_single(volatile void *vaddr, size_t len,
+ unsigned long paddr)
+{
+}
+
+#endif /* __ASM_RISCV_DMA_MAPPING_H */
--
2.17.1
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[U-Boot] [PATCH v2 3/3] riscv: qemu: Imply MACB ethernet for emulation
From: Anup Patel This patch enables Cadence MACB ethernet driver for QEMU RISC-V emulation by implying MACB, MII, RGMII and NET_RANDOM_ETHADDR on BOARD_SPECIFIC_OPTIONS. Signed-off-by: Anup Patel Reviewed-by: Bin Meng --- board/emulation/qemu-riscv/Kconfig | 4 1 file changed, 4 insertions(+) diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig index 0d865acf10..5d9611bdc7 100644 --- a/board/emulation/qemu-riscv/Kconfig +++ b/board/emulation/qemu-riscv/Kconfig @@ -34,5 +34,9 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply BOARD_LATE_INIT imply OF_BOARD_SETUP imply SIFIVE_SERIAL + imply MACB + imply RGMII + imply MII + imply NET_RANDOM_ETHADDR endif -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 2/3] net: macb: Fix clk API usage for RISC-V systems
From: Anup Patel This patch does following fixes in MACB ethernet driver for using it on RISC-V systems (particularly QEMU sifive_u machine): 1. asm/arch/clk.h is not available on RISC-V port so include it only for non-RISC-V systems. 2. Don't fail in macb_enable_clk() if clk_enable() returns -ENOSYS because we get -ENOSYS for fixed-rate clocks. Signed-off-by: Anup Patel Reviewed-by: Bin Meng --- drivers/net/macb.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/net/macb.c b/drivers/net/macb.c index 94c89c762b..9a06b523cc 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -38,7 +38,9 @@ #include #include #include +#ifndef CONFIG_RISCV #include +#endif #include #include "macb.h" @@ -1066,7 +1068,7 @@ static int macb_enable_clk(struct udevice *dev) */ #ifndef CONFIG_MACB_ZYNQ ret = clk_enable(&clk); - if (ret) + if (ret && ret != -ENOSYS) return ret; #endif -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] USB: musb-new: omap2430: Add hooks for Peripheral support.
On Wed, Dec 19, 2018 at 4:59 AM Jean-Jacques Hiblot wrote:
>
>
> On 17/12/2018 21:34, Adam Ford wrote:
> > Borrowing from the updates to ti-musb.c, this glue layer checks
> > to see if the MUSB controller is gadget or host. Going under
> > the assumpution there is only one MUSB controller, this only builds
> > either the host probe or the gadget probe. OTG would be preferred,
> > but it doesn't appear to be working yet.
>
> You can support both host and periph mode at the same time:
>
> Create a new driver (a MISC UCLASS for ex) compatible with ti,omap3-musb.
>
> Provide a bind function. In this function check the value of dr_mode and
> bind the appropriate child driver (host or peripheral).
>
> This is how it is done in ti-musb.c.
I tried that first. Anytime I tried to use the MISC_UCLASS, I would
get the err -96 like others are reporting. If you have any other
suggestions on how to fix the -96 issue, I'm willing to try them.
Since we didn't have OTG working before, and it was either host or
gadget, I felt this was at least one step forward by making it DM_USB
compliant.
adam
>
> JJ
>
> >
> > Signed-off-by: Adam Ford
> >
> > diff --git a/drivers/usb/musb-new/omap2430.c
> > b/drivers/usb/musb-new/omap2430.c
> > index b6e1320538..780d21c693 100644
> > --- a/drivers/usb/musb-new/omap2430.c
> > +++ b/drivers/usb/musb-new/omap2430.c
> > @@ -203,7 +203,7 @@ static int omap2430_musb_ofdata_to_platdata(struct
> > udevice *dev)
> > return 0;
> > }
> >
> > -#ifdef CONFIG_USB_MUSB_HOST
> > +#ifndef CONFIG_USB_MUSB_GADGET
> > static int omap2430_musb_probe(struct udevice *dev)
> > {
> > struct musb_host_data *host = dev_get_priv(dev);
> > @@ -241,7 +241,7 @@ static int omap2430_musb_remove(struct udevice *dev)
> > #if CONFIG_IS_ENABLED(OF_CONTROL)
> > static int omap2430_musb_host_ofdata_to_platdata(struct udevice *dev)
> > {
> > - struct ti_musb_platdata *platdata = dev_get_platdata(dev);
> > + struct omap2430_musb_platdata *platdata = dev_get_platdata(dev);
> > const void *fdt = gd->fdt_blob;
> > int node = dev_of_offset(dev);
> > int ret;
> > @@ -272,6 +272,83 @@ U_BOOT_DRIVER(omap2430_musb) = {
> > .priv_auto_alloc_size = sizeof(struct musb_host_data),
> > };
> >
> > +#else
> > +
> > +struct omap2430_musb_peripheral {
> > + struct musb *periph;
> > +};
> > +
> > +#if CONFIG_IS_ENABLED(OF_CONTROL)
> > +static int omap2430_musb_peripheral_ofdata_to_platdata(struct udevice *dev)
> > +{
> > + struct ti_musb_platdata *platdata = dev_get_platdata(dev);
> > + const void *fdt = gd->fdt_blob;
> > + int node = dev_of_offset(dev);
> > + int ret;
> > +
> > + ret = omap2430_musb_ofdata_to_platdata(dev);
> > + if (ret) {
> > + pr_err("platdata dt parse error\n");
> > + return ret;
> > + }
> > + platdata->plat.mode = MUSB_PERIPHERAL;
> > +
> > + return 0;
> > +}
> > +#endif
> > +
> > +int dm_usb_gadget_handle_interrupts(struct udevice *dev)
> > +{
> > + struct omap2430_musb_peripheral *priv = dev_get_priv(dev);
> > +
> > + priv->periph->isr(0, priv->periph);
> > +
> > + return 0;
> > +}
> > +
> > +static int omap2430_musb_peripheral_probe(struct udevice *dev)
> > +{
> > + struct omap2430_musb_peripheral *priv = dev_get_priv(dev);
> > + struct omap2430_musb_platdata *platdata = dev_get_platdata(dev);
> > + struct omap_musb_board_data *otg_board_data;
> > + int ret;
> > +
> > + otg_board_data = &platdata->otg_board_data;
> > + priv->periph = musb_init_controller(&platdata->plat,
> > + (struct device *)otg_board_data,
> > + platdata->base);
> > + if (!priv->periph)
> > + return -EIO;
> > +
> > + /* ti_musb_set_phy_power(dev, 1); */
> > + musb_gadget_setup(priv->periph);
> > + return usb_add_gadget_udc((struct device *)dev, &priv->periph->g);
> > +}
> > +
> > +static int omap2430_musb_peripheral_remove(struct udevice *dev)
> > +{
> > + struct omap2430_musb_peripheral *priv = dev_get_priv(dev);
> > +
> > + usb_del_gadget_udc(&priv->periph->g);
> > + /* ti_musb_set_phy_power(dev, 0); */
> > +
> > + return 0;
> > +}
> > +
> > +U_BOOT_DRIVER(omap2430_musb_peripheral) = {
> > + .name = "ti-musb-peripheral",
> > + .id = UCLASS_USB_GADGET_GENERIC,
> > + .of_match = omap2430_musb_ids,
> > +#if CONFIG_IS_ENABLED(OF_CONTROL)
> > + .ofdata_to_platdata = omap2430_musb_peripheral_ofdata_to_platdata,
> > +#endif
> > + .probe = omap2430_musb_peripheral_probe,
> > + .remove = omap2430_musb_peripheral_remove,
> > + .ops= &musb_usb_ops,
> > + .platdata_auto_alloc_size = sizeof(struct omap2430_musb_platdata),
> > + .priv_auto_alloc_size = sizeof(struct omap2430_musb_peripheral),
> > + .flags = DM_FLAG_PRE_RELOC,
> > +};
> > #endif
> >
> > #endif /* CONFIG_IS_ENABLED(DM_USB) */
__
[U-Boot] [PATCH] Revert "sunxi: board: Print error after power initialization fails"
From: "From: Karl Palsson"
Commit a8011eb84dfa("sunxi: board: Print error after power initialization
fails") moved the DRAM init after the increase of the CPU clock
frequency. This lead to various DRAM initialisation failures on some
boards (hangs or wrong size reported, on a NanoPi Duo2 and OrangePi
Zero, for instance). Lowering the CPU frequency significantly (for instance
to 408 MHz) seems to work around the problem, so this points to some timing
issues in the DRAM code.
Debugging this sounds like a larger job, so let's just revert this patch
to bring back those boards.
Beside this probably unintended change the patch just moved the error
message around, so reverting this is not a real loss.
This reverts commit a8011eb84dfac5187cebf00ed8bc981bdb5c1fa1.
Tested-By: Priit Laes
Signed-off-by: Karl Palsson
Signed-off-by: Andre Przywara
---
board/sunxi/board.c | 18 --
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 917f5b18f6..f022f365e9 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -637,6 +637,13 @@ void sunxi_board_init(void)
power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
#endif
#endif
+ printf("DRAM:");
+ gd->ram_size = sunxi_dram_init();
+ printf(" %d MiB\n", (int)(gd->ram_size >> 20));
+ if (!gd->ram_size)
+ hang();
+
+ sunxi_spl_store_dram_size(gd->ram_size);
/*
* Only clock up the CPU to full speed if we are reasonably
@@ -645,16 +652,7 @@ void sunxi_board_init(void)
if (!power_failed)
clock_set_pll1(CONFIG_SYS_CLK_FREQ);
else
- printf("Error setting up the power controller.\n"
- "CPU frequency not set.\n");
-
- printf("DRAM:");
- gd->ram_size = sunxi_dram_init();
- printf(" %d MiB\n", (int)(gd->ram_size >> 20));
- if (!gd->ram_size)
- hang();
-
- sunxi_spl_store_dram_size(gd->ram_size);
+ printf("Failed to set core voltage! Can't set CPU frequency\n");
}
#endif
--
2.14.5
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Re: [U-Boot] [PATCH v4 06/10] dm: usb: create a new UCLASS ID for USB gadget devices
On Wed, Dec 19, 2018 at 4:34 AM Jean-Jacques Hiblot wrote: > > > On 19/12/2018 11:31, Jean-Jacques Hiblot wrote: > > > > On 18/12/2018 13:08, Jagan Teki wrote: > >> On Thu, Nov 29, 2018 at 3:30 PM Jean-Jacques Hiblot > >> wrote: > >>> UCLASS_USB_DEV_GENERIC was meant for USB devices connected to host > >>> controllers, not gadget devices. > >>> Adding a new UCLASS for gadget devices alone. > >>> > >>> Also move the generic DM code for USB gadgets in a separate file for > >>> clarity. > >>> > >>> Signed-off-by: Jean-Jacques Hiblot > >>> > >>> --- > >>> > >>> Changes in v4: None > >>> Changes in v3: None > >>> Changes in v2: None > >>> > >>> board/sunxi/board.c | 2 +- > >>> drivers/usb/dwc3/dwc3-generic.c | 2 +- > >>> drivers/usb/gadget/ether.c | 2 +- > >>> drivers/usb/gadget/udc/Makefile | 4 +++ > >>> drivers/usb/gadget/udc/udc-core.c | 41 -- > >>> drivers/usb/gadget/udc/udc-uclass.c | 58 > >>> + > >>> drivers/usb/musb-new/omap2430.c | 2 +- > >>> drivers/usb/musb-new/sunxi.c| 2 +- > >>> include/dm/uclass-id.h | 1 + > >>> 9 files changed, 68 insertions(+), 46 deletions(-) > >>> create mode 100644 drivers/usb/gadget/udc/udc-uclass.c > >>> > >>> diff --git a/board/sunxi/board.c b/board/sunxi/board.c > >>> index 64ccbc7..9b36cc7 100644 > >>> --- a/board/sunxi/board.c > >>> +++ b/board/sunxi/board.c > >>> @@ -663,7 +663,7 @@ int g_dnl_board_usb_cable_connected(void) > >>> struct phy phy; > >>> int ret; > >>> > >>> - ret = uclass_get_device(UCLASS_USB_DEV_GENERIC, 0, &dev); > >>> + ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, &dev); > >> This is breaking sunxi boards which uses gadget mode. > >> > >> U-Boot 2019.01-rc2 (Dec 18 2018 - 17:31:53 +0530) Allwinner Technology > >> > >> CPU: Allwinner H3 (SUN8I 1680) > >> Model: Banana Pi BPI-M2-Plus > >> DRAM: 1 GiB > >> Error binding driver 'sunxi-musb': -96 > >> Some drivers failed to bind > > > > Can you try with DM_USB_GADGET enabled ? > > The reasoning is that UCLASS_DRIVER(usb_gadget_generic) is defined if > and only if DM_USB_GADGET is enabled. I tried this when trying to port to the omap2430 glue, and got the same -96 error when using the MISC class driver and I enabled DM_USB_GADGET. adam > > > > > JJ > > > > > >> Error binding driver 'generic_simple_bus': -96 > >> Some drivers failed to bind > >> initcall sequence 7dfd127c failed at call 4a00c3a3 (err=-96) > >> ### ERROR ### Please RESET the board ### > >> > > ___ > > U-Boot mailing list > > U-Boot@lists.denx.de > > https://lists.denx.de/listinfo/u-boot > ___ > U-Boot mailing list > U-Boot@lists.denx.de > https://lists.denx.de/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 1/2] mtd/spi: Add JEDEC SFDP support in SPI framework
Hi,
>>
>> Unfortunately thats a problem with U-Boot spi_flash layer today. Many
>> newer flashes like Micron's mt35x series dont support BAR registers.
>> Accessing above 16MB is broken for such flashes today.
>>
>>> Also, initially I wanted to make SFDP optional so that none of the drivers
>> are affected
>>> and one could enable it using a flag as per requirement. Shall we get back
>> to making
>>> this optional (similar to v1 of this patch)?
>>>
>>
>> How does that help? With opt-in approach you mark some flash devices as
>> SFDP capable, but you still don't update opcodes, thus breaking boards
>> that have such flash devices. So, porting full bfpt parsing and always
>> using opcode to 4 byte addressing opcodes when available will be needed.
>> Thus you would end up with SFDP as default instead of opt-in.
>
> Hi Vignesh
>
> Porting full bftp parsing requires time. I am seeing a conflict with a patch
> of yours
> https://patchwork.ozlabs.org/cover/1012146/
>
Yes, I ended up porting all of Linux SPI NOR features including SFDP and
4 byte addressing.
> It seem above RFC patch will bring SFDP to U-boot. Do you still want me
> to put effort in porting SFDP in current version?
>
No need to post this series as my patches including this change. I would
appreciate any review/test of my series.
You can find Patch v1 here: https://patchwork.ozlabs.org/cover/1012146/
(Please drop patch 9/16 while testing). Thanks!
Regards
Vignesh
> Regards
> Rajat
>
>>
>>> Regards
>>> Rajat
>>>
Additionally, there are flash chips with a 3-/4-byte mode change
>> instruction.
But using 4-byte opcodes should be preferred.
Simon
>
> In particular you are not parsing entire bfpt like in [1] and will
> break flash operations
>
>
>> [1]https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2F
> elixir.bootlin.com%2Flinux%2Flatest%2Fsource%2Fdrivers%2Fmtd%2Fspi-
nor
> %2Fspi-
nor.c%23L2259&data=02%7C01%7Crajat.srivastava%40nxp.com%7Ca
>
>> cee153f50194bba71c808d64bad8d2e%7C686ea1d3bc2b4c6fa92cd99c5c30163
>> 5
%7C0
>
>> %7C0%7C636779606107591743&sdata=UACl919%2BMQmdtBo5GUTAy
M428u1bT1bU
> rXuX2GsSjb0%3D&reserved=0
>
> Regards
> Vignesh
>
>> Regards
>> Rajat
>>
>>>
>>> Regards
>>> Vigensh
>>>
>>>
+ default:
+ break;
+ }
+
+ /* Flash Memory Density (in bits). */
+ flash->size = bfpt.dwords[BFPT_DWORD(2)];
+ if (flash->size & BIT(31)) {
+ flash->size &= ~BIT(31);
+
+ /*
+* Prevent overflows on flash->size. Anyway, a NOR of 2^64
+* bits is unlikely to exist so this error probably means
+* the BFPT we are reading is corrupted/wrong.
+*/
+ if (flash->size > 63)
+ return -EINVAL;
+
+ flash->size = 1ULL << flash->size;
+ } else {
+ flash->size++;
+ }
+ flash->size >>= 3; /* Convert to bytes. */
+
+ /* Stop here if not JESD216 rev A or later. */
+ if (bfpt_header->length < BFPT_DWORD_MAX)
+ return 0;
+
+ /* Page size: this field specifies 'N' so the page size = 2^N
bytes. */
+ flash->page_size = bfpt.dwords[BFPT_DWORD(11)];
+ flash->page_size &= BFPT_DWORD11_PAGE_SIZE_MASK;
+ flash->page_size >>= BFPT_DWORD11_PAGE_SIZE_SHIFT;
+ flash->page_size = 1U << flash->page_size;
+
+ return 0;
+}
+
+/*
+ * spi_flash_parse_sfdp() - parse the Serial Flash Discoverable
>>> Parameters.
+ * @flash: pointer to a 'struct spi_flash'
+ *
+ * The Serial Flash Discoverable Parameters are described by the
+JEDEC JESD216
+ * specification. This is a standard which tends to supported by
+almost all
+ * (Q)SPI memory manufacturers. Those hard-coded tables allow us
+to learn at
+ * runtime the main parameters needed to perform basic SPI flash
>>> operations.
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
+static int spi_flash_parse_sfdp(struct spi_flash *flash) {
+ const struct sfdp_parameter_header *param_header,
>>> *bfpt_header;
+ struct sfdp_parameter_header *param_headers = NULL;
+ struct sfdp_header header;
+ size_t psize;
+ int i, err;
+
+ /* Get the SFDP header. */
+ err = spi_flash_read_sfdp(flash, 0, sizeof(header), &header);
+ if (err < 0)
+ return err;
+
+ /* Check the SFDP header version. */
+ if (le32
Re: [U-Boot] [PATCH 2/2] USB: musb-new: omap2430: Add hooks for Peripheral support.
On 19/12/2018 13:59, Adam Ford wrote:
On Wed, Dec 19, 2018 at 4:59 AM Jean-Jacques Hiblot wrote:
On 17/12/2018 21:34, Adam Ford wrote:
Borrowing from the updates to ti-musb.c, this glue layer checks
to see if the MUSB controller is gadget or host. Going under
the assumpution there is only one MUSB controller, this only builds
either the host probe or the gadget probe. OTG would be preferred,
but it doesn't appear to be working yet.
You can support both host and periph mode at the same time:
Create a new driver (a MISC UCLASS for ex) compatible with ti,omap3-musb.
Provide a bind function. In this function check the value of dr_mode and
bind the appropriate child driver (host or peripheral).
This is how it is done in ti-musb.c.
I tried that first. Anytime I tried to use the MISC_UCLASS, I would
You need to enable CONFIG_MISC in that case. That is probably the error
get the err -96 like others are reporting. If you have any other
suggestions on how to fix the -96 issue, I'm willing to try them.
Since we didn't have OTG working before, and it was either host or
gadget, I felt this was at least one step forward by making it DM_USB
compliant.
adam
JJ
Signed-off-by: Adam Ford
diff --git a/drivers/usb/musb-new/omap2430.c b/drivers/usb/musb-new/omap2430.c
index b6e1320538..780d21c693 100644
--- a/drivers/usb/musb-new/omap2430.c
+++ b/drivers/usb/musb-new/omap2430.c
@@ -203,7 +203,7 @@ static int omap2430_musb_ofdata_to_platdata(struct udevice
*dev)
return 0;
}
-#ifdef CONFIG_USB_MUSB_HOST
+#ifndef CONFIG_USB_MUSB_GADGET
static int omap2430_musb_probe(struct udevice *dev)
{
struct musb_host_data *host = dev_get_priv(dev);
@@ -241,7 +241,7 @@ static int omap2430_musb_remove(struct udevice *dev)
#if CONFIG_IS_ENABLED(OF_CONTROL)
static int omap2430_musb_host_ofdata_to_platdata(struct udevice *dev)
{
- struct ti_musb_platdata *platdata = dev_get_platdata(dev);
+ struct omap2430_musb_platdata *platdata = dev_get_platdata(dev);
const void *fdt = gd->fdt_blob;
int node = dev_of_offset(dev);
int ret;
@@ -272,6 +272,83 @@ U_BOOT_DRIVER(omap2430_musb) = {
.priv_auto_alloc_size = sizeof(struct musb_host_data),
};
+#else
+
+struct omap2430_musb_peripheral {
+ struct musb *periph;
+};
+
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+static int omap2430_musb_peripheral_ofdata_to_platdata(struct udevice *dev)
+{
+ struct ti_musb_platdata *platdata = dev_get_platdata(dev);
+ const void *fdt = gd->fdt_blob;
+ int node = dev_of_offset(dev);
+ int ret;
+
+ ret = omap2430_musb_ofdata_to_platdata(dev);
+ if (ret) {
+ pr_err("platdata dt parse error\n");
+ return ret;
+ }
+ platdata->plat.mode = MUSB_PERIPHERAL;
+
+ return 0;
+}
+#endif
+
+int dm_usb_gadget_handle_interrupts(struct udevice *dev)
+{
+ struct omap2430_musb_peripheral *priv = dev_get_priv(dev);
+
+ priv->periph->isr(0, priv->periph);
+
+ return 0;
+}
+
+static int omap2430_musb_peripheral_probe(struct udevice *dev)
+{
+ struct omap2430_musb_peripheral *priv = dev_get_priv(dev);
+ struct omap2430_musb_platdata *platdata = dev_get_platdata(dev);
+ struct omap_musb_board_data *otg_board_data;
+ int ret;
+
+ otg_board_data = &platdata->otg_board_data;
+ priv->periph = musb_init_controller(&platdata->plat,
+ (struct device *)otg_board_data,
+ platdata->base);
+ if (!priv->periph)
+ return -EIO;
+
+ /* ti_musb_set_phy_power(dev, 1); */
+ musb_gadget_setup(priv->periph);
+ return usb_add_gadget_udc((struct device *)dev, &priv->periph->g);
+}
+
+static int omap2430_musb_peripheral_remove(struct udevice *dev)
+{
+ struct omap2430_musb_peripheral *priv = dev_get_priv(dev);
+
+ usb_del_gadget_udc(&priv->periph->g);
+ /* ti_musb_set_phy_power(dev, 0); */
+
+ return 0;
+}
+
+U_BOOT_DRIVER(omap2430_musb_peripheral) = {
+ .name = "ti-musb-peripheral",
+ .id = UCLASS_USB_GADGET_GENERIC,
+ .of_match = omap2430_musb_ids,
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+ .ofdata_to_platdata = omap2430_musb_peripheral_ofdata_to_platdata,
+#endif
+ .probe = omap2430_musb_peripheral_probe,
+ .remove = omap2430_musb_peripheral_remove,
+ .ops= &musb_usb_ops,
+ .platdata_auto_alloc_size = sizeof(struct omap2430_musb_platdata),
+ .priv_auto_alloc_size = sizeof(struct omap2430_musb_peripheral),
+ .flags = DM_FLAG_PRE_RELOC,
+};
#endif
#endif /* CONFIG_IS_ENABLED(DM_USB) */
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[U-Boot] [PATCH 1/3] videomodes: Allow EDID timings where hsync/vsync pulse is 0
From: Priit Laes Current EDID detailed timing parser errors out when either horizontal or vertical pulse sync width is 0, thus not allowing a display with EDID listed below work properly. Of-course, this is somewhat quirky HDMI display with following anti-features: - HPD pin is not usable - although resolution is 640x480, only top 240 pixels are visible $ xxd -p display.edid 000005a1e0030100150f0103800f05780a0f6ea05748 9a2610474f20010101010101010101010101010101012a08804520e0 0b10200040009536001800fd0034441a2403000a202020202020 001000310a202020202020202020202000102a4030701300 782d111e006b $ edid-decode display.edid EDID version: 1.3 Manufacturer: AMA Model 3e0 Serial Number 1 Digital display Maximum image size: 15 cm x 5 cm Gamma: 2.20 RGB color display First detailed timing is preferred timing Display x,y Chromaticity: Red: 0.6250, 0.3398 Green: 0.2841, 0.6044 Blue: 0.1494, 0.0644 White: 0.2802, 0.3105 Established timings supported: 640x480@60Hz 4:3 HorFreq: 31469 Hz Clock: 25.175 MHz Standard timings supported: Detailed mode: Clock 20.900 MHz, 149 mm x 54 mm 640 672 672 709 hborder 0 480 484 484 491 vborder 0 -hsync -vsync VertFreq: 60 Hz, HorFreq: 29478 Hz Monitor ranges (GTF): 52-68Hz V, 26-36kHz H, max dotclock 30MHz Dummy block Dummy block Checksum: 0x6b (valid) Signed-off-by: Priit Laes --- drivers/video/videomodes.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/video/videomodes.c b/drivers/video/videomodes.c index 74bafff011..1cfeaa980f 100644 --- a/drivers/video/videomodes.c +++ b/drivers/video/videomodes.c @@ -396,9 +396,7 @@ int video_edid_dtd_to_ctfb_res_modes(struct edid_detailed_timing *t, EDID_DETAILED_TIMING_VERTICAL_ACTIVE(*t) == 0 || EDID_DETAILED_TIMING_VERTICAL_BLANKING(*t) == 0 || EDID_DETAILED_TIMING_HSYNC_OFFSET(*t) == 0 || - EDID_DETAILED_TIMING_HSYNC_PULSE_WIDTH(*t) == 0 || EDID_DETAILED_TIMING_VSYNC_OFFSET(*t) == 0 || - EDID_DETAILED_TIMING_VSYNC_PULSE_WIDTH(*t) == 0 || /* 3d formats are not supported*/ EDID_DETAILED_TIMING_FLAG_STEREO(*t) != 0) return -EINVAL; -- 2.11.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 3/3] sunxi: display: Implement fallback to ddc probe when hpd fails
From: Priit Laes
There are HDMI displays where hpd pin is not connected, thus
we cannot get it to work unless we specifically set the resolution.
Rework the display probing, so hotplug detect failure causes
fallback to probing ddc for EDID data.
Signed-off-by: Priit Laes
---
drivers/video/sunxi/sunxi_display.c | 28 +---
1 file changed, 21 insertions(+), 7 deletions(-)
diff --git a/drivers/video/sunxi/sunxi_display.c
b/drivers/video/sunxi/sunxi_display.c
index 0362071f72..46436b88c5 100644
--- a/drivers/video/sunxi/sunxi_display.c
+++ b/drivers/video/sunxi/sunxi_display.c
@@ -210,7 +210,8 @@ static int sunxi_hdmi_edid_get_block(int block, u8 *buf)
return r;
}
-static int sunxi_hdmi_edid_get_mode(struct ctfb_res_modes *mode)
+static int sunxi_hdmi_edid_get_mode(struct ctfb_res_modes *mode,
+ bool verbose_mode)
{
struct edid1_info edid1;
struct edid_cea861_info cea681[4];
@@ -241,7 +242,8 @@ static int sunxi_hdmi_edid_get_mode(struct ctfb_res_modes
*mode)
if (r == 0) {
r = edid_check_info(&edid1);
if (r) {
- printf("EDID: invalid EDID data\n");
+ if (verbose_mode)
+ printf("EDID: invalid EDID data\n");
r = -EINVAL;
}
}
@@ -1082,7 +1084,8 @@ void *video_hw_init(void)
struct ctfb_res_modes custom;
const char *options;
#ifdef CONFIG_VIDEO_HDMI
- int ret, hpd, hpd_delay, edid;
+ int hpd, hpd_delay, edid;
+ bool hdmi_present;
#endif
int i, overscan_offset, overscan_x, overscan_y;
unsigned int fb_dma_addr;
@@ -1118,12 +1121,23 @@ void *video_hw_init(void)
if (sunxi_display.monitor == sunxi_monitor_dvi ||
sunxi_display.monitor == sunxi_monitor_hdmi) {
/* Always call hdp_detect, as it also enables clocks, etc. */
- ret = sunxi_hdmi_hpd_detect(hpd_delay);
- if (ret) {
+ hdmi_present = (sunxi_hdmi_hpd_detect(hpd_delay) == 1);
+ if (hdmi_present && edid) {
printf("HDMI connected: ");
- if (edid && sunxi_hdmi_edid_get_mode(&custom) == 0)
+ if (sunxi_hdmi_edid_get_mode(&custom, true) == 0)
mode = &custom;
- } else if (hpd) {
+ else
+ hdmi_present = false;
+ }
+ /* Fall back to EDID in case HPD failed */
+ if (edid && !hdmi_present) {
+ if (sunxi_hdmi_edid_get_mode(&custom, false) == 0) {
+ mode = &custom;
+ hdmi_present = true;
+ }
+ }
+ /* Shut down when display was not found */
+ if ((hpd || edid) && !hdmi_present) {
sunxi_hdmi_shutdown();
sunxi_display.monitor = sunxi_get_default_mon(false);
} /* else continue with hdmi/dvi without a cable connected */
--
2.11.0
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[U-Boot] [PATCH 2/3] sunxi: display: Move DDC PLL setup to HDMI init
From: Priit Laes
Move PLL initialization code to single place so
we won't call it every time we query for EDID data.
Signed-off-by: Priit Laes
---
drivers/video/sunxi/sunxi_display.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/video/sunxi/sunxi_display.c
b/drivers/video/sunxi/sunxi_display.c
index 6dd9bec351..0362071f72 100644
--- a/drivers/video/sunxi/sunxi_display.c
+++ b/drivers/video/sunxi/sunxi_display.c
@@ -113,6 +113,13 @@ static int sunxi_hdmi_hpd_detect(int hpd_delay)
writel(SUNXI_HDMI_CTRL_ENABLE, &hdmi->ctrl);
writel(SUNXI_HDMI_PAD_CTRL0_HDP, &hdmi->pad_ctrl0);
+ /* Enable PLLs for eventual DDC */
+ writel(SUNXI_HDMI_PAD_CTRL1 | SUNXI_HDMI_PAD_CTRL1_HALVE,
+ &hdmi->pad_ctrl1);
+ writel(SUNXI_HDMI_PLL_CTRL | SUNXI_HDMI_PLL_CTRL_DIV(15),
+ &hdmi->pll_ctrl);
+ writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);
+
while (timer_get_us() < tmo) {
if (readl(&hdmi->hpd) & SUNXI_HDMI_HPD_DETECT)
return 1;
@@ -215,13 +222,6 @@ static int sunxi_hdmi_edid_get_mode(struct ctfb_res_modes
*mode)
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
int i, r, ext_blocks = 0;
- /* SUNXI_HDMI_CTRL_ENABLE & PAD_CTRL0 are already set by hpd_detect */
- writel(SUNXI_HDMI_PAD_CTRL1 | SUNXI_HDMI_PAD_CTRL1_HALVE,
- &hdmi->pad_ctrl1);
- writel(SUNXI_HDMI_PLL_CTRL | SUNXI_HDMI_PLL_CTRL_DIV(15),
- &hdmi->pll_ctrl);
- writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);
-
/* Reset i2c controller */
setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE);
writel(SUNXI_HMDI_DDC_CTRL_ENABLE |
--
2.11.0
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[U-Boot] [PATCH 0/6] mips: mscc: Add multi-dtb support to luton+ocelot
This patch series add support for using multi-dtb on the MSCC luton and ocelot SOC reference boards. The appropriate board will be determined during startup, and the right DT will be selected. The patch is based off u-boot-mips repo. Lars Povlsen (6): mips: luton+ocelot: Remove board-specific config options mips: mscc: Add generic PHY MIIM utility functions mips: mscc: Add generic GPIO control utility function mips: luton: DT: Add pcb090 mips: luton: Add multi-dtb support mips: ocelot: Add multi-dtb support arch/mips/dts/Makefile| 2 + arch/mips/dts/luton_pcb090.dts| 36 + arch/mips/mach-mscc/Kconfig | 38 +++--- arch/mips/mach-mscc/Makefile | 2 +- arch/mips/mach-mscc/gpio.c| 33 + arch/mips/mach-mscc/include/mach/common.h | 22 ++ .../include/mach/luton/luton_devcpu_gcb.h | 4 + .../mach/luton/luton_devcpu_gcb_miim_regs.h | 26 +++ .../include/mach/ocelot/ocelot_devcpu_gcb.h | 2 + .../mach/ocelot/ocelot_devcpu_gcb_miim_regs.h | 25 +++ arch/mips/mach-mscc/phy.c | 73 +++ board/mscc/luton/luton.c | 46 +++- board/mscc/ocelot/ocelot.c| 52 +++-- configs/mscc_luton_defconfig | 7 +- configs/mscc_ocelot_defconfig | 7 +- configs/mscc_ocelot_pcb120_defconfig | 60 --- include/configs/vcoreiii.h| 2 + 17 files changed, 333 insertions(+), 104 deletions(-) create mode 100644 arch/mips/dts/luton_pcb090.dts create mode 100644 arch/mips/mach-mscc/gpio.c create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb_miim_regs.h create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb_miim_regs.h create mode 100644 arch/mips/mach-mscc/phy.c delete mode 100644 configs/mscc_ocelot_pcb120_defconfig -- 2.19.2 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/6] mips: luton+ocelot: Remove board-specific config options
As we are moving to multi-dtb and board detection, remove static board config options. Signed-off-by: Lars Povlsen --- arch/mips/mach-mscc/Kconfig | 38 ++--- 1 file changed, 10 insertions(+), 28 deletions(-) diff --git a/arch/mips/mach-mscc/Kconfig b/arch/mips/mach-mscc/Kconfig index 0e35b77c9d..37ef432e48 100644 --- a/arch/mips/mach-mscc/Kconfig +++ b/arch/mips/mach-mscc/Kconfig @@ -15,47 +15,29 @@ config SOC_VCOREIII config SYS_SOC default "mscc" +choice + + prompt "SOC Family Variant" + config SOC_OCELOT - bool + bool "Ocelot SOC Family" select SOC_VCOREIII + select DESIGNWARE_SPI help This supports MSCC Ocelot family of SOCs. config SOC_LUTON - bool + bool "Luton SOC Family" select SOC_VCOREIII + select MSCC_BITBANG_SPI_GPIO help This supports MSCC Luton family of SOCs. +endchoice + config SYS_CONFIG_NAME default "vcoreiii" -choice - prompt "Board select" - -config TARGET_OCELOT_PCB120 - bool "MSCC PCB120 Reference Board (aka VSC5635EV)" - select SOC_OCELOT - help - When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to - ocelot_pcb120 - -config TARGET_OCELOT_PCB123 - bool "MSCC PCB123 Reference Board (aka VSC7514EV))" - select SOC_OCELOT - help - When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to - ocelot_pcb123 - -config TARGET_LUTON_PCB091 - bool "MSCC PCB091 Reference Board" - select SOC_LUTON - select MSCC_BITBANG_SPI_GPIO - help - When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to - luton_pcb091 -endchoice - choice prompt "DDR type" -- 2.19.2 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 2/6] mips: mscc: Add generic PHY MIIM utility functions
The PHY MIIM utility functions can/will be used for board detection purposes. Signed-off-by: Lars Povlsen --- arch/mips/mach-mscc/Makefile | 2 +- arch/mips/mach-mscc/include/mach/common.h | 20 + .../mach/luton/luton_devcpu_gcb_miim_regs.h | 26 +++ .../mach/ocelot/ocelot_devcpu_gcb_miim_regs.h | 25 +++ arch/mips/mach-mscc/phy.c | 73 +++ 5 files changed, 145 insertions(+), 1 deletion(-) create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb_miim_regs.h create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb_miim_regs.h create mode 100644 arch/mips/mach-mscc/phy.c diff --git a/arch/mips/mach-mscc/Makefile b/arch/mips/mach-mscc/Makefile index 6c60f26ca4..300c88b5cd 100644 --- a/arch/mips/mach-mscc/Makefile +++ b/arch/mips/mach-mscc/Makefile @@ -2,5 +2,5 @@ CFLAGS_cpu.o += -finline-limit=64000 -obj-y += cpu.o dram.o reset.o lowlevel_init.o +obj-y += cpu.o dram.o reset.o phy.o lowlevel_init.o obj-$(CONFIG_SOC_LUTON) += lowlevel_init_luton.o diff --git a/arch/mips/mach-mscc/include/mach/common.h b/arch/mips/mach-mscc/include/mach/common.h index 931ecd7985..92a055561e 100644 --- a/arch/mips/mach-mscc/include/mach/common.h +++ b/arch/mips/mach-mscc/include/mach/common.h @@ -9,10 +9,12 @@ #if defined(CONFIG_SOC_OCELOT) #include #include +#include #include #elif defined(CONFIG_SOC_LUTON) #include #include +#include #include #else #error Unsupported platform @@ -25,4 +27,22 @@ #define VCOREIII_TIMER_DIVIDER 25 /* Clock tick ~ 0.1 us */ +/* Common utility functions */ + +int mscc_phy_rd_wr(u8 read, + u32 miim_controller, + u8 miim_addr, + u8 addr, + u16 *value); + +int mscc_phy_rd(u32 miim_controller, + u8 miim_addr, + u8 addr, + u16 *value); + +int mscc_phy_wr(u32 miim_controller, + u8 miim_addr, + u8 addr, + u16 value); + #endif /* __ASM_MACH_COMMON_H */ diff --git a/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb_miim_regs.h b/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb_miim_regs.h new file mode 100644 index 00..2303734894 --- /dev/null +++ b/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb_miim_regs.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Microsemi Ocelot Switch driver + * + * Copyright (c) 2018 Microsemi Corporation + */ + +#ifndef _MSCC_LUTON_MIIM_REGS_H_ +#define _MSCC_LUTON_MIIM_REGS_H_ + +#define MIIM_MII_STATUS(gi) (0xa0 + (gi * 36)) +#define MIIM_MII_CMD(gi)(0xa8 + (gi * 36)) +#define MIIM_MII_DATA(gi) (0xac + (gi * 36)) + +#define MSCC_F_MII_STATUS_MIIM_STAT_BUSY(x) (x ? BIT(3) : 0) + +#define MSCC_F_MII_CMD_MIIM_CMD_VLD(x)(x ? BIT(31) : 0) +#define MSCC_F_MII_CMD_MIIM_CMD_PHYAD(x) (GENMASK(29, 25) & (x << 25)) +#define MSCC_F_MII_CMD_MIIM_CMD_REGAD(x) (GENMASK(24, 20) & (x << 20)) +#define MSCC_F_MII_CMD_MIIM_CMD_WRDATA(x) (GENMASK(19, 4) & (x << 4)) +#define MSCC_F_MII_CMD_MIIM_CMD_OPR_FIELD(x) (GENMASK(2, 1) & (x << 1)) + +#define MSCC_M_MII_DATA_MIIM_DATA_SUCCESS GENMASK(17, 16) +#define MSCC_X_MII_DATA_MIIM_DATA_RDDATA(x) ((x >> 0) & GENMASK(15, 0)) + +#endif diff --git a/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb_miim_regs.h b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb_miim_regs.h new file mode 100644 index 00..4ad92214a3 --- /dev/null +++ b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb_miim_regs.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +#ifndef _MSCC_OCELOT_DEVCPU_GCB_MIIM_REGS_H_ +#define _MSCC_OCELOT_DEVCPU_GCB_MIIM_REGS_H_ + +#define MIIM_MII_STATUS(gi) (0x9c + (gi * 36)) +#define MIIM_MII_CMD(gi)(0xa4 + (gi * 36)) +#define MIIM_MII_DATA(gi) (0xa8 + (gi * 36)) + +#define MSCC_F_MII_STATUS_MIIM_STAT_BUSY(x) ((x) ? BIT(3) : 0) + +#define MSCC_F_MII_CMD_MIIM_CMD_VLD(x)((x) ? BIT(31) : 0) +#define MSCC_F_MII_CMD_MIIM_CMD_PHYAD(x) (GENMASK(29, 25) & ((x) << 25)) +#define MSCC_F_MII_CMD_MIIM_CMD_REGAD(x) (GENMASK(24, 20) & ((x) << 20)) +#define MSCC_F_MII_CMD_MIIM_CMD_WRDATA(x) (GENMASK(19, 4) & ((x) << 4)) +#define MSCC_F_MII_CMD_MIIM_CMD_OPR_FIELD(x) (GENMASK(2, 1) & ((x) << 1)) +#define MSCC_F_MII_CMD_MIIM_CMD_SCAN(x) ((x) ? BIT(0) : 0) + +#define MSCC_M_MII_DATA_MIIM_DATA_SUCCESS GENMASK(17, 16) +#define MSCC_X_MII_DATA_MIIM_DATA_RDDATA(x) (((x) >> 0) & GENMASK(15, 0)) + +#endif diff --git a/arch/mips/mach-mscc/phy.c b/arch/mips/mach-mscc/phy.c new file mode 100644 index 00..add6280e38 --- /dev/null +++ b/arch/mips/mach-mscc/phy.c @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +#include +#include + +i
[U-Boot] [PATCH 3/6] mips: mscc: Add generic GPIO control utility function
The GPIO control function can be used for controlling alternate
functions associated with a GPIO.
Signed-off-by: Lars Povlsen
---
arch/mips/mach-mscc/Makefile | 2 +-
arch/mips/mach-mscc/gpio.c| 33 +++
arch/mips/mach-mscc/include/mach/common.h | 2 ++
.../include/mach/luton/luton_devcpu_gcb.h | 2 ++
.../include/mach/ocelot/ocelot_devcpu_gcb.h | 2 ++
5 files changed, 40 insertions(+), 1 deletion(-)
create mode 100644 arch/mips/mach-mscc/gpio.c
diff --git a/arch/mips/mach-mscc/Makefile b/arch/mips/mach-mscc/Makefile
index 300c88b5cd..44538b7118 100644
--- a/arch/mips/mach-mscc/Makefile
+++ b/arch/mips/mach-mscc/Makefile
@@ -2,5 +2,5 @@
CFLAGS_cpu.o += -finline-limit=64000
-obj-y += cpu.o dram.o reset.o phy.o lowlevel_init.o
+obj-y += cpu.o dram.o reset.o phy.o gpio.o lowlevel_init.o
obj-$(CONFIG_SOC_LUTON) += lowlevel_init_luton.o
diff --git a/arch/mips/mach-mscc/gpio.c b/arch/mips/mach-mscc/gpio.c
new file mode 100644
index 00..5e3a53372d
--- /dev/null
+++ b/arch/mips/mach-mscc/gpio.c
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include
+#include
+
+void mscc_gpio_set_alternate(int gpio, int mode)
+{
+ u32 mask = BIT(gpio);
+ u32 val0, val1;
+
+ val0 = readl(BASE_DEVCPU_GCB + GPIO_ALT(0));
+ val1 = readl(BASE_DEVCPU_GCB + GPIO_ALT(1));
+
+ if (mode == 1) {
+ val0 |= mask;
+ val1 &= ~mask;
+ } else if (mode == 2) {
+ val0 &= ~mask;
+ val1 |= mask;
+ } else if (mode == 3) {
+ val0 |= mask;
+ val1 |= mask;
+ } else {
+ val0 &= ~mask;
+ val1 &= ~mask;
+ }
+
+ writel(val0, BASE_DEVCPU_GCB + GPIO_ALT(0));
+ writel(val1, BASE_DEVCPU_GCB + GPIO_ALT(1));
+}
diff --git a/arch/mips/mach-mscc/include/mach/common.h
b/arch/mips/mach-mscc/include/mach/common.h
index 92a055561e..d18ae78bfd 100644
--- a/arch/mips/mach-mscc/include/mach/common.h
+++ b/arch/mips/mach-mscc/include/mach/common.h
@@ -45,4 +45,6 @@ int mscc_phy_wr(u32 miim_controller,
u8 addr,
u16 value);
+void mscc_gpio_set_alternate(int gpio, int mode);
+
#endif /* __ASM_MACH_COMMON_H */
diff --git a/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h
b/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h
index 8c0b612325..a06cf819b0 100644
--- a/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h
+++ b/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h
@@ -11,4 +11,6 @@
#define PERF_SOFT_RST_SOFT_SWC_RSTBIT(1)
#define PERF_SOFT_RST_SOFT_CHIP_RST BIT(0)
+#define GPIO_ALT(x)(0x88 + 4 * (x))
+
#endif
diff --git a/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h
b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h
index f8aa97ba26..d3a76412e2 100644
--- a/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h
+++ b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h
@@ -18,4 +18,6 @@
#define PERF_GPIO_OE 0x44
+#define GPIO_ALT(x)(0x54 + 4 * (x))
+
#endif
--
2.19.2
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[U-Boot] [PATCH 4/6] mips: luton: DT: Add pcb090
This prepares individual device trees for MSCC luton-based reference
boards - pcb090 and pcb091.
Note: Even though the devices trees are quite common, they will differ
significantly in coming patches.
Signed-off-by: Lars Povlsen
---
arch/mips/dts/luton_pcb090.dts | 36 ++
1 file changed, 36 insertions(+)
create mode 100644 arch/mips/dts/luton_pcb090.dts
diff --git a/arch/mips/dts/luton_pcb090.dts b/arch/mips/dts/luton_pcb090.dts
new file mode 100644
index 00..a3f8926ad9
--- /dev/null
+++ b/arch/mips/dts/luton_pcb090.dts
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+/dts-v1/;
+#include "mscc,luton.dtsi"
+
+/ {
+ model = "Luton26 PCB090 Reference Board";
+ compatible = "mscc,luton-pcb090", "mscc,luton";
+
+ aliases {
+ serial0 = &uart0;
+ spi0 = &spi0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&spi0 {
+ status = "okay";
+ spi-flash@0 {
+ compatible = "spi-flash";
+ spi-max-frequency = <1800>; /* input clock */
+ reg = <0>; /* CS0 */
+ spi-cs-high;
+ };
+};
+
--
2.19.2
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[U-Boot] [PATCH 5/6] mips: luton: Add multi-dtb support
This add single-binary support for the two MSCC luton-based reference
boards - pcb090 and pcb091.
Signed-off-by: Lars Povlsen
---
arch/mips/dts/Makefile| 1 +
.../include/mach/luton/luton_devcpu_gcb.h | 2 +
board/mscc/luton/luton.c | 46 +--
configs/mscc_luton_defconfig | 7 ++-
include/configs/vcoreiii.h| 2 +
5 files changed, 52 insertions(+), 6 deletions(-)
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index 647d2bf0d5..3d436b2248 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -17,6 +17,7 @@ dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) +=
netgear,dgnd3700v2.dtb
dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f...@st1704.dtb
dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
dtb-$(CONFIG_TARGET_JZ4780_CI20) += ci20.dtb
+dtb-$(CONFIG_SOC_LUTON) += luton_pcb090.dtb luton_pcb091.dtb
targets += $(dtb-y)
diff --git a/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h
b/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h
index a06cf819b0..a74a68593d 100644
--- a/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h
+++ b/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h
@@ -13,4 +13,6 @@
#define GPIO_ALT(x)(0x88 + 4 * (x))
+#define CHIP_ID(0x08)
+
#endif
diff --git a/board/mscc/luton/luton.c b/board/mscc/luton/luton.c
index 41fc6d56a7..b509b6beb3 100644
--- a/board/mscc/luton/luton.c
+++ b/board/mscc/luton/luton.c
@@ -6,15 +6,18 @@
#include
#include
-#define MSCC_GPIO_ALT0 0x88
-#define MSCC_GPIO_ALT1 0x8C
-
DECLARE_GLOBAL_DATA_PTR;
+enum {
+ BOARD_TYPE_PCB090 = 0xAABBCD00,
+ BOARD_TYPE_PCB091,
+};
+
void board_debug_uart_init(void)
{
/* too early for the pinctrl driver, so configure the UART pins here */
- setbits_le32(BASE_DEVCPU_GCB + MSCC_GPIO_ALT0, BIT(30) | BIT(31));
+ mscc_gpio_set_alternate(30, 1);
+ mscc_gpio_set_alternate(31, 1);
}
int board_early_init_r(void)
@@ -26,3 +29,38 @@ int board_early_init_r(void)
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
return 0;
}
+
+static void do_board_detect(void)
+{
+ u32 chipid = (readl(BASE_DEVCPU_GCB + CHIP_ID) >> 12) & 0x;
+
+ if (chipid == 0x7428 || chipid == 0x7424)
+ gd->board_type = BOARD_TYPE_PCB091;// Lu10
+ else
+ gd->board_type = BOARD_TYPE_PCB090;// Lu26
+}
+
+#if defined(CONFIG_MULTI_DTB_FIT)
+int board_fit_config_name_match(const char *name)
+{
+ if (gd->board_type == BOARD_TYPE_PCB090 &&
+ strcmp(name, "luton_pcb090") == 0)
+ return 0;
+
+ if (gd->board_type == BOARD_TYPE_PCB091 &&
+ strcmp(name, "luton_pcb091") == 0)
+ return 0;
+
+ return -1;
+}
+#endif
+
+#if defined(CONFIG_DTB_RESELECT)
+int embedded_dtb_select(void)
+{
+ do_board_detect();
+ fdtdec_setup();
+
+ return 0;
+}
+#endif
diff --git a/configs/mscc_luton_defconfig b/configs/mscc_luton_defconfig
index d7476c4863..03922f5379 100644
--- a/configs/mscc_luton_defconfig
+++ b/configs/mscc_luton_defconfig
@@ -5,7 +5,7 @@ CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0x7010
CONFIG_DEBUG_UART_CLOCK=20833
CONFIG_ARCH_MSCC=y
-CONFIG_TARGET_LUTON_PCB091=y
+CONFIG_SOC_LUTON=y
CONFIG_DDRTYPE_MT47H128M8HQ=y
CONFIG_SYS_LITTLE_ENDIAN=y
CONFIG_MIPS_BOOT_FDT=y
@@ -16,7 +16,7 @@ CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
CONFIG_LOGLEVEL=7
CONFIG_DISPLAY_CPUINFO=y
-CONFIG_SYS_PROMPT="pcb091 # "
+CONFIG_SYS_PROMPT="luton # "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_ELF is not set
@@ -39,6 +39,9 @@ CONFIG_MTDIDS_DEFAULT="nor0=spi_flash"
CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:512k(UBoot),256k(Env),256k(conf),6m@1m(linux)"
# CONFIG_ISO_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="luton_pcb091"
+CONFIG_OF_LIST="luton_pcb090 luton_pcb091"
+CONFIG_DTB_RESELECT=y
+CONFIG_MULTI_DTB_FIT=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_CLK=y
diff --git a/include/configs/vcoreiii.h b/include/configs/vcoreiii.h
index df89cdaebf..4ea5f40ec5 100644
--- a/include/configs/vcoreiii.h
+++ b/include/configs/vcoreiii.h
@@ -22,6 +22,8 @@
#endif
#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_MIPS_TIMER_FREQ
+#define CONFIG_BOARD_TYPES
+
#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET)
#define CONFIG_ENV_OFFSET (1024 * 1024)
#define CONFIG_ENV_SIZE(256 * 1024)
--
2.19.2
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[U-Boot] [PATCH 6/6] mips: ocelot: Add multi-dtb support
This add single-binary support for the two MSCC ocelot-based reference
boards - pcb120 and pcb123.
The PHY ids on specific ports are used to determine the board type.
Signed-off-by: Lars Povlsen
---
arch/mips/dts/Makefile | 1 +
board/mscc/ocelot/ocelot.c | 52 +---
configs/mscc_ocelot_defconfig| 7 ++--
configs/mscc_ocelot_pcb120_defconfig | 60
4 files changed, 51 insertions(+), 69 deletions(-)
delete mode 100644 configs/mscc_ocelot_pcb120_defconfig
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index 3d436b2248..b61afe6504 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -18,6 +18,7 @@ dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f...@st1704.dtb
dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
dtb-$(CONFIG_TARGET_JZ4780_CI20) += ci20.dtb
dtb-$(CONFIG_SOC_LUTON) += luton_pcb090.dtb luton_pcb091.dtb
+dtb-$(CONFIG_SOC_OCELOT) += ocelot_pcb120.dtb ocelot_pcb123.dtb
targets += $(dtb-y)
diff --git a/board/mscc/ocelot/ocelot.c b/board/mscc/ocelot/ocelot.c
index d521a61957..a557cacd1b 100644
--- a/board/mscc/ocelot/ocelot.c
+++ b/board/mscc/ocelot/ocelot.c
@@ -12,16 +12,18 @@
DECLARE_GLOBAL_DATA_PTR;
-#define MSCC_GPIO_ALT0 0x54
-#define MSCC_GPIO_ALT1 0x58
+enum {
+ BOARD_TYPE_PCB120 = 0xAABBCC00,
+ BOARD_TYPE_PCB123,
+};
void external_cs_manage(struct udevice *dev, bool enable)
{
u32 cs = spi_chip_select(dev);
/* IF_SI0_OWNER, select the owner of the SI interface
* Encoding: 0: SI Slave
-* 1: SI Boot Master
-* 2: SI Master Controller
+* 1: SI Boot Master
+* 2: SI Master Controller
*/
if (!enable) {
writel(ICPU_SW_MODE_SW_PIN_CTRL_MODE |
@@ -40,8 +42,8 @@ void external_cs_manage(struct udevice *dev, bool enable)
void board_debug_uart_init(void)
{
/* too early for the pinctrl driver, so configure the UART pins here */
- setbits_le32(BASE_DEVCPU_GCB + MSCC_GPIO_ALT0, BIT(6) | BIT(7));
- clrbits_le32(BASE_DEVCPU_GCB + MSCC_GPIO_ALT1, BIT(6) | BIT(7));
+ mscc_gpio_set_alternate(6, 1);
+ mscc_gpio_set_alternate(7, 1);
}
int board_early_init_r(void)
@@ -56,3 +58,41 @@ int board_early_init_r(void)
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
return 0;
}
+
+static void do_board_detect(void)
+{
+ u16 dummy = 0;
+
+ /* Enable MIIM */
+ mscc_gpio_set_alternate(14, 1);
+ mscc_gpio_set_alternate(15, 1);
+ if (mscc_phy_rd(1, 0, 0, &dummy) == 0)
+ gd->board_type = BOARD_TYPE_PCB120;
+ else
+ gd->board_type = BOARD_TYPE_PCB123;
+}
+
+#if defined(CONFIG_MULTI_DTB_FIT)
+int board_fit_config_name_match(const char *name)
+{
+ if (gd->board_type == BOARD_TYPE_PCB120 &&
+ strcmp(name, "ocelot_pcb120") == 0)
+ return 0;
+
+ if (gd->board_type == BOARD_TYPE_PCB123 &&
+ strcmp(name, "ocelot_pcb123") == 0)
+ return 0;
+
+ return -1;
+}
+#endif
+
+#if defined(CONFIG_DTB_RESELECT)
+int embedded_dtb_select(void)
+{
+ do_board_detect();
+ fdtdec_setup();
+
+ return 0;
+}
+#endif
diff --git a/configs/mscc_ocelot_defconfig b/configs/mscc_ocelot_defconfig
index 5fa74db2ff..66451000d9 100644
--- a/configs/mscc_ocelot_defconfig
+++ b/configs/mscc_ocelot_defconfig
@@ -5,7 +5,6 @@ CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0x7010
CONFIG_DEBUG_UART_CLOCK=25000
CONFIG_ARCH_MSCC=y
-CONFIG_TARGET_OCELOT_PCB123=y
CONFIG_SYS_LITTLE_ENDIAN=y
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
@@ -14,7 +13,7 @@ CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
CONFIG_LOGLEVEL=7
CONFIG_DISPLAY_CPUINFO=y
-CONFIG_SYS_PROMPT="pcb123 # "
+CONFIG_SYS_PROMPT="ocelot # "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_ELF is not set
@@ -40,6 +39,9 @@ CONFIG_CMD_UBI=y
# CONFIG_CMD_UBIFS is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="ocelot_pcb123"
+CONFIG_OF_LIST="ocelot_pcb120 ocelot_pcb123"
+CONFIG_DTB_RESELECT=y
+CONFIG_MULTI_DTB_FIT=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_CLK=y
@@ -63,5 +65,4 @@ CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
-CONFIG_DESIGNWARE_SPI=y
CONFIG_LZMA=y
diff --git a/configs/mscc_ocelot_pcb120_defconfig
b/configs/mscc_ocelot_pcb120_defconfig
deleted file mode 100644
index c5a9f96977..00
--- a/configs/mscc_ocelot_pcb120_defconfig
+++ /dev/null
@@ -1,60 +0,0 @@
-CONFIG_MIPS=y
-CONFIG_SYS_TEXT_BASE=0x4000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_ARCH_MSCC=y
-CONFIG_SYS_LITTLE_ENDIAN=y
-CONFIG_FIT=y
-CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200"
-CONFIG_LOGLEVEL=7
-CONFIG_DISPLAY_CPUINFO=y
-CONFIG_SYS_PROMPT="pcb120 # "
-# CONFIG_CMD_BDI is not set
-#
Re: [U-Boot] i.MX8M layout, rephrased
Hi Sergey, > -Original Message- > From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Sergey > Kubushyn > Sent: 2018年12月18日 9:54 > To: U-Boot list > Subject: [U-Boot] i.MX8M layout, rephrased > > I'm looking at U-Boot master tree and u-boot-imx repository. What we have > now is quite a mess for i.MX8M. > > In master we have the following directories: > > arch/arm/mach-imx/imx8 > arch/arm/mach-imx/mx8m > > arch/arm/include/asm/arch-imx8 > arch/arm/include/asm/arch-mx8m > > In u-boot-imx it is different: > > arch/arm/mach-imx/imx8 > arch/arm/mach-imx/imx8m (vs ../mx8m in master) > > arch/arm/include/asm/arch/arch-imx8 > arch/arm/include/asm/arch/arch-imx8m (vs ../mx8m in master) > > The question is which one is going to make it in the master tree? i.MX8/8X/8M are 3 soc families. i.MX8/8X share similar architecture, so code mostly under imx8 or arch-imx8 i.MX8MQ/MM share similar architecture, so code mostly under imx8m or arch-imx8m. > > The problem here is that files from those directories are referenced in > multiple places and the "imx8m"/"mx8m" is all over in the header files and > sources so once we decided on either naming one tree would have to make a > lot of changes either adding or removing that 'i' before "mx8m". For newer i.MX SoCs, we will add the "i" to represent i.MX brand. > > Can anybody responsible tell _WHICH_ one is going to make it into the main > source tree? Would it be better if we decide on it sooner than later (i.e. > _NOW_) so we won't have to hunt it all over the tree later on? > > I assume it should be "mx8m" as it is in master tree following suit for other > flavors so it is u-boot-imx tree that has to be fixed. http://git.denx.de/?p=u-boot/u-boot-imx.git;a=commit;h=3d145ff59d183850f11ba4157f03d05fc2fcb992 imx tree has switch to imx8m, and the patch will be merged to master tree, so the master will also switch to imx8m. > > > Another issue is that ARCH_IMX8 and ARCH_IMX8M are treated as different > ARCHITECTURES in u-boot-imx unlike e.g. IMX6 that is treated as one ARCH > with different flavors (SX/DL/Q/whatever). That makes a lot of unnecessary > confusion and, IMHO, should be somehow cleaned up to make it consistent. IMX8 and IMX8M uses totally different architecture. Regards, Peng. > > > Can anybody tell something on this? Any thoughts, ideas, recomendations? > > --- > ** > > * KSI@homeKOI8 Net < > The impossible we do immediately. * > * Las Vegas NV, USA < > Miracles require 24-hour notice. * > ** > > ___ > U-Boot mailing list > U-Boot@lists.denx.de > https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists. > denx.de%2Flistinfo%2Fu-boot&data=02%7C01%7CPeng.Fan%40nxp.co > m%7Cf91122ecf133487aa45608d6648bc117%7C686ea1d3bc2b4c6fa92cd99 > c5c301635%7C0%7C0%7C636806948762235491&sdata=202DqjIQfSABs > BtuLUN0QvbhadrtMP61mGnmH1QMUpI%3D&reserved=0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 00/10] i.MX8QXP: MEK: support SPL
This is to support SPL for i.MX8QXP MEK board and default support SPL. In this patchset, use SPL FIT, but actually we could not use SPL FIT for secure boot, in NXP vendor tree, there is another format called container, NXP use SPL + container for secure boot. The container support is on my TODO list. But to make SPL work in upstream, use SPL FIT here. Peng Fan (10): imx8qxp: add SUPPORT_SPL option imx8: scu: use dedicated MU for SPL arm: imx: build mach-imx for i.MX8 gpio: introduce CONFIG_SPL_DM_PCA953X spl: imx8: add spl boot device dts: imx8qxp-mek: introduce u-boot dtsi imx: mkimage_fit_atf: introduce BL33_BASE_ADDR imx: build flash.bin for i.MX8 imx8qxp: mek: default enable SPL imx8qxp: mek: update README Makefile | 2 +- arch/arm/Makefile| 2 +- arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi | 112 +++ arch/arm/dts/fsl-imx8qxp-mek.dts | 1 + arch/arm/mach-imx/Makefile | 15 - arch/arm/mach-imx/imx8/Kconfig | 8 +++ arch/arm/mach-imx/mkimage_fit_atf.sh | 3 +- arch/arm/mach-imx/spl.c | 14 +++- board/freescale/imx8qxp_mek/Makefile | 1 + board/freescale/imx8qxp_mek/README | 8 ++- board/freescale/imx8qxp_mek/imximage.cfg | 4 +- board/freescale/imx8qxp_mek/spl.c| 75 + configs/imx8qxp_mek_defconfig| 24 +++ drivers/gpio/Kconfig | 23 +++ drivers/gpio/Makefile| 2 +- drivers/misc/imx8/scu.c | 4 ++ include/configs/imx8qxp_mek.h| 26 +++ 17 files changed, 311 insertions(+), 13 deletions(-) create mode 100644 arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi create mode 100644 board/freescale/imx8qxp_mek/spl.c -- 2.14.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 01/10] imx8qxp: add SUPPORT_SPL option
Enable SUPPORT_SPL option for i.MX8QXP, then we could enable SPL. Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index 0d3a87cd74..9671107cb6 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -5,6 +5,7 @@ config IMX8 config IMX8QXP select IMX8 + select SUPPORT_SPL bool config SYS_SOC -- 2.14.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 03/10] arm: imx: build mach-imx for i.MX8
To enable SPL for i.MX8, we could reuse code in arch/arm/mach-imx. Signed-off-by: Peng Fan --- arch/arm/Makefile | 2 +- arch/arm/mach-imx/Makefile | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 87d9d4b9f7..0e2cfd4534 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -103,7 +103,7 @@ libs-y += arch/arm/cpu/ libs-y += arch/arm/lib/ ifeq ($(CONFIG_SPL_BUILD),y) -ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m)) +ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8)) libs-y += arch/arm/mach-imx/ endif else diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 04783fa04e..5424848ad3 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -24,7 +24,7 @@ obj-y += cpu.o speed.o obj-$(CONFIG_GPT_TIMER) += timer.o obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o endif -ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs imx8m)) +ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs imx8m imx8)) obj-y += misc.o obj-$(CONFIG_SPL_BUILD)+= spl.o endif -- 2.14.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 04/10] gpio: introduce CONFIG_SPL_DM_PCA953X
Introduce CONFIG_SPL_DM_PCA953X for SPL usage. Signed-off-by: Peng Fan --- drivers/gpio/Kconfig | 23 +++ drivers/gpio/Makefile | 2 +- 2 files changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 35344e57c6..b1c9404aaf 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -292,6 +292,29 @@ config DM_PCA953X Now, max 24 bits chips and PCA953X compatible chips are supported +config SPL_DM_PCA953X + bool "PCA95[357]x, PCA9698, TCA64xx, and MAX7310 I/O ports in SPL" + depends on DM_GPIO + help + Say yes here to provide access to several register-oriented + SMBus I/O expanders, made mostly by NXP or TI. Compatible + models include: + + 4 bits: pca9536, pca9537 + + 8 bits: max7310, max7315, pca6107, pca9534, pca9538, pca9554, + pca9556, pca9557, pca9574, tca6408, xra1202 + + 16 bits: max7312, max7313, pca9535, pca9539, pca9555, pca9575, + tca6416 + + 24 bits: tca6424 + + 40 bits: pca9505, pca9698 + + Now, max 24 bits chips and PCA953X compatible chips are + supported + config MPC8XXX_GPIO bool "Freescale MPC8XXX GPIO driver" depends on DM_GPIO diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 7ed9a4ec42..dac238ae06 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -9,7 +9,7 @@ obj-$(CONFIG_AXP_GPIO) += axp_gpio.o endif obj-$(CONFIG_DM_GPIO) += gpio-uclass.o -obj-$(CONFIG_DM_PCA953X) += pca953x_gpio.o +obj-$(CONFIG_$(SPL_)DM_PCA953X)+= pca953x_gpio.o obj-$(CONFIG_DM_74X164)+= 74x164_gpio.o obj-$(CONFIG_AT91_GPIO)+= at91_gpio.o -- 2.14.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 07/10] imx: mkimage_fit_atf: introduce BL33_BASE_ADDR
Introduce BL33_BASE_ADDR, then we could reuse this script for i.MX8QXP.
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/mkimage_fit_atf.sh | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/mkimage_fit_atf.sh
b/arch/arm/mach-imx/mkimage_fit_atf.sh
index 77f7143263..38c9858e84 100755
--- a/arch/arm/mach-imx/mkimage_fit_atf.sh
+++ b/arch/arm/mach-imx/mkimage_fit_atf.sh
@@ -9,6 +9,7 @@
[ -z "$BL31" ] && BL31="bl31.bin"
[ -z "$TEE_LOAD_ADDR" ] && TEE_LOAD_ADDR="0xfe00"
[ -z "$ATF_LOAD_ADDR" ] && ATF_LOAD_ADDR="0x0091"
+[ -z "$BL33_LOAD_ADDR" ] && BL33_LOAD_ADDR="0x4020"
if [ ! -f $BL31 ]; then
echo "ERROR: BL31 file $BL31 NOT found" >&2
@@ -58,7 +59,7 @@ cat << __HEADER_EOF
type = "standalone";
arch = "arm64";
compression = "none";
- load = <0x4020>;
+ load = <$BL33_LOAD_ADDR>;
};
atf@1 {
description = "ARM Trusted Firmware";
--
2.14.1
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[U-Boot] [PATCH 05/10] spl: imx8: add spl boot device
Add spl_boot_device for i.MX8, also add BOOT_DEVICE_MMC2_2 for
spl_boot_mode.
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/spl.c | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c
index 58a92278df..3ee5061b08 100644
--- a/arch/arm/mach-imx/spl.c
+++ b/arch/arm/mach-imx/spl.c
@@ -96,7 +96,7 @@ u32 spl_boot_device(void)
return BOOT_DEVICE_NONE;
}
-#elif defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
+#elif defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8)
/* Translate iMX7/i.MX8M boot device to the SPL boot device enumeration */
u32 spl_boot_device(void)
{
@@ -134,6 +134,15 @@ u32 spl_boot_device(void)
case SD3_BOOT:
case MMC3_BOOT:
return BOOT_DEVICE_MMC1;
+#elif defined(CONFIG_IMX8)
+ case MMC1_BOOT:
+ return BOOT_DEVICE_MMC1;
+ case SD2_BOOT:
+ return BOOT_DEVICE_MMC2_2;
+ case SD3_BOOT:
+ return BOOT_DEVICE_MMC1;
+ case FLEXSPI_BOOT:
+ return BOOT_DEVICE_SPI;
#elif defined(CONFIG_IMX8M)
case SD1_BOOT:
case MMC1_BOOT:
@@ -152,7 +161,7 @@ u32 spl_boot_device(void)
return BOOT_DEVICE_NONE;
}
}
-#endif /* CONFIG_MX7 || CONFIG_IMX8M */
+#endif /* CONFIG_MX7 || CONFIG_IMX8M || CONFIG_IMX8 */
#ifdef CONFIG_SPL_USB_GADGET_SUPPORT
int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
@@ -171,6 +180,7 @@ u32 spl_boot_mode(const u32 boot_device)
/* for MMC return either RAW or FAT mode */
case BOOT_DEVICE_MMC1:
case BOOT_DEVICE_MMC2:
+ case BOOT_DEVICE_MMC2_2:
#if defined(CONFIG_SPL_FAT_SUPPORT)
return MMCSD_MODE_FS;
#elif defined(CONFIG_SUPPORT_EMMC_BOOT)
--
2.14.1
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[U-Boot] [PATCH 02/10] imx8: scu: use dedicated MU for SPL
SPL runs in EL3 mode, except MU0_A, others are not powered on, and could not be used. However normal U-Boot use MU1_A, so we could not reuse the one in dts. And we could not replace the one in dts with MU0_A, because MU0_A is reserved in secure world. Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8/Kconfig | 7 +++ drivers/misc/imx8/scu.c| 4 2 files changed, 11 insertions(+) diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index 9671107cb6..f76a139684 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -3,6 +3,13 @@ if ARCH_IMX8 config IMX8 bool +config MU_BASE_SPL + hex "MU base address used in SPL" + default 0x5d1b + help + SPL runs in EL3 mode, it use MU0_A to communicate with SCU. + So we could not reuse the one in dts which is for normal U-Boot. + config IMX8QXP select IMX8 select SUPPORT_SPL diff --git a/drivers/misc/imx8/scu.c b/drivers/misc/imx8/scu.c index 15101b3e5f..1b9c49c99c 100644 --- a/drivers/misc/imx8/scu.c +++ b/drivers/misc/imx8/scu.c @@ -191,7 +191,11 @@ static int imx8_scu_probe(struct udevice *dev) if (addr == FDT_ADDR_T_NONE) return -EINVAL; +#ifdef CONFIG_SPL_BUILD + plat->base = (struct mu_type *)CONFIG_MU_BASE_SPL; +#else plat->base = (struct mu_type *)addr; +#endif /* U-Boot not enable interrupts, so need to enable RX interrupts */ mu_hal_init(plat->base); -- 2.14.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 06/10] dts: imx8qxp-mek: introduce u-boot dtsi
Introduce u-boot dtsi for i.MX8QXP MEK board.
we do not introduce a common dtsi for SoC, because different board
has different requirement on which needs to be enabled in SPL DM.
Signed-off-by: Peng Fan
---
arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi | 112 +++
arch/arm/dts/fsl-imx8qxp-mek.dts | 1 +
2 files changed, 113 insertions(+)
create mode 100644 arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
diff --git a/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
b/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
new file mode 100644
index 00..5d50eb028e
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
@@ -0,0 +1,112 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+&mu {
+ u-boot,dm-spl;
+};
+
+&clk {
+ u-boot,dm-spl;
+};
+
+&iomuxc {
+ u-boot,dm-spl;
+};
+
+&pd_lsio {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio0 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio1 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio2 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio3 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio4 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio5 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio6 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio7 {
+ u-boot,dm-spl;
+};
+
+&pd_conn {
+ u-boot,dm-spl;
+};
+
+&pd_conn_sdch0 {
+ u-boot,dm-spl;
+};
+
+&pd_conn_sdch1 {
+ u-boot,dm-spl;
+};
+
+&pd_conn_sdch2 {
+ u-boot,dm-spl;
+};
+
+&gpio0 {
+ u-boot,dm-spl;
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+};
+
+&gpio3 {
+ u-boot,dm-spl;
+};
+
+&gpio4 {
+ u-boot,dm-spl;
+};
+
+&gpio5 {
+ u-boot,dm-spl;
+};
+
+&gpio6 {
+ u-boot,dm-spl;
+};
+
+&gpio7 {
+ u-boot,dm-spl;
+};
+
+&lpuart0 {
+ u-boot,dm-spl;
+};
+
+&usdhc1 {
+ u-boot,dm-spl;
+};
+
+&usdhc2 {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/fsl-imx8qxp-mek.dts b/arch/arm/dts/fsl-imx8qxp-mek.dts
index adab494cdf..41f7ec1763 100644
--- a/arch/arm/dts/fsl-imx8qxp-mek.dts
+++ b/arch/arm/dts/fsl-imx8qxp-mek.dts
@@ -6,6 +6,7 @@
/dts-v1/;
#include "fsl-imx8qxp.dtsi"
+#include "fsl-imx8qxp-mek-u-boot.dtsi"
/ {
model = "Freescale i.MX8QXP MEK";
--
2.14.1
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[U-Boot] [PATCH 08/10] imx: build flash.bin for i.MX8
Build flash.bin for i.MX8 when SPL enabled. Signed-off-by: Peng Fan --- Makefile | 2 +- arch/arm/mach-imx/Makefile | 13 + 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 74d4259eb6..e9a0d3ab3a 100644 --- a/Makefile +++ b/Makefile @@ -1200,7 +1200,7 @@ tpl/u-boot-with-tpl.bin: tpl/u-boot-tpl.bin u-boot.bin FORCE SPL: spl/u-boot-spl.bin FORCE $(Q)$(MAKE) $(build)=arch/arm/mach-imx $@ -ifeq ($(CONFIG_ARCH_IMX8M), y) +ifeq ($(CONFIG_ARCH_IMX8M)$(CONFIG_ARCH_IMX8), y) flash.bin: spl/u-boot-spl.bin u-boot.itb FORCE $(Q)$(MAKE) $(build)=arch/arm/mach-imx $@ endif diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 5424848ad3..e84798b35c 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -105,6 +105,7 @@ IMX_CONFIG = $(CONFIG_IMX_CONFIG:"%"=%) ifeq ($(CONFIG_ARCH_IMX8), y) CNTR_DEPFILES := $(srctree)/tools/imx_cntr_image.sh IMAGE_TYPE := imx8image +SPL_DEPFILE_EXISTS := $(shell $(CPP) $(cpp_flags) -x c -o spl/u-boot-spl.cfgout $(srctree)/$(IMX_CONFIG); if [ -f spl/u-boot-spl.cfgout ]; then $(CNTR_DEPFILES) spl/u-boot-spl.cfgout; echo $$?; fi) DEPFILE_EXISTS := $(shell $(CPP) $(cpp_flags) -x c -o u-boot-dtb.cfgout $(srctree)/$(IMX_CONFIG); if [ -f u-boot-dtb.cfgout ]; then $(CNTR_DEPFILES) u-boot-dtb.cfgout; echo $$?; fi) else ifeq ($(CONFIG_ARCH_IMX8M), y) IMAGE_TYPE := imx8mimage @@ -153,6 +154,18 @@ ifeq ($(DEPFILE_EXISTS),0) endif endif +ifeq ($(CONFIG_ARCH_IMX8), y) +SPL: + +MKIMAGEFLAGS_flash.bin = -n spl/u-boot-spl.cfgout -T $(IMAGE_TYPE) -e 0x10 +flash.bin: MKIMAGEOUTPUT = flash.log + +flash.bin: spl/u-boot-spl.bin u-boot.itb FORCE +ifeq ($(SPL_DEPFILE_EXISTS),0) + $(call if_changed,mkimage) +endif +endif + else MKIMAGEFLAGS_SPL = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) \ -T $(IMAGE_TYPE) -e $(CONFIG_SPL_TEXT_BASE) -- 2.14.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 10/10] imx8qxp: mek: update README
Update README after we switch to use SPL Signed-off-by: Peng Fan --- board/freescale/imx8qxp_mek/README | 8 +--- include/configs/imx8qxp_mek.h | 2 +- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/board/freescale/imx8qxp_mek/README b/board/freescale/imx8qxp_mek/README index e91e193d11..f32290e3a2 100644 --- a/board/freescale/imx8qxp_mek/README +++ b/board/freescale/imx8qxp_mek/README @@ -39,16 +39,18 @@ $ cp imx-sc-firmware-0.7/mx8qx-mek-scfw-tcm.bin . Build U-Boot - +$ export ATF_LOAD_ADDR=0x8000 +$ export BL33_LOAD_ADDR=0x8002 $ make imx8qxp_mek_defconfig -$ make +$ make flash.bin +$ dd if=u-boot.itb of=flash.bin bs=512 seek=528 Flash the binary into the SD card = Burn the flash.bin binary to SD card offset 32KB: -$ sudo dd if=u-boot-dtb.imx of=/dev/sd[x] bs=1024 seek=32 +$ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32 Boot diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h index 5372e7f95e..312e30dc6c 100644 --- a/include/configs/imx8qxp_mek.h +++ b/include/configs/imx8qxp_mek.h @@ -10,7 +10,7 @@ #include #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_TEXT_BASE 0x10 +#define CONFIG_SPL_TEXT_BASE 0x0 #define CONFIG_SPL_MAX_SIZE(124 * 1024) #define CONFIG_SYS_MONITOR_LEN (1024 * 1024) #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR -- 2.14.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 09/10] imx8qxp: mek: default enable SPL
Enable SPL for i.MX8QXP MEK, and currently use SPL FIT.
The SPL enable SPL_DM to use MMC/PINCTRL/POWER DOMAIN/CLK.
Note: SPL FIT could not support secure boot chain, because i.MX8/8X
only support i.MX container format. This container format has
not been upstreamed, so we use FIT for now. When SPL container
supported, we could switch to that.
Signed-off-by: Peng Fan
---
board/freescale/imx8qxp_mek/Makefile | 1 +
board/freescale/imx8qxp_mek/imximage.cfg | 4 +-
board/freescale/imx8qxp_mek/spl.c| 75
configs/imx8qxp_mek_defconfig| 24 ++
include/configs/imx8qxp_mek.h| 26 +++
5 files changed, 127 insertions(+), 3 deletions(-)
create mode 100644 board/freescale/imx8qxp_mek/spl.c
diff --git a/board/freescale/imx8qxp_mek/Makefile
b/board/freescale/imx8qxp_mek/Makefile
index f9ee8aeff3..acaadcd84a 100644
--- a/board/freescale/imx8qxp_mek/Makefile
+++ b/board/freescale/imx8qxp_mek/Makefile
@@ -5,3 +5,4 @@
#
obj-y += imx8qxp_mek.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
diff --git a/board/freescale/imx8qxp_mek/imximage.cfg
b/board/freescale/imx8qxp_mek/imximage.cfg
index bbffb1a88f..259a1646bf 100644
--- a/board/freescale/imx8qxp_mek/imximage.cfg
+++ b/board/freescale/imx8qxp_mek/imximage.cfg
@@ -19,6 +19,4 @@ CONTAINER
/* Add scfw image with exec attribute */
IMAGE SCU mx8qx-mek-scfw-tcm.bin
/* Add ATF image with exec attribute */
-IMAGE A35 bl31.bin 0x8000
-/* Add U-Boot image with load attribute */
-DATA A35 u-boot-dtb.bin 0x8002
+IMAGE A35 spl/u-boot-spl.bin 0x0010
diff --git a/board/freescale/imx8qxp_mek/spl.c
b/board/freescale/imx8qxp_mek/spl.c
new file mode 100644
index 00..95ce9f37e8
--- /dev/null
+++ b/board/freescale/imx8qxp_mek/spl.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void spl_board_init(void)
+{
+ struct udevice *dev;
+ int offset;
+
+ uclass_find_first_device(UCLASS_MISC, &dev);
+
+ for (; dev; uclass_find_next_device(&dev)) {
+ if (device_probe(dev))
+ continue;
+ }
+
+ offset = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "nxp,imx8-pd");
+ while (offset != -FDT_ERR_NOTFOUND) {
+ lists_bind_fdt(gd->dm_root, offset_to_ofnode(offset),
+ NULL, true);
+ offset = fdt_node_offset_by_compatible(gd->fdt_blob, offset,
+ "nxp,imx8-pd");
+ }
+
+ uclass_find_first_device(UCLASS_POWER_DOMAIN, &dev);
+
+ for (; dev; uclass_find_next_device(&dev)) {
+ if (device_probe(dev))
+ continue;
+ }
+
+ arch_cpu_init();
+
+ board_early_init_f();
+
+ timer_init();
+
+ preloader_console_init();
+
+ puts("Normal Boot\n");
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ /* Just empty function now - can't decide what to choose */
+ debug("%s: %s\n", __func__, name);
+
+ return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+ /* Clear global data */
+ memset((void *)gd, 0, sizeof(gd_t));
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ board_init_r(NULL, 0);
+}
diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig
index 58b4ca0861..a87dbd17ff 100644
--- a/configs/imx8qxp_mek_defconfig
+++ b/configs/imx8qxp_mek_defconfig
@@ -1,11 +1,28 @@
CONFIG_ARM=y
CONFIG_ARCH_IMX8=y
CONFIG_SYS_TEXT_BASE=0x8002
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_IMX8QXP_MEK=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
CONFIG_NR_DRAM_BANKS=3
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qxp_mek/imximage.cfg"
CONFIG_BOOTDELAY=3
+CONFIG_LOG=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_IMPORTENV is not set
CONFIG_CMD_CLK=y
@@ -18,8 +35,11 @@ CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_FAT=y
+CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek"
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
CONFIG_CLK_IMX8=y
CONFIG_CPU=y
CONFIG_DM_GPIO=y
@@ -41,12 +61,16 @@ CONFIG_FEC_MXC_MDIO_BASE=0x5B04
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX8=y
CONFIG_POWER_DOMAIN=y
CONFIG_IMX8_POWER_DOMAIN=y
CONFIG_DM_REGULATOR=y
+CONF
[U-Boot] getting usb working
Hi, i'm trying to get USB working in uboot. first thing i've noticed: usb3 and usb2 cannot be used together (multiple definition of "submit_control_msg" and other functions). next i try to enable usb-command (which seems to be needed), then i get this: common/usb_storage.c: In function ‘usb_stor_probe_device’: common/usb_storage.c:206:32: error: ‘struct usb_device’ has no member named ‘dev’; did you mean ‘devnum’? data = dev_get_platdata(udev->dev); ^~~ devnum common/usb_storage.c:216:34: error: ‘struct usb_device’ has no member named ‘dev’; did you mean ‘devnum’? ret = blk_create_devicef(udev->dev, "usb_storage_blk", str, ^~~ devnum is there a vendor-specific driver (bpi-r2) missing or do i make anything wrong? how about sata...is there anything needed from vendor? regards Frank ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] getting usb working
it seems that "Enable driver model for USB" (DM_USB) is needed for this...after
enabling this i can build it, but uboot hangs after autoboot-message
CPU: MediaTek MT7623 E3
DRAM: 2 GiB
MMC: Loading Environment from MMC... board/mediatek/mt7623/mt7623_rfb.c:39 mmv
Boot From SD(id:1)
*** Warning - No MMC card found, using default environment
In:serial
Out: serial
Err: serial
Net: Net Initialization Skipped
No ethernet found.
Hit any key to stop autoboot: 0
any thoughts?
after disabling usb (cli+driver), my env can be read from MMC (i had not
selected usb-env) and bootcmd works as expected. seems initialization of usb
breaks mmc-initialization and bootup
CPU: MediaTek MT7623 E3
DRAM: 2 GiB
MMC: mmc@1123: 0, mmc@1124: 1
Loading Environment from MMC... board/mediatek/mt7623/mt7623_rfb.c:39 mmc_get_ev
Boot From SD(id:1)
OK
In:serial
Out: serial
Err: serial
Net: Net Initialization Skipped
No ethernet found.
Hit any key to stop autoboot: 0
Interface: MMC
Device 1: Vendor: Man 1b Snr a42cb700 Rev: 7.8 Prod: 0
Type: Removable Hard Disk
Capacity: 7788.0 MB = 7.6 GB (15949824 x 512)
Filesystem: FAT16 "BPI-BOOT "
Boot from SD
960 bytes read in 6 ms (156.3 KiB/s)
i guess the hang results in mmc-init (which seems to fail) and my bootcmd-chain
U-Boot> printenv bootcmd
bootcmd=setenv bootdelay 3; run reloadmenu;
U-Boot> printenv reloadmenu
reloadmenu=run selectmmc;if run checkenv; then run loadbootenv; else echo file
not found; fi;bootmenu;
U-Boot> printenv selectmmc
selectmmc=if run checksd; then echo Boot from SD ; setenv partition 1:1;else
echo Boot from eMMC; setenv partition 0:1 ; fi;
U-Boot> printenv checksd
checksd=fatinfo ${device} 1:1
U-Boot> printenv checkenv
checkenv=test -e ${device} ${partition} ${bpi}/${board}/${service}/${bootenv}
why does usb influence mmc-init? what else is needed to get USB working
(DTS-nodes,driver,..)?
regards Frank
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[U-Boot] [PATCH] MIPS: remove local_irq_[save|restore] from CP0 macros
With moving write_on_tlb() to arch/mips/include/asm/mipsregs.h
there are now compiler warnings when some generic code includes
asm/io.h. This happens for example when enabling OF live tree.
Signed-off-by: Daniel Schwierzeck
---
arch/mips/include/asm/mipsregs.h | 7 ---
1 file changed, 7 deletions(-)
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 930562ebb2..f80311e64e 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -1013,9 +1013,7 @@ do {
\
#define __read_64bit_c0_split(source, sel) \
({ \
unsigned long long __val; \
- unsigned long __flags; \
\
- local_irq_save(__flags);\
if (sel == 0) \
__asm__ __volatile__( \
".set\tmips64\n\t" \
@@ -1034,16 +1032,12 @@ do {
\
"dsra\t%L0, %L0, 32\n\t"\
".set\tmips0" \
: "=r" (__val));\
- local_irq_restore(__flags); \
\
__val; \
})
#define __write_64bit_c0_split(source, sel, val) \
do { \
- unsigned long __flags; \
- \
- local_irq_save(__flags);\
if (sel == 0) \
__asm__ __volatile__( \
".set\tmips64\n\t" \
@@ -1064,7 +1058,6 @@ do {
\
"dmtc0\t%L0, " #source ", " #sel "\n\t" \
".set\tmips0" \
: : "r" (val)); \
- local_irq_restore(__flags); \
} while (0)
#define __readx_32bit_c0_register(source) \
--
2.20.1
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Re: [U-Boot] [PATCH u-boot] arm: dts: s400: Fix status for eMMC and SDIO ports
On Mon, 2018-12-17 at 10:26 +0100, Neil Armstrong wrote:
> Under U-boot, the WiFi SDIO Module should be disabled and the
> eMMC modules should be enabled, so this patch adds an s400-u-boot.dtsi
> include file specific for U-Boot that will be included by the build system.
>
> Signed-off-by: Neil Armstrong
Tested-by: Jerome Brunet
> ---
> arch/arm/dts/meson-axg-s400-u-boot.dtsi | 14 ++
> 1 file changed, 14 insertions(+)
> create mode 100644 arch/arm/dts/meson-axg-s400-u-boot.dtsi
>
> diff --git a/arch/arm/dts/meson-axg-s400-u-boot.dtsi b/arch/arm/dts/meson-
> axg-s400-u-boot.dtsi
> new file mode 100644
> index 00..c46eb3f38d
> --- /dev/null
> +++ b/arch/arm/dts/meson-axg-s400-u-boot.dtsi
> @@ -0,0 +1,14 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
> + */
> +
> +/* wifi module */
> +&sd_emmc_b {
> + status = "disabled";
> +};
> +
> +/* emmc storage */
> +&sd_emmc_c {
> + status = "okay";
> +};
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[U-Boot] [PULL] MIPS updates for v2019.01
Hi Tom, though it's a little big for rc2, it's beside some bugfixes almost only new code which is isolated to drivers and MIPS. The patches were on the list for several weeks/months but the review process took a bit longer. Please consider pulling, thanks. https://travis-ci.org/danielschwierzeck/u-boot/builds/470042933 The following changes since commit 1f2e948d6d53f77a2ddb2dde3531b0d5bc2815ad: Prepare v2019.01-rc2 (2018-12-17 20:25:24 -0500) are available in the Git repository at: git://git.denx.de/u-boot-mips.git tags/mips-updates-for-2019.11 for you to fetch changes up to 25c7de2255128743fcbe436b6f3b17a70d0cdd82: mips: jz47xx: Add Creator CI20 platform (2018-12-19 15:23:02 +0100) - mips: fix some DTC warnings - bmips: bcm6348: add DMA driver - bmips: bcm5348: add ethernet driver - bmips: bcm6368: add ethernet driver - mips: mt76xx: fix DMA problems, disable CONFIG_OF_EMBED - mips: mscc: add support for Microsemi Ocelot and Luton SoCs - mips: mscc: add support for Ocelot and Luton evaluation boards - mips: jz47xx: add basic support for Ingenic JZ4780 SoC - mips: jz47xx: add support for Imgtec Creator CI20 board Daniel Schwierzeck (3): mips: ath79: fix DTC warnings mips: xilfpga: fix DTC warnings MIPS: remove local_irq_[save|restore] from CP0 macros Gregory CLEMENT (9): DW SPI: Allow to overload the management of the external CS pinctrl: mscc: Add gpio and pinctrl driver for MSCC MIPS SoCs (VcoreIII based) gpio: mscc-bitbang-spi: Add a simple gpio driver for bitbgang spi MIPS: move create_tlb() in an proper header: mipsregs.h MIPS: Allow to prefetch and lock instructions into cache MSCC: add support for Ocelot SoCs MSCC: add support for Luton SoCs MSCC: add board support for the Ocelots based evaluation boards MSCC: add board support for the Luton based evaluation board Paul Burton (5): misc: Add JZ47xx efuse driver mmc: Add JZ47xx SD/MMC controller driver mips: Add SPL header mips: jz47xx: Add JZ4780 SoC support mips: jz47xx: Add Creator CI20 platform Stefan Roese (2): mips: mt76xx: Flush d-cache in arch_misc_init() to solve d-cache issues mips: mt76xx: linkit/gardena: Don't use CONFIG_OF_EMBED Álvaro Fernández Rojas (28): dma: add bcm6348-iudma support bmips: bcm6338: add bcm6348-iudma support bmips: bcm6348: add bcm6348-iudma support bmips: bcm6358: add bcm6348-iudma support bmips: bcm6368: add bcm6348-iudma support bmips: bcm6328: add bcm6348-iudma support bmips: bcm6362: add bcm6348-iudma support bmips: bcm63268: add bcm6348-iudma support bmips: bcm6318: add bcm6348-iudma support net: add support for bcm6348-enet bmips: bcm6338: add support for bcm6348-enet bmips: enable f@st1704 enet support bmips: bcm6348: add support for bcm6348-enet bmips: enable ct-5361 enet support bmips: bcm6358: add support for bcm6348-enet bmips: enable hg556a enet support bmips: enable nb4-ser enet support net: add support for bcm6368-enet bmips: bcm6368: add support for bcm6368-enet bmips: enable wap-5813n enet support bmips: bcm6328: add support for bcm6368-enet bmips: enable ar-5387un enet support bmips: bcm6362: add support for bcm6368-enet bmips: enable dgnd3700v2 enet support bmips: bcm63268: add support for bcm6368-enet bmips: enable vr-3032u enet support bmips: bcm6318: add support for bcm6368-enet bmips: enable ar-5315u enet support MAINTAINERS| 18 + arch/mips/Kconfig | 15 +- arch/mips/Makefile | 2 + arch/mips/cpu/cpu.c| 10 - arch/mips/dts/Makefile | 1 + arch/mips/dts/ar933x.dtsi | 3 - arch/mips/dts/brcm,bcm6318.dtsi| 38 + arch/mips/dts/brcm,bcm63268.dtsi | 38 + arch/mips/dts/brcm,bcm6328.dtsi| 30 + arch/mips/dts/brcm,bcm6338.dtsi| 29 + arch/mips/dts/brcm,bcm6348.dtsi| 42 ++ arch/mips/dts/brcm,bcm6358.dtsi| 46 ++ arch/mips/dts/brcm,bcm6362.dtsi| 32 + arch/mips/dts/brcm,bcm6368.dtsi| 32 + arch/mips/dts/ci20.dts | 122 +++ arch/mips/dts/comtrend,ar-5315u.dts| 32 + arch/mips/dts/comtrend,ar-5387un.dts | 32 + arch/mips/dts/comtrend,ct-5361.dts | 12 + arch/mips/dts/comtrend,vr-3032u.dts| 32 + arch/mips/dts/comtrend,wap-5813n.dts | 14 + arch/mips/dts/huawei,hg556a.dts| 12 + arch/mips/dts
Re: [U-Boot] [PATCH] MIPS: remove local_irq_[save|restore] from CP0 macros
Am 19.12.18 um 15:18 schrieb Daniel Schwierzeck: > With moving write_on_tlb() to arch/mips/include/asm/mipsregs.h > there are now compiler warnings when some generic code includes > asm/io.h. This happens for example when enabling OF live tree. > > Signed-off-by: Daniel Schwierzeck > > --- > > arch/mips/include/asm/mipsregs.h | 7 --- > 1 file changed, 7 deletions(-) > applied to u-boot-mips -- - Daniel ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] spi: soft_spi: Fix null ptr when probing soft_spi.
When probing soft_spi the result of dev_get_parent_priv(dev) in probe
function is null ptr because the spi is on the ahb bus which has
per_child_auto_alloc_size set to 0. Therefore it would generate an Ooops
messages when accessing spi_slave structure.
The fix consist of delaying the read of dm_spi_slave_platdata until a
child under the spi is probed, to be able to read SPI mode. Therefore
implement .child_pre_probe in which updates soft_spi_platdata based on
child dm_spi_slave_platdata.
Signed-off-by: Horatiu Vultur
---
drivers/spi/soft_spi.c | 24 +---
1 file changed, 17 insertions(+), 7 deletions(-)
diff --git a/drivers/spi/soft_spi.c b/drivers/spi/soft_spi.c
index b06883f..e28591b 100644
--- a/drivers/spi/soft_spi.c
+++ b/drivers/spi/soft_spi.c
@@ -210,18 +210,13 @@ static int soft_spi_ofdata_to_platdata(struct udevice
*dev)
static int soft_spi_probe(struct udevice *dev)
{
- struct spi_slave *slave = dev_get_parent_priv(dev);
struct soft_spi_platdata *plat = dev->platdata;
- int cs_flags, clk_flags;
int ret;
- cs_flags = (slave->mode & SPI_CS_HIGH) ? 0 : GPIOD_ACTIVE_LOW;
- clk_flags = (slave->mode & SPI_CPOL) ? GPIOD_ACTIVE_LOW : 0;
-
if (gpio_request_by_name(dev, "cs-gpios", 0, &plat->cs,
-GPIOD_IS_OUT | cs_flags) ||
+GPIOD_IS_OUT) ||
gpio_request_by_name(dev, "gpio-sck", 0, &plat->sclk,
-GPIOD_IS_OUT | clk_flags))
+GPIOD_IS_OUT))
return -EINVAL;
ret = gpio_request_by_name(dev, "gpio-mosi", 0, &plat->mosi,
@@ -241,6 +236,20 @@ static int soft_spi_probe(struct udevice *dev)
return 0;
}
+static int soft_spi_child_pre_probe(struct udevice *dev)
+{
+ struct udevice *bus = dev_get_parent(dev);
+ struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
+ struct soft_spi_platdata *plat = bus->platdata;
+
+ if (!(slave->mode & SPI_CS_HIGH))
+ plat->cs.flags |= GPIOD_ACTIVE_LOW;
+ if (slave->mode & SPI_CPOL)
+ plat->sclk.flags |= GPIOD_ACTIVE_LOW;
+
+ return 0;
+}
+
static const struct udevice_id soft_spi_ids[] = {
{ .compatible = "spi-gpio" },
{ }
@@ -254,5 +263,6 @@ U_BOOT_DRIVER(soft_spi) = {
.ofdata_to_platdata = soft_spi_ofdata_to_platdata,
.platdata_auto_alloc_size = sizeof(struct soft_spi_platdata),
.priv_auto_alloc_size = sizeof(struct soft_spi_priv),
+ .child_pre_probe = soft_spi_child_pre_probe,
.probe = soft_spi_probe,
};
--
2.7.4
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Re: [U-Boot] [PATCH u-boot] arm: dts: s400: Fix status for eMMC and SDIO ports
On 19/12/2018 15:44, Jerome Brunet wrote:
> On Mon, 2018-12-17 at 10:26 +0100, Neil Armstrong wrote:
>> Under U-boot, the WiFi SDIO Module should be disabled and the
>> eMMC modules should be enabled, so this patch adds an s400-u-boot.dtsi
>> include file specific for U-Boot that will be included by the build system.
>>
>> Signed-off-by: Neil Armstrong
>
> Tested-by: Jerome Brunet
>
>> ---
>> arch/arm/dts/meson-axg-s400-u-boot.dtsi | 14 ++
>> 1 file changed, 14 insertions(+)
>> create mode 100644 arch/arm/dts/meson-axg-s400-u-boot.dtsi
>>
>> diff --git a/arch/arm/dts/meson-axg-s400-u-boot.dtsi b/arch/arm/dts/meson-
>> axg-s400-u-boot.dtsi
>> new file mode 100644
>> index 00..c46eb3f38d
>> --- /dev/null
>> +++ b/arch/arm/dts/meson-axg-s400-u-boot.dtsi
>> @@ -0,0 +1,14 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
>> + */
>> +
>> +/* wifi module */
>> +&sd_emmc_b {
>> +status = "disabled";
>> +};
>> +
>> +/* emmc storage */
>> +&sd_emmc_c {
>> +status = "okay";
>> +};
>
>
Applied !
Neil
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Re: [U-Boot] [PATCH v2] net: macb: fix mapping of registers
Am 18.12.18 um 21:49 schrieb Ramon Fried:
> Some architectures (MIPS) needs mapping to access IOMEM.
> Fix that.
>
> Fixes: f1dcc19b213d ("net: macb: Convert to driver model")
>
> Signed-off-by: Ramon Fried
> ---
> v2: switched to use dev_reamp_addr() to reduce boilerplate code.
> (as suggested by Daniel Schwierzeck)
>
>
> drivers/net/macb.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
Reviewed-by: Daniel Schwierzeck
--
- Daniel
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[U-Boot] [PULL u-boot] Please pull u-boot-amlogic-20181219
Hi Tom, Here is single U-Boot DT fixup for the S400 board. Thanks, Neil The following changes since commit 1f2e948d6d53f77a2ddb2dde3531b0d5bc2815ad: Prepare v2019.01-rc2 (2018-12-17 20:25:24 -0500) are available in the Git repository at: git://git.denx.de/u-boot-amlogic.git tags/u-boot-amlogic-20181219 for you to fetch changes up to 53904dc7c13841497835090a8057930d4a84c4de: arm: dts: s400: Fix status for eMMC and SDIO ports (2018-12-19 16:20:50 +0100) A single fix to properly enable eMMC on the AXG S400 board. Neil Armstrong (1): arm: dts: s400: Fix status for eMMC and SDIO ports arch/arm/dts/meson-axg-s400-u-boot.dtsi | 14 ++ 1 file changed, 14 insertions(+) create mode 100644 arch/arm/dts/meson-axg-s400-u-boot.dtsi ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] phy: Fix u-boot coruption when fixed-phy is used
When fixed-link phy is used subnode offset is used as phy address. This number is bigger then space allocated for bus structure (allocated via mdio_alloc). bus->phymap[] array has PHY_MAX_ADDR size (32). That's why writing bus->phymap[addr] where addr is < 0 or > PHY_MAX_ADDR is causing write to memory which can caused full U-Boot crash. The patch is checking if address is in correct range. Signed-off-by: Michal Simek --- search_for_existing_phy() is using this array but there is if check already that's why it shouldn't be a big deal. --- drivers/net/phy/phy.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index e837eb7688cc..cda4caa8034d 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -656,7 +656,8 @@ static struct phy_device *phy_device_create(struct mii_dev *bus, int addr, phy_probe(dev); - bus->phymap[addr] = dev; + if (addr >= 0 && addr < PHY_MAX_ADDR) + bus->phymap[addr] = dev; return dev; } -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [linux-sunxi] CONFIG_DM_USB breakage on sunxi boards with musb?
On Wed, Dec 19, 2018 at 01:14:22PM +0100, Jean-Jacques Hiblot wrote: > > On 19/12/2018 12:37, Priit Laes wrote: > > On Wed, Dec 19, 2018 at 01:26:18PM +0530, Jagan Teki wrote: > > > On Wed, Dec 19, 2018 at 1:23 PM Priit Laes wrote: > > > > Heya! > > > > > > > > I ran into following error when trying to fel-boot > > > > A20 OLinuxino Lime2 eMMC board with latest u-boot: > > > > > > > > [snip] > > > > U-Boot 2019.01-rc2-5-gbf60dae9dd (Dec 19 2018 - 09:47:08 +0200) > > > > Allwinner Technology > > > > > > > > CPU: Allwinner A20 (SUN7I) > > > > Model: Olimex A20-OLinuXino-LIME2-eMMC > > > > I2C: ready > > > > DRAM: 1 GiB > > > > Error binding driver 'sunxi-musb': -96 > > > > Some drivers failed to bind > > > > Error binding driver 'generic_simple_bus': -96 > > > > Some drivers failed to bind > > > > initcall sequence 7efbdfc8 failed at call 4a00d07b (err=-96) > > > > ### ERROR ### Please RESET the board ### > > > > [/snip] > > > > > > > > > > > > Could it be caused by a side effect of the upcoming CONFIG_DM_USB > > > > changes? > > > No, board file change wrt this commit > > > 0131162439508801b9f8a330fa731f04273c9337 > > > > > > Need to figure out. > > Yup, bisecting points to the same commit and reverting fixes the issue. > > Can you try with DM_USB_GADGET enabled? Yes, the result is: drivers/usb/gadget/udc/udc-uclass.c:52: undefined reference to `dm_usb_gadget_handle_interrupts u-boot configuration file is A20-OLinuXino-Lime2-eMMC_defconfig > > > > > > 0131162439508801b9f8a330fa731f04273c9337 is the first bad commit > > commit 0131162439508801b9f8a330fa731f04273c9337 > > Author: Jean-Jacques Hiblot > > Date: Thu Nov 29 10:52:46 2018 +0100 > > > > dm: usb: create a new UCLASS ID for USB gadget devices > > UCLASS_USB_DEV_GENERIC was meant for USB devices connected to host > > controllers, not gadget devices. > > Adding a new UCLASS for gadget devices alone. > > Also move the generic DM code for USB gadgets in a separate file for > > clarity. > > Signed-off-by: Jean-Jacques Hiblot > > > > :04 04 5223a6058a0c4a1e877f32355c947d4a607fef1b > > d3f89658db63ec26d887163740cf5d974dd2c0e5 M board > > :04 04 67c4404917ada478595b408d7747a6f5c17c0c99 > > 8c67ea39df65e4e982d9b9eeb984d66678a33fc8 M drivers > > :04 04 89243fd62729e128489d80e206db4fa9b946dc99 > > 16783bd1f210ae3454255cb1c4eaa05fe7eaa6ed M include > > > > $ git bisect log > > git bisect start > > # bad: [058701534ffde8032649ba8421a0428959519b79] WIP > > git bisect bad 058701534ffde8032649ba8421a0428959519b79 > > # bad: [d94604d558cda9f89722c967d6f8d6269a2db21c] Merge tag > > 'fsl-qoriq-for-v2019.01-rc2' of git://git.denx.de/u-boot-fsl-qoriq > > git bisect bad d94604d558cda9f89722c967d6f8d6269a2db21c > > # good: [c49aff3e66b930aa06936afee401cf5e19377958] Merge branch 'master' of > > git://git.denx.de/u-boot-sunxi > > git bisect good c49aff3e66b930aa06936afee401cf5e19377958 > > # bad: [7ff485c68b7e5573e5a4a877066e98398283a24f] Merge branch 'master' of > > git://git.denx.de/u-boot-i2c > > git bisect bad 7ff485c68b7e5573e5a4a877066e98398283a24f > > # good: [19f8c4dfb6e744a31da59bdd23b24d144152f1dc] cmd: i2c: Fix help > > output of i2c command. > > git bisect good 19f8c4dfb6e744a31da59bdd23b24d144152f1dc > > # bad: [b491afa0f3c0df88027b08f18934cc034c40d659] configs: enable DM_USB > > and DM_USB_DEV for all DRA7 platforms > > git bisect bad b491afa0f3c0df88027b08f18934cc034c40d659 > > # bad: [93991cf1969077108ae36e90acb3cd25a6a449ac] dwc3-generic: Add > > select_dr_mode operation > > git bisect bad 93991cf1969077108ae36e90acb3cd25a6a449ac > > # good: [20bebd866690bb09dd1c1cb8ac674c3b17b63c6d] dwc3_generic: do not > > probe the USB device driver when it's bound > > git bisect good 20bebd866690bb09dd1c1cb8ac674c3b17b63c6d > > # bad: [0131162439508801b9f8a330fa731f04273c9337] dm: usb: create a new > > UCLASS ID for USB gadget devices > > git bisect bad 0131162439508801b9f8a330fa731f04273c9337 > > # good: [d648a50c0a27452a5439e7982b23b97c64820430] dwc3: move phy operation > > to core.c > > git bisect good d648a50c0a27452a5439e7982b23b97c64820430 > > # first bad commit: [0131162439508801b9f8a330fa731f04273c9337] dm: usb: > > create a new UCLASS ID for USB gadget devices > > > > > > > -- > > > You received this message because you are subscribed to the Google Groups > > > "linux-sunxi" group. > > > To unsubscribe from this group and stop receiving emails from it, send an > > > email to linux-sunxi+unsubscr...@googlegroups.com. > > > For more options, visit https://groups.google.com/d/optout. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/6] mips: luton+ocelot: Remove board-specific config options
Am 19.12.18 um 13:42 schrieb Lars Povlsen: > As we are moving to multi-dtb and board detection, remove static board > config options. > > Signed-off-by: Lars Povlsen > --- > arch/mips/mach-mscc/Kconfig | 38 ++--- > 1 file changed, 10 insertions(+), 28 deletions(-) > This patch should be squashed into the last commit to not break bisectability. After only applying this patch you can't build any Ocelot/Luton baords anymore until the last patch is applied. Otherwise the series looks good. > diff --git a/arch/mips/mach-mscc/Kconfig b/arch/mips/mach-mscc/Kconfig > index 0e35b77c9d..37ef432e48 100644 > --- a/arch/mips/mach-mscc/Kconfig > +++ b/arch/mips/mach-mscc/Kconfig > @@ -15,47 +15,29 @@ config SOC_VCOREIII > config SYS_SOC > default "mscc" > > +choice > + > + prompt "SOC Family Variant" > + > config SOC_OCELOT > - bool > + bool "Ocelot SOC Family" > select SOC_VCOREIII > + select DESIGNWARE_SPI > help > This supports MSCC Ocelot family of SOCs. > > config SOC_LUTON > - bool > + bool "Luton SOC Family" > select SOC_VCOREIII > + select MSCC_BITBANG_SPI_GPIO > help > This supports MSCC Luton family of SOCs. > > +endchoice > + > config SYS_CONFIG_NAME > default "vcoreiii" > > -choice > - prompt "Board select" > - > -config TARGET_OCELOT_PCB120 > - bool "MSCC PCB120 Reference Board (aka VSC5635EV)" > - select SOC_OCELOT > - help > - When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to > - ocelot_pcb120 > - > -config TARGET_OCELOT_PCB123 > - bool "MSCC PCB123 Reference Board (aka VSC7514EV))" > - select SOC_OCELOT > - help > - When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to > - ocelot_pcb123 > - > -config TARGET_LUTON_PCB091 > - bool "MSCC PCB091 Reference Board" > - select SOC_LUTON > - select MSCC_BITBANG_SPI_GPIO > - help > - When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to > - luton_pcb091 > -endchoice > - > choice > prompt "DDR type" > > -- - Daniel ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v9 01/10] test: add test for lib/lmb.c
Add basic tests for the lmb memory allocation code used to reserve and
allocate memory during boot.
Signed-off-by: Simon Goldschmidt
---
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5:
- this patch is new in v5
Changes in v4: None
Changes in v2: None
test/lib/Makefile | 1 +
test/lib/lmb.c| 297 ++
2 files changed, 298 insertions(+)
create mode 100644 test/lib/lmb.c
diff --git a/test/lib/Makefile b/test/lib/Makefile
index ea68fae566..5a636aac74 100644
--- a/test/lib/Makefile
+++ b/test/lib/Makefile
@@ -3,3 +3,4 @@
# (C) Copyright 2018
# Mario Six, Guntermann & Drunck GmbH, mario@gdsys.cc
obj-y += hexdump.o
+obj-y += lmb.o
diff --git a/test/lib/lmb.c b/test/lib/lmb.c
new file mode 100644
index 00..dd7ba14b34
--- /dev/null
+++ b/test/lib/lmb.c
@@ -0,0 +1,297 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018 Simon Goldschmidt
+ */
+
+#include
+#include
+#include
+#include
+
+static int check_lmb(struct unit_test_state *uts, struct lmb *lmb,
+phys_addr_t ram_base, phys_size_t ram_size,
+unsigned long num_reserved,
+phys_addr_t base1, phys_size_t size1,
+phys_addr_t base2, phys_size_t size2,
+phys_addr_t base3, phys_size_t size3)
+{
+ ut_asserteq(lmb->memory.cnt, 1);
+ ut_asserteq(lmb->memory.region[0].base, ram_base);
+ ut_asserteq(lmb->memory.region[0].size, ram_size);
+
+ ut_asserteq(lmb->reserved.cnt, num_reserved);
+ if (num_reserved > 0) {
+ ut_asserteq(lmb->reserved.region[0].base, base1);
+ ut_asserteq(lmb->reserved.region[0].size, size1);
+ }
+ if (num_reserved > 1) {
+ ut_asserteq(lmb->reserved.region[1].base, base2);
+ ut_asserteq(lmb->reserved.region[1].size, size2);
+ }
+ if (num_reserved > 2) {
+ ut_asserteq(lmb->reserved.region[2].base, base3);
+ ut_asserteq(lmb->reserved.region[2].size, size3);
+ }
+ return 0;
+}
+
+#define ASSERT_LMB(lmb, ram_base, ram_size, num_reserved, base1, size1, \
+ base2, size2, base3, size3) \
+ ut_assert(!check_lmb(uts, lmb, ram_base, ram_size, \
+num_reserved, base1, size1, base2, size2, base3, \
+size3))
+
+/*
+ * Test helper function that reserves 64 KiB somewhere in the simulated RAM and
+ * then does some alloc + free tests.
+ */
+static int test_multi_alloc(struct unit_test_state *uts,
+ const phys_addr_t ram, const phys_size_t ram_size,
+ const phys_addr_t alloc_64k_addr)
+{
+ const phys_addr_t ram_end = ram + ram_size;
+ const phys_addr_t alloc_64k_end = alloc_64k_addr + 0x1;
+
+ struct lmb lmb;
+ long ret;
+ phys_addr_t a, a2, b, b2, c, d;
+
+ /* check for overflow */
+ ut_assert(ram_end == 0 || ram_end > ram);
+ ut_assert(alloc_64k_end > alloc_64k_addr);
+ /* check input addresses + size */
+ ut_assert(alloc_64k_addr >= ram + 8);
+ ut_assert(alloc_64k_end <= ram_end - 8);
+
+ lmb_init(&lmb);
+
+ ret = lmb_add(&lmb, ram, ram_size);
+ ut_asserteq(ret, 0);
+
+ /* reserve 64KiB somewhere */
+ ret = lmb_reserve(&lmb, alloc_64k_addr, 0x1);
+ ut_asserteq(ret, 0);
+ ASSERT_LMB(&lmb, ram, ram_size, 1, alloc_64k_addr, 0x1,
+ 0, 0, 0, 0);
+
+ /* allocate somewhere, should be at the end of RAM */
+ a = lmb_alloc(&lmb, 4, 1);
+ ut_asserteq(a, ram_end - 4);
+ ASSERT_LMB(&lmb, ram, ram_size, 2, alloc_64k_addr, 0x1,
+ ram_end - 4, 4, 0, 0);
+ /* alloc below end of reserved region -> below reserved region */
+ b = lmb_alloc_base(&lmb, 4, 1, alloc_64k_end);
+ ut_asserteq(b, alloc_64k_addr - 4);
+ ASSERT_LMB(&lmb, ram, ram_size, 2,
+ alloc_64k_addr - 4, 0x1 + 4, ram_end - 4, 4, 0, 0);
+
+ /* 2nd time */
+ c = lmb_alloc(&lmb, 4, 1);
+ ut_asserteq(c, ram_end - 8);
+ ASSERT_LMB(&lmb, ram, ram_size, 2,
+ alloc_64k_addr - 4, 0x1 + 4, ram_end - 8, 8, 0, 0);
+ d = lmb_alloc_base(&lmb, 4, 1, alloc_64k_end);
+ ut_asserteq(d, alloc_64k_addr - 8);
+ ASSERT_LMB(&lmb, ram, ram_size, 2,
+ alloc_64k_addr - 8, 0x1 + 8, ram_end - 8, 8, 0, 0);
+
+ ret = lmb_free(&lmb, a, 4);
+ ut_asserteq(ret, 0);
+ ASSERT_LMB(&lmb, ram, ram_size, 2,
+ alloc_64k_addr - 8, 0x1 + 8, ram_end - 8, 4, 0, 0);
+ /* allocate again to ensure we get the same address */
+ a2 = lmb_alloc(&lmb, 4, 1);
+ ut_asserteq(a, a2);
+ ASSERT_LMB(&lmb, ram, ram_size, 2,
+ alloc_64k_addr - 8, 0x1 + 8, ram_end - 8, 8, 0, 0);
[U-Boot] [PATCH v9 02/10] lmb: fix allocation at end of address range
The lmb code fails if base + size of RAM overflows to zero.
Fix this by calculating end as 'base + size - 1' instead of 'base + size'
where appropriate.
Added tests to assert this is fixed.
Signed-off-by: Simon Goldschmidt
---
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5:
- this patch is new in v5
Changes in v4: None
Changes in v2: None
lib/lmb.c | 29 -
test/lib/lmb.c | 29 ++---
2 files changed, 38 insertions(+), 20 deletions(-)
diff --git a/lib/lmb.c b/lib/lmb.c
index 1705417348..6d3dcf4e09 100644
--- a/lib/lmb.c
+++ b/lib/lmb.c
@@ -43,7 +43,10 @@ void lmb_dump_all(struct lmb *lmb)
static long lmb_addrs_overlap(phys_addr_t base1,
phys_size_t size1, phys_addr_t base2, phys_size_t size2)
{
- return ((base1 < (base2+size2)) && (base2 < (base1+size1)));
+ const phys_addr_t base1_end = base1 + size1 - 1;
+ const phys_addr_t base2_end = base2 + size2 - 1;
+
+ return ((base1 <= base2_end) && (base2 <= base1_end));
}
static long lmb_addrs_adjacent(phys_addr_t base1, phys_size_t size1,
@@ -89,18 +92,9 @@ static void lmb_coalesce_regions(struct lmb_region *rgn,
void lmb_init(struct lmb *lmb)
{
- /* Create a dummy zero size LMB which will get coalesced away later.
-* This simplifies the lmb_add() code below...
-*/
- lmb->memory.region[0].base = 0;
- lmb->memory.region[0].size = 0;
- lmb->memory.cnt = 1;
+ lmb->memory.cnt = 0;
lmb->memory.size = 0;
-
- /* Ditto. */
- lmb->reserved.region[0].base = 0;
- lmb->reserved.region[0].size = 0;
- lmb->reserved.cnt = 1;
+ lmb->reserved.cnt = 0;
lmb->reserved.size = 0;
}
@@ -110,9 +104,10 @@ static long lmb_add_region(struct lmb_region *rgn,
phys_addr_t base, phys_size_t
unsigned long coalesced = 0;
long adjacent, i;
- if ((rgn->cnt == 1) && (rgn->region[0].size == 0)) {
+ if (rgn->cnt == 0) {
rgn->region[0].base = base;
rgn->region[0].size = size;
+ rgn->cnt = 1;
return 0;
}
@@ -183,7 +178,7 @@ long lmb_free(struct lmb *lmb, phys_addr_t base,
phys_size_t size)
{
struct lmb_region *rgn = &(lmb->reserved);
phys_addr_t rgnbegin, rgnend;
- phys_addr_t end = base + size;
+ phys_addr_t end = base + size - 1;
int i;
rgnbegin = rgnend = 0; /* supress gcc warnings */
@@ -191,7 +186,7 @@ long lmb_free(struct lmb *lmb, phys_addr_t base,
phys_size_t size)
/* Find the region where (base, size) belongs to */
for (i=0; i < rgn->cnt; i++) {
rgnbegin = rgn->region[i].base;
- rgnend = rgnbegin + rgn->region[i].size;
+ rgnend = rgnbegin + rgn->region[i].size - 1;
if ((rgnbegin <= base) && (end <= rgnend))
break;
@@ -209,7 +204,7 @@ long lmb_free(struct lmb *lmb, phys_addr_t base,
phys_size_t size)
/* Check to see if region is matching at the front */
if (rgnbegin == base) {
- rgn->region[i].base = end;
+ rgn->region[i].base = end + 1;
rgn->region[i].size -= size;
return 0;
}
@@ -225,7 +220,7 @@ long lmb_free(struct lmb *lmb, phys_addr_t base,
phys_size_t size)
* beginging of the hole and add the region after hole.
*/
rgn->region[i].size = base - rgn->region[i].base;
- return lmb_add_region(rgn, end, rgnend - end);
+ return lmb_add_region(rgn, end + 1, rgnend - end);
}
long lmb_reserve(struct lmb *lmb, phys_addr_t base, phys_size_t size)
diff --git a/test/lib/lmb.c b/test/lib/lmb.c
index dd7ba14b34..fb7ca45ef1 100644
--- a/test/lib/lmb.c
+++ b/test/lib/lmb.c
@@ -146,8 +146,15 @@ static int test_multi_alloc_512mb(struct unit_test_state
*uts,
/* Create a memory region with one reserved region and allocate */
static int lib_test_lmb_simple(struct unit_test_state *uts)
{
+ int ret;
+
/* simulate 512 MiB RAM beginning at 1GiB */
- return test_multi_alloc_512mb(uts, 0x4000);
+ ret = test_multi_alloc_512mb(uts, 0x4000);
+ if (ret)
+ return ret;
+
+ /* simulate 512 MiB RAM beginning at 1.5GiB */
+ return test_multi_alloc_512mb(uts, 0xE000);
}
DM_TEST(lib_test_lmb_simple, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
@@ -206,7 +213,15 @@ static int test_bigblock(struct unit_test_state *uts,
const phys_addr_t ram)
static int lib_test_lmb_big(struct unit_test_state *uts)
{
- return test_bigblock(uts, 0x4000);
+ int ret;
+
+ /* simulate 512 MiB RAM beginning at 1GiB */
+ ret = test_bigblock(uts, 0x4000);
+ if (ret)
+ return ret;
+
+ /* simulate 512 MiB RAM beginning at 1.5GiB */
+ return test_bigblock(uts, 0xE000);
}
DM_TEST(l
[U-Boot] [PATCH v9 03/10] lib: lmb: reserving overlapping regions should fail
lmb_add_region handles overlapping regions wrong: instead of merging
or rejecting to add a new reserved region that overlaps an existing
one, it just adds the new region.
Since internally the same function is used for lmb_alloc, change
lmb_add_region to reject overlapping regions.
Also, to keep reserved memory correct after 'free', reserved entries
created by allocating memory must not set their size to a multiple
of alignment but to the original size. This ensures the reserved
region is completely removed when the caller calls 'lmb_free', as
this one takes the same size as passed to 'lmb_alloc' etc.
Add test to assert this.
Signed-off-by: Simon Goldschmidt
---
Changes in v9: None
Changes in v8: None
Changes in v7:
- add braces around if/else with macros accross more than one line
Changes in v6:
- fix size of allocated regions that need alignment padding
Changes in v5:
- added a test for this bug
Changes in v4: None
Changes in v2: None
lib/lmb.c | 11 +++---
test/lib/lmb.c | 95 +-
2 files changed, 91 insertions(+), 15 deletions(-)
diff --git a/lib/lmb.c b/lib/lmb.c
index 6d3dcf4e09..cd297f8202 100644
--- a/lib/lmb.c
+++ b/lib/lmb.c
@@ -131,6 +131,9 @@ static long lmb_add_region(struct lmb_region *rgn,
phys_addr_t base, phys_size_t
rgn->region[i].size += size;
coalesced++;
break;
+ } else if (lmb_addrs_overlap(base, size, rgnbase, rgnsize)) {
+ /* regions overlap */
+ return -1;
}
}
@@ -269,11 +272,6 @@ static phys_addr_t lmb_align_down(phys_addr_t addr,
phys_size_t size)
return addr & ~(size - 1);
}
-static phys_addr_t lmb_align_up(phys_addr_t addr, ulong size)
-{
- return (addr + (size - 1)) & ~(size - 1);
-}
-
phys_addr_t __lmb_alloc_base(struct lmb *lmb, phys_size_t size, ulong align,
phys_addr_t max_addr)
{
long i, j;
@@ -302,8 +300,7 @@ phys_addr_t __lmb_alloc_base(struct lmb *lmb, phys_size_t
size, ulong align, phy
if (j < 0) {
/* This area isn't reserved, take it */
if (lmb_add_region(&lmb->reserved, base,
- lmb_align_up(size,
- align)) < 0)
+ size) < 0)
return 0;
return base;
}
diff --git a/test/lib/lmb.c b/test/lib/lmb.c
index fb7ca45ef1..e6acb70e76 100644
--- a/test/lib/lmb.c
+++ b/test/lib/lmb.c
@@ -227,13 +227,16 @@ static int lib_test_lmb_big(struct unit_test_state *uts)
DM_TEST(lib_test_lmb_big, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
/* Simulate 512 MiB RAM, allocate a block without previous reservation */
-static int test_noreserved(struct unit_test_state *uts, const phys_addr_t ram)
+static int test_noreserved(struct unit_test_state *uts, const phys_addr_t ram,
+ const phys_addr_t alloc_size, const ulong align)
{
const phys_size_t ram_size = 0x2000;
const phys_addr_t ram_end = ram + ram_size;
struct lmb lmb;
long ret;
phys_addr_t a, b;
+ const phys_addr_t alloc_size_aligned = (alloc_size + align - 1) &
+ ~(align - 1);
/* check for overflow */
ut_assert(ram_end == 0 || ram_end > ram);
@@ -242,20 +245,43 @@ static int test_noreserved(struct unit_test_state *uts,
const phys_addr_t ram)
ret = lmb_add(&lmb, ram, ram_size);
ut_asserteq(ret, 0);
+ ASSERT_LMB(&lmb, ram, ram_size, 0, 0, 0, 0, 0, 0, 0);
/* allocate a block */
- a = lmb_alloc(&lmb, 4, 1);
+ a = lmb_alloc(&lmb, alloc_size, align);
ut_assert(a != 0);
- /* and free it */
- ret = lmb_free(&lmb, a, 4);
+ ASSERT_LMB(&lmb, ram, ram_size, 1, ram + ram_size - alloc_size_aligned,
+ alloc_size, 0, 0, 0, 0);
+ /* allocate another block */
+ b = lmb_alloc(&lmb, alloc_size, align);
+ ut_assert(b != 0);
+ if (alloc_size == alloc_size_aligned) {
+ ASSERT_LMB(&lmb, ram, ram_size, 1, ram + ram_size -
+ (alloc_size_aligned * 2), alloc_size * 2, 0, 0, 0,
+ 0);
+ } else {
+ ASSERT_LMB(&lmb, ram, ram_size, 2, ram + ram_size -
+ (alloc_size_aligned * 2), alloc_size, ram + ram_size
+ - alloc_size_aligned, alloc_size, 0, 0);
+ }
+ /* and free them */
+ ret = lmb_free(&lmb, b, alloc_size);
ut_asserteq(ret, 0);
+ ASSERT_LMB(&lmb, ram, ram_size, 1, ram + ram_size - alloc_size_aligned,
+ alloc_size, 0, 0, 0, 0);
+ ret = lmb_free(&lmb, a, alloc_size);
+ ut_a
[U-Boot] [PATCH v9 05/10] lib: lmb: extend lmb for checks at load time
This adds two new functions, lmb_alloc_addr and
lmb_get_unreserved_size.
lmb_alloc_addr behaves like lmb_alloc, but it tries to allocate a
pre-specified address range. Unlike lmb_reserve, this address range
must be inside one of the memory ranges that has been set up with
lmb_add.
lmb_get_unreserved_size returns the number of bytes that can be
used up to the next reserved region or the end of valid ram. This
can be 0 if the address passed is reserved.
Added test for these new functions.
Signed-off-by: Simon Goldschmidt
---
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5:
- fixed lmb_alloc_addr when resulting reserved ranges get combined
- added test for these new functions
Changes in v4: None
Changes in v2:
- added lmb_get_unreserved_size() for tftp
include/lmb.h | 3 +
lib/lmb.c | 53 +
test/lib/lmb.c | 202 +
3 files changed, 258 insertions(+)
diff --git a/include/lmb.h b/include/lmb.h
index f04d058093..7d7e2a78dc 100644
--- a/include/lmb.h
+++ b/include/lmb.h
@@ -38,6 +38,9 @@ extern phys_addr_t lmb_alloc_base(struct lmb *lmb,
phys_size_t size, ulong align
phys_addr_t max_addr);
extern phys_addr_t __lmb_alloc_base(struct lmb *lmb, phys_size_t size, ulong
align,
phys_addr_t max_addr);
+extern phys_addr_t lmb_alloc_addr(struct lmb *lmb, phys_addr_t base,
+ phys_size_t size);
+extern phys_size_t lmb_get_unreserved_size(struct lmb *lmb, phys_addr_t addr);
extern int lmb_is_reserved(struct lmb *lmb, phys_addr_t addr);
extern long lmb_free(struct lmb *lmb, phys_addr_t base, phys_size_t size);
diff --git a/lib/lmb.c b/lib/lmb.c
index cd297f8202..e380a0a722 100644
--- a/lib/lmb.c
+++ b/lib/lmb.c
@@ -313,6 +313,59 @@ phys_addr_t __lmb_alloc_base(struct lmb *lmb, phys_size_t
size, ulong align, phy
return 0;
}
+/*
+ * Try to allocate a specific address range: must be in defined memory but not
+ * reserved
+ */
+phys_addr_t lmb_alloc_addr(struct lmb *lmb, phys_addr_t base, phys_size_t size)
+{
+ long j;
+
+ /* Check if the requested address is in one of the memory regions */
+ j = lmb_overlaps_region(&lmb->memory, base, size);
+ if (j >= 0) {
+ /*
+* Check if the requested end address is in the same memory
+* region we found.
+*/
+ if (lmb_addrs_overlap(lmb->memory.region[j].base,
+ lmb->memory.region[j].size, base + size -
+ 1, 1)) {
+ /* ok, reserve the memory */
+ if (lmb_reserve(lmb, base, size) >= 0)
+ return base;
+ }
+ }
+ return 0;
+}
+
+/* Return number of bytes from a given address that are free */
+phys_size_t lmb_get_unreserved_size(struct lmb *lmb, phys_addr_t addr)
+{
+ int i;
+ long j;
+
+ /* check if the requested address is in the memory regions */
+ j = lmb_overlaps_region(&lmb->memory, addr, 1);
+ if (j >= 0) {
+ for (i = 0; i < lmb->reserved.cnt; i++) {
+ if (addr < lmb->reserved.region[i].base) {
+ /* first reserved range > requested address */
+ return lmb->reserved.region[i].base - addr;
+ }
+ if (lmb->reserved.region[i].base +
+ lmb->reserved.region[i].size > addr) {
+ /* requested addr is in this reserved range */
+ return 0;
+ }
+ }
+ /* if we come here: no reserved ranges above requested addr */
+ return lmb->memory.region[lmb->memory.cnt - 1].base +
+ lmb->memory.region[lmb->memory.cnt - 1].size - addr;
+ }
+ return 0;
+}
+
int lmb_is_reserved(struct lmb *lmb, phys_addr_t addr)
{
int i;
diff --git a/test/lib/lmb.c b/test/lib/lmb.c
index e6acb70e76..058d3c332b 100644
--- a/test/lib/lmb.c
+++ b/test/lib/lmb.c
@@ -397,3 +397,205 @@ static int lib_test_lmb_overlapping_reserve(struct
unit_test_state *uts)
DM_TEST(lib_test_lmb_overlapping_reserve,
DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/*
+ * Simulate 512 MiB RAM, reserve 3 blocks, allocate addresses in between.
+ * Expect addresses outside the memory range to fail.
+ */
+static int test_alloc_addr(struct unit_test_state *uts, const phys_addr_t ram)
+{
+ const phys_size_t ram_size = 0x2000;
+ const phys_addr_t ram_end = ram + ram_size;
+ const phys_size_t alloc_addr_a = ram + 0x800;
+ const phys_size_t alloc_addr_b = ram + 0x800 * 2;
+ const phys_size_t alloc_addr_c = ram + 0x800 * 3;
+ struct lmb lmb;
+ long ret;
+
[U-Boot] [PATCH v9 04/10] fdt: parse "reserved-memory" for memory reservation
boot_fdt_add_mem_rsv_regions() adds reserved memory sections to an lmb
struct. Currently, it only parses regions described by /memreserve/
entries.
Extend this to the more commonly used scheme of the "reserved-memory"
node.
Signed-off-by: Simon Goldschmidt
---
Changes in v9: None
Changes in v8: None
Changes in v7:
- fix compiling without CONFIG_FIT
Changes in v6:
- fix compiling without OF_CONTROL
Changes in v5: None
Changes in v4:
- fixed invalid 'if' statement without braces in boot_fdt_reserve_region
Changes in v2:
- this patch is new in v2
common/image-fdt.c | 53 +++---
lib/Makefile | 1 +
2 files changed, 46 insertions(+), 8 deletions(-)
diff --git a/common/image-fdt.c b/common/image-fdt.c
index 95748f0ae1..5c0d6db3fe 100644
--- a/common/image-fdt.c
+++ b/common/image-fdt.c
@@ -10,6 +10,7 @@
#include
#include
+#include
#include
#include
#include
@@ -67,30 +68,66 @@ static const image_header_t *image_get_fdt(ulong fdt_addr)
}
#endif
+static void boot_fdt_reserve_region(struct lmb *lmb, uint64_t addr,
+ uint64_t size)
+{
+ int ret;
+
+ ret = lmb_reserve(lmb, addr, size);
+ if (!ret) {
+ debug(" reserving fdt memory region: addr=%llx size=%llx\n",
+ (unsigned long long)addr, (unsigned long long)size);
+ } else {
+ puts("ERROR: reserving fdt memory region failed ");
+ printf("(addr=%llx size=%llx)\n",
+ (unsigned long long)addr, (unsigned long long)size);
+ }
+}
+
/**
- * boot_fdt_add_mem_rsv_regions - Mark the memreserve sections as unusable
+ * boot_fdt_add_mem_rsv_regions - Mark the memreserve and reserved-memory
+ * sections as unusable
* @lmb: pointer to lmb handle, will be used for memory mgmt
* @fdt_blob: pointer to fdt blob base address
*
- * Adds the memreserve regions in the dtb to the lmb block. Adding the
- * memreserve regions prevents u-boot from using them to store the initrd
- * or the fdt blob.
+ * Adds the and reserved-memorymemreserve regions in the dtb to the lmb block.
+ * Adding the memreserve regions prevents u-boot from using them to store the
+ * initrd or the fdt blob.
*/
void boot_fdt_add_mem_rsv_regions(struct lmb *lmb, void *fdt_blob)
{
uint64_t addr, size;
- int i, total;
+ int i, total, ret;
+ int nodeoffset, subnode;
+ struct fdt_resource res;
if (fdt_check_header(fdt_blob) != 0)
return;
+ /* process memreserve sections */
total = fdt_num_mem_rsv(fdt_blob);
for (i = 0; i < total; i++) {
if (fdt_get_mem_rsv(fdt_blob, i, &addr, &size) != 0)
continue;
- printf(" reserving fdt memory region: addr=%llx size=%llx\n",
- (unsigned long long)addr, (unsigned long long)size);
- lmb_reserve(lmb, addr, size);
+ boot_fdt_reserve_region(lmb, addr, size);
+ }
+
+ /* process reserved-memory */
+ nodeoffset = fdt_subnode_offset(fdt_blob, 0, "reserved-memory");
+ if (nodeoffset >= 0) {
+ subnode = fdt_first_subnode(fdt_blob, nodeoffset);
+ while (subnode >= 0) {
+ /* check if this subnode has a reg property */
+ ret = fdt_get_resource(fdt_blob, subnode, "reg", 0,
+ &res);
+ if (!ret) {
+ addr = res.start;
+ size = res.end - res.start + 1;
+ boot_fdt_reserve_region(lmb, addr, size);
+ }
+
+ subnode = fdt_next_subnode(fdt_blob, subnode);
+ }
}
}
diff --git a/lib/Makefile b/lib/Makefile
index a6dd928a92..358789ff12 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -30,6 +30,7 @@ obj-y += crc7.o
obj-y += crc8.o
obj-y += crc16.o
obj-$(CONFIG_ERRNO_STR) += errno_str.o
+obj-$(CONFIG_OF_LIBFDT) += fdtdec.o
obj-$(CONFIG_FIT) += fdtdec_common.o
obj-$(CONFIG_TEST_FDTDEC) += fdtdec_test.o
obj-$(CONFIG_GZIP_COMPRESSED) += gzip.o
--
2.17.1
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v9 06/10] fs: prevent overwriting reserved memory
This fixes CVE-2018-18440 ("insufficient boundary checks in filesystem
image load") by using lmb to check the load size of a file against
reserved memory addresses.
Signed-off-by: Simon Goldschmidt
---
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6:
- fixed NULL pointer access in 'fdt_blob' passed to
'boot_fdt_add_mem_rsv_regions'
Changes in v5: None
Changes in v4: None
Changes in v2: None
fs/fs.c | 56 ---
include/lmb.h | 2 ++
lib/lmb.c | 13
3 files changed, 68 insertions(+), 3 deletions(-)
diff --git a/fs/fs.c b/fs/fs.c
index cb265174e2..400aa921a7 100644
--- a/fs/fs.c
+++ b/fs/fs.c
@@ -429,13 +429,57 @@ int fs_size(const char *filename, loff_t *size)
return ret;
}
-int fs_read(const char *filename, ulong addr, loff_t offset, loff_t len,
- loff_t *actread)
+#ifdef CONFIG_LMB
+/* Check if a file may be read to the given address */
+static int fs_read_lmb_check(const char *filename, ulong addr, loff_t offset,
+loff_t len, struct fstype_info *info)
+{
+ struct lmb lmb;
+ int ret;
+ loff_t size;
+ loff_t read_len;
+
+ /* get the actual size of the file */
+ ret = info->size(filename, &size);
+ if (ret)
+ return ret;
+ if (offset >= size) {
+ /* offset >= EOF, no bytes will be written */
+ return 0;
+ }
+ read_len = size - offset;
+
+ /* limit to 'len' if it is smaller */
+ if (len && len < read_len)
+ read_len = len;
+
+ lmb_init_and_reserve(&lmb, gd->bd->bi_dram[0].start,
+gd->bd->bi_dram[0].size, (void *)gd->fdt_blob);
+ lmb_dump_all(&lmb);
+
+ if (lmb_alloc_addr(&lmb, addr, read_len) == addr)
+ return 0;
+
+ printf("** Reading file would overwrite reserved memory **\n");
+ return -1;
+}
+#endif
+
+static int _fs_read(const char *filename, ulong addr, loff_t offset, loff_t
len,
+ int do_lmb_check, loff_t *actread)
{
struct fstype_info *info = fs_get_info(fs_type);
void *buf;
int ret;
+#ifdef CONFIG_LMB
+ if (do_lmb_check) {
+ ret = fs_read_lmb_check(filename, addr, offset, len, info);
+ if (ret)
+ return ret;
+ }
+#endif
+
/*
* We don't actually know how many bytes are being read, since len==0
* means read the whole file.
@@ -452,6 +496,12 @@ int fs_read(const char *filename, ulong addr, loff_t
offset, loff_t len,
return ret;
}
+int fs_read(const char *filename, ulong addr, loff_t offset, loff_t len,
+ loff_t *actread)
+{
+ return _fs_read(filename, addr, offset, len, 0, actread);
+}
+
int fs_write(const char *filename, ulong addr, loff_t offset, loff_t len,
loff_t *actwrite)
{
@@ -622,7 +672,7 @@ int do_load(cmd_tbl_t *cmdtp, int flag, int argc, char *
const argv[],
pos = 0;
time = get_timer(0);
- ret = fs_read(filename, addr, pos, bytes, &len_read);
+ ret = _fs_read(filename, addr, pos, bytes, 1, &len_read);
time = get_timer(time);
if (ret < 0)
return 1;
diff --git a/include/lmb.h b/include/lmb.h
index 7d7e2a78dc..62da85e716 100644
--- a/include/lmb.h
+++ b/include/lmb.h
@@ -31,6 +31,8 @@ struct lmb {
extern struct lmb lmb;
extern void lmb_init(struct lmb *lmb);
+extern void lmb_init_and_reserve(struct lmb *lmb, phys_addr_t base,
+phys_size_t size, void *fdt_blob);
extern long lmb_add(struct lmb *lmb, phys_addr_t base, phys_size_t size);
extern long lmb_reserve(struct lmb *lmb, phys_addr_t base, phys_size_t size);
extern phys_addr_t lmb_alloc(struct lmb *lmb, phys_size_t size, ulong align);
diff --git a/lib/lmb.c b/lib/lmb.c
index e380a0a722..3407705fa7 100644
--- a/lib/lmb.c
+++ b/lib/lmb.c
@@ -98,6 +98,19 @@ void lmb_init(struct lmb *lmb)
lmb->reserved.size = 0;
}
+/* Initialize the struct, add memory and call arch/board reserve functions */
+void lmb_init_and_reserve(struct lmb *lmb, phys_addr_t base, phys_size_t size,
+ void *fdt_blob)
+{
+ lmb_init(lmb);
+ lmb_add(lmb, base, size);
+ arch_lmb_reserve(lmb);
+ board_lmb_reserve(lmb);
+
+ if (IMAGE_ENABLE_OF_LIBFDT && fdt_blob)
+ boot_fdt_add_mem_rsv_regions(lmb, fdt_blob);
+}
+
/* This routine called with relocation disabled. */
static long lmb_add_region(struct lmb_region *rgn, phys_addr_t base,
phys_size_t size)
{
--
2.17.1
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[U-Boot] [PATCH v9 10/10] arm: bootm: fix sp detection at end of address range
This fixes 'arch_lmb_reserve()' for ARM that tries to detect in which
DRAM bank 'sp' is in.
This code failed if a bank was at the end of physical address range
(i.e. size + length overflowed to 0).
To fix this, calculate 'bank_end' as 'size + length - 1' so that such
banks end at 0x, not 0.
Fixes: 15751403b6 ("ARM: bootm: don't assume sp is in DRAM bank 0")
Reported-by: Frank Wunderlich
Signed-off-by: Simon Goldschmidt
Reviewed-by: Stephen Warren
---
Changes in v9:
- fix compile error in arch/arm/lib/bootm.c
Changes in v8:
- this patch is new in v8
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v2: None
arch/arm/lib/bootm.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index c3c1d2fdfa..329f20c2bf 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -64,13 +64,15 @@ void arch_lmb_reserve(struct lmb *lmb)
/* adjust sp by 4K to be safe */
sp -= 4096;
for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
- if (sp < gd->bd->bi_dram[bank].start)
+ if (!gd->bd->bi_dram[bank].size ||
+ sp < gd->bd->bi_dram[bank].start)
continue;
+ /* Watch out for RAM at end of address space! */
bank_end = gd->bd->bi_dram[bank].start +
- gd->bd->bi_dram[bank].size;
- if (sp >= bank_end)
+ gd->bd->bi_dram[bank].size - 1;
+ if (sp > bank_end)
continue;
- lmb_reserve(lmb, sp, bank_end - sp);
+ lmb_reserve(lmb, sp, bank_end - sp + 1);
break;
}
}
--
2.17.1
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[U-Boot] [PATCH v9 07/10] bootm: use new common function lmb_init_and_reserve
This reduces duplicate code only. Signed-off-by: Simon Goldschmidt --- Changes in v9: None Changes in v8: None Changes in v7: None Changes in v6: None Changes in v5: None Changes in v4: None Changes in v2: None common/bootm.c | 8 ++-- 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/common/bootm.c b/common/bootm.c index 8bf84ebcb7..31e4f0f794 100644 --- a/common/bootm.c +++ b/common/bootm.c @@ -56,15 +56,11 @@ static void boot_start_lmb(bootm_headers_t *images) ulong mem_start; phys_size_t mem_size; - lmb_init(&images->lmb); - mem_start = env_get_bootm_low(); mem_size = env_get_bootm_size(); - lmb_add(&images->lmb, (phys_addr_t)mem_start, mem_size); - - arch_lmb_reserve(&images->lmb); - board_lmb_reserve(&images->lmb); + lmb_init_and_reserve(&images->lmb, (phys_addr_t)mem_start, mem_size, +NULL); } #else #define lmb_reserve(lmb, base, size) -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v9 09/10] tftp: prevent overwriting reserved memory
This fixes CVE-2018-18439 ("insufficient boundary checks in network
image boot") by using lmb to check for a valid range to store
received blocks.
Signed-off-by: Simon Goldschmidt
---
Changes in v9: None
Changes in v8: None
Changes in v7:
- fix compiling without CONFIG_LMB
Changes in v6: None
Changes in v5: None
Changes in v4:
- this was patch 8, is now patch 7
- lines changed because v3 patch 7 got removed and MCAST_TFTP still
exists
Changes in v2:
- this patch is new in v2
net/tftp.c | 73 ++
1 file changed, 63 insertions(+), 10 deletions(-)
diff --git a/net/tftp.c b/net/tftp.c
index 68ffd81414..a9335b1b7e 100644
--- a/net/tftp.c
+++ b/net/tftp.c
@@ -17,6 +17,8 @@
#include
#endif
+DECLARE_GLOBAL_DATA_PTR;
+
/* Well known TFTP port # */
#define WELL_KNOWN_PORT69
/* Millisecs to timeout for lost pkt */
@@ -81,6 +83,10 @@ static ulong tftp_block_wrap;
/* memory offset due to wrapping */
static ulong tftp_block_wrap_offset;
static int tftp_state;
+static ulong tftp_load_addr;
+#ifdef CONFIG_LMB
+static ulong tftp_load_size;
+#endif
#ifdef CONFIG_TFTP_TSIZE
/* The file size reported by the server */
static int tftp_tsize;
@@ -164,10 +170,11 @@ static void mcast_cleanup(void)
#endif /* CONFIG_MCAST_TFTP */
-static inline void store_block(int block, uchar *src, unsigned len)
+static inline int store_block(int block, uchar *src, unsigned int len)
{
ulong offset = block * tftp_block_size + tftp_block_wrap_offset;
ulong newsize = offset + len;
+ ulong store_addr = tftp_load_addr + offset;
#ifdef CONFIG_SYS_DIRECT_FLASH_TFTP
int i, rc = 0;
@@ -175,24 +182,32 @@ static inline void store_block(int block, uchar *src,
unsigned len)
/* start address in flash? */
if (flash_info[i].flash_id == FLASH_UNKNOWN)
continue;
- if (load_addr + offset >= flash_info[i].start[0]) {
+ if (store_addr >= flash_info[i].start[0]) {
rc = 1;
break;
}
}
if (rc) { /* Flash is destination for this packet */
- rc = flash_write((char *)src, (ulong)(load_addr+offset), len);
+ rc = flash_write((char *)src, store_addr, len);
if (rc) {
flash_perror(rc);
- net_set_state(NETLOOP_FAIL);
- return;
+ return rc;
}
} else
#endif /* CONFIG_SYS_DIRECT_FLASH_TFTP */
{
- void *ptr = map_sysmem(load_addr + offset, len);
-
+ void *ptr;
+
+#ifdef CONFIG_LMB
+ if (store_addr < tftp_load_addr ||
+ store_addr + len > tftp_load_addr + tftp_load_size) {
+ puts("\nTFTP error: ");
+ puts("trying to overwrite reserved memory...\n");
+ return -1;
+ }
+#endif
+ ptr = map_sysmem(store_addr, len);
memcpy(ptr, src, len);
unmap_sysmem(ptr);
}
@@ -203,6 +218,8 @@ static inline void store_block(int block, uchar *src,
unsigned len)
if (net_boot_file_size < newsize)
net_boot_file_size = newsize;
+
+ return 0;
}
/* Clear our state ready for a new transfer */
@@ -606,7 +623,11 @@ static void tftp_handler(uchar *pkt, unsigned dest, struct
in_addr sip,
timeout_count_max = tftp_timeout_count_max;
net_set_timeout_handler(timeout_ms, tftp_timeout_handler);
- store_block(tftp_cur_block - 1, pkt + 2, len);
+ if (store_block(tftp_cur_block - 1, pkt + 2, len)) {
+ eth_halt();
+ net_set_state(NETLOOP_FAIL);
+ break;
+ }
/*
* Acknowledge the block just received, which will prompt
@@ -695,6 +716,25 @@ static void tftp_timeout_handler(void)
}
}
+/* Initialize tftp_load_addr and tftp_load_size from load_addr and lmb */
+static int tftp_init_load_addr(void)
+{
+#ifdef CONFIG_LMB
+ struct lmb lmb;
+ phys_size_t max_size;
+
+ lmb_init_and_reserve(&lmb, gd->bd->bi_dram[0].start,
+gd->bd->bi_dram[0].size, (void *)gd->fdt_blob);
+
+ max_size = lmb_get_unreserved_size(&lmb, load_addr);
+ if (!max_size)
+ return -1;
+
+ tftp_load_size = max_size;
+#endif
+ tftp_load_addr = load_addr;
+ return 0;
+}
void tftp_start(enum proto_t protocol)
{
@@ -791,7 +831,14 @@ void tftp_start(enum proto_t protocol)
} else
#endif
{
- printf("Load address: 0x%lx\n", load_addr);
+ if (tftp_init_load_addr()) {
+ eth_halt();
+ net_set_state(NETLOOP_FAIL);
+
[U-Boot] [PATCH v9 08/10] lmb: remove unused extern declaration
lmb.h includes an extern declaration of "struct lmb lmb;" which
is not used anywhere, so remove it.
Signed-off-by: Simon Goldschmidt
---
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v2:
- this patch is new in v2
include/lmb.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/include/lmb.h b/include/lmb.h
index 62da85e716..1bb003e35e 100644
--- a/include/lmb.h
+++ b/include/lmb.h
@@ -28,8 +28,6 @@ struct lmb {
struct lmb_region reserved;
};
-extern struct lmb lmb;
-
extern void lmb_init(struct lmb *lmb);
extern void lmb_init_and_reserve(struct lmb *lmb, phys_addr_t base,
phys_size_t size, void *fdt_blob);
--
2.17.1
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[U-Boot] SPL Platdata howto?
Hi, while searching for bytes to save in SPL in order to add FIT signature handling, I am currently trying to get socfpga-gen5 to use OF_PLATDATA. To begin, I stripped down socfpga_socrates_defconfig to absolutely nothing but serial drivers in SPL (with some modifications to the Kconfig) and enabled DEBUG_UART to see what's going on. Now while this config runs OK with a dtb (it just won't boot as drivers are missing -> "failed to boot from all boot devices"), it does not find the serial driver after enabling OF_PLATDATA. So since serial_rockchip.c already uses OF_PLATDATA and is based on ns16550 that my socfpga-gen5 platform is using: what do I have to do besides enabling OF_PLATDATA to get this working? I just seems like uclass_first_device does not find any UCLASS_SERIAL deivce when OF_PLATDATA is enabled. (And when answering this, keep in mind I need to get MMC and QSPI drivers working with OF_PLATDATA - I already fixed compiler errors in those, nothing more.) Thanks, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 1/1] efi_loader: efi_add_runtime_mmio()
The first parameter of efi_add_runtime_mmio() is a pointer to a
pointer. This should be reflected both in the signature and in the
documentation.
Signed-off-by: Heinrich Schuchardt
---
v2
Correct the commit message and title. This patch changes
efi_add_runtime_mmio().
---
include/efi_loader.h | 2 +-
lib/efi_loader/efi_runtime.c | 5 +++--
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/include/efi_loader.h b/include/efi_loader.h
index 53f08161ab..0581c0940d 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -483,7 +483,7 @@ void __efi_runtime efi_update_table_header_crc32(struct
efi_table_hdr *table);
/* Call this with mmio_ptr as the _pointer_ to a pointer to an MMIO region
* to make it available at runtime */
-efi_status_t efi_add_runtime_mmio(void *mmio_ptr, u64 len);
+efi_status_t efi_add_runtime_mmio(void **mmio_ptr, u64 len);
/* Boards may provide the functions below to implement RTS functionality */
diff --git a/lib/efi_loader/efi_runtime.c b/lib/efi_loader/efi_runtime.c
index 95844efdb0..377a4fe602 100644
--- a/lib/efi_loader/efi_runtime.c
+++ b/lib/efi_loader/efi_runtime.c
@@ -502,11 +502,12 @@ static efi_status_t EFIAPI efi_set_virtual_address_map(
* This function adds a memory-mapped IO region to the memory map to make it
* available at runtime.
*
- * @mmio_ptr: address of the memory-mapped IO region
+ * @mmio_ptr: pointer to a pointer to the start of the memory-mapped
+ * IO region
* @len: size of the memory-mapped IO region
* Returns:status code
*/
-efi_status_t efi_add_runtime_mmio(void *mmio_ptr, u64 len)
+efi_status_t efi_add_runtime_mmio(void **mmio_ptr, u64 len)
{
struct efi_runtime_mmio_list *newmmio;
u64 pages = (len + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT;
--
2.19.2
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Re: [U-Boot] Unable to saveenv to MMC
Thank you for the clarification. I've correct my issue by partitioning the MMC storage and formatting the partition FAT. Then burning the U-Boot Image to 8K in on the raw media. On Tue, Dec 18, 2018 at 12:48 AM Heinrich Schuchardt wrote: > On 12/6/18 7:12 PM, Robin Polak wrote: > > Hello. > > > > I'm having trouble persisting my environment variables to the SD Card > > onto which I have FAT formatted and then written U-Boot to using the > > following command: > > > > sudo dd if=u-boot-sunxi-with-spl.bin of=/dev/disk2 bs=1024 seek=8 > > > > I get the following error when booting a Linksprite_pcDuino3_Nano with > the > > SD Card I've built: > > > > U-Boot SPL 2018.11 (Dec 06 2018 - 17:57:48 +) > > DRAM: 1024 MiB > > CPU: 91200Hz, AXI/AHB/APB: 3/2/2 > > Trying to boot from MMC1 > > > > > > U-Boot 2018.11 (Dec 06 2018 - 17:57:48 +) Allwinner Technology > > > > CPU: Allwinner A20 (SUN7I) > > Model: LinkSprite pcDuino3 Nano > > I2C: ready > > DRAM: 1 GiB > > MMC: SUNXI SD/MMC: 0 > > Loading Environment from FAT... Unable to use mmc 0:0... In:serial > > Out: serial > > Err: serial > > SCSI: SATA link 0 timeout. > > AHCI 0001.0100 32 slots 1 ports 3 Gbps 0x1 impl SATA mode > > flags: ncq stag pm led clo only pmp pio slum part ccc apst > > > > Net: eth0: ethernet@1c5 > > starting USB... > > USB0: USB EHCI 1.00 > > USB1: USB OHCI 1.0 > > USB2: USB EHCI 1.00 > > USB3: USB OHCI 1.0 > > scanning bus 0 for devices... 1 USB Device(s) found > > scanning bus 2 for devices... 1 USB Device(s) found > >scanning usb for storage devices... 0 Storage Device(s) found > > Hit any key to stop autoboot: 0 > > => saveenv > > Saving Environment to FAT... Unable to use mmc 0:0... Failed (1) > > Partitions are numbered from 1. So partition 1 would be mmc 0:1. > > mmc 0:0 would require that there is no partition table and the FAT file > system starts in block 0. > > Please, check the value of CONFIG_ENV_FAT_DEVICE_AND_PART in your > configuration. The default is CONFIG_ENV_FAT_DEVICE_AND_PART="0:auto" > > With "auto" function blk_get_device_part_str() looks for the first > partition that has the bootable flag set. > > So to analyze your problem further please look at the output of > > sudo fdisk -l /dev/ > > assuming that you use a DOS partition table. > > Best regards > > Heinrich > > > > > Thank you for any light that may be shed upon this error. > > > > -- -- Robin Polak ro...@robinpolak.com 917-494-2080 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v8 0/5] Stratix10 FPGA reconfiguration support
From: "Ang, Chee Hong" Forked latest master branch from u-boot (github) and applied these 5 patches on top of it and test build with Travis CI. Travis CI report: https://travis-ci.org/JeremyAngCH/u-boot/jobs/470074691 New changes: - Add new dependency patch (1/5) to support the common FPGA configuration functions to resolve build errors History of changes: - Fix compilation warnings/errors in stratix10.c - Fix misplace of FPGA data structure in misc_arria10.c - socfpga_fpga_add() in misc.c - Add FPGA structure for Arria10, Cyclone5 and Stratix10 platforms - removed for-loop in socfpga_fpga_add() (only 1 FPGA device added) - Removed CONFIG_FPGA_STRATIX10 from defconfig - select CONFIG_FPGA_STRATIX10 when build for Stratix10 platform Ang, Chee Hong (5): arm: socfpga: stratix10: Add generic FPGA reconfig mailbox API for S10 arm: socfpga: stratix10: Add macros for mailbox's arguments arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver arm: socfpga: stratix10: Add Stratix10 FPGA into FPGA device table arm: socfpga: stratix10: Enable Stratix10 FPGA Reconfiguration arch/arm/mach-socfpga/Kconfig| 1 + arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 9 +- arch/arm/mach-socfpga/include/mach/misc.h| 4 +- arch/arm/mach-socfpga/mailbox_s10.c | 48 arch/arm/mach-socfpga/misc.c | 26 +- arch/arm/mach-socfpga/misc_arria10.c | 23 +- arch/arm/mach-socfpga/misc_gen5.c| 22 +- arch/arm/mach-socfpga/misc_s10.c | 22 ++ drivers/fpga/Kconfig | 11 + drivers/fpga/Makefile| 1 + drivers/fpga/altera.c| 6 + drivers/fpga/stratix10.c | 288 +++ include/altera.h | 8 + 13 files changed, 440 insertions(+), 29 deletions(-) create mode 100644 drivers/fpga/stratix10.c -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v8 1/5] arm: socfpga: stratix10: Add generic FPGA reconfig mailbox API for S10
From: "Ang, Chee Hong"
Add a generic mailbox API for FPGA reconfig status which can be
called by others. This new function accepts 2 different mailbox
commands: CONFIG_STATUS or RECONFIG_STATUS.
Signed-off-by: Ang, Chee Hong
---
arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 3 +-
arch/arm/mach-socfpga/mailbox_s10.c | 48
2 files changed, 50 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
index 81a609d..660df35 100644
--- a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
@@ -140,5 +140,6 @@ int mbox_qspi_open(void);
#endif
int mbox_reset_cold(void);
-
+int mbox_get_fpga_config_status(u32 cmd);
+int mbox_get_fpga_config_status_psci(u32 cmd);
#endif /* _MAILBOX_S10_H_ */
diff --git a/arch/arm/mach-socfpga/mailbox_s10.c
b/arch/arm/mach-socfpga/mailbox_s10.c
index 0d906c3..3c33223 100644
--- a/arch/arm/mach-socfpga/mailbox_s10.c
+++ b/arch/arm/mach-socfpga/mailbox_s10.c
@@ -342,6 +342,54 @@ int mbox_reset_cold(void)
return 0;
}
+/* Accepted commands: CONFIG_STATUS or RECONFIG_STATUS */
+static __always_inline int mbox_get_fpga_config_status_common(u32 cmd)
+{
+ u32 reconfig_status_resp_len;
+ u32 reconfig_status_resp[RECONFIG_STATUS_RESPONSE_LEN];
+ int ret;
+
+ reconfig_status_resp_len = RECONFIG_STATUS_RESPONSE_LEN;
+ ret = mbox_send_cmd_common(MBOX_ID_UBOOT, cmd,
+ MBOX_CMD_DIRECT, 0, NULL, 0,
+ &reconfig_status_resp_len,
+ reconfig_status_resp);
+
+ if (ret)
+ return ret;
+
+ /* Check for any error */
+ ret = reconfig_status_resp[RECONFIG_STATUS_STATE];
+ if (ret && ret != MBOX_CFGSTAT_STATE_CONFIG)
+ return ret;
+
+ /* Make sure nStatus is not 0 */
+ ret = reconfig_status_resp[RECONFIG_STATUS_PIN_STATUS];
+ if (!(ret & RCF_PIN_STATUS_NSTATUS))
+ return MBOX_CFGSTAT_STATE_ERROR_HARDWARE;
+
+ ret = reconfig_status_resp[RECONFIG_STATUS_SOFTFUNC_STATUS];
+ if (ret & RCF_SOFTFUNC_STATUS_SEU_ERROR)
+ return MBOX_CFGSTAT_STATE_ERROR_HARDWARE;
+
+ if ((ret & RCF_SOFTFUNC_STATUS_CONF_DONE) &&
+ (ret & RCF_SOFTFUNC_STATUS_INIT_DONE) &&
+ !reconfig_status_resp[RECONFIG_STATUS_STATE])
+ return 0; /* configuration success */
+
+ return MBOX_CFGSTAT_STATE_CONFIG;
+}
+
+int mbox_get_fpga_config_status(u32 cmd)
+{
+ return mbox_get_fpga_config_status_common(cmd);
+}
+
+int __secure mbox_get_fpga_config_status_psci(u32 cmd)
+{
+ return mbox_get_fpga_config_status_common(cmd);
+}
+
int mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg,
u8 urgent, u32 *resp_buf_len, u32 *resp_buf)
{
--
2.7.4
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[U-Boot] [PATCH v8 2/5] arm: socfpga: stratix10: Add macros for mailbox's arguments
From: "Ang, Chee Hong"
Add macros for specifying number of arguments in mailbox command.
Signed-off-by: Ang, Chee Hong
---
arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
index 660df35..ae728a5 100644
--- a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
@@ -107,6 +107,12 @@ enum ALT_SDM_MBOX_RESP_CODE {
#define RECONFIG_STATUS_PIN_STATUS 2
#define RECONFIG_STATUS_SOFTFUNC_STATUS3
+/* Macros for specifying number of arguments in mailbox command */
+#define MBOX_NUM_ARGS(n, b)(((n) & 0xFF) << (b))
+#define MBOX_DIRECT_COUNT(n) MBOX_NUM_ARGS((n), 0)
+#define MBOX_ARG_DESC_COUNT(n) MBOX_NUM_ARGS((n), 8)
+#define MBOX_RESP_DESC_COUNT(n)
MBOX_NUM_ARGS((n), 16)
+
#define MBOX_CFGSTAT_STATE_IDLE0x
#define MBOX_CFGSTAT_STATE_CONFIG 0x1000
#define MBOX_CFGSTAT_STATE_FAILACK 0x0800
--
2.7.4
___
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[U-Boot] [PATCH v8 3/5] arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver
From: "Ang, Chee Hong"
Enable FPGA reconfiguration support for Stratix 10 SoC.
Signed-off-by: Ang, Chee Hong
---
drivers/fpga/Kconfig | 11 ++
drivers/fpga/Makefile| 1 +
drivers/fpga/stratix10.c | 288 +++
include/altera.h | 4 +
4 files changed, 304 insertions(+)
create mode 100644 drivers/fpga/stratix10.c
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index 50e9019..8f59193 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -31,6 +31,17 @@ config FPGA_CYCLON2
Enable FPGA driver for loading bitstream in BIT and BIN format
on Altera Cyclone II device.
+config FPGA_STRATIX10
+ bool "Enable Altera FPGA driver for Stratix 10"
+ depends on TARGET_SOCFPGA_STRATIX10
+ select FPGA_ALTERA
+ help
+ Say Y here to enable the Altera Stratix 10 FPGA specific driver
+
+ This provides common functionality for Altera Stratix 10 devices.
+ Enable FPGA driver for writing bitstream into Altera Stratix10
+ device.
+
config FPGA_XILINX
bool "Enable Xilinx FPGA drivers"
select FPGA
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 97d7d5d..5a778c1 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o
obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o
obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o
+obj-$(CONFIG_FPGA_STRATIX10) += stratix10.o
obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o
obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o
obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += socfpga_arria10.o
diff --git a/drivers/fpga/stratix10.c b/drivers/fpga/stratix10.c
new file mode 100644
index 000..aae0521
--- /dev/null
+++ b/drivers/fpga/stratix10.c
@@ -0,0 +1,288 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Intel Corporation
+ */
+
+#include
+#include
+#include
+
+#define RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS 6
+#define RECONFIG_STATUS_INTERVAL_DELAY_US 100
+
+static const struct mbox_cfgstat_state {
+ int err_no;
+ const char *error_name;
+} mbox_cfgstat_state[] = {
+ {MBOX_CFGSTAT_STATE_IDLE, "FPGA in idle mode."},
+ {MBOX_CFGSTAT_STATE_CONFIG, "FPGA in config mode."},
+ {MBOX_CFGSTAT_STATE_FAILACK, "Acknowledgment failed!"},
+ {MBOX_CFGSTAT_STATE_ERROR_INVALID, "Invalid bitstream!"},
+ {MBOX_CFGSTAT_STATE_ERROR_CORRUPT, "Corrupted bitstream!"},
+ {MBOX_CFGSTAT_STATE_ERROR_AUTH, "Authentication failed!"},
+ {MBOX_CFGSTAT_STATE_ERROR_CORE_IO, "I/O error!"},
+ {MBOX_CFGSTAT_STATE_ERROR_HARDWARE, "Hardware error!"},
+ {MBOX_CFGSTAT_STATE_ERROR_FAKE, "Fake error!"},
+ {MBOX_CFGSTAT_STATE_ERROR_BOOT_INFO, "Error in boot info!"},
+ {MBOX_CFGSTAT_STATE_ERROR_QSPI_ERROR, "Error in QSPI!"},
+ {MBOX_RESP_ERROR, "Mailbox general error!"},
+ {-ETIMEDOUT, "I/O timeout error"},
+ {-1, "Unknown error!"}
+};
+
+#define MBOX_CFGSTAT_MAX ARRAY_SIZE(mbox_cfgstat_state)
+
+static const char *mbox_cfgstat_to_str(int err)
+{
+ int i;
+
+ for (i = 0; i < MBOX_CFGSTAT_MAX - 1; i++) {
+ if (mbox_cfgstat_state[i].err_no == err)
+ return mbox_cfgstat_state[i].error_name;
+ }
+
+ return mbox_cfgstat_state[MBOX_CFGSTAT_MAX - 1].error_name;
+}
+
+/*
+ * Add the ongoing transaction's command ID into pending list and return
+ * the command ID for next transfer.
+ */
+static u8 add_transfer(u32 *xfer_pending_list, size_t list_size, u8 id)
+{
+ int i;
+
+ for (i = 0; i < list_size; i++) {
+ if (xfer_pending_list[i])
+ continue;
+ xfer_pending_list[i] = id;
+ debug("ID(%d) added to transaction pending list\n", id);
+ /*
+* Increment command ID for next transaction.
+* Valid command ID (4 bits) is from 1 to 15.
+*/
+ id = (id % 15) + 1;
+ break;
+ }
+
+ return id;
+}
+
+/*
+ * Check whether response ID match the command ID in the transfer
+ * pending list. If a match is found in the transfer pending list,
+ * it clears the transfer pending list and return the matched
+ * command ID.
+ */
+static int get_and_clr_transfer(u32 *xfer_pending_list, size_t list_size,
+ u8 id)
+{
+ int i;
+
+ for (i = 0; i < list_size; i++) {
+ if (id != xfer_pending_list[i])
+ continue;
+ xfer_pending_list[i] = 0;
+ return id;
+ }
+
+ return 0;
+}
+
+/*
+ * Polling the FPGA configuration status.
+ * Return 0 for success, non-zero for error.
+ */
+static int reconfig_status_polling_resp(void)
+{
+ int ret;
+ unsigned long start = get_timer(0);
+
+
[U-Boot] [PATCH v8 5/5] arm: socfpga: stratix10: Enable Stratix10 FPGA Reconfiguration
From: "Ang, Chee Hong" Select CONFIG_FPGA_STRATIX10 for CONFIG_TARGET_SOCFPGA_STRATIX10. Signed-off-by: Ang, Chee Hong --- arch/arm/mach-socfpga/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 06f8527..5e87371 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -35,6 +35,7 @@ config TARGET_SOCFPGA_STRATIX10 select ARMV8_MULTIENTRY select ARMV8_SET_SMPEN select ARMV8_SPIN_TABLE + select FPGA_STRATIX10 choice prompt "Altera SOCFPGA board select" -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v8 4/5] arm: socfpga: stratix10: Add Stratix10 FPGA into FPGA device table
From: "Ang, Chee Hong"
Enable 'fpga' command in u-boot. User will be able to use the FPGA
command to program the FPGA on Stratix10 SoC.
Signed-off-by: Ang, Chee Hong
---
arch/arm/mach-socfpga/include/mach/misc.h | 4 ++--
arch/arm/mach-socfpga/misc.c | 26 ++
arch/arm/mach-socfpga/misc_arria10.c | 23 ++-
arch/arm/mach-socfpga/misc_gen5.c | 22 +-
arch/arm/mach-socfpga/misc_s10.c | 22 ++
drivers/fpga/altera.c | 6 ++
include/altera.h | 4
7 files changed, 79 insertions(+), 28 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/misc.h
b/arch/arm/mach-socfpga/include/mach/misc.h
index 2660992..86d5d2b 100644
--- a/arch/arm/mach-socfpga/include/mach/misc.h
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -18,9 +18,9 @@ struct bsel {
extern struct bsel bsel_str[];
#ifdef CONFIG_FPGA
-void socfpga_fpga_add(void);
+void socfpga_fpga_add(void *fpga_desc);
#else
-static inline void socfpga_fpga_add(void) {}
+inline void socfpga_fpga_add(void *fpga_desc) {}
#endif
#ifdef CONFIG_TARGET_SOCFPGA_GEN5
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index a4f6d5c..78fbe28 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -88,33 +88,11 @@ int overwrite_console(void)
#endif
#ifdef CONFIG_FPGA
-/*
- * FPGA programming support for SoC FPGA Cyclone V
- */
-static Altera_desc altera_fpga[] = {
- {
- /* Family */
- Altera_SoCFPGA,
- /* Interface type */
- fast_passive_parallel,
- /* No limitation as additional data will be ignored */
- -1,
- /* No device function table */
- NULL,
- /* Base interface address specified in driver */
- NULL,
- /* No cookie implementation */
- 0
- },
-};
-
/* add device descriptor to FPGA device table */
-void socfpga_fpga_add(void)
+void socfpga_fpga_add(void *fpga_desc)
{
- int i;
fpga_init();
- for (i = 0; i < ARRAY_SIZE(altera_fpga); i++)
- fpga_add(fpga_altera, &altera_fpga[i]);
+ fpga_add(fpga_altera, fpga_desc);
}
#endif
diff --git a/arch/arm/mach-socfpga/misc_arria10.c
b/arch/arm/mach-socfpga/misc_arria10.c
index f347ae8..63b8c75 100644
--- a/arch/arm/mach-socfpga/misc_arria10.c
+++ b/arch/arm/mach-socfpga/misc_arria10.c
@@ -30,6 +30,27 @@
static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+
+/*
+ * FPGA programming support for SoC FPGA Arria 10
+ */
+static Altera_desc altera_fpga[] = {
+ {
+ /* Family */
+ Altera_SoCFPGA,
+ /* Interface type */
+ fast_passive_parallel,
+ /* No limitation as additional data will be ignored */
+ -1,
+ /* No device function table */
+ NULL,
+ /* Base interface address specified in driver */
+ NULL,
+ /* No cookie implementation */
+ 0
+ },
+};
+
#if defined(CONFIG_SPL_BUILD)
static struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
@@ -73,7 +94,7 @@ void socfpga_sdram_remap_zero(void)
int arch_early_init_r(void)
{
/* Add device descriptor to FPGA device table */
- socfpga_fpga_add();
+ socfpga_fpga_add(&altera_fpga[0]);
return 0;
}
diff --git a/arch/arm/mach-socfpga/misc_gen5.c
b/arch/arm/mach-socfpga/misc_gen5.c
index 5fa4093..04f237d 100644
--- a/arch/arm/mach-socfpga/misc_gen5.c
+++ b/arch/arm/mach-socfpga/misc_gen5.c
@@ -35,6 +35,26 @@ static struct scu_registers *scu_regs =
(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
/*
+ * FPGA programming support for SoC FPGA Cyclone V
+ */
+static Altera_desc altera_fpga[] = {
+ {
+ /* Family */
+ Altera_SoCFPGA,
+ /* Interface type */
+ fast_passive_parallel,
+ /* No limitation as additional data will be ignored */
+ -1,
+ /* No device function table */
+ NULL,
+ /* Base interface address specified in driver */
+ NULL,
+ /* No cookie implementation */
+ 0
+ },
+};
+
+/*
* DesignWare Ethernet initialization
*/
#ifdef CONFIG_ETH_DESIGNWARE
@@ -221,7 +241,7 @@ int arch_early_init_r(void)
socfpga_sdram_remap_zero();
/* Add device descriptor to FPGA device table */
- socfpga_fpga_add();
+ socfpga_fpga_add(&altera_fpga[0]);
#ifdef CONFIG_DESIGNWARE_SPI
/* Get Designware SPI controller out of reset */
diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c
index e59936
[U-Boot] [RFC PATCH] ARM: mvebu: add support for Allied Telesis x530
From: Chris Packham
This is a range of stackable network switches. The SoC is Armada-385 and
there are a number of variants with differing network port
configurations. The DP variants are intended for a harsher operating
environment so they use a different i2c mux and fit industrial-temp
parts.
Signed-off-by: Chris Packham
---
This needs http://patchwork.ozlabs.org/patch/1010285/
I imagine that the dts names may want some extra qualifiers. The boards
aren't in upstream Linux (the source for our fork is published for GPL
compliance) so there is some flexibility to change the name.
arch/arm/dts/Makefile | 4 +-
arch/arm/dts/x530.dts | 48 +
arch/arm/dts/x530.dtsi| 269 ++
arch/arm/dts/x530DP.dts | 50 +
arch/arm/dts/x530DP.dtsi | 149 ++
arch/arm/mach-mvebu/Kconfig | 7 +
board/alliedtelesis/common/gpio_hog.c | 36
board/alliedtelesis/common/gpio_hog.h | 13 ++
board/alliedtelesis/x530/MAINTAINERS | 12 ++
board/alliedtelesis/x530/Makefile | 9 +
board/alliedtelesis/x530/kwbimage.cfg | 12 ++
board/alliedtelesis/x530/x530.c | 161 +++
configs/x530_defconfig| 71 +++
include/configs/x530.h| 134 +
14 files changed, 974 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/x530.dts
create mode 100644 arch/arm/dts/x530.dtsi
create mode 100644 arch/arm/dts/x530DP.dts
create mode 100644 arch/arm/dts/x530DP.dtsi
create mode 100644 board/alliedtelesis/common/gpio_hog.c
create mode 100644 board/alliedtelesis/common/gpio_hog.h
create mode 100644 board/alliedtelesis/x530/MAINTAINERS
create mode 100644 board/alliedtelesis/x530/Makefile
create mode 100644 board/alliedtelesis/x530/kwbimage.cfg
create mode 100644 board/alliedtelesis/x530/x530.c
create mode 100644 configs/x530_defconfig
create mode 100644 include/configs/x530.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index dc6f6b233a6a..72d78d011c14 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -109,7 +109,9 @@ dtb-$(CONFIG_ARCH_MVEBU) += \
armada-xp-maxbcm.dtb\
armada-xp-synology-ds414.dtb\
armada-xp-theadorable.dtb \
- armada-38x-controlcenterdc.dtb
+ armada-38x-controlcenterdc.dtb \
+ x530.dtb\
+ x530DP.dtb
dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \
uniphier-ld11-global.dtb \
diff --git a/arch/arm/dts/x530.dts b/arch/arm/dts/x530.dts
new file mode 100644
index ..22f1c4268b7d
--- /dev/null
+++ b/arch/arm/dts/x530.dts
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+#include "x530.dtsi"
+
+/ {
+ model = "Allied Telesis x530";
+ compatible = "alliedtelesis,x530", "marvell,armada385",
"marvell,armada380";
+
+ nand-protect {
+ compatible = "atl,nand-protect";
+ protect-gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>;
+ };
+
+ usb-enable {
+ compatible = "atl,usb-enable";
+ enable-gpio = <&gpio0 19 GPIO_ACTIVE_HIGH>;
+ };
+
+ boot-board {
+ compatible = "atl,boot-board";
+ present-gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>;
+ override-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+ };
+
+ phy-reset {
+ compatible = "atl,phy-reset";
+ reset-gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>,
+<&gpio1 21 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-enable {
+ compatible = "atl,led-enable";
+ enable-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>;
+ };
+
+ led_7seg {
+ compatible = "atl,of-led-7seg";
+ segment-gpios = <
+ &led_7seg_gpio 0 0
+ &led_7seg_gpio 1 0
+ &led_7seg_gpio 2 0
+ &led_7seg_gpio 3 0
+ &led_7seg_gpio 4 0
+ &led_7seg_gpio 5 0
+ &led_7seg_gpio 6 0
+ &led_7seg_gpio 7 0>;
+ };
+};
diff --git a/arch/arm/dts/x530.dtsi b/arch/arm/dts/x530.dtsi
new file mode 100644
index ..664fc6a8fe31
--- /dev/null
+++ b/arch/arm/dts/x530.dtsi
@@ -0,0 +1,269 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include
+#include "armada-385.dtsi"
+
+/ {
+ model = "Allied Telesis x530";
+ compatible = "alliedtelesis,x530", "marvell,armada385",
"marvell,armada380";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ bootargs = "console=ttyS0,115200 earlyprintk";
+ };
+
+ aliases {
+ spi1 = &spi1;
+ i2c0 = &i2c0;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x 0 0x4000>; /* 1 GB */
[U-Boot] [PATCH 2/2] rockchip: ram: update license for sdram driver
Rockchip may use this sdram copy of source code for both open source and internal project, update the license to use both GPL2.0+ and BSD-3 Clause. Signed-off-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3128.c | 2 +- drivers/ram/rockchip/sdram_rk3188.c | 2 +- drivers/ram/rockchip/sdram_rk322x.c | 2 +- drivers/ram/rockchip/sdram_rk3288.c | 2 +- drivers/ram/rockchip/sdram_rk3328.c | 2 +- drivers/ram/rockchip/sdram_rk3399.c | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3128.c b/drivers/ram/rockchip/sdram_rk3128.c index 4968900211..df7b988703 100644 --- a/drivers/ram/rockchip/sdram_rk3128.c +++ b/drivers/ram/rockchip/sdram_rk3128.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause /* * (C) Copyright 2017 Rockchip Electronics Co., Ltd. */ diff --git a/drivers/ram/rockchip/sdram_rk3188.c b/drivers/ram/rockchip/sdram_rk3188.c index 3774abfa98..fdd500aa47 100644 --- a/drivers/ram/rockchip/sdram_rk3188.c +++ b/drivers/ram/rockchip/sdram_rk3188.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause /* * (C) Copyright 2015 Google, Inc * Copyright 2014 Rockchip Inc. diff --git a/drivers/ram/rockchip/sdram_rk322x.c b/drivers/ram/rockchip/sdram_rk322x.c index e079ef7a70..53835a9cd0 100644 --- a/drivers/ram/rockchip/sdram_rk322x.c +++ b/drivers/ram/rockchip/sdram_rk322x.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause /* * (C) Copyright 2017 Rockchip Electronics Co., Ltd */ diff --git a/drivers/ram/rockchip/sdram_rk3288.c b/drivers/ram/rockchip/sdram_rk3288.c index bb3cf48788..d1e52d84e7 100644 --- a/drivers/ram/rockchip/sdram_rk3288.c +++ b/drivers/ram/rockchip/sdram_rk3288.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause /* * (C) Copyright 2015 Google, Inc * Copyright 2014 Rockchip Inc. diff --git a/drivers/ram/rockchip/sdram_rk3328.c b/drivers/ram/rockchip/sdram_rk3328.c index 89d95b4f89..e8b234d866 100644 --- a/drivers/ram/rockchip/sdram_rk3328.c +++ b/drivers/ram/rockchip/sdram_rk3328.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause /* * (C) Copyright 2017 Rockchip Electronics Co., Ltd. */ diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 49ebd8809f..94dd01156a 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause /* * (C) Copyright 2016-2017 Rockchip Inc. * -- 2.18.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/2] rockchip: rk3036: ram: update license
All the source code of sdram_rk3036.c are from Rockchip, update the copyright to owned by Rockchip. Because rockchip may use this copy of code both for open source project and internal project, update the license to use both GPL2.0+ and BSD-3 Clause. Signed-off-by: Kever Yang --- arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c index 4e5690eae3..2012d9fe04 100644 --- a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c +++ b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause /* - * (C) Copyright 2015 Google, Inc + * (C) Copyright 2015 Rockchip Electronics Co., Ltd */ #include #include -- 2.18.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 0/3] Ethernet support for QEMU sifive_u machine
+Michal On Wed, Dec 19, 2018 at 6:02 PM Anup Patel wrote: > > This patchset enables Cadance MACB ethernet driver for > QEMU sifive_u machine. The Cadance MACB ethernet driver > works fine for QEMU sifive_u machince in both M-mode and > S-mode with some minor fixes. > > The patches are based upon latest RISC-V U-Boot tree > (git://git.denx.de/u-boot-riscv.git) at commit id > 9deb8d2fcd13d4a40a4e63c396fe4376af46efac > > To try on QEMU, please ensure following patches are > applied to QEMU sources: > https://patchwork.kernel.org/patch/10729579/ > https://patchwork.kernel.org/patch/10729581/ > > Changes since v1: > - Minor nit changes in PATCH1 > > Anup Patel (3): > riscv: Add asm/dma-mapping.h for DMA mappings > net: macb: Fix clk API usage for RISC-V systems > riscv: qemu: Imply MACB ethernet for emulation > > arch/riscv/include/asm/dma-mapping.h | 38 > board/emulation/qemu-riscv/Kconfig | 4 +++ > drivers/net/macb.c | 4 ++- > 3 files changed, 45 insertions(+), 1 deletion(-) > create mode 100644 arch/riscv/include/asm/dma-mapping.h > > -- > 2.17.1 > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] riscv: Add asm/dma-mapping.h for DMA mappings
+Michal
On Mon, Dec 17, 2018 at 5:21 PM Anup Patel wrote:
>
> From: Anup Patel
>
> This patch adds asm/dma-mapping.h for Linux-like DMA mappings
> APIs required by some of the drivers (such as, Cadance MACB
> Ethernet driver).
>
> Signed-off-by: Anup Patel
> ---
> arch/riscv/include/asm/dma-mapping.h | 37
> 1 file changed, 37 insertions(+)
> create mode 100644 arch/riscv/include/asm/dma-mapping.h
>
> diff --git a/arch/riscv/include/asm/dma-mapping.h
> b/arch/riscv/include/asm/dma-mapping.h
> new file mode 100644
> index 00..9782b6f168
> --- /dev/null
> +++ b/arch/riscv/include/asm/dma-mapping.h
> @@ -0,0 +1,37 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (c) 2018 Western Digital Corporation or its affiliates.
> + *
> + * Authors:
> + * Anup Patel
> + */
> +#ifndef __ASM_RISCV_DMA_MAPPING_H
> +#define __ASM_RISCV_DMA_MAPPING_H
> +
> +#include
> +
> +#definedma_mapping_error(x, y) 0
> +
> +static inline void *dma_alloc_coherent(size_t len, unsigned long *handle)
> +{
> + *handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, len);
> + return (void *)*handle;
> +}
> +
> +static inline void dma_free_coherent(void *addr)
> +{
> + free(addr);
> +}
> +
> +static inline unsigned long dma_map_single(volatile void *vaddr, size_t len,
> + enum dma_data_direction dir)
> +{
> + return (unsigned long)vaddr;
> +}
> +
> +static inline void dma_unmap_single(volatile void *vaddr, size_t len,
> + unsigned long paddr)
> +{
> +}
> +
> +#endif /* __ASM_RISCV_DMA_MAPPING_H */
> --
> 2.17.1
>
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