Re: [U-Boot] [PATCH v5 01/16] arm: socfpga: Restructure clock manager driver
On Fri, Apr 14, 2017 at 6:15 PM, Marek Vasut wrote:
> On 04/13/2017 07:41 PM, Ley Foon Tan wrote:
>> Restructure clock manager driver in the preparation to support A10.
>> Move the Gen5 specific code to _gen5 files.
>>
>> - Change all uint32_t to u32 and change to use macro BIT(n) for bit shift.
>> - Check return value from wait_for_bit(). So change return type to int for
>> cm_write_with_phase() and cm_basic_init().
>>
>> Signed-off-by: Ley Foon Tan
>
> [...]
>
>> /* function to write a clock register that has phase information */
>> -static void cm_write_with_phase(uint32_t value,
>> - uint32_t reg_address, uint32_t mask)
>> +static int cm_write_with_phase(u32 value, u32 reg_address, u32 mask)
>> {
>> + int ret;
>> +
>> /* poll until phase is zero */
>> - while (readl(reg_address) & mask)
>> - ;
>> + ret = wait_for_bit(__func__, (const u32 *)reg_address, mask,
>> +false, 2, false);
>> + if (ret)
>> + return ret;
>>
>> writel(value, reg_address);
>>
>> - while (readl(reg_address) & mask)
>> - ;
>> + return wait_for_bit(__func__, (const u32 *)reg_address, mask,
>> + false, 2, false);
>> }
>>
>
> Could it be that this active wait is here so that it'd work without an
> initialized timer ? Because at this point, you don't have timer and I
> think wait_for_bit() uses timer.
>
Timer is initialized before calling to this function. So, should be no problem.
In arch/arm/mach-socfpga/spl.c, timer is initialized before calling to
cm_basic_init(). Note, cm_write_with_phase() is called by
cm_basic_init().
socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
timer_init();
debug("Reconfigure Clock Manager\n");
/* reconfigure the PLLs */
if (cm_basic_init(cm_default_cfg))
hang();
Regards
Ley Foon
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[U-Boot] [PATCH 1/3][v4] arm: ls1043ardb: Add SD secure boot target
- Add SD secure boot target for ls1043ardb.
- Implement FSL_LSCH2 specific spl_board_init() to setup CAAM stream ID and
corresponding stream ID in SMMU.
- Change the u-boot size defined by a macro for copying the main U-Boot by SPL
to also include the u-boot Secure Boot header size as header is appended to
u-boot image. So header will also be copied from SD to DDR.
- CONFIG_MAX_SPL_SIZE is limited to 90K.SPL is copied to OCRAM (128K) where 32K
are reserved for use by boot ROM and 6K for secure boto header
- Error messages during SPL boot are limited to error code numbers instead of
strings
to reduce the size of SPL image
Signed-off-by: Vinitha Pillai-B57223
Signed-off-by: Sumit Garg
Signed-off-by: Ruchika Gupta
---
Changes in v4:
Updated Maintainers file
Changes in v3:
Moved spl_board_init function to arch/arm/cpu/armv8/fsl-layerscape/spl.c
Changes in v2:
Rebased to latest dependent patches: - No change
Dependent patch set:
SECURE boot target addition for NOR on LS1043, LS1046
https://patchwork.ozlabs.org/patch/742548/
https://patchwork.ozlabs.org/patch/742552/
https://patchwork.ozlabs.org/patch/742549/
https://patchwork.ozlabs.org/patch/742551/
https://patchwork.ozlabs.org/patch/742550/
https://patchwork.ozlabs.org/patch/742553/
https://patchwork.ozlabs.org/patch/742554/
and
SPL size reduction patches
https://patchwork.ozlabs.org/patch/744755/
https://patchwork.ozlabs.org/patch/744756/
arch/arm/cpu/armv8/fsl-layerscape/spl.c | 18
arch/arm/include/asm/fsl_secure_boot.h | 9 +++-
board/freescale/common/fsl_validate.c | 4 ++
board/freescale/ls1043ardb/MAINTAINERS | 1 +
configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig | 57 +
include/configs/ls1043a_common.h| 16 ++-
6 files changed, 101 insertions(+), 4 deletions(-)
create mode 100644 configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c
b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
index 73a8680..dfacf98 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
@@ -41,6 +41,24 @@ u32 spl_boot_mode(const u32 boot_device)
}
#ifdef CONFIG_SPL_BUILD
+
+void spl_board_init(void)
+{
+#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_LSCH2)
+ /*
+* In case of Secure Boot, the IBR configures the SMMU
+* to allow only Secure transactions.
+* SMMU must be reset in bypass mode.
+* Set the ClientPD bit and Clear the USFCFG Bit
+ */
+ u32 val;
+ val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
+ out_le32(SMMU_SCR0, val);
+ val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
+ out_le32(SMMU_NSCR0, val);
+#endif
+}
+
void board_init_f(ulong dummy)
{
/* Clear global data */
diff --git a/arch/arm/include/asm/fsl_secure_boot.h
b/arch/arm/include/asm/fsl_secure_boot.h
index 423c2c4..56a6ba0 100644
--- a/arch/arm/include/asm/fsl_secure_boot.h
+++ b/arch/arm/include/asm/fsl_secure_boot.h
@@ -27,10 +27,11 @@
#define CONFIG_SPL_UBOOT_KEY_HASH NULL
#endif /* ifdef CONFIG_SPL_BUILD */
+#define CONFIG_KEY_REVOCATION
+
#ifndef CONFIG_SPL_BUILD
#define CONFIG_CMD_BLOB
#define CONFIG_CMD_HASH
-#define CONFIG_KEY_REVOCATION
#ifndef CONFIG_SYS_RAMBOOT
/* The key used for verification of next level images
* is picked up from an Extension Table which has
@@ -87,7 +88,11 @@
/* For SD boot address and size are assigned in terms of sector
* offset and no. of sectors respectively.
*/
-#define CONFIG_BS_HDR_ADDR_DEVICE 0x0900
+#if defined(CONFIG_LS1043A)
+#define CONFIG_BS_HDR_ADDR_DEVICE 0x0920
+#else
+#define CONFIG_BS_HDR_ADDR_DEVICE 0x0900
+#endif
#define CONFIG_BS_ADDR_DEVICE 0x0940
#define CONFIG_BS_HDR_SIZE 0x0010
#define CONFIG_BS_SIZE 0x0008
diff --git a/board/freescale/common/fsl_validate.c
b/board/freescale/common/fsl_validate.c
index 2b723a4..235c6ab 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -356,6 +356,7 @@ static void fsl_secboot_bootscript_parse_failure(void)
*/
void fsl_secboot_handle_error(int error)
{
+#ifndef CONFIG_SPL_BUILD
const struct fsl_secboot_errcode *e;
for (e = fsl_secboot_errcodes; e->errcode != ERROR_ESBC_CLIENT_MAX;
@@ -363,6 +364,9 @@ void fsl_secboot_handle_error(int error)
if (e->errcode == error)
printf("ERROR :: %x :: %s\n", error, e->name);
}
+#else
+ printf("ERROR :: %x\n", error);
+#endif
/* If Boot Mode is secure, transition the SNVS state and issue
* reset based on type of failure and ITS setting.
diff --git a/board/freescale/ls1043ardb/MAINTAINERS
b/board/freescale/ls1043ardb/MAINTAINERS
index 0503a3f..8b69892 100644
--- a/board/freescale/ls1043ardb/MAINTAINERS
+++ b/board/
[U-Boot] [PATCH 2/3][v4] arm: ls1043ardb: Add NAND secure boot target
Add NAND secure boot target for ls1043ardb. - Change the u-boot size defined by a macro for copying the main U-Boot by SPL to also include the u-boot Secure Boot header size as header is appended to u-boot image. So header will also be copied from SD to DDR. - MACRO for CONFIG_BOOTSCRIPT_COPY_RAM is enabled to copy Bootscript from NAND to DDR. Offsets for Bootscript on NAND and DDR have been also defined. Signed-off-by: Vinitha Pillai Signed-off-by: Sumit Garg Signed-off-by: Ruchika Gupta --- Changes in v4: Updated Maintainers file Changes in v3: Removed changes to ls1043ardb.c Changes in v2: - Rebased this patch to the latest dependent patch-set. Dependent patch set: SECURE boot target addition for NOR on LS1043, LS1046 https://patchwork.ozlabs.org/patch/742548/ https://patchwork.ozlabs.org/patch/742552/ https://patchwork.ozlabs.org/patch/742549/ https://patchwork.ozlabs.org/patch/742551/ https://patchwork.ozlabs.org/patch/742550/ https://patchwork.ozlabs.org/patch/742553/ https://patchwork.ozlabs.org/patch/742554/ and SPL size reduction patches https://patchwork.ozlabs.org/patch/744755/ https://patchwork.ozlabs.org/patch/744756/ arch/arm/include/asm/fsl_secure_boot.h| 7 +++- board/freescale/ls1043ardb/MAINTAINERS| 1 + configs/ls1043ardb_nand_SECURE_BOOT_defconfig | 57 +++ include/config_fsl_chain_trust.h | 9 +++-- include/configs/ls1043a_common.h | 18 - include/configs/ls1043ardb.h | 2 +- 6 files changed, 87 insertions(+), 7 deletions(-) create mode 100644 configs/ls1043ardb_nand_SECURE_BOOT_defconfig diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index 56a6ba0..9ca7abe 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -70,7 +70,7 @@ /* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from * Non-XIP Memory (Nand/SD)*/ #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_FSL_LSCH3) || \ - defined(CONFIG_SD_BOOT) + defined(CONFIG_SD_BOOT) || defined(CONFIG_NAND_BOOT) #define CONFIG_BOOTSCRIPT_COPY_RAM #endif /* The address needs to be modified according to NOR, NAND, SD and @@ -96,6 +96,11 @@ #define CONFIG_BS_ADDR_DEVICE 0x0940 #define CONFIG_BS_HDR_SIZE 0x0010 #define CONFIG_BS_SIZE 0x0008 +#elif defined(CONFIG_NAND_BOOT) +#define CONFIG_BS_HDR_ADDR_DEVICE 0x0080 +#define CONFIG_BS_ADDR_DEVICE 0x00802000 +#define CONFIG_BS_HDR_SIZE 0x2000 +#define CONFIG_BS_SIZE 0x1000 #elif defined(CONFIG_QSPI_BOOT) #ifdef CONFIG_ARCH_LS1046A #define CONFIG_BS_HDR_ADDR_DEVICE 0x4078 diff --git a/board/freescale/ls1043ardb/MAINTAINERS b/board/freescale/ls1043ardb/MAINTAINERS index 8b69892..87aa006 100644 --- a/board/freescale/ls1043ardb/MAINTAINERS +++ b/board/freescale/ls1043ardb/MAINTAINERS @@ -13,3 +13,4 @@ M:Ruchika Gupta S: Maintained F: configs/ls1043ardb_SECURE_BOOT_defconfig F: configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig +F: configs/ls1043ardb_nand_SECURE_BOOT_defconfig diff --git a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig new file mode 100644 index 000..66c89fa --- /dev/null +++ b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig @@ -0,0 +1,57 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1043ARDB=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT" +CONFIG_NAND_BOOT=y +CONFIG_SECURE_BOOT=y +CONFIG_BOOTDELAY=10 +CONFIG_SPL=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0 +CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PXE=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_FAT=y +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_SYS_NS16550=y +CONFIG_DM_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_STORAGE=y +CONFIG_RSA=y +CONFIG_SPL_RSA=y +CONFIG_SPL_CRYPTO_SUPPORT=y +CONFIG_SPL_HASH_SUPPORT=y diff --git a/include/config_fsl_chain_trust.h b/include/config_fsl_chain_trust.h index eb45e98..40d323e 100644 --- a/include/config_fsl_chain_trust.h +++ b/include/config_fsl_chain_trust.h @@ -81,
[U-Boot] [PATCH 3/3][v5] arm: ls1046ardb: Add SD secure boot target
- Add SD secure boot target for ls1046ardb. - Change the u-boot size defined by a macro for copying the main U-Boot by SPL to also include the u-boot Secure Boot header size as header is appended to u-boot image. So header will also be copied from SD to DDR. - CONFIG_MAX_SPL_SIZE is limited to 90K.SPL is copied to OCRAM (128K) where 32K are reserved for use by boot ROM and 6K for the header - Reduce the size of CAAM driver for SPL Blobification functions and descriptors, that are not required at the time of SPL are disabled. Further error code conversion to strings is disabled for SPL build. Signed-off-by: Vinitha Pillai Signed-off-by: Sumit Garg Signed-off-by: Ruchika Gupta --- Changes in v5: Updated MAINTAINERS file Changes in v4: Removed spl_board_init from board specific file. Changes in v3: Resend Changes in v2: - Rebased patches to latest dependent patch set - With the dependent path set , spl imag size increased to 94K. So - additionally reduce the spl image size by removing the functions from - CAAM driver that are not required in SPL flow Dependent patch set: SECURE boot target addition for NOR on LS1043, LS1046 https://patchwork.ozlabs.org/patch/742548/ https://patchwork.ozlabs.org/patch/742552/ https://patchwork.ozlabs.org/patch/742549/ https://patchwork.ozlabs.org/patch/742551/ https://patchwork.ozlabs.org/patch/742550/ https://patchwork.ozlabs.org/patch/742553/ https://patchwork.ozlabs.org/patch/742554/ and SPL size reduction patches https://patchwork.ozlabs.org/patch/744755/ https://patchwork.ozlabs.org/patch/744756/ arch/arm/include/asm/fsl_secure_boot.h | 2 +- board/freescale/ls1046ardb/MAINTAINERS | 6 configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig | 45 + drivers/crypto/fsl/jobdesc.c| 4 +-- drivers/crypto/fsl/jr.c | 19 ++- include/configs/ls1046a_common.h| 17 -- 6 files changed, 78 insertions(+), 15 deletions(-) create mode 100644 configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index 9ca7abe..97eab64 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -88,7 +88,7 @@ /* For SD boot address and size are assigned in terms of sector * offset and no. of sectors respectively. */ -#if defined(CONFIG_LS1043A) +#if defined(CONFIG_LS1043A) || defined(CONFIG_ARCH_LS1046A) #define CONFIG_BS_HDR_ADDR_DEVICE 0x0920 #else #define CONFIG_BS_HDR_ADDR_DEVICE 0x0900 diff --git a/board/freescale/ls1046ardb/MAINTAINERS b/board/freescale/ls1046ardb/MAINTAINERS index ff42bef..8148b90 100644 --- a/board/freescale/ls1046ardb/MAINTAINERS +++ b/board/freescale/ls1046ardb/MAINTAINERS @@ -7,3 +7,9 @@ F: include/configs/ls1046ardb.h F: configs/ls1046ardb_qspi_defconfig F: configs/ls1046ardb_sdcard_defconfig F: configs/ls1046ardb_emmc_defconfig + +LS1046A_SECURE_BOOT BOARD +M: Ruchika Gupta +S: Maintained +F: configs/ls1046ardb_SECURE_BOOT_defconfig +F: configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig diff --git a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig new file mode 100644 index 000..a41ec80 --- /dev/null +++ b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig @@ -0,0 +1,45 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1046ARDB=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb" +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL" +CONFIG_SECURE_BOOT=y +CONFIG_SD_BOOT=y +CONFIG_BOOTDELAY=10 +CONFIG_SPL=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110 +CONFIG_HUSH_PARSER=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_FAT=y +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_SYS_NS16550=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_RSA=y +CONFIG_SPL_RSA=y +CONFIG_SPL_CRYPTO_SUPPORT=y +CONFIG_SPL_HASH_SUPPORT=y diff --git a/drivers/crypto/fsl/jobdesc.c b/drivers/crypto/fsl/jobdesc.c index 6125bbb..375ff9d 100644 --- a/drivers/crypto/fsl/jobdesc.c +++ b/drivers/crypto/fsl/jobdesc.c @@ -204,7 +204,7 @@ void inline_cnstr_jobdesc_hash(uint32_t *desc, append_store(desc, dma_addr_out, storelen, LDST_CLASS_2_CCB | LDST_SRCDST_BYTE_CONTEXT); } - +#ifndef CONFIG_SPL_BUILD void inline_cnstr_jobdesc_blob_encap(uint32_t *desc, uint8_t *key_idnfr, uint8_t *plain_txt, uint8_t *enc_blob,
Re: [U-Boot] U-boot-sunxi status?
On Mon, Apr 17, 2017 at 3:38 AM, Chen-Yu Tsai wrote: > Hi, > > (Resent from my main email address.) > > What's the current status of u-boot-sunxi? There are still some > patch series floating around. Some of them have been around for > a while now, listed here in no particular order: > > - sunxi: Add support for R40 SoC v2 (by Chen-Yu Tsai) > - sunxi: Remove SYS_EXTRA_OPTIONS v3 (by Mylene Josserand) > - sunxi: video: Add support for HDMI output on A64/H3/H5 v3 (by > Jernej Skrabec) > - Allwinner V3s and Lichee Pi Zero support (w/o SPL) v5 (by Icenowy Zheng) > - Allwinner DesignWare-like DRAM controllers refactor v1 (by Icenowy Zheng) > - Various DM related patch series from Philipp Tomsich > > Also sunxi related but probably not going through u-boot-sunxi: > > - SPL: extend FIT loading support v3 (by Andre Przywara) > - Retrieve MAC address from EEPROM v5 (by Olliver Schinagl) > > Some of these series have been fully reviewed, others only partially. > I'm sure there are more out there, but I don't track U-boot patches > as closely as kernel patches. So how can we help getting all these > things ready and merged? Has the AW A64 ATF support patch series been merged? Peter ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3][v3] arm: ls1043ardb: Add SD secure boot target
> -Original Message- > From: York Sun [mailto:york@nxp.com] > Sent: Wednesday, April 12, 2017 9:10 PM > To: Ruchika Gupta ; u-boot@lists.denx.de > Cc: Vini Pillai ; Sumit Garg > Subject: Re: [PATCH 1/3][v3] arm: ls1043ardb: Add SD secure boot target > > On 04/04/2017 10:36 AM, Ruchika Gupta wrote: > > - Add SD secure boot target for ls1043ardb. > > - Implement FSL_LSCH2 specific spl_board_init() to setup CAAM stream ID and > > corresponding stream ID in SMMU. > > - Change the u-boot size defined by a macro for copying the main U-Boot by > SPL > > to also include the u-boot Secure Boot header size as header is appended > > to > > u-boot image. So header will also be copied from SD to DDR. > > - CONFIG_MAX_SPL_SIZE is limited to 90K.SPL is copied to OCRAM (128K) > where 32K > > are reserved for use by boot ROM and 6K for secure boto header > > - Error messages during SPL boot are limited to error code numbers instead > > of > strings > > to reduce the size of SPL image > > > > Signed-off-by: Vinitha Pillai-B57223 > > Signed-off-by: Sumit Garg > > Signed-off-by: Ruchika Gupta > > --- > > Changes in v3: > > Moved spl_board_init function to > > arch/arm/cpu/armv8/fsl-layerscape/spl.c > > > > Changes in v2: > > Rebased to latest dependent patches: - No change > > > > Dependent patch set: > > SECURE boot target addition for NOR on LS1043, LS1046 > > https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpat > > > chwork.ozlabs.org%2Fpatch%2F742548%2F&data=01%7C01%7Cyork.sun%40nx > p.co > > > m%7Cf396ee2809844110a67208d47b811229%7C686ea1d3bc2b4c6fa92cd99c5 > c30163 > > > 5%7C0&sdata=TREZk2QQagpnbnEhKaW3XRWqIkFUMZSpP7o%2FBRsZWzw%3D > &reserved= > > 0 > > https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpat > > > chwork.ozlabs.org%2Fpatch%2F742552%2F&data=01%7C01%7Cyork.sun%40nx > p.co > > > m%7Cf396ee2809844110a67208d47b811229%7C686ea1d3bc2b4c6fa92cd99c5 > c30163 > > > 5%7C0&sdata=bBUdA%2FzXtcqmDujeuwzCBEttEsuiWRhX5Neliw7bCb8%3D&res > erved= > > 0 > > https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpat > > > chwork.ozlabs.org%2Fpatch%2F742549%2F&data=01%7C01%7Cyork.sun%40nx > p.co > > > m%7Cf396ee2809844110a67208d47b811229%7C686ea1d3bc2b4c6fa92cd99c5 > c30163 > > > 5%7C0&sdata=jxL2qZrSQsz2ABZWXSoxBu9CRcE0to%2FVeUZhatcRIqw%3D&res > erved= > > 0 > > https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpat > > > chwork.ozlabs.org%2Fpatch%2F742551%2F&data=01%7C01%7Cyork.sun%40nx > p.co > > > m%7Cf396ee2809844110a67208d47b811229%7C686ea1d3bc2b4c6fa92cd99c5 > c30163 > > > 5%7C0&sdata=RGdT6UfnwGmmTs%2Boq5hXQVpLKoMrySlEQnUV6moXeZo%3D > &reserved= > > 0 > > https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpat > > > chwork.ozlabs.org%2Fpatch%2F742550%2F&data=01%7C01%7Cyork.sun%40nx > p.co > > > m%7Cf396ee2809844110a67208d47b811229%7C686ea1d3bc2b4c6fa92cd99c5 > c30163 > > > 5%7C0&sdata=RyfAhL%2Fx65BdUorLVM63Uq0TyL%2B9mhLD16npVY5ZvEw%3 > D&reserve > > d=0 > > https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpat > > > chwork.ozlabs.org%2Fpatch%2F742553%2F&data=01%7C01%7Cyork.sun%40nx > p.co > > > m%7Cf396ee2809844110a67208d47b811229%7C686ea1d3bc2b4c6fa92cd99c5 > c30163 > > > 5%7C0&sdata=cpegSJ%2F6R5hooE%2BUfKxtaNRoi97BPvpsTXbQKY3vDsA%3D&r > eserve > > d=0 > > https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpat > > > chwork.ozlabs.org%2Fpatch%2F742554%2F&data=01%7C01%7Cyork.sun%40nx > p.co > > > m%7Cf396ee2809844110a67208d47b811229%7C686ea1d3bc2b4c6fa92cd99c5 > c30163 > > > 5%7C0&sdata=oHsnTFilBpdmpQ5rroTH5Rf8auUe4PzN6rQDPEhsGRM%3D&reser > ved=0 > > > > and > > SPL size reduction patches > > https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpat > > > chwork.ozlabs.org%2Fpatch%2F744755%2F&data=01%7C01%7Cyork.sun%40nx > p.co > > > m%7Cf396ee2809844110a67208d47b811229%7C686ea1d3bc2b4c6fa92cd99c5 > c30163 > > > 5%7C0&sdata=HWmVUuGfRXsOt%2B6ld6NpzreZouBQETLOWFYNoZO3ri4%3D& > reserved= > > 0 > > https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpat > > > chwork.ozlabs.org%2Fpatch%2F744756%2F&data=01%7C01%7Cyork.sun%40nx > p.co > > > m%7Cf396ee2809844110a67208d47b811229%7C686ea1d3bc2b4c6fa92cd99c5 > c30163 > > > 5%7C0&sdata=e%2BlipO5SmoKq5dNc3%2FjlTqmLwwMvFCyFC3s40GLAvR0%3D > &reserve > > d=0 > > > > arch/arm/cpu/armv8/fsl-layerscape/spl.c | 18 > > arch/arm/include/asm/fsl_secure_boot.h | 9 +++- > > board/freescale/common/fsl_validate.c | 4 ++ > > configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig | 57 > + > > include/configs/ls1043a_common.h| 16 ++- > > 5 files changed, 100 insertions(+), 4 deletions(-) create mode > > 100644 configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig > > Please update MAINTAINERS files. > > York Next version of patch-set has been sent with updated MAINTAINERS files. Ruchika ___ U-Boot mailing list U-B
[U-Boot] [PATCH] rockchip: rk3399: correct memory region
RK3399 device memory region is 0xf800~0x.
Signed-off-by: Kever Yang
---
arch/arm/mach-rockchip/rk3399/rk3399.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c
b/arch/arm/mach-rockchip/rk3399/rk3399.c
index 8bb950e..a621a6f 100644
--- a/arch/arm/mach-rockchip/rk3399/rk3399.c
+++ b/arch/arm/mach-rockchip/rk3399/rk3399.c
@@ -15,13 +15,13 @@ static struct mm_region rk3399_mem_map[] = {
{
.virt = 0x0UL,
.phys = 0x0UL,
- .size = 0x8000UL,
+ .size = 0xf800UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
- .virt = 0xf000UL,
- .phys = 0xf000UL,
- .size = 0x1000UL,
+ .virt = 0xf800UL,
+ .phys = 0xf800UL,
+ .size = 0x0800UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
--
1.9.1
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Re: [U-Boot] [PATCH] rockchip: reserve memory for rk3399 ATF data
Hi Philipp, On 04/14/2017 06:51 PM, Dr. Philipp Tomsich wrote: Kever, Do we really need to change the SPL layout (i.e. BL2) for this? The SPL code should remain independent of later stages. This change would tie the U-Boot SPL (BL2) to a specific implementation/memory layout of the later BL31 stage. It should rather remain the responsibility of the BL31 stage to properly relocate itself as needed upon startup... We make this change because people think it's BL2's responsibility to load everything, to its loading address. I don't have much detail, but I do know that the upstream ATF of rk3399 is already using .elf format instead of .bin format and require BL2 to load 3 region data, bl31 do not do any relocation. I don't know if we can optimize the flow to reduce the memory dependency, I only met one issue if I don't apply this patch: board_fit_config_name_match function in arch/arm/mach-rockchip/rk3399-board-spl.c is corrupt after bl31 images loaded. This issue is because both BL2(SPL) and BL31 are using iram, I think it's OK to reserve memory for bl31 when there is enough memory, just like we need U-Boot and kernel reserved memory for ATF. Our (yet unreleased) development tree (for ATF) uses a much less intrusive approach to achieve the same result (using the knowledge that the ATF will not return to SPL and thus allowing the ATF to overwrite memory areas previously used by SPL): 1. ATF (BL31), the M0-firmware and the second-stage U-Boot are loaded as separate firmware blobs into DRAM using Andre's FIT image loader patches 2. SPL transfers control to ATF (with a vendor-specific parameter payload, which contains the location of the M0 firmware in DRAM) 3. ATF installs the M0 firmware into its final location The latest version ATF does no do this operation, which version of ATF are you using? Note that we’ve split the M0 firmware off the ATF build (and into a separate repository), as we’d otherwise end up with ELF files that has data/code/etc in the first MB of the address space and the M0 binary at 0xff8c — if you convert such an ELF to a binary, you’d end up with a file size of approx. 4GB. In other words: we don’t include the M0 binary into the ATF, but load it separately through the FIT image loader... I need 3 "loadable" binaries now, bl31, m0-firmware and bl31 data at iram, they are load separately through the FIT, and maybe secure check in the future. I’ll try to get our Cortex-M0 and ATF repositories pushed to our public GIT by early next week, so you can review… I will try to ask our ATF owner and related engineer to review, but since the latest version which bl31 do not do the relocate already in production for our rk3399 chromebook and Android project, but I think people won't change there already has a lot of discuss on this. Thanks, - Kever Regards, Philipp. On 14 Apr 2017, at 12:21, Kever Yang wrote: There are 3 region used by rk3399 ATF: - bl31 code, locate at 0x1; - cortex-m0 code and data, locate at 0xff8c; - bl31 data, locate at 0xff8c1000 ~ 0xff8c4000; SPL_TEXT_BASE starts from 0xff8c2000, we need to reserve memory for ATF data, or else there will have memory corrupt after SPL load ATF image. More detail about cortex-M0 code in ATF: https://github.com/ARM-software/arm-trusted-firmware/commit/ 8382e17c4c6bffd15119dfce1ee4372e3c1a7890 Signed-off-by: Kever Yang --- arch/arm/include/asm/arch-rockchip/boot0.h | 4 1 file changed, 4 insertions(+) diff --git a/arch/arm/include/asm/arch-rockchip/boot0.h b/arch/arm/include/asm/arch-rockchip/boot0.h index 8d7bc9a..f85a4db 100644 --- a/arch/arm/include/asm/arch-rockchip/boot0.h +++ b/arch/arm/include/asm/arch-rockchip/boot0.h @@ -16,3 +16,7 @@ .space 0x4 /* space for the 'RK33' */ #endif b reset + +#ifdef defined(CONFIG_ROCKCHIP_RK3399) && defined(CONFIG_SPL_BUILD) + .space 0x4000 /* space for the ATF data */ +#endif -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 11/22] x86: acpi: Resume OS if resume vector is found
Hi Bin,
On 12.04.2017 10:14, Bin Meng wrote:
> On Wed, Mar 22, 2017 at 4:06 AM, Simon Glass wrote:
>> Hi Bin,
>>
>> On 16 March 2017 at 08:26, Bin Meng wrote:
>>> In an S3 resume path, U-Boot does everything like a cold boot except
>>> in the last_stage_init() it jumps to the OS resume vector.
>>>
>>> Signed-off-by: Bin Meng
>>> ---
>>>
>>> arch/x86/cpu/cpu.c | 8
>>> arch/x86/include/asm/acpi_s3.h | 10 ++
>>> arch/x86/lib/Makefile | 1 +
>>> arch/x86/lib/acpi_s3.c | 26 ++
>>> 4 files changed, 45 insertions(+)
>>> create mode 100644 arch/x86/lib/acpi_s3.c
>>
>> Reviewed-by: Simon Glass
>>
>>>
>>> diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
>>> index 9dde54c..afc8645 100644
>>> --- a/arch/x86/cpu/cpu.c
>>> +++ b/arch/x86/cpu/cpu.c
>>> @@ -26,6 +26,7 @@
>>> #include
>>> #include
>>> #include
>>> +#include
>>> #include
>>> #include
>>> #include
>>> @@ -204,6 +205,13 @@ __weak void board_final_cleanup(void)
>>>
>>> int last_stage_init(void)
>>> {
>>> +#if CONFIG_HAVE_ACPI_RESUME
>>> + void *wake_vector = acpi_find_wakeup_vector();
>>> +
>>> + if (wake_vector != NULL && gd->arch.prev_sleep_state == ACPI_S3)
>>> + acpi_resume(wake_vector);
>>> +#endif
>>> +
>>> write_tables();
>>>
>>> board_final_cleanup();
>>> diff --git a/arch/x86/include/asm/acpi_s3.h b/arch/x86/include/asm/acpi_s3.h
>>> index f9d4739..5892a8b 100644
>>> --- a/arch/x86/include/asm/acpi_s3.h
>>> +++ b/arch/x86/include/asm/acpi_s3.h
>>> @@ -100,6 +100,16 @@ enum acpi_sleep_state chipset_prev_sleep_state(void);
>>> */
>>> void chipset_clear_sleep_state(void);
>>>
>>> +/**
>>> + * acpi_resume() - Do ACPI S3 resume
>>> + *
>>> + * This calls U-Boot wake up assembly stub and jumps to OS's wake up
>>> vector.
>>> + *
>>> + * @wake_vec: OS wake up vector
>>> + * @return:Never returns
>>> + */
>>> +void acpi_resume(void *wake_vec);
>>> +
>>> #endif /* __ASSEMBLY__ */
>>>
>>> #endif /* __ASM_ACPI_S3_H__ */
>>> diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
>>> index 1c2c085..c61f931 100644
>>> --- a/arch/x86/lib/Makefile
>>> +++ b/arch/x86/lib/Makefile
>>> @@ -35,6 +35,7 @@ obj-$(CONFIG_X86_RAMTEST) += ramtest.o
>>> obj-y += sections.o
>>> obj-y += sfi.o
>>> obj-y += string.o
>>> +obj-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.o
>>> ifndef CONFIG_QEMU
>>> obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi_table.o
>>> endif
>>> diff --git a/arch/x86/lib/acpi_s3.c b/arch/x86/lib/acpi_s3.c
>>> new file mode 100644
>>> index 000..f679c06
>>> --- /dev/null
>>> +++ b/arch/x86/lib/acpi_s3.c
>>> @@ -0,0 +1,26 @@
>>> +/*
>>> + * Copyright (C) 2017, Bin Meng
>>> + *
>>> + * SPDX-License-Identifier:GPL-2.0+
>>> + */
>>> +
>>> +#include
>>> +#include
>>> +#include
>>> +
>>> +static void asmlinkage (*acpi_do_wakeup)(void *vector) = (void
>>> *)WAKEUP_BASE;
>>> +
>>> +static void acpi_jump_to_wakeup(void *vector)
>>> +{
>>> + /* Copy wakeup trampoline in place */
>>> + memcpy((void *)WAKEUP_BASE, __wakeup, __wakeup_size);
>>> +
>>> + printf("Jumping to OS waking vector %p\n", vector);
>>
>> Should this be debug()?
>>
>
> I wanted to explicitly print this to show that we are in S3 and
> jumping to OS vector.
I also vote for this explicit print line in this case.
> Actually I was even thinking we should introduce
> a log level for U-Boot, just like coreboot/linux.
Interesting idea. How could the log-level be configured in U-Boot?
Via some env variable?
Thanks,
Stefan
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[U-Boot] [PATCH v2] rockchip: dts: evb-rk3399: add gmac support
Enable gmac for evb-rk3399.
Signed-off-by: Kever Yang
---
Changes in v2:
- correct rst pin number
arch/arm/dts/rk3399-evb.dts | 24
configs/evb-rk3399_defconfig | 4
2 files changed, 28 insertions(+)
diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts
index 769d5a0..7d27f40 100644
--- a/arch/arm/dts/rk3399-evb.dts
+++ b/arch/arm/dts/rk3399-evb.dts
@@ -6,6 +6,7 @@
/dts-v1/;
#include
+#include
#include "rk3399.dtsi"
#include "rk3399-sdram-lpddr3-4GB-1600.dtsi"
@@ -58,6 +59,13 @@
regulator-name = "vcc5v0_host";
gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
};
+
+ clkin_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <12500>;
+ clock-output-names = "clkin_gmac";
+ #clock-cells = <0>;
+ };
};
&emmc_phy {
@@ -163,3 +171,19 @@
};
};
};
+
+&gmac {
+phy-supply = <&vcc_phy>;
+ phy-mode = "rgmii";
+ clock_in_out = "input";
+ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 1 5>;
+ assigned-clocks = <&cru SCLK_RMII_SRC>;
+ assigned-clock-parents = <&clkin_gmac>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ tx_delay = <0x10>;
+ rx_delay = <0x10>;
+ status = "okay";
+};
diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
index c14764d..c5c86d8 100644
--- a/configs/evb-rk3399_defconfig
+++ b/configs/evb-rk3399_defconfig
@@ -49,6 +49,10 @@ CONFIG_PMIC_CHILDREN=y
CONFIG_SPL_PMIC_CHILDREN=y
CONFIG_PMIC_RK808=y
CONFIG_REGULATOR_RK808=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_GMAC_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_ROCKCHIP_RK3399_PINCTRL=y
--
1.9.1
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[U-Boot] [PATCH] rockchip: dts: evb-rk3399: correct pwm3 polarity
The pwm3 on evb-rk3399 is used for pwm regulator, need to invert
the polarity to make it works correct.
Signed-off-by: Kever Yang
---
arch/arm/dts/rk3399-evb.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts
index d2ded77..b01ce1e 100644
--- a/arch/arm/dts/rk3399-evb.dts
+++ b/arch/arm/dts/rk3399-evb.dts
@@ -20,7 +20,7 @@
vdd_center: vdd-center {
compatible = "pwm-regulator";
- pwms = <&pwm3 0 25000 0>;
+ pwms = <&pwm3 0 25000 1>;
regulator-name = "vdd_center";
regulator-min-microvolt = <80>;
regulator-max-microvolt = <140>;
--
1.9.1
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[U-Boot] [PATCH 0/2] Add Kconfig for rockchip video driver.
Eric Gao (2): rockchip: video: Kconfig: Add Kconfig for rockchip video driver rockchip: video: Makefile: Modify Makefile for rockchip video driver configs/chromebit_mickey_defconfig | 1 + configs/chromebook_jerry_defconfig | 2 ++ configs/chromebook_minnie_defconfig | 2 ++ configs/firefly-rk3288_defconfig| 1 + configs/miqi-rk3288_defconfig | 1 + configs/rock2_defconfig | 1 + drivers/video/Kconfig | 10 + drivers/video/rockchip/Kconfig | 43 + drivers/video/rockchip/Makefile | 8 ++- 9 files changed, 59 insertions(+), 10 deletions(-) create mode 100644 drivers/video/rockchip/Kconfig -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/2] rockchip: video: Kconfig: Add Kconfig for rockchip video driver
1. add Kconfig for rockchip video driver, so that video port can be selected as needed. 2. move VIDEO_ROCKCHIP option to new Kconfig for concision. Signed-off-by: Eric Gao --- configs/chromebit_mickey_defconfig | 1 + configs/chromebook_jerry_defconfig | 2 ++ configs/chromebook_minnie_defconfig | 2 ++ configs/firefly-rk3288_defconfig| 1 + configs/miqi-rk3288_defconfig | 1 + configs/rock2_defconfig | 1 + drivers/video/Kconfig | 10 + drivers/video/rockchip/Kconfig | 43 + 8 files changed, 52 insertions(+), 9 deletions(-) create mode 100644 drivers/video/rockchip/Kconfig diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig index a29e4e5..f04ecb4 100644 --- a/configs/chromebit_mickey_defconfig +++ b/configs/chromebit_mickey_defconfig @@ -72,6 +72,7 @@ CONFIG_SYSRESET=y CONFIG_DM_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index e642b8d..dd0476b 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -72,6 +72,8 @@ CONFIG_SYSRESET=y CONFIG_DM_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_EDP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig index 1812362..cecae5f 100644 --- a/configs/chromebook_minnie_defconfig +++ b/configs/chromebook_minnie_defconfig @@ -72,6 +72,8 @@ CONFIG_SYSRESET=y CONFIG_DM_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y +CONFIG_DISPLAY_ROCKCHIP_EDP=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index b0741d7..b975383 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -70,6 +70,7 @@ CONFIG_USB_STORAGE=y CONFIG_DM_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig index 203824b..71e4db7 100644 --- a/configs/miqi-rk3288_defconfig +++ b/configs/miqi-rk3288_defconfig @@ -67,6 +67,7 @@ CONFIG_USB_STORAGE=y CONFIG_DM_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig index e9a32a9..5ddca5a 100644 --- a/configs/rock2_defconfig +++ b/configs/rock2_defconfig @@ -64,6 +64,7 @@ CONFIG_SYSRESET=y CONFIG_DM_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 19e9745..818f738 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -416,15 +416,7 @@ config VIDEO_FSL_DCU_MAX_FB_SIZE_MB Set maximum framebuffer size to be used for Freescale Display Controller Unit (DCU4). -config VIDEO_ROCKCHIP - bool "Enable Rockchip video support" - depends on DM_VIDEO - help - Rockchip SoCs provide video output capabilities for High-Definition - Multimedia Interface (HDMI), Low-voltage Differential Signalling - (LVDS), embedded DisplayPort (eDP) and Display Serial Interface - (DSI). This driver supports the on-chip video output device, and - targets the Rockchip RK3288. +source "drivers/video/rockchip/Kconfig" config VIDEO_SANDBOX_SDL bool "Enable sandbox video console using SDL" diff --git a/drivers/video/rockchip/Kconfig b/drivers/video/rockchip/Kconfig new file mode 100644 index 000..529288d --- /dev/null +++ b/drivers/video/rockchip/Kconfig @@ -0,0 +1,43 @@ +# +# Video drivers selection for rockchip soc. These configs only impact the +# compile process. You can surely check all the options. In this case, all the +# display driver will be compiled, but which drivers finally will be used is +# decided by device tree configuration. What's more, enable needed power for +# display by configure the device tree, and the vop driver will do the rest. +# +# Author: Eric Gao +# + +#menuconfig VIDEO_ROCKCHIP + bool "Enable Rockchip Video Support" + depends on DM_VIDEO + help + Rockchip SoCs provide video output capabilities for High-Definition + Multimedia Interface (HDMI), Low-voltage Differential Signalling + (LVDS), embedded DisplayPort (eDP) and Display Serial Interface +
[U-Boot] [PATCH 2/2] rockchip: video: Makefile: Modify Makefile for rockchip video driver
Modify Makefile for rockchip video driver according to Kconfig, so that source code will not be compiled if not needed. Signed-off-by: Eric Gao --- drivers/video/rockchip/Makefile | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/video/rockchip/Makefile b/drivers/video/rockchip/Makefile index 755350b..cd850a6 100644 --- a/drivers/video/rockchip/Makefile +++ b/drivers/video/rockchip/Makefile @@ -5,4 +5,10 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += rk_edp.o rk_hdmi.o rk_vop.o rk_lvds.o ../dw_hdmi.o +ifdef CONFIG_VIDEO_ROCKCHIP +obj-y += rk_vop.o +obj-$(CONFIG_DISPLAY_ROCKCHIP_MIPI) += rk_mipi.o +obj-$(CONFIG_DISPLAY_ROCKCHIP_EDP) += rk_edp.o +obj-$(CONFIG_DISPLAY_ROCKCHIP_LVDS) += rk_lvds.o +obj-$(CONFIG_DISPLAY_ROCKCHIP_HDMI) += rk_hdmi.o ../dw_hdmi.o +endif -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 1/2] rockchip: video: Kconfig: Add Kconfig for rockchip video driver
1. add Kconfig for rockchip video driver, so that video port can be selected as needed. 2. move VIDEO_ROCKCHIP option to new Kconfig for concision. Signed-off-by: Eric Gao --- configs/chromebit_mickey_defconfig | 1 + configs/chromebook_jerry_defconfig | 2 ++ configs/chromebook_minnie_defconfig | 2 ++ configs/firefly-rk3288_defconfig| 1 + configs/miqi-rk3288_defconfig | 1 + configs/rock2_defconfig | 1 + drivers/video/Kconfig | 10 + drivers/video/rockchip/Kconfig | 43 + 8 files changed, 52 insertions(+), 9 deletions(-) create mode 100644 drivers/video/rockchip/Kconfig diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig index a29e4e5..f04ecb4 100644 --- a/configs/chromebit_mickey_defconfig +++ b/configs/chromebit_mickey_defconfig @@ -72,6 +72,7 @@ CONFIG_SYSRESET=y CONFIG_DM_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index e642b8d..dd0476b 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -72,6 +72,8 @@ CONFIG_SYSRESET=y CONFIG_DM_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_EDP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig index 1812362..cecae5f 100644 --- a/configs/chromebook_minnie_defconfig +++ b/configs/chromebook_minnie_defconfig @@ -72,6 +72,8 @@ CONFIG_SYSRESET=y CONFIG_DM_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y +CONFIG_DISPLAY_ROCKCHIP_EDP=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index b0741d7..b975383 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -70,6 +70,7 @@ CONFIG_USB_STORAGE=y CONFIG_DM_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig index 203824b..71e4db7 100644 --- a/configs/miqi-rk3288_defconfig +++ b/configs/miqi-rk3288_defconfig @@ -67,6 +67,7 @@ CONFIG_USB_STORAGE=y CONFIG_DM_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig index e9a32a9..5ddca5a 100644 --- a/configs/rock2_defconfig +++ b/configs/rock2_defconfig @@ -64,6 +64,7 @@ CONFIG_SYSRESET=y CONFIG_DM_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 19e9745..818f738 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -416,15 +416,7 @@ config VIDEO_FSL_DCU_MAX_FB_SIZE_MB Set maximum framebuffer size to be used for Freescale Display Controller Unit (DCU4). -config VIDEO_ROCKCHIP - bool "Enable Rockchip video support" - depends on DM_VIDEO - help - Rockchip SoCs provide video output capabilities for High-Definition - Multimedia Interface (HDMI), Low-voltage Differential Signalling - (LVDS), embedded DisplayPort (eDP) and Display Serial Interface - (DSI). This driver supports the on-chip video output device, and - targets the Rockchip RK3288. +source "drivers/video/rockchip/Kconfig" config VIDEO_SANDBOX_SDL bool "Enable sandbox video console using SDL" diff --git a/drivers/video/rockchip/Kconfig b/drivers/video/rockchip/Kconfig new file mode 100644 index 000..529288d --- /dev/null +++ b/drivers/video/rockchip/Kconfig @@ -0,0 +1,43 @@ +# +# Video drivers selection for rockchip soc. These configs only impact the +# compile process. You can surely check all the options. In this case, all the +# display driver will be compiled, but which drivers finally will be used is +# decided by device tree configuration. What's more, enable needed power for +# display by configure the device tree, and the vop driver will do the rest. +# +# Author: Eric Gao +# + +#menuconfig VIDEO_ROCKCHIP + bool "Enable Rockchip Video Support" + depends on DM_VIDEO + help + Rockchip SoCs provide video output capabilities for High-Definition + Multimedia Interface (HDMI), Low-voltage Differential Signalling + (LVDS), embedded DisplayPort (eDP) and Display Serial Interface +
[U-Boot] [PATCH v2 0/2] Add Kconfig for rockchip video driver.
patch 1: add Kconfig file rockchip video driver. patch 2: modify Makefile according to the new Kconfig. Eric Gao (2): rockchip: video: Kconfig: Add Kconfig for rockchip video driver rockchip: video: Makefile: Modify Makefile for rockchip video driver configs/chromebit_mickey_defconfig | 1 + configs/chromebook_jerry_defconfig | 2 ++ configs/chromebook_minnie_defconfig | 2 ++ configs/firefly-rk3288_defconfig| 1 + configs/miqi-rk3288_defconfig | 1 + configs/rock2_defconfig | 1 + drivers/video/Kconfig | 10 + drivers/video/rockchip/Kconfig | 43 + drivers/video/rockchip/Makefile | 7 +- 9 files changed, 58 insertions(+), 10 deletions(-) create mode 100644 drivers/video/rockchip/Kconfig -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 2/2] rockchip: video: Makefile: Modify Makefile for rockchip video driver
Modify Makefile for rockchip video driver according to Kconfig, so that source code will not be compiled if not needed. Signed-off-by: Eric Gao --- drivers/video/rockchip/Makefile | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/video/rockchip/Makefile b/drivers/video/rockchip/Makefile index 755350b..3bb0519 100644 --- a/drivers/video/rockchip/Makefile +++ b/drivers/video/rockchip/Makefile @@ -5,4 +5,9 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += rk_edp.o rk_hdmi.o rk_vop.o rk_lvds.o ../dw_hdmi.o +ifdef CONFIG_VIDEO_ROCKCHIP +obj-y += rk_vop.o +obj-$(CONFIG_DISPLAY_ROCKCHIP_EDP) += rk_edp.o +obj-$(CONFIG_DISPLAY_ROCKCHIP_LVDS) += rk_lvds.o +obj-$(CONFIG_DISPLAY_ROCKCHIP_HDMI) += rk_hdmi.o ../dw_hdmi.o +endif -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v5 05/16] arm: socfpga: Add A10 macros
On 04/17/2017 06:49 AM, Ley Foon Tan wrote: > On Fri, Apr 14, 2017 at 6:20 PM, Marek Vasut wrote: >> On 04/13/2017 07:41 PM, Ley Foon Tan wrote: >>> Add i2c, timer and other A10 macros. >> >> What's NOC anyway ? > Network on chip. Ah, OK :) >>> Signed-off-by: Ley Foon Tan >>> --- >>> arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 8 +++- >>> 1 file changed, 7 insertions(+), 1 deletion(-) >>> >>> diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h >>> b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h >>> index a7056d4..448fbdc 100644 >>> --- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h >>> +++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h >>> @@ -1,5 +1,5 @@ >>> /* >>> - * Copyright (C) 2014 Altera Corporation >>> + * Copyright (C) 2014-2017 Altera Corporation >>> * >>> * SPDX-License-Identifier: GPL-2.0+ >>> */ >>> @@ -29,14 +29,20 @@ >>> #define SOCFPGA_MPUL2_ADDRESS0xf000 >>> #define SOCFPGA_I2C0_ADDRESS 0xffc02200 >>> #define SOCFPGA_I2C1_ADDRESS 0xffc02300 >>> +#define SOCFPGA_I2C2_ADDRESS 0xffc02400 >>> +#define SOCFPGA_I2C3_ADDRESS 0xffc02500 >>> +#define SOCFPGA_I2C4_ADDRESS 0xffc02600 >>> >>> #define SOCFPGA_ECC_OCRAM_ADDRESS0xff8c3000 >>> #define SOCFPGA_UART0_ADDRESS0xffc02000 >>> #define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd0 >>> +#define SOCFPGA_OSC1TIMER1_ADDRESS 0xffd00100 >>> #define SOCFPGA_CLKMGR_ADDRESS 0xffd04000 >>> #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 >>> >>> #define SOCFPGA_SDR_ADDRESS 0xffcfb000 >>> +#define SOCFPGA_NOC_L4_PRIV_FLT_OFST 0xffd11000 >>> +#define SOCFPGA_NOC_FW_H2F_SCR_OFST 0xffd13500 >> >> Keep the list sorted by address at least :) > Okay. >> >>> #define SOCFPGA_SDR_SCHEDULER_ADDRESS0xffd12400 >>> #define SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS 0xffd13200 >>> #define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS0xffd13300 >>> > Regards > Ley Foon > -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v5 14/16] arm: socfpga: Add config and defconfig for Arria 10
On 04/17/2017 05:05 AM, Ley Foon Tan wrote: > On Fri, Apr 14, 2017 at 6:25 PM, Marek Vasut wrote: >> On 04/13/2017 07:41 PM, Ley Foon Tan wrote: >>> Add config and defconfig for the Arria10 and update socfpga_common.h. >>> >>> Signed-off-by: Tien Fong Chee >>> Signed-off-by: Ley Foon Tan >> >> [...] >> >>> @@ -298,7 +306,10 @@ unsigned int cm_get_qspi_controller_clk_hz(void); >>> */ >>> #define CONFIG_SPL_FRAMEWORK >>> #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR >>> -#define CONFIG_SPL_MAX_SIZE (64 * 1024) >>> +#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE >>> +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) >>> +#define CONFIG_SPL_BOARD_INIT >> >> This should be in Kconfig and selected by arch/arm/mach-socfpga/Kconfig >> entry for A10 > We can't use Kconfig method for CONFIG_SPL_BOARD_INIT, it is not a > Kconfig parameter now. OK. You can turn it into one, although that is out of the scope of this patchset. -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v5 01/16] arm: socfpga: Restructure clock manager driver
On 04/17/2017 09:20 AM, Ley Foon Tan wrote:
> On Fri, Apr 14, 2017 at 6:15 PM, Marek Vasut wrote:
>> On 04/13/2017 07:41 PM, Ley Foon Tan wrote:
>>> Restructure clock manager driver in the preparation to support A10.
>>> Move the Gen5 specific code to _gen5 files.
>>>
>>> - Change all uint32_t to u32 and change to use macro BIT(n) for bit shift.
>>> - Check return value from wait_for_bit(). So change return type to int for
>>> cm_write_with_phase() and cm_basic_init().
>>>
>>> Signed-off-by: Ley Foon Tan
>>
>> [...]
>>
>>> /* function to write a clock register that has phase information */
>>> -static void cm_write_with_phase(uint32_t value,
>>> - uint32_t reg_address, uint32_t mask)
>>> +static int cm_write_with_phase(u32 value, u32 reg_address, u32 mask)
>>> {
>>> + int ret;
>>> +
>>> /* poll until phase is zero */
>>> - while (readl(reg_address) & mask)
>>> - ;
>>> + ret = wait_for_bit(__func__, (const u32 *)reg_address, mask,
>>> +false, 2, false);
>>> + if (ret)
>>> + return ret;
>>>
>>> writel(value, reg_address);
>>>
>>> - while (readl(reg_address) & mask)
>>> - ;
>>> + return wait_for_bit(__func__, (const u32 *)reg_address, mask,
>>> + false, 2, false);
>>> }
>>>
>>
>> Could it be that this active wait is here so that it'd work without an
>> initialized timer ? Because at this point, you don't have timer and I
>> think wait_for_bit() uses timer.
>>
> Timer is initialized before calling to this function. So, should be no
> problem.
>
> In arch/arm/mach-socfpga/spl.c, timer is initialized before calling to
> cm_basic_init(). Note, cm_write_with_phase() is called by
> cm_basic_init().
>
> socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
>
> timer_init();
>
> debug("Reconfigure Clock Manager\n");
> /* reconfigure the PLLs */
> if (cm_basic_init(cm_default_cfg))
> hang();
OK, perfect.
--
Best regards,
Marek Vasut
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[U-Boot] rockchip: rk3288: grf: FIX the correct gmac tx_delay shift
If the tx_delay is not enabled, the RGMII/1000M can't work.
Signed-off-by: David Wu
---
arch/arm/include/asm/arch-rockchip/grf_rk3288.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
index 1a7c819..6e5a947 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
@@ -813,7 +813,7 @@ enum {
(1 << RK3288_TXCLK_DLY_ENA_GMAC_SHIFT),
RK3288_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
RK3288_TXCLK_DLY_ENA_GMAC_ENABLE =
- (1 << RK3288_RXCLK_DLY_ENA_GMAC_SHIFT),
+ (1 << RK3288_TXCLK_DLY_ENA_GMAC_SHIFT),
RK3288_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
RK3288_CLK_RX_DL_CFG_GMAC_MASK =
--
1.9.1
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Re: [U-Boot] [PATCHv2 03/21] net: core: Inform the user of the device MAC address
Hi Oliver,
On 10 April 2017 at 09:33, Olliver Schinagl wrote:
> In certain conditions we currently print the MAC address. For example a
> warning when a random mac address is in use or a missmatch between HW
> and ENV.
>
> If all things went well however (but even if there is a miss-match) we
> do not inform the user what the final MAC address of the device is.
>
> Lets print the final MAC address of the device with which it has been
> setup.
>
> Signed-off-by: Olliver Schinagl
> ---
> net/eth-uclass.c | 9 ++---
> net/eth_legacy.c | 3 +++
> 2 files changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/net/eth-uclass.c b/net/eth-uclass.c
> index c3cc3152a2..781376955a 100644
> --- a/net/eth-uclass.c
> +++ b/net/eth-uclass.c
> @@ -413,11 +413,12 @@ int eth_initialize(void)
> }
>
> bootstage_mark(BOOTSTAGE_ID_NET_ETH_INIT);
> + putc('\n');
> do {
> - if (num_devices)
> - printf(", ");
> + struct eth_pdata *pdata = dev->platdata;
>
> - printf("eth%d: %s", dev->seq, dev->name);
> + printf("eth%d: %s [%pM]\n", dev->seq, dev->name,
> +pdata->enetaddr);
>
> if (ethprime && dev == prime_dev)
> printf(" [PRIME]");
> @@ -525,6 +526,8 @@ static int eth_post_probe(struct udevice *dev)
> #endif
> }
>
> + printf("%s ", dev->name);
> +
> return 0;
> }
>
> diff --git a/net/eth_legacy.c b/net/eth_legacy.c
> index e4bd0f4c1a..687763682a 100644
> --- a/net/eth_legacy.c
> +++ b/net/eth_legacy.c
> @@ -179,6 +179,9 @@ int eth_write_hwaddr(struct eth_device *dev, const char
> *base_name,
>dev->name);
> }
>
> + printf("%s (eth%d) has MAC address: %pM\n",
> + dev->name, eth_number, dev->enetaddr);
As a general rule I don't think we should be adding new features to
legacy code. If people want the new features they can switch over to
driver model.
Regards,
Simon
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[U-Boot] [PATCH] Add ARM errata workaround 852421 and 852423 for Cortex-A17
ARM errata 852421 and 852423 applies to r1p0, r1p1 and r1p2 revisions of Cortex-A17 processors. These workarounds exist in Linux kernel and I thought it would be better to add them in to U-Boot. Signed-off-by: Nisal Menuka --- arch/arm/cpu/armv7/start.S | 12 1 file changed, 12 insertions(+) diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 1a6aee9..f06fd28 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -283,6 +283,18 @@ skip_errata_621766: skip_errata_725233: #endif +#ifdef CONFIG_ARM_ERRATA_852421 + mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register + orr r0, r0, #1 << 24@ set bit #24 + mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register +#endif + +#ifdef CONFIG_ARM_ERRATA_852423 + mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register + orr r0, r0, #1 << 12@ set bit #12 + mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register +#endif + mov pc, r5 @ back to my caller ENDPROC(cpu_init_cp15) -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH][v2] driver: net: fsl-mc: Update fsl_mc_ldpaa_exit() path
When MC is loaded, but DPL is not deployed, it results in FDT fix-up
code execution hang.
To resolve this, returns success instead of return -ENODEV and print message
on console.
This update allows to continue fdt fixup execution.
Signed-off-by: Yogesh Gaur
Signed-off-by: Priyanka Jain
---
Changes for v2:
Incorporated Prabhakar's review comments.
drivers/net/fsl-mc/mc.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index 079082a..d47fa1f 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -1268,10 +1268,12 @@ int fsl_mc_ldpaa_exit(bd_t *bd)
if (bd && get_mc_boot_status() != 0)
return 0;
+ /* For case MC is loaded but DPL is not deployed, return success and
+* print message on console. Else FDT fix-up code execution hanged. */
if (bd && !get_mc_boot_status() && get_dpl_apply_status() == -1) {
- printf("ERROR: fsl-mc: DPL is not applied\n");
- err = -ENODEV;
- return err;
+ printf("fsl-mc: MC is loaded but DPL is not deployed \n\
+ So, DPAA2 ethernet will not work in Linux\n");
+ return 0;
}
if (bd && !get_mc_boot_status() && !get_dpl_apply_status())
--
1.9.1
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Re: [U-Boot] [PATCH 03/19] fdt: Use SPDX format for licenses in the libfdt headers
On Sun, Apr 16, 2017 at 08:22:17PM -0600, Simon Glass wrote: > These should follow the UBoot standard. Update them. > > Signed-off-by: Simon Glass > --- > > include/fdt.h| 46 +- > include/libfdt.h | 46 +- > 2 files changed, 2 insertions(+), 90 deletions(-) We're syncing these as-is, right? If so, just like DTB files, we don't need to whack in an SPDX tag as that just complicates future re-syncs. -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH V2 0/9] Add Device Tree for OMAP3 and omap3_logic
This patch series copies the Linux Device trees for the OMAP3 and OMAP3630 platforms as well as some additional device trees to support the Logic PD Torpedo and Logic PD SOM-LV both based on DM3730 (OMAP3630) processors. There are no changes to patches 2-6 from the initial version posted as RFC, but I added "Reviewed-by: Lokesh Vutla " to patches 2-6 Part 1 Changes the method for the MMC base address offsets to be caluclated. These offsets are different between OMAP3 and am33xx and omap4+. This moves away from an #ifdef method to a method of that uses .compatible to determine the offset. This is needed for OMAP3 device tree support. This rest of this series allows us move to DM_I2C and DM_MMC and push the DM_SERIAL setup to the OF except when in SPL. This should give enough background for other OMAP3 boards to migrate to device tree. The dm uclass dump is as follows: uclass 0: root - * root_driver @ 8df38028, seq 0, (req -1) uclass 9: simple_bus - * ocp@6800 @ 8df382e0, seq 0, (req -1) - l4@4800 @ 8df38348 - scm@2000 @ 8df383b0 - scm_conf@270 @ 8df38418 uclass 19: gpio - gpio_omap @ 8df380b0 - gpio_omap @ 8df38108 - gpio_omap @ 8df38160 - gpio_omap @ 8df381b8 - gpio_omap @ 8df38210 - gpio_omap @ 8df38268 - gpio@4831 @ 8df38480 - gpio@4905 @ 8df384e8 - gpio@49052000 @ 8df38550 - * gpio@49054000 @ 8df385b8, seq 0, (req -1) - gpio@49056000 @ 8df38620 - gpio@49058000 @ 8df38688 uclass 20: i2c - * i2c@4807 @ 8df38880, seq 0, (req 0) - i2c@48072000 @ 8df388d8, seq -1, (req 1) - i2c@4806 @ 8df38930, seq -1, (req 2) uclass 22: i2c_generic - * generic_4b @ 8df4b178, seq 0, (req -1) uclass 31: mmc - * mmc@4809c000 @ 8df389a8, seq 0, (req -1) - * mmc@480ad000 @ 8df38b80, seq 1, (req -1) uclass 52: serial - * serial@4806a000 @ 8df38710, seq 0, (req 0) - serial@4806c000 @ 8df38780, seq -1, (req 1) - serial@4902 @ 8df387f0, seq -1, (req 2) - serial@49042000 @ 8df38d58, seq -1, (req 3) Adam Ford (9): omap_hsmmc: update struct hsmmc to accommodate omap3 from DT omap3: Copy Device tree from Linux 4.9.y stable omap3630: Copy Device tree from Linux 4.9.y stable ARM: OMAP: I2C: Support New read, write and probe functions for OMAP3 omap3: Copy twl4030 device tree from Linux 4.9.y stable OMAP3: Add SMSC9221 device tree for omap devices connected on GPMC. ARM: DTS: Add Logic PD DM3730 SOM-LV initial support ARM: DTS: Add Logic PD DM3730 Torpedo Device Tree omap3_logic: Add Device Tree Support and more DM drivers arch/arm/dts/Makefile |4 + arch/arm/dts/logicpd-som-lv-37xx-devkit.dts| 269 arch/arm/dts/logicpd-som-lv.dtsi | 271 arch/arm/dts/logicpd-torpedo-37xx-devkit.dts | 411 + arch/arm/dts/logicpd-torpedo-som.dtsi | 217 +++ arch/arm/dts/omap-gpmc-smsc9221.dtsi | 58 + arch/arm/dts/omap3.dtsi| 854 ++ arch/arm/dts/omap34xx-omap36xx-clocks.dtsi | 268 .../omap36xx-am35xx-omap3430es2plus-clocks.dtsi| 242 +++ arch/arm/dts/omap36xx-clocks.dtsi | 110 ++ arch/arm/dts/omap36xx-omap3430es2plus-clocks.dtsi | 198 +++ arch/arm/dts/omap36xx.dtsi | 118 ++ arch/arm/dts/omap3xxx-clocks.dtsi | 1665 arch/arm/dts/twl4030.dtsi | 161 ++ arch/arm/dts/twl4030_omap3.dtsi| 42 + arch/arm/include/asm/omap_mmc.h|3 - board/logicpd/omap3som/README | 19 + board/logicpd/omap3som/omap3logic.c| 18 +- configs/omap3_logic_defconfig |8 +- drivers/i2c/omap24xx_i2c.c |1 + drivers/mmc/omap_hsmmc.c | 35 +- include/configs/omap3_logic.h | 25 +- include/dt-bindings/media/omap3-isp.h | 22 + 23 files changed, 4993 insertions(+), 26 deletions(-) create mode 100644 arch/arm/dts/logicpd-som-lv-37xx-devkit.dts create mode 100644 arch/arm/dts/logicpd-som-lv.dtsi create mode 100644 arch/arm/dts/logicpd-torpedo-37xx-devkit.dts create mode 100644 arch/arm/dts/logicpd-torpedo-som.dtsi create mode 100644 arch/arm/dts/omap-gpmc-smsc9221.dtsi create mode 100644 arch/arm/dts/omap3.dtsi create mode 100644 arch/arm/dts/omap34xx-omap36xx-clocks.dtsi create mode 100644 arch/arm/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi create mode 100644 arch/arm/dts/omap36xx-clocks.dtsi create mode 100644 arch/arm/dts/omap36xx-omap3430es2plus-clocks.dtsi create mode 100644 arch/arm/dts/omap36xx.dtsi create mode 100644 arch/arm/dts/omap3xxx-clocks.dtsi create mode 100644 arch/arm/dts/twl4030.dtsi create mode 100644 arch/arm/dts/twl4030_omap3.dtsi create mode 100644 board/logicpd/omap3som/README create mode 100644 include/dt-bindings/media/omap3-isp.h -- 2.7.4
[U-Boot] [PATCH V2 1/9] omap_hsmmc: update struct hsmmc to accommodate omap3 from DT
This patch changes the way DM_MMC calculates offset to the base register of
MMC. Previously this was through an #ifdef but that wasn't necessary for OMAP3.
This patch will now add in the offset to the base address based on the
.compatible flags.
Signed-off-by: Adam Ford
V2: Remove ifdef completely and reference offset from the omap_hsmmc_ids table.
V1: Change ifdef to ignore OMAP3
diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h
index f2bf645..93e003a 100644
--- a/arch/arm/include/asm/omap_mmc.h
+++ b/arch/arm/include/asm/omap_mmc.h
@@ -26,9 +26,6 @@
#define OMAP_MMC_H_
struct hsmmc {
-#ifdef CONFIG_DM_MMC
- unsigned char res0[0x100];
-#endif
unsigned char res1[0x10];
unsigned int sysconfig; /* 0x10 */
unsigned int sysstatus; /* 0x14 */
diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index 83dda09..d151fe7 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -61,6 +61,10 @@ struct omap_hsmmc_plat {
struct mmc mmc;
};
+struct omap2_mmc_platform_config {
+ u32 reg_offset;
+};
+
struct omap_hsmmc_data {
struct hsmmc *base_addr;
#ifndef CONFIG_DM_MMC
@@ -778,12 +782,14 @@ static int omap_hsmmc_ofdata_to_platdata(struct udevice
*dev)
struct omap_hsmmc_data *priv = dev_get_priv(dev);
struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
struct mmc_config *cfg = &plat->cfg;
+ struct omap2_mmc_platform_config *data =
+ (struct omap2_mmc_platform_config *)dev_get_driver_data(dev);
const void *fdt = gd->fdt_blob;
int node = dev_of_offset(dev);
int val;
priv->base_addr = map_physmem(dev_get_addr(dev), sizeof(struct hsmmc *),
- MAP_NOCACHE);
+ MAP_NOCACHE) + data->reg_offset;
cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
val = fdtdec_get_int(fdt, node, "bus-width", -1);
@@ -854,10 +860,31 @@ static int omap_hsmmc_probe(struct udevice *dev)
return 0;
}
+static const struct omap2_mmc_platform_config omap3_mmc_pdata = {
+ .reg_offset = 0,
+};
+
+static const struct omap2_mmc_platform_config am33xx_mmc_pdata = {
+ .reg_offset = 0x100,
+};
+
+static const struct omap2_mmc_platform_config omap4_mmc_pdata = {
+ .reg_offset = 0x100,
+};
+
static const struct udevice_id omap_hsmmc_ids[] = {
- { .compatible = "ti,omap3-hsmmc" },
- { .compatible = "ti,omap4-hsmmc" },
- { .compatible = "ti,am33xx-hsmmc" },
+ {
+ .compatible = "ti,omap3-hsmmc",
+ .data = (ulong)&omap3_mmc_pdata
+ },
+ {
+ .compatible = "ti,omap4-hsmmc",
+ .data = (ulong)&omap4_mmc_pdata
+ },
+ {
+ .compatible = "ti,am33xx-hsmmc",
+ .data = (ulong)&am33xx_mmc_pdata
+ },
{ }
};
--
2.7.4
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[U-Boot] [PATCH V2 3/9] omap3630: Copy Device tree from Linux 4.9.y stable
Add device tree support to allow for CONFIG_OF_CONTROL in OMAP3630 boards.
DM3730 can use this same device tree.
Signed-off-by: Adam Ford
Reviewed-by: Lokesh Vutla
diff --git a/arch/arm/dts/omap34xx-omap36xx-clocks.dtsi
b/arch/arm/dts/omap34xx-omap36xx-clocks.dtsi
new file mode 100644
index 000..db47f12
--- /dev/null
+++ b/arch/arm/dts/omap34xx-omap36xx-clocks.dtsi
@@ -0,0 +1,268 @@
+/*
+ * Device Tree Source for OMAP34XX/OMAP36XX clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&cm_clocks {
+ security_l4_ick2: security_l4_ick2 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l4_ick>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ aes1_ick: aes1_ick@a14 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&security_l4_ick2>;
+ ti,bit-shift = <3>;
+ reg = <0x0a14>;
+ };
+
+ rng_ick: rng_ick@a14 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&security_l4_ick2>;
+ reg = <0x0a14>;
+ ti,bit-shift = <2>;
+ };
+
+ sha11_ick: sha11_ick@a14 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&security_l4_ick2>;
+ reg = <0x0a14>;
+ ti,bit-shift = <1>;
+ };
+
+ des1_ick: des1_ick@a14 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&security_l4_ick2>;
+ reg = <0x0a14>;
+ ti,bit-shift = <0>;
+ };
+
+ cam_mclk: cam_mclk@f00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll4_m5x2_ck>;
+ ti,bit-shift = <0>;
+ reg = <0x0f00>;
+ ti,set-rate-parent;
+ };
+
+ cam_ick: cam_ick@f10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-no-wait-interface-clock";
+ clocks = <&l4_ick>;
+ reg = <0x0f10>;
+ ti,bit-shift = <0>;
+ };
+
+ csi2_96m_fck: csi2_96m_fck@f00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&core_96m_fck>;
+ reg = <0x0f00>;
+ ti,bit-shift = <1>;
+ };
+
+ security_l3_ick: security_l3_ick {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l3_ick>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ pka_ick: pka_ick@a14 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&security_l3_ick>;
+ reg = <0x0a14>;
+ ti,bit-shift = <4>;
+ };
+
+ icr_ick: icr_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <29>;
+ };
+
+ des2_ick: des2_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <26>;
+ };
+
+ mspro_ick: mspro_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <23>;
+ };
+
+ mailboxes_ick: mailboxes_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <7>;
+ };
+
+ ssi_l4_ick: ssi_l4_ick {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l4_ick>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ sr1_fck: sr1_fck@c00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&sys_ck>;
+ reg = <0x0c00>;
+ ti,bit-shift = <6>;
+ };
+
+ sr2_fck: sr2_fck@c00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&sys_ck>;
+ reg = <0x0c00>;
+ ti,bit-shift = <7>;
+ };
+
+ sr_l4_ick: sr_l4_ick {
+
[U-Boot] [PATCH V2 5/9] omap3: Copy twl4030 device tree from Linux 4.9.y stable
Many OMAP3 boards use a TWL4030 PMIC. This brings in the related
device tree information for common TWL4030 and TWL4030 with OMAP3.
Signed-off-by: Adam Ford
Reviewed-by: Lokesh Vutla
diff --git a/arch/arm/dts/twl4030.dtsi b/arch/arm/dts/twl4030.dtsi
new file mode 100644
index 000..6cb0a01
--- /dev/null
+++ b/arch/arm/dts/twl4030.dtsi
@@ -0,0 +1,161 @@
+/*
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * Integrated Power Management Chip
+ */
+&twl {
+ compatible = "ti,twl4030";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ rtc {
+ compatible = "ti,twl4030-rtc";
+ interrupts = <11>;
+ };
+
+ charger: bci {
+ compatible = "ti,twl4030-bci";
+ interrupts = <9>, <2>;
+ bci3v1-supply = <&vusb3v1>;
+ };
+
+ watchdog {
+ compatible = "ti,twl4030-wdt";
+ };
+
+ vaux1: regulator-vaux1 {
+ compatible = "ti,twl4030-vaux1";
+ };
+
+ vaux2: regulator-vaux2 {
+ compatible = "ti,twl4030-vaux2";
+ };
+
+ vaux3: regulator-vaux3 {
+ compatible = "ti,twl4030-vaux3";
+ };
+
+ vaux4: regulator-vaux4 {
+ compatible = "ti,twl4030-vaux4";
+ };
+
+ vcc: regulator-vdd1 {
+ compatible = "ti,twl4030-vdd1";
+ regulator-min-microvolt = <60>;
+ regulator-max-microvolt = <145>;
+ };
+
+ vdac: regulator-vdac {
+ compatible = "ti,twl4030-vdac";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ };
+
+ vio: regulator-vio {
+ compatible = "ti,twl4030-vio";
+ };
+
+ vintana1: regulator-vintana1 {
+ compatible = "ti,twl4030-vintana1";
+ };
+
+ vintana2: regulator-vintana2 {
+ compatible = "ti,twl4030-vintana2";
+ };
+
+ vintdig: regulator-vintdig {
+ compatible = "ti,twl4030-vintdig";
+ };
+
+ vmmc1: regulator-vmmc1 {
+ compatible = "ti,twl4030-vmmc1";
+ regulator-min-microvolt = <185>;
+ regulator-max-microvolt = <315>;
+ };
+
+ vmmc2: regulator-vmmc2 {
+ compatible = "ti,twl4030-vmmc2";
+ regulator-min-microvolt = <185>;
+ regulator-max-microvolt = <315>;
+ };
+
+ vusb1v5: regulator-vusb1v5 {
+ compatible = "ti,twl4030-vusb1v5";
+ };
+
+ vusb1v8: regulator-vusb1v8 {
+ compatible = "ti,twl4030-vusb1v8";
+ };
+
+ vusb3v1: regulator-vusb3v1 {
+ compatible = "ti,twl4030-vusb3v1";
+ };
+
+ vpll1: regulator-vpll1 {
+ compatible = "ti,twl4030-vpll1";
+ };
+
+ vpll2: regulator-vpll2 {
+ compatible = "ti,twl4030-vpll2";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ };
+
+ vsim: regulator-vsim {
+ compatible = "ti,twl4030-vsim";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <300>;
+ };
+
+ twl_gpio: gpio {
+ compatible = "ti,twl4030-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ usb2_phy: twl4030-usb {
+ compatible = "ti,twl4030-usb";
+ interrupts = <10>, <4>;
+ usb1v5-supply = <&vusb1v5>;
+ usb1v8-supply = <&vusb1v8>;
+ usb3v1-supply = <&vusb3v1>;
+ usb_mode = <1>;
+ #phy-cells = <0>;
+ };
+
+ twl_pwm: pwm {
+ compatible = "ti,twl4030-pwm";
+ #pwm-cells = <2>;
+ };
+
+ twl_pwmled: pwmled {
+ compatible = "ti,twl4030-pwmled";
+ #pwm-cells = <2>;
+ };
+
+ twl_pwrbutton: pwrbutton {
+ compatible = "ti,twl4030-pwrbutton";
+ interrupts = <8>;
+ };
+
+ twl_keypad: keypad {
+ compatible = "ti,twl4030-keypad";
+ interrupts = <1>;
+ keypad,num-rows = <8>;
+ keypad,num-columns = <8>;
+ };
+
+ twl_madc: madc {
+ compatible = "ti,twl4030-madc";
+ interrupts = <3>;
+ #io-channel-cells = <1>;
+ };
+};
diff --git a/arch/arm/dts/twl4030_omap3.dtsi b/arch/arm/dts/twl4030_omap3.dtsi
new file mode 100644
index 000..f9aaa53
--- /dev/null
+++ b/arch/arm/dts/twl4030_omap
[U-Boot] [PATCH V2 2/9] omap3: Copy Device tree from Linux 4.9.y stable
Add device tree support to allow for CONFIG_OF_CONTROL in OMAP3 boards.
Signed-off-by: Adam Ford
Reviewed-by: Lokesh Vutla
diff --git a/arch/arm/dts/omap3.dtsi b/arch/arm/dts/omap3.dtsi
new file mode 100644
index 000..a0f2412
--- /dev/null
+++ b/arch/arm/dts/omap3.dtsi
@@ -0,0 +1,854 @@
+/*
+ * Device Tree Source for OMAP3 SoC
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include
+#include
+#include
+
+/ {
+ compatible = "ti,omap3430", "ti,omap3";
+ interrupt-parent = <&intc>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ chosen { };
+
+ aliases {
+ i2c0 = &i2c1;
+ i2c1 = &i2c2;
+ i2c2 = &i2c3;
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a8";
+ device_type = "cpu";
+ reg = <0x0>;
+
+ clocks = <&dpll1_ck>;
+ clock-names = "cpu";
+
+ clock-latency = <30>; /* From omap-cpufreq driver */
+ };
+ };
+
+ pmu@5400 {
+ compatible = "arm,cortex-a8-pmu";
+ reg = <0x5400 0x80>;
+ interrupts = <3>;
+ ti,hwmods = "debugss";
+ };
+
+ /*
+* The soc node represents the soc top level view. It is used for IPs
+* that are not memory mapped in the MPU view or for the MPU itself.
+*/
+ soc {
+ compatible = "ti,omap-infra";
+ mpu {
+ compatible = "ti,omap3-mpu";
+ ti,hwmods = "mpu";
+ };
+
+ iva: iva {
+ compatible = "ti,iva2.2";
+ ti,hwmods = "iva";
+
+ dsp {
+ compatible = "ti,omap3-c64";
+ };
+ };
+ };
+
+ /*
+* XXX: Use a flat representation of the OMAP3 interconnect.
+* The real OMAP interconnect network is quite complex.
+* Since it will not bring real advantage to represent that in DT for
+* the moment, just use a fake OCP bus entry to represent the whole bus
+* hierarchy.
+*/
+ ocp@6800 {
+ compatible = "ti,omap3-l3-smx", "simple-bus";
+ reg = <0x6800 0x1>;
+ interrupts = <9 10>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ ti,hwmods = "l3_main";
+
+ l4_core: l4@4800 {
+ compatible = "ti,omap3-l4-core", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x4800 0x100>;
+
+ scm: scm@2000 {
+ compatible = "ti,omap3-scm", "simple-bus";
+ reg = <0x2000 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x2000 0x2000>;
+
+ omap3_pmx_core: pinmux@30 {
+ compatible = "ti,omap3-padconf",
+"pinctrl-single";
+ reg = <0x30 0x238>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ pinctrl-single,register-width = <16>;
+ pinctrl-single,function-mask = <0xff1f>;
+ };
+
+ scm_conf: scm_conf@270 {
+ compatible = "syscon", "simple-bus";
+ reg = <0x270 0x330>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x270 0x330>;
+
+ pbias_regulator: pbias_regulator@2b0 {
+ compatible = "ti,pbias-omap3",
"ti,pbias-omap";
+ reg = <0x2b0 0x4>;
+ syscon = <&scm_conf>;
+
[U-Boot] [PATCH V2 6/9] OMAP3: Add SMSC9221 device tree for omap devices connected on GPMC.
Some OMAP3 devices support an SMSC ethernet PHY connected to the GPMC bus.
This copies this device tree from Linux 4.9.y stable
Signed-off-by: Adam Ford
Reviewed-by: Lokesh Vutla
diff --git a/arch/arm/dts/omap-gpmc-smsc9221.dtsi
b/arch/arm/dts/omap-gpmc-smsc9221.dtsi
new file mode 100644
index 000..73e272f
--- /dev/null
+++ b/arch/arm/dts/omap-gpmc-smsc9221.dtsi
@@ -0,0 +1,58 @@
+/*
+ * Common file for GPMC connected smsc9221 on omaps
+ *
+ * Compared to smsc911x, smsc9221 (and others like smsc9217
+ * or smsc 9218) has faster timings, leading to higher
+ * bandwidth.
+ *
+ * Note that the board specifc DTS file needs to specify
+ * ranges, pinctrl, reg, interrupt parent and interrupts.
+ */
+
+/ {
+ vddvario: regulator-vddvario {
+ compatible = "regulator-fixed";
+ regulator-name = "vddvario";
+ regulator-always-on;
+ };
+
+ vdd33a: regulator-vdd33a {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd33a";
+ regulator-always-on;
+ };
+};
+
+&gpmc {
+ ethernet@gpmc {
+ compatible = "smsc,lan9221","smsc,lan9115";
+ bank-width = <2>;
+
+ gpmc,mux-add-data;
+ gpmc,cs-on-ns = <0>;
+ gpmc,cs-rd-off-ns = <42>;
+ gpmc,cs-wr-off-ns = <36>;
+ gpmc,adv-on-ns = <6>;
+ gpmc,adv-rd-off-ns = <12>;
+ gpmc,adv-wr-off-ns = <12>;
+ gpmc,oe-on-ns = <0>;
+ gpmc,oe-off-ns = <42>;
+ gpmc,we-on-ns = <0>;
+ gpmc,we-off-ns = <36>;
+ gpmc,rd-cycle-ns = <60>;
+ gpmc,wr-cycle-ns = <54>;
+ gpmc,access-ns = <36>;
+ gpmc,page-burst-access-ns = <0>;
+ gpmc,bus-turnaround-ns = <0>;
+ gpmc,cycle2cycle-delay-ns = <0>;
+ gpmc,wr-data-mux-bus-ns = <18>;
+ gpmc,wr-access-ns = <42>;
+ gpmc,cycle2cycle-samecsen;
+ gpmc,cycle2cycle-diffcsen;
+
+ vddvario-supply = <&vddvario>;
+ vdd33a-supply = <&vdd33a>;
+ reg-io-width = <4>;
+ smsc,save-mac-address;
+ };
+};
--
2.7.4
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH V2 9/9] omap3_logic: Add Device Tree Support and more DM drivers
This patch also removes all the excessive code for NS16550 intiailization
as the device tree can do that now. This also adds DM_I2C and DM_MMC
since the overlying drivers have the built-in support already. The
corresponding include/config/omap3_logic.h also reduced in size
due to the new device tree support.
Signed-off-by: Adam Ford
Changes in V2:
Retain Auto-detect ability between SOM-LV and Torpedo
Split this off from the device sub submissions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 7378c88..44c586d 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -341,6 +341,10 @@ dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \
keystone-k2e-evm.dtb \
keystone-k2g-evm.dtb
+dtb-$(CONFIG_TARGET_OMAP3_LOGIC) += \
+ logicpd-torpedo-37xx-devkit.dtb \
+ logicpd-som-lv-37xx-devkit.dts
+
dtb-$(CONFIG_TARGET_SAMA5D2_XPLAINED) += \
at91-sama5d2_xplained.dtb
diff --git a/board/logicpd/omap3som/README b/board/logicpd/omap3som/README
new file mode 100644
index 000..06b3998
--- /dev/null
+++ b/board/logicpd/omap3som/README
@@ -0,0 +1,19 @@
+Summary
+===
+
+The source for omap3som encompases the DM3730 SOM-LV and DM3730 Torpedo
platforms.
+
+By default, the Torpedo Device Tree is integrated into U-Boot,but the MMC
controller, GPIO and I2C controllers are the same, so for the purposes of
loading U-Boot, it should be sufficient. However this will display the Model
as "LogicPD Zoom DM3730 Torpedo + Wireless Development Kit" upon boot.
+
+The actual board remains autodetected and the Board will read "DM37xx SOM LV"
when used on the DM37 SOM-LV. The device tree loaded with Linux is also
correct.
+
+Integrating the SOM-LV Device Tree into U-Boot
+==
+
+This step is optional, but should you want to change the default to the
SOM-LV, locate the configs/omap3_logic_defconfig file and make the following
change.
+
+ CONFIG_DEFAULT_DEVICE_TREE="logicpd-som-lv-37xx-devkit"
+
+ make distclean
+ make omap3_logic_defconfig
+
diff --git a/board/logicpd/omap3som/omap3logic.c
b/board/logicpd/omap3som/omap3logic.c
index 4ad496e..ce17db6 100644
--- a/board/logicpd/omap3som/omap3logic.c
+++ b/board/logicpd/omap3som/omap3logic.c
@@ -36,16 +36,8 @@
DECLARE_GLOBAL_DATA_PTR;
-#define CONTROL_WKUP_CTRL 0x48002a5c
-#define GPIO_IO_PWRDNZ (1 << 6)
-#define PBIASLITEVMODE1(1 << 8)
-
-/*
- * two dimensional array of strucures containining board name and Linux
- * machine IDs; row it selected based on CPU column is slected based
- * on hsusb0_data5 pin having a pulldown resistor
- */
-
+/* This is only needed until SPL gets OF support */
+#ifdef CONFIG_SPL_BUILD
static const struct ns16550_platdata omap3logic_serial = {
.base = OMAP34XX_UART1,
.reg_shift = 2,
@@ -57,7 +49,13 @@ U_BOOT_DEVICE(omap3logic_uart) = {
"ns16550_serial",
&omap3logic_serial
};
+#endif
+/*
+ * two dimensional array of strucures containining board name and Linux
+ * machine IDs; row it selected based on CPU column is slected based
+ * on hsusb0_data5 pin having a pulldown resistor
+ */
static struct board_id {
char *name;
int machine_id;
diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig
index 89bf38f..86f34bb 100644
--- a/configs/omap3_logic_defconfig
+++ b/configs/omap3_logic_defconfig
@@ -3,6 +3,8 @@ CONFIG_OMAP34XX=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_OMAP3_LOGIC=y
CONFIG_SPL_STACK_R_ADDR=0x8200
+CONFIG_DEFAULT_DEVICE_TREE="logicpd-torpedo-37xx-devkit"
+CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
@@ -36,6 +38,11 @@ CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
+CONFIG_OF_CONTROL=y
+# CONFIG_BLK is not set
+CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
+# CONFIG_DM_MMC_OPS is not set
CONFIG_MMC_OMAP_HS=y
CONFIG_MMC_OMAP36XX_PINS=y
CONFIG_SYS_NS16550=y
@@ -46,4 +53,3 @@ CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_G_DNL_MANUFACTURER="TI"
CONFIG_G_DNL_VENDOR_NUM=0x0451
CONFIG_G_DNL_PRODUCT_NUM=0xd022
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
index 706175c..772fc60 100644
--- a/include/configs/omap3_logic.h
+++ b/include/configs/omap3_logic.h
@@ -17,12 +17,28 @@
#include
+#ifdef CONFIG_SPL_BUILD
+/*
+ * Disable MMC DM for SPL build and can be re-enabled after adding
+ * DM support in SPL
+ */
+#undef CONFIG_DM_MMC
+#undef OMAP_HSMMC_USE_GPIO
+
+/* select serial console configuration for SPL */
+#undef CONFIG_CONS_INDEX
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550_COM1OMAP34XX_UART1
+#endif
+
+
/*
* We are only ever GP parts and will utilize all of the "downloaded image"
* area in SRAM which starts at 0x4020 and ends at 0x4020 (64KB) in
* order to allow for BCH8 to fit in.
*/
#undef CONFIG_SPL_TEXT_BASE
+#define CONFIG_
[U-Boot] [PATCH V2 7/9] ARM: DTS: Add Logic PD DM3730 SOM-LV initial support
This adds the device tree. Previous commit added both boards at the
same time.
Signed-off-by: Adam Ford
Changes in V2:
Split the SOM-LV from Torpedo
diff --git a/arch/arm/dts/logicpd-som-lv-37xx-devkit.dts
b/arch/arm/dts/logicpd-som-lv-37xx-devkit.dts
new file mode 100644
index 000..1702b9e
--- /dev/null
+++ b/arch/arm/dts/logicpd-som-lv-37xx-devkit.dts
@@ -0,0 +1,269 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include "omap36xx.dtsi"
+#include "logicpd-som-lv.dtsi"
+#include "omap-gpmc-smsc9221.dtsi"
+
+/ {
+ model = "LogicPD Zoom DM3730 SOM-LV Development Kit";
+ compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3630", "ti,omap3";
+
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_key_pins>;
+
+ sysboot2 {
+ label = "gpio3";
+ gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;/* gpio_111 /
uP_GPIO_3 */
+ linux,code = ;
+ wakeup-source;
+ };
+ };
+
+ sound {
+ compatible = "ti,omap-twl4030";
+ ti,model = "omap3logic";
+ ti,mcbsp = <&mcbsp2>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins &led_pins_wkup>;
+
+ led1 {
+ label = "led1";
+ gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; /* gpio133 */
+ linux,default-trigger = "cpu0";
+ };
+
+ led2 {
+ label = "led2";
+ gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;/* gpio11 */
+ linux,default-trigger = "none";
+ };
+ };
+};
+
+&vaux1 {
+ regulator-min-microvolt = <300>;
+ regulator-max-microvolt = <300>;
+};
+
+&vaux4 {
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+};
+
+&mcbsp2 {
+ status = "okay";
+};
+
+&charger {
+ ti,bb-uvolt = <320>;
+ ti,bb-uamp = <150>;
+};
+
+&gpmc {
+ ranges = <1 0 0x0800 0x100>;/* CS1: 16MB for LAN9221 */
+
+ ethernet@gpmc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&lan9221_pins>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <24 IRQ_TYPE_LEVEL_LOW>; /* gpio_152 */
+ reg = <1 0 0xff>;
+ };
+};
+
+&vpll2 {
+ regulator-always-on;
+};
+
+&dss {
+ status = "ok";
+ vdds_dsi-supply = <&vpll2>;
+ vdda_video-supply = <&video_reg>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&dss_dpi_pins1>;
+ port {
+ dpi_out: endpoint {
+ remote-endpoint = <&lcd_in>;
+ data-lines = <16>;
+ };
+ };
+};
+
+/ {
+ aliases {
+ display0 = &lcd0;
+ };
+
+ video_reg: video_reg {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-supply";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ };
+
+ lcd0: display@0 {
+ compatible = "panel-dpi";
+ label = "28";
+ status = "okay";
+ /* default-on; */
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_enable_pin>;
+ enable-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>;/* gpio155, lcd
INI */
+ port {
+ lcd_in: endpoint {
+ remote-endpoint = <&dpi_out>;
+ };
+ };
+
+ panel-timing {
+ clock-frequency = <900>;
+ hactive = <480>;
+ vactive = <272>;
+ hfront-porch = <3>;
+ hback-porch = <2>;
+ hsync-len = <42>;
+ vback-porch = <3>;
+ vfront-porch = <2>;
+ vsync-len = <11>;
+ hsync-active = <1>;
+ vsync-active = <1>;
+ de-active = <1>;
+ pixelclk-active = <0>;
+ };
+ };
+
+ bl: backlight {
+ compatible = "pwm-backlight";
+ pinctrl-names = "default";
+ pinctrl-0 = <&backlight_pins>;
+ pwms = <&twl_pwm 0 500>;
+ brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
+ default-brightness-le
Re: [U-Boot] [PATCH 03/19] fdt: Use SPDX format for licenses in the libfdt headers
Hi Tom, 2017-04-17 22:05 GMT+09:00 Tom Rini : > On Sun, Apr 16, 2017 at 08:22:17PM -0600, Simon Glass wrote: > >> These should follow the UBoot standard. Update them. >> >> Signed-off-by: Simon Glass >> --- >> >> include/fdt.h| 46 +- >> include/libfdt.h | 46 +- >> 2 files changed, 2 insertions(+), 90 deletions(-) > > We're syncing these as-is, right? If so, just like DTB files, we don't > need to whack in an SPDX tag as that just complicates future re-syncs. > Do we have consistent policy for this? For example, git show 5b8031ccb4e -- scripts/kconfig/ ... complicates Kconfig re-syncs? -- Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH V2 8/9] ARM: DTS: Add Logic PD DM3730 Torpedo Device Tree
Previous commit has this combined with SOM-LV. This commit has only
the Torpedo Device Tree.
The device trees were sync'd with 4.9.y stable with two changes:
disable mmc2 and stdout-path = &uart1. Both of those two changes
will be submitted to the linux-omap list
Signed-off-by: Adam Ford
Changes in V2:
Split device tree from other board
diff --git a/arch/arm/dts/logicpd-torpedo-37xx-devkit.dts
b/arch/arm/dts/logicpd-torpedo-37xx-devkit.dts
new file mode 100644
index 000..de603a4
--- /dev/null
+++ b/arch/arm/dts/logicpd-torpedo-37xx-devkit.dts
@@ -0,0 +1,411 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include "omap36xx.dtsi"
+#include "logicpd-torpedo-som.dtsi"
+#include "omap-gpmc-smsc9221.dtsi"
+
+/ {
+ model = "LogicPD Zoom DM3730 Torpedo + Wireless Development Kit";
+ compatible = "logicpd,dm3730-torpedo-devkit", "ti,omap3630", "ti,omap3";
+
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_key_pins &gpio_key_pins_wkup>;
+
+ sysboot2 {
+ label = "sysboot2";
+ gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; /* gpio2 */
+ linux,code = ;
+ wakeup-source;
+ };
+
+ sysboot5 {
+ label = "sysboot5";
+ gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; /* gpio7 */
+ linux,code = ;
+ wakeup-source;
+ };
+
+ gpio1 {
+ label = "gpio1";
+ gpios = <&gpio6 21 GPIO_ACTIVE_LOW>;/* gpio181 */
+ linux,code = ;
+ wakeup-source;
+ };
+
+ gpio2 {
+ label = "gpio2";
+ gpios = <&gpio6 18 GPIO_ACTIVE_LOW>;/* gpio178 */
+ linux,code = ;
+ wakeup-source;
+ };
+ };
+
+ sound {
+ compatible = "ti,omap-twl4030";
+ ti,model = "omap3logic";
+ ti,mcbsp = <&mcbsp2>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins>;
+
+ led1 {
+ label = "led1";
+ gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>; /* gpio180 */
+ linux,default-trigger = "cpu0";
+ };
+
+ led2 {
+ label = "led2";
+ gpios = <&gpio6 19 GPIO_ACTIVE_HIGH>; /* gpio179 */
+ linux,default-trigger = "none";
+ };
+ };
+
+ pwm10: dmtimer-pwm {
+ compatible = "ti,omap-dmtimer-pwm";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm_pins>;
+ ti,timers = <&timer10>;
+ #pwm-cells = <3>;
+ };
+
+};
+
+&vaux1 {
+ regulator-min-microvolt = <300>;
+ regulator-max-microvolt = <300>;
+};
+
+&vaux4 {
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+};
+
+&mcbsp2 {
+ status = "okay";
+};
+
+&charger {
+ ti,bb-uvolt = <320>;
+ ti,bb-uamp = <150>;
+};
+
+&gpmc {
+ ranges = <0 0 0x3000 0x100 /* CS0: 16MB for NAND */
+ 1 0 0x2c00 0x100>;/* CS1: 16MB for LAN9221 */
+
+ ethernet@gpmc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&lan9221_pins>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <1 IRQ_TYPE_LEVEL_LOW>;/* gpio129 */
+ reg = <1 0 0xff>;
+ };
+};
+
+&vpll2 {
+ regulator-always-on;
+};
+
+&dss {
+ status = "ok";
+ vdds_dsi-supply = <&vpll2>;
+ vdda_video-supply = <&video_reg>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&dss_dpi_pins1>;
+ port {
+ dpi_out: endpoint {
+ remote-endpoint = <&lcd_in>;
+ data-lines = <16>;
+ };
+ };
+};
+
+/ {
+ aliases {
+ display0 = &lcd0;
+ };
+
+ video_reg: video_reg {
+ pinctrl-names = "default";
+ pinctrl-0 = <&panel_pwr_pins>;
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-supply";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ gpio = <&gpio5 27 GPIO_ACTIVE_HIGH>;/* gpio155, lcd INI */
+ };
+
+ lcd0: display {
+
[U-Boot] [PATCH V2 4/9] ARM: OMAP: I2C: Support New read, write and probe functions for OMAP3
New i2c_read, i2c_write and i2c_probe functions, tested on OMAP4
(4430/60/70), OMAP5 (5430) and AM335X (3359) were added in 960187ffa125(
"ARM: OMAP: I2C: New read, write and probe functions") but not tested
on OMAP3. This patch will allow the updated drivers using device tree and
DM_I2C to operate on OMAP3.
Signed-off-by: Adam Ford
Reviewed-by: Lokesh Vutla
diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
index 26996e9..a23737a 100644
--- a/drivers/i2c/omap24xx_i2c.c
+++ b/drivers/i2c/omap24xx_i2c.c
@@ -910,6 +910,7 @@ static const struct dm_i2c_ops omap_i2c_ops = {
};
static const struct udevice_id omap_i2c_ids[] = {
+ { .compatible = "ti,omap3-i2c" },
{ .compatible = "ti,omap4-i2c" },
{ }
};
--
2.7.4
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[U-Boot] [PATCH v2 3/3] arm: Warn that starting with v2018.01 gcc-6 or later is required
There are more and more cases where if we do not use gcc-6.0 or later we run into problems where our binaries are too large for the targets. Given the prevalence of gcc-6.0 or later toolchains at this point in time, we give notice now that starting with v2018.01 we will require gcc-6 (or later) for ARM. Signed-off-by: Tom Rini --- Changes in v2: - Move logic out of THUMB check so we always do it, as noted by Masahiro. - Reword the message slightly so it's shorter than 80 characters. --- arch/arm/config.mk | 12 +++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm/config.mk b/arch/arm/config.mk index 907c69371b94..eb09b0e37878 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -45,7 +45,7 @@ endif # Only test once ifeq ($(CONFIG_$(SPL_)SYS_THUMB_BUILD),y) -archprepare: checkthumb +archprepare: checkthumb checkgcc6 checkthumb: @if test "$(call cc-name)" = "gcc" -a \ @@ -55,8 +55,18 @@ checkthumb: echo '*** Your board is configured for THUMB mode.'; \ false; \ fi +else +archprepare: checkgcc6 endif +checkgcc6: + @if test "$(call cc-name)" = "gcc" -a \ + "$(call cc-version)" -lt "0600"; then \ + echo -n '*** Your GCC is older than 6.0 and will not be '; \ + echo 'supported starting in v2018.01.'; \ + fi + + # Try if EABI is supported, else fall back to old API, # i. e. for example: # - with ELDK 4.2 (EABI supported), use: -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 00/35] ARM: i.MX6: SabreSD: Add dts support
On Mon, Apr 10, 2017 at 4:43 AM, Fabio Estevam wrote: > On Sun, Apr 9, 2017 at 4:12 PM, Jagan Teki wrote: > >> Bcz we need to define dtb through CONFIG_DEFAULT_DEVICE_TREE > > Having 3 defconfigs for SPL is not good. Looks like a step in the > opposite direction. > > Can this limitation be changed? This isn't a limitation, all the defconfigs on various boards follows the same but except by giving dtb explicitly doing make, like make DEVICE_TREE=imx6l-sabresd thanks! -- Jagan Teki Free Software Engineer | www.openedev.com U-Boot, Linux | Upstream Maintainer Hyderabad, India. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 03/19] fdt: Use SPDX format for licenses in the libfdt headers
On Mon, Apr 17, 2017 at 10:13:06PM +0900, Masahiro Yamada wrote: > Hi Tom, > > > 2017-04-17 22:05 GMT+09:00 Tom Rini : > > On Sun, Apr 16, 2017 at 08:22:17PM -0600, Simon Glass wrote: > > > >> These should follow the UBoot standard. Update them. > >> > >> Signed-off-by: Simon Glass > >> --- > >> > >> include/fdt.h| 46 +- > >> include/libfdt.h | 46 +- > >> 2 files changed, 2 insertions(+), 90 deletions(-) > > > > We're syncing these as-is, right? If so, just like DTB files, we don't > > need to whack in an SPDX tag as that just complicates future re-syncs. > > Do we have consistent policy for this? > > For example, > > git show 5b8031ccb4e -- scripts/kconfig/ > > ... complicates Kconfig re-syncs? We ought to be consistent here, and if you happen to stomp on that next time you re-sync I really can't complain. We certainly don't do it in dtb files as that's just annoyed upstream when people have tried to push the changes back up. In cases where we are able to 100% drop-in upstream files, it's best to not do the conversion. In other cases, say MTD and 78e9e71c83cf, we have other changes, re-sync requires attention and we do have some U-Boot'isms, we might as well convert. -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 03/19] fdt: Use SPDX format for licenses in the libfdt headers
Hi Tom, On 17 April 2017 at 07:33, Tom Rini wrote: > > On Mon, Apr 17, 2017 at 10:13:06PM +0900, Masahiro Yamada wrote: > > Hi Tom, > > > > > > 2017-04-17 22:05 GMT+09:00 Tom Rini : > > > On Sun, Apr 16, 2017 at 08:22:17PM -0600, Simon Glass wrote: > > > > > >> These should follow the UBoot standard. Update them. > > >> > > >> Signed-off-by: Simon Glass > > >> --- > > >> > > >> include/fdt.h| 46 +- > > >> include/libfdt.h | 46 +- > > >> 2 files changed, 2 insertions(+), 90 deletions(-) > > > > > > We're syncing these as-is, right? If so, just like DTB files, we don't > > > need to whack in an SPDX tag as that just complicates future re-syncs. > > > > Do we have consistent policy for this? > > > > For example, > > > > git show 5b8031ccb4e -- scripts/kconfig/ > > > > ... complicates Kconfig re-syncs? > > We ought to be consistent here, and if you happen to stomp on that next > time you re-sync I really can't complain. We certainly don't do it in > dtb files as that's just annoyed upstream when people have tried to push > the changes back up. In cases where we are able to 100% drop-in > upstream files, it's best to not do the conversion. In other cases, say > MTD and 78e9e71c83cf, we have other changes, re-sync requires attention > and we do have some U-Boot'isms, we might as well convert. These files are not exactly the same, since we have different header includes and a few other features that are not yet upstream. I am always comparing the files anyway so it's no bother to ignore the license at the top. The rest of the libfdt files in U-Boot use SPDX. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 03/19] fdt: Use SPDX format for licenses in the libfdt headers
On Mon, Apr 17, 2017 at 07:47:34AM -0600, Simon Glass wrote: > Hi Tom, > > On 17 April 2017 at 07:33, Tom Rini wrote: > > > > On Mon, Apr 17, 2017 at 10:13:06PM +0900, Masahiro Yamada wrote: > > > Hi Tom, > > > > > > > > > 2017-04-17 22:05 GMT+09:00 Tom Rini : > > > > On Sun, Apr 16, 2017 at 08:22:17PM -0600, Simon Glass wrote: > > > > > > > >> These should follow the UBoot standard. Update them. > > > >> > > > >> Signed-off-by: Simon Glass > > > >> --- > > > >> > > > >> include/fdt.h| 46 +- > > > >> include/libfdt.h | 46 +- > > > >> 2 files changed, 2 insertions(+), 90 deletions(-) > > > > > > > > We're syncing these as-is, right? If so, just like DTB files, we don't > > > > need to whack in an SPDX tag as that just complicates future re-syncs. > > > > > > Do we have consistent policy for this? > > > > > > For example, > > > > > > git show 5b8031ccb4e -- scripts/kconfig/ > > > > > > ... complicates Kconfig re-syncs? > > > > We ought to be consistent here, and if you happen to stomp on that next > > time you re-sync I really can't complain. We certainly don't do it in > > dtb files as that's just annoyed upstream when people have tried to push > > the changes back up. In cases where we are able to 100% drop-in > > upstream files, it's best to not do the conversion. In other cases, say > > MTD and 78e9e71c83cf, we have other changes, re-sync requires attention > > and we do have some U-Boot'isms, we might as well convert. > > These files are not exactly the same, since we have different header > includes and a few other features that are not yet upstream. I am > always comparing the files anyway so it's no bother to ignore the > license at the top. The rest of the libfdt files in U-Boot use SPDX. OK, thanks. -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 0/8] Add mipi display support for rk3399
Eric Gao (8): rockchip: video: Add mipi dsi driver for rk3399 rockchip: video: vop: Add mipi display mode for rk3399 rockchip: video: vop: Set different bitwidth for different display mode rockchip: video: vop: Reserve enough space for mipi dispaly rockchip: board: evb_rk3399: initialize pwm0 for dispaly backlight rockchip: dts: Add mipi dsi support for rk3399 rockchip: configs: Enable mipi dsi for rk3399 rockchip: video: vop: Fix clk_set_rate() return error arch/arm/dts/rk3399-evb.dts | 84 arch/arm/dts/rk3399.dtsi | 72 arch/arm/include/asm/arch-rockchip/grf_rk3399.h | 25 ++ arch/arm/include/asm/arch-rockchip/mipi_rk3399.h | 195 + arch/arm/include/asm/arch-rockchip/vop_rk3288.h | 1 + board/rockchip/evb_rk3399/evb-rk3399.c | 7 + configs/evb-rk3399_defconfig | 6 + drivers/video/rockchip/Kconfig | 11 +- drivers/video/rockchip/Makefile | 1 + drivers/video/rockchip/rk_mipi.c | 484 +++ drivers/video/rockchip/rk_vop.c | 30 +- 11 files changed, 908 insertions(+), 8 deletions(-) create mode 100644 arch/arm/include/asm/arch-rockchip/mipi_rk3399.h create mode 100644 drivers/video/rockchip/rk_mipi.c -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/8] rockchip: video: Add mipi dsi driver for rk3399
Signed-off-by: Eric Gao
---
arch/arm/include/asm/arch-rockchip/grf_rk3399.h | 25 ++
arch/arm/include/asm/arch-rockchip/mipi_rk3399.h | 195 +
drivers/video/rockchip/Kconfig | 11 +-
drivers/video/rockchip/Makefile | 1 +
drivers/video/rockchip/rk_mipi.c | 484 +++
5 files changed, 714 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/include/asm/arch-rockchip/mipi_rk3399.h
create mode 100644 drivers/video/rockchip/rk_mipi.c
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
index b340b05..b4ba436 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
@@ -440,6 +440,31 @@ enum {
GRF_UART_DBG_SEL_MASK = 3 << GRF_UART_DBG_SEL_SHIFT,
GRF_UART_DBG_SEL_C = 2,
+ /* GRF_SOC_CON20 */
+ GRF_DSI0_VOP_SEL_SHIFT = 0,
+ GRF_DSI0_VOP_SEL_MASK = 1 << GRF_DSI0_VOP_SEL_SHIFT,
+ GRF_DSI0_VOP_SEL_B = 0,
+ GRF_DSI0_VOP_SEL_L,
+
+ /* GRF_SOC_CON22 */
+ GRF_DPHY_TX0_RXMODE_SHIFT = 0,
+ GRF_DPHY_TX0_RXMODE_MASK =
+ 0xf << GRF_DPHY_TX0_RXMODE_SHIFT,
+ GRF_DPHY_TX0_RXMODE_EN = 0xb,
+ GRF_DPHY_TX0_RXMODE_DIS = 0,
+
+ GRF_DPHY_TX0_TXSTOPMODE_SHIFT = 4,
+ GRF_DPHY_TX0_TXSTOPMODE_MASK =
+ 0xf0 << GRF_DPHY_TX0_TXSTOPMODE_SHIFT,
+ GRF_DPHY_TX0_TXSTOPMODE_EN = 0xc,
+ GRF_DPHY_TX0_TXSTOPMODE_DIS = 0,
+
+ GRF_DPHY_TX0_TURNREQUEST_SHIFT = 12,
+ GRF_DPHY_TX0_TURNREQUEST_MASK =
+ 0xf000 << GRF_DPHY_TX0_TURNREQUEST_SHIFT,
+ GRF_DPHY_TX0_TURNREQUEST_EN = 0x1,
+ GRF_DPHY_TX0_TURNREQUEST_DIS = 0,
+
/* PMUGRF_GPIO0A_IOMUX */
PMUGRF_GPIO0A6_SEL_SHIFT= 12,
PMUGRF_GPIO0A6_SEL_MASK = 3 << PMUGRF_GPIO0A6_SEL_SHIFT,
diff --git a/arch/arm/include/asm/arch-rockchip/mipi_rk3399.h
b/arch/arm/include/asm/arch-rockchip/mipi_rk3399.h
new file mode 100644
index 000..f55ffb6
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/mipi_rk3399.h
@@ -0,0 +1,195 @@
+/*
+ * Copyright (C) 2017-2025 Fuzhou Rockchip Electronics Co., Ltd
+ * author: Eric Gao
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef RK33_MIPI_DSI_H
+#define RK33_MIPI_DSI_H
+
+/*
+ * All these mipi controller register declaration provide reg address offset,
+ * bits width, bit offset for a specified register bits. With these message, we
+ * can set or clear every bits individually for a 32bit widthregister. We use
+ * DSI_HOST_BITS macro definition to combinat these message using the following
+ * format: val(32bit) = addr(16bit) | width(8bit) | offest(8bit)
+ * For example:
+ *#define SHUTDOWNZ DSI_HOST_BITS(0x004, 1, 0)
+ * means SHUTDOWNZ is a signal reg bit with bit offset qual 0,and it's reg addr
+ * offset is 0x004.The conbinat result = (0x004 << 16) | (1 << 8) | 0
+ */
+#define ADDR_SHIFT 16
+#define BITS_SHIFT 8
+#define OFFSET_SHIFT 0
+#define DSI_HOST_BITS(addr, bits, bit_offset) \
+((addr << ADDR_SHIFT) | (bits << BITS_SHIFT) | (bit_offset << OFFSET_SHIFT))
+
+/* DWC_DSI_VERSION_0x3133302A */
+#define VERSIONDSI_HOST_BITS(0x000, 32, 0)
+#define SHUTDOWNZ DSI_HOST_BITS(0x004, 1, 0)
+#define TO_CLK_DIVISIONDSI_HOST_BITS(0x008, 8, 8)
+#define TX_ESC_CLK_DIVISIONDSI_HOST_BITS(0x008, 8, 0)
+#define DPI_VCID DSI_HOST_BITS(0x00c, 2, 0)
+#define EN18_LOOSELY DSI_HOST_BITS(0x010, 1, 8)
+#define DPI_COLOR_CODING DSI_HOST_BITS(0x010, 4, 0)
+#define COLORM_ACTIVE_LOW DSI_HOST_BITS(0x014, 1, 4)
+#define SHUTD_ACTIVE_LOW DSI_HOST_BITS(0x014, 1, 3)
+#define HSYNC_ACTIVE_LOW DSI_HOST_BITS(0x014, 1, 2)
+#define VSYNC_ACTIVE_LOW DSI_HOST_BITS(0x014, 1, 1)
+#define DATAEN_ACTIVE_LOW DSI_HOST_BITS(0x014, 1, 0)
+#define OUTVACT_LPCMD_TIME DSI_HOST_BITS(0x018, 8, 16)
+#define INVACT_LPCMD_TIME DSI_HOST_BITS(0x018, 8, 0)
+#define CRC_RX_EN DSI_HOST_BITS(0x02c, 1, 4)
+#define ECC_RX_EN DSI_HOST_BITS(0x02c, 1, 3)
+#define BTA_EN DSI_HOST_BITS(0x02c, 1, 2)
+#define EOTP_RX_EN DSI_HOST_BITS(0x02c, 1, 1)
+#define EOTP_TX_EN DSI_HOST_BITS(0x02c, 1, 0)
+#define GEN_VID_RX DSI_HOST_BITS(0x030, 2, 0)
+#define CMD_VIDEO_MODE DSI_HOST_BITS(0x034, 1, 0)
+#define VPG_ORIENTATIONDSI_HOST_BITS(0x038, 1, 24)
+#define VPG_MODE DSI_HOST_BITS(0x038, 1, 20)
+#define VPG_EN DSI_HOST_BITS(0x038, 1, 16)
+#define LP_CMD_EN DSI_HOST_BITS(0x038, 1, 15)
+#define FRAME_BTA_ACK_EN DSI_HOST_BITS(0x038, 1, 14)
+#define LP_HFP_EN DSI_HOST_BITS(0x038, 1, 13)
+#define LP_HBP_EN D
[U-Boot] [PATCH 2/8] rockchip: video: vop: Add mipi display mode for rk3399
Add mipi display mode for rk3399 vop, so that we can use mipi panel
for display.
Signed-off-by: Eric Gao
---
arch/arm/include/asm/arch-rockchip/vop_rk3288.h | 1 +
drivers/video/rockchip/rk_vop.c | 6 ++
2 files changed, 7 insertions(+)
diff --git a/arch/arm/include/asm/arch-rockchip/vop_rk3288.h
b/arch/arm/include/asm/arch-rockchip/vop_rk3288.h
index 0ce3d67..d5599ec 100644
--- a/arch/arm/include/asm/arch-rockchip/vop_rk3288.h
+++ b/arch/arm/include/asm/arch-rockchip/vop_rk3288.h
@@ -90,6 +90,7 @@ enum vop_modes {
VOP_MODE_EDP = 0,
VOP_MODE_HDMI,
VOP_MODE_LVDS,
+ VOP_MODE_MIPI,
VOP_MODE_NONE,
VOP_MODE_AUTO_DETECT,
VOP_MODE_UNKNOWN,
diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c
index bc02f80..84d6627 100644
--- a/drivers/video/rockchip/rk_vop.c
+++ b/drivers/video/rockchip/rk_vop.c
@@ -117,6 +117,10 @@ void rkvop_mode_set(struct rk3288_vop *regs,
clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN,
V_RGB_OUT_EN(1));
break;
+ case VOP_MODE_MIPI:
+ clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN,
+ V_MIPI_OUT_EN(1));
+break;
}
if (mode == VOP_MODE_HDMI || mode == VOP_MODE_EDP)
@@ -350,6 +354,8 @@ static const struct video_ops rk_vop_ops = {
};
static const struct udevice_id rk_vop_ids[] = {
+ { .compatible = "rockchip,rk3399-vop-big" },
+ { .compatible = "rockchip,rk3399-vop-lit" },
{ .compatible = "rockchip,rk3288-vop" },
{ }
};
--
1.9.1
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[U-Boot] [PATCH 3/8] rockchip: video: vop: Set different bitwidth for different display mode
Because the bitwidth is different for different display mode, so we need
to set them according to demand.
Signed-off-by: Eric Gao
---
drivers/video/rockchip/rk_vop.c | 20
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c
index 84d6627..a637f7d 100644
--- a/drivers/video/rockchip/rk_vop.c
+++ b/drivers/video/rockchip/rk_vop.c
@@ -181,13 +181,11 @@ void rkvop_mode_set(struct rk3288_vop *regs,
*
* @dev: VOP device that we want to connect to the display
* @fbbase:Frame buffer address
- * @l2bpp Log2 of bits-per-pixels for the display
* @ep_node: Device tree node to process - this is the offset of an endpoint
* node within the VOP's 'port' list.
* @return 0 if OK, -ve if something went wrong
*/
-int rk_display_init(struct udevice *dev, ulong fbbase,
- enum video_log2_bpp l2bpp, int ep_node)
+int rk_display_init(struct udevice *dev, ulong fbbase, int ep_node)
{
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
const void *blob = gd->fdt_blob;
@@ -199,6 +197,7 @@ int rk_display_init(struct udevice *dev, ulong fbbase,
int ret, remote, i, offset;
struct display_plat *disp_uc_plat;
struct clk clk;
+ enum video_log2_bpp l2bpp;
vop_id = fdtdec_get_int(blob, ep_node, "reg", -1);
debug("vop_id=%d\n", vop_id);
@@ -253,6 +252,19 @@ int rk_display_init(struct udevice *dev, ulong fbbase,
return ret;
}
+ /* Set bitwidth for vop display according to vop mode */
+ switch (vop_id) {
+ case VOP_MODE_EDP:
+ case VOP_MODE_HDMI:
+ case VOP_MODE_LVDS:
+ l2bpp = VIDEO_BPP16;
+ break;
+ case VOP_MODE_MIPI:
+ l2bpp = VIDEO_BPP32;
+ break;
+ default:
+ l2bpp = VIDEO_BPP16;
+ }
rkvop_mode_set(regs, &timing, vop_id);
rkvop_enable(regs, fbbase, 1 << l2bpp, &timing);
@@ -330,7 +342,7 @@ static int rk_vop_probe(struct udevice *dev)
for (node = fdt_first_subnode(blob, port);
node > 0;
node = fdt_next_subnode(blob, node)) {
- ret = rk_display_init(dev, plat->base, VIDEO_BPP16, node);
+ ret = rk_display_init(dev, plat->base, node);
if (ret)
debug("Device failed: ret=%d\n", ret);
if (!ret)
--
1.9.1
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[U-Boot] [PATCH 4/8] rockchip: video: vop: Reserve enough space for mipi dispaly
plat->size here is used to reserve enough frame buffer space befor relocation.
our mipi display mode need more space, so reset it.
Signed-off-by: Eric Gao
---
drivers/video/rockchip/rk_vop.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c
index a637f7d..ac9e7db 100644
--- a/drivers/video/rockchip/rk_vop.c
+++ b/drivers/video/rockchip/rk_vop.c
@@ -357,7 +357,7 @@ static int rk_vop_bind(struct udevice *dev)
{
struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
- plat->size = 1920 * 1080 * 2;
+ plat->size = 1920 * 1200 * 4;
return 0;
}
--
1.9.1
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[U-Boot] [PATCH 5/8] rockchip: board: evb_rk3399: initialize pwm0 for dispaly backlight
Signed-off-by: Eric Gao
---
board/rockchip/evb_rk3399/evb-rk3399.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/board/rockchip/evb_rk3399/evb-rk3399.c
b/board/rockchip/evb_rk3399/evb-rk3399.c
index 362fa0b..76ab467 100644
--- a/board/rockchip/evb_rk3399/evb-rk3399.c
+++ b/board/rockchip/evb_rk3399/evb-rk3399.c
@@ -28,6 +28,13 @@ int board_init(void)
goto out;
}
+ /* Enable pwm0 for panel backlight */
+ ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_PWM0);
+ if (ret) {
+ debug("%s PWM0 pinctrl init fail!\n", __func__);
+ goto out;
+ }
+
ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_PWM2);
if (ret) {
debug("%s PWM2 pinctrl init fail!\n", __func__);
--
1.9.1
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[U-Boot] [PATCH v3 0/2] Add Kconfig for rockchip video driver.
patch 1: add Kconfig file rockchip video driver. patch 2: modify Makefile according to the new Kconfig. Eric Gao (2): rockchip: video: Kconfig: Add Kconfig for rockchip video driver rockchip: video: Makefile: Modify Makefile for rockchip video driver configs/chromebit_mickey_defconfig | 1 + configs/chromebook_jerry_defconfig | 2 ++ configs/chromebook_minnie_defconfig | 2 ++ configs/firefly-rk3288_defconfig| 1 + configs/miqi-rk3288_defconfig | 1 + configs/rock2_defconfig | 1 + drivers/video/Kconfig | 10 + drivers/video/rockchip/Kconfig | 43 + drivers/video/rockchip/Makefile | 7 +- 9 files changed, 58 insertions(+), 10 deletions(-) create mode 100644 drivers/video/rockchip/Kconfig -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 6/8] rockchip: dts: Add mipi dsi support for rk3399
Add dts config for mipi display, include vop, mipi controller, panel, backlight
. And Enable rk808 for lcd_3v3 in another patch.
Signed-off-by: Eric Gao
---
arch/arm/dts/rk3399-evb.dts | 84 +
arch/arm/dts/rk3399.dtsi| 72 ++
2 files changed, 156 insertions(+)
diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts
index e1f867b..3d6f3ce 100644
--- a/arch/arm/dts/rk3399-evb.dts
+++ b/arch/arm/dts/rk3399-evb.dts
@@ -59,6 +59,15 @@
gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
};
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ status = "disabled";
+ };
+
+ panel:panel {
+ compatible = "simple-panel";
+ status = "disabled";
+ };
};
&emmc_phy {
@@ -141,6 +150,7 @@
status = "okay";
vcc12-supply = <&vcc3v3_sys>;
+
regulators {
vcc33_lcd: SWITCH_REG2 {
regulator-always-on;
@@ -151,6 +161,80 @@
};
};
+&backlight {
+ power-supply = <&vccsys>;
+ enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+ brightness-levels = <
+ 0 1 2 3 4 5 6 7
+ 8 9 10 11 12 13 14 15
+16 17 18 19 20 21 22 23
+24 25 26 27 28 29 30 31
+32 33 34 35 36 37 38 39
+40 41 42 43 44 45 46 47
+48 49 50 51 52 53 54 55
+56 57 58 59 60 61 62 63
+64 65 66 67 68 69 70 71
+72 73 74 75 76 77 78 79
+80 81 82 83 84 85 86 87
+88 89 90 91 92 93 94 95
+96 97 98 99 100 101 102 103
+ 104 105 106 107 108 109 110 111
+ 112 113 114 115 116 117 118 119
+ 120 121 122 123 124 125 126 127
+ 128 129 130 131 132 133 134 135
+ 136 137 138 139 140 141 142 143
+ 144 145 146 147 148 149 150 151
+ 152 153 154 155 156 157 158 159
+ 160 161 162 163 164 165 166 167
+ 168 169 170 171 172 173 174 175
+ 176 177 178 179 180 181 182 183
+ 184 185 186 187 188 189 190 191
+ 192 193 194 195 196 197 198 199
+ 200 201 202 203 204 205 206 207
+ 208 209 210 211 212 213 214 215
+ 216 217 218 219 220 221 222 223
+ 224 225 226 227 228 229 230 231
+ 232 233 234 235 236 237 238 239
+ 240 241 242 243 244 245 246 247
+ 248 249 250 251 252 253 254 255>;
+ default-brightness-level = <200>;
+ pwms = <&pwm0 0 25000 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_pin>;
+ pwm-delay-us = <1>;
+ status = "okay";
+ };
+
+&panel {
+ power-supply = <&vcc33_lcd>;
+ backlight = <&backlight>;
+ /*enable-gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>;*/
+ status = "okay";
+};
+
+&mipi_dsi {
+ status = "okay";
+ rockchip,panel = <&panel>;
+ display-timings {
+ timing0 {
+ bits-per-pixel = <24>;
+ clock-frequency = <16000>;
+ hfront-porch = <120>;
+ hsync-len = <20>;
+ hback-porch = <21>;
+ hactive = <1200>;
+ vfront-porch = <21>;
+ vsync-len = <3>;
+ vback-porch = <18>;
+ vactive = <1920>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <1>;
+ pixelclk-active = <0>;
+ };
+ };
+};
+
&pinctrl {
pmic {
pmic_int_l: pmic-int-l {
diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi
index d94d780..9344a43 100644
--- a/arch/arm/dts/rk3399.dtsi
+++ b/arch/arm/dts/rk3399.dtsi
@@ -684,6 +684,78 @@
status = "disabled";
};
+ vopl: vop@ff8f {
+ u-boot,dm-pre-reloc;
+ compatible = "rockchip,rk3399-vop-lit";
+ reg = <0x0 0xff8f 0x0 0x3efc>;
+ interrupts = ;
+ clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
+ clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+ resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru
SRST_D_VOP1>;
+ reset-names = "axi", "ahb", "dclk";
+ status = "
[U-Boot] [PATCH 8/8] rockchip: video: vop: Fix clk_set_rate() return error
The function clk_set_rate() will return it's input parameter, so it's return
value in normal condition is nonzero. In this case, we should report an error
when it return zero rather than return a nonzero value.
Signed-off-by: Eric Gao
---
drivers/video/rockchip/rk_vop.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c
index ac9e7db..e8fa177 100644
--- a/drivers/video/rockchip/rk_vop.c
+++ b/drivers/video/rockchip/rk_vop.c
@@ -247,7 +247,7 @@ int rk_display_init(struct udevice *dev, ulong fbbase, int
ep_node)
ret = clk_get_by_index(dev, 1, &clk);
if (!ret)
ret = clk_set_rate(&clk, timing.pixelclock.typ);
- if (ret) {
+ if (!ret) {
debug("%s: Failed to set pixel clock: ret=%d\n", __func__, ret);
return ret;
}
--
1.9.1
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[U-Boot] [PATCH 7/8] rockchip: configs: Enable mipi dsi for rk3399
Enable mipi dsi by default for rk3399-evb board Signed-off-by: Eric Gao --- configs/evb-rk3399_defconfig| 6 ++ drivers/video/rockchip/Kconfig | 2 +- drivers/video/rockchip/Makefile | 2 +- 3 files changed, 8 insertions(+), 2 deletions(-) diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index cef8506..3405857 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -66,3 +66,9 @@ CONFIG_PMIC_CHILDREN=y CONFIG_SPL_PMIC_CHILDREN=y CONFIG_PMIC_RK808=y CONFIG_REGULATOR_RK808=y +CONFIG_DM_VIDEO=y +CONFIG_DM_PWM=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_MIPI=y diff --git a/drivers/video/rockchip/Kconfig b/drivers/video/rockchip/Kconfig index 3f57d5c..1383efa 100644 --- a/drivers/video/rockchip/Kconfig +++ b/drivers/video/rockchip/Kconfig @@ -40,7 +40,7 @@ if VIDEO_ROCKCHIP This enable High-Definition Multimedia Interface(HDMI) display support. - config DISPLAY_MIPI + config DISPLAY_ROCKCHIP_MIPI bool "MIPI Port" depends on VIDEO_ROCKCHIP help diff --git a/drivers/video/rockchip/Makefile b/drivers/video/rockchip/Makefile index f9d1abf..c742902 100644 --- a/drivers/video/rockchip/Makefile +++ b/drivers/video/rockchip/Makefile @@ -10,5 +10,5 @@ obj-y += rk_vop.o obj-$(CONFIG_DISPLAY_ROCKCHIP_EDP) += rk_edp.o obj-$(CONFIG_DISPLAY_ROCKCHIP_LVDS) += rk_lvds.o obj-$(CONFIG_DISPLAY_ROCKCHIP_HDMI) += rk_hdmi.o ../dw_hdmi.o -obj-$(CONFIG_DISPLAY_MIPI) += rk_mipi.o +obj-$(CONFIG_DISPLAY_ROCKCHIP_MIPI) += rk_mipi.o endif -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 2/2] rockchip: video: Makefile: Modify Makefile for rockchip video driver
Modify Makefile for rockchip video driver according to Kconfig, so that source code will not be compiled if not needed. Signed-off-by: Eric Gao --- drivers/video/rockchip/Makefile | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/video/rockchip/Makefile b/drivers/video/rockchip/Makefile index 755350b..3bb0519 100644 --- a/drivers/video/rockchip/Makefile +++ b/drivers/video/rockchip/Makefile @@ -5,4 +5,9 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += rk_edp.o rk_hdmi.o rk_vop.o rk_lvds.o ../dw_hdmi.o +ifdef CONFIG_VIDEO_ROCKCHIP +obj-y += rk_vop.o +obj-$(CONFIG_DISPLAY_ROCKCHIP_EDP) += rk_edp.o +obj-$(CONFIG_DISPLAY_ROCKCHIP_LVDS) += rk_lvds.o +obj-$(CONFIG_DISPLAY_ROCKCHIP_HDMI) += rk_hdmi.o ../dw_hdmi.o +endif -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 1/2] rockchip: video: Kconfig: Add Kconfig for rockchip video driver
1. add Kconfig for rockchip video driver, so that video port can be selected as needed. 2. move VIDEO_ROCKCHIP option to new Kconfig for concision. Signed-off-by: Eric Gao --- configs/chromebit_mickey_defconfig | 1 + configs/chromebook_jerry_defconfig | 2 ++ configs/chromebook_minnie_defconfig | 2 ++ configs/firefly-rk3288_defconfig| 1 + configs/miqi-rk3288_defconfig | 1 + configs/rock2_defconfig | 1 + drivers/video/Kconfig | 10 + drivers/video/rockchip/Kconfig | 43 + 8 files changed, 52 insertions(+), 9 deletions(-) create mode 100644 drivers/video/rockchip/Kconfig diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig index a29e4e5..f04ecb4 100644 --- a/configs/chromebit_mickey_defconfig +++ b/configs/chromebit_mickey_defconfig @@ -72,6 +72,7 @@ CONFIG_SYSRESET=y CONFIG_DM_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index e642b8d..dd0476b 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -72,6 +72,8 @@ CONFIG_SYSRESET=y CONFIG_DM_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_EDP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig index 1812362..cecae5f 100644 --- a/configs/chromebook_minnie_defconfig +++ b/configs/chromebook_minnie_defconfig @@ -72,6 +72,8 @@ CONFIG_SYSRESET=y CONFIG_DM_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y +CONFIG_DISPLAY_ROCKCHIP_EDP=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index b0741d7..b975383 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -70,6 +70,7 @@ CONFIG_USB_STORAGE=y CONFIG_DM_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig index 203824b..71e4db7 100644 --- a/configs/miqi-rk3288_defconfig +++ b/configs/miqi-rk3288_defconfig @@ -67,6 +67,7 @@ CONFIG_USB_STORAGE=y CONFIG_DM_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig index e9a32a9..5ddca5a 100644 --- a/configs/rock2_defconfig +++ b/configs/rock2_defconfig @@ -64,6 +64,7 @@ CONFIG_SYSRESET=y CONFIG_DM_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 19e9745..818f738 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -416,15 +416,7 @@ config VIDEO_FSL_DCU_MAX_FB_SIZE_MB Set maximum framebuffer size to be used for Freescale Display Controller Unit (DCU4). -config VIDEO_ROCKCHIP - bool "Enable Rockchip video support" - depends on DM_VIDEO - help - Rockchip SoCs provide video output capabilities for High-Definition - Multimedia Interface (HDMI), Low-voltage Differential Signalling - (LVDS), embedded DisplayPort (eDP) and Display Serial Interface - (DSI). This driver supports the on-chip video output device, and - targets the Rockchip RK3288. +source "drivers/video/rockchip/Kconfig" config VIDEO_SANDBOX_SDL bool "Enable sandbox video console using SDL" diff --git a/drivers/video/rockchip/Kconfig b/drivers/video/rockchip/Kconfig new file mode 100644 index 000..09c4ea2 --- /dev/null +++ b/drivers/video/rockchip/Kconfig @@ -0,0 +1,43 @@ +# +# Video drivers selection for rockchip soc. These configs only impact the +# compile process. You can surely check all the options. In this case, all the +# display driver will be compiled, but which drivers finally will be used is +# decided by device tree configuration. What's more, enable needed power for +# display by configure the device tree, and the vop driver will do the rest. +# +# Author: Eric Gao +# + +menuconfig VIDEO_ROCKCHIP + bool "Enable Rockchip Video Support" + depends on DM_VIDEO + help + Rockchip SoCs provide video output capabilities for High-Definition + Multimedia Interface (HDMI), Low-voltage Differential Signalling + (LVDS), embedded DisplayPort (eDP) and Display Serial Interface + (
Re: [U-Boot] [PATCH V2 12/12] imx: mx7dsabresd: add board revision check
On Thu, Apr 13, 2017 at 3:10 AM, Peng Fan wrote:
> +#define BOARD_REV_C 0x300
> +#define BOARD_REV_B 0x200
> +#define BOARD_REV_A 0x100
> +
> +static int mx7sabre_rev(void)
> +{
> + /*
> +* Get Board ID information from OCOTP_GP1[15:8]
> +* i.MX7D SDB RevA: 0x41
> +* i.MX7D SDB RevB: 0x42
Isn't this versioning scheme shared with other NXP boards? If so, it
would be better to put this in common code.
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[U-Boot] [PATCH v3 1/7] rockchip: clk: rk3399: add clock support for SCLK_SPI1 and SCLK_SPI5
This change adds support for configuring the module clocks for SPI1 and
SPI5 from the 594MHz GPLL.
Note that the driver (rk_spi.c) always sets this to 99MHz, but the
implemented functionality is more general and will also support
different clock configurations.
X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich
Tested-by: Jakob Unterwurzacher
Tested-by: Klaus Goger
Cover-Letter:
rockchip: spi: rk3399: add SPI support for the RK3399
This series adds SPI support for the RK3399 (SPI1 and SPI5). This
consists of the following individual changes:
- clock support for the SPI blocks clocked from GRF (i.e. SPI1, SPI2,
SPI 4 and SPI5)
- pinctrl for SPI1 and SPI5
- changes the SPI module input clock to 198MHz (instead of 99MHz) for
the RK3399 to improve the available bitrates at higher frequencies
(e.g. adding the 39MBit and 28MBit operating points)
- modifies the calculation of the top frequency permissible (as the
49.5MBit operating point had not been permissible due to a hard
limit at 48MBit)
END
---
Changes in v3:
- replaced macro-pasting with a lookup table to improve readability
(as requested by Simon)
Changes in v2:
- fixes a wrong macro usage, which caused the SPI module input clock
frequency to be significantly higher than intended
- frequencies have now been validated using an oscilloscope (keep in mind
that all frequencies are derived from a 99MHz module input clock) at the
following measurement points (assuming the other fix for the usage of
DIV_RATE from the series):
* 1 MHz ... 0.99 MHz
* 5 MHz ... 4.95 MHz
* 10 MHz ... 9.9 MHz
* 30 MHz ... 33MHz
* 50 MHz ... 49.5 MHz
drivers/clk/rockchip/clk_rk3399.c | 114 --
1 file changed, 108 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/rockchip/clk_rk3399.c
b/drivers/clk/rockchip/clk_rk3399.c
index f778ddf..fab36fa 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -1,5 +1,6 @@
/*
* (C) Copyright 2015 Google, Inc
+ * (C) 2017 Theobroma Systems Design und Consulting GmbH
*
* SPDX-License-Identifier:GPL-2.0
*/
@@ -207,12 +208,15 @@ enum {
DCLK_VOP_DIV_CON_SHIFT = 0,
/* CLKSEL_CON58 */
- CLK_SPI_PLL_SEL_MASK= 1,
- CLK_SPI_PLL_SEL_CPLL= 0,
- CLK_SPI_PLL_SEL_GPLL= 1,
- CLK_SPI_PLL_DIV_CON_MASK= 0x7f,
- CLK_SPI5_PLL_DIV_CON_SHIFT = 8,
- CLK_SPI5_PLL_SEL_SHIFT = 15,
+ CLK_SPI_PLL_SEL_WIDTH = 1,
+ CLK_SPI_PLL_SEL_MASK = ((1 < CLK_SPI_PLL_SEL_WIDTH) - 1),
+ CLK_SPI_PLL_SEL_CPLL = 0,
+ CLK_SPI_PLL_SEL_GPLL = 1,
+ CLK_SPI_PLL_DIV_CON_WIDTH = 7,
+ CLK_SPI_PLL_DIV_CON_MASK = ((1 << CLK_SPI_PLL_DIV_CON_WIDTH) - 1),
+
+ CLK_SPI5_PLL_DIV_CON_SHIFT = 8,
+ CLK_SPI5_PLL_SEL_SHIFT = 15,
/* CLKSEL_CON59 */
CLK_SPI1_PLL_SEL_SHIFT = 15,
@@ -605,6 +609,96 @@ static ulong rk3399_i2c_set_clk(struct rk3399_cru *cru,
ulong clk_id, uint hz)
return DIV_TO_RATE(GPLL_HZ, src_clk_div);
}
+/*
+ * RK3399 SPI clocks have a common divider-width (7 bits) and a single bit
+ * to select either CPLL or GPLL as the clock-parent. The location within
+ * the enclosing CLKSEL_CON (i.e. div_shift and sel_shift) are variable.
+ */
+
+struct spi_clkreg {
+ uint8_t reg; /* CLKSEL_CON[reg] register in CRU */
+ uint8_t div_shift;
+ uint8_t sel_shift;
+};
+
+/*
+ * The entries are numbered relative to their offset from SCLK_SPI0.
+ *
+ * Note that SCLK_SPI3 (which is configured via PMUCRU and requires different
+ * logic is not supported).
+ */
+static const struct spi_clkreg spi_clkregs[] = {
+ [0] = { .reg = 59,
+ .div_shift = CLK_SPI0_PLL_DIV_CON_SHIFT,
+ .sel_shift = CLK_SPI0_PLL_SEL_SHIFT, },
+ [1] = { .reg = 59,
+ .div_shift = CLK_SPI1_PLL_DIV_CON_SHIFT,
+ .sel_shift = CLK_SPI1_PLL_SEL_SHIFT, },
+ [2] = { .reg = 60,
+ .div_shift = CLK_SPI2_PLL_DIV_CON_SHIFT,
+ .sel_shift = CLK_SPI2_PLL_SEL_SHIFT, },
+ [3] = { .reg = 60,
+ .div_shift = CLK_SPI4_PLL_DIV_CON_SHIFT,
+ .sel_shift = CLK_SPI4_PLL_SEL_SHIFT, },
+ [4] = { .reg = 58,
+ .div_shift = CLK_SPI5_PLL_DIV_CON_SHIFT,
+ .sel_shift = CLK_SPI5_PLL_SEL_SHIFT, },
+};
+
+static inline u32 extract_bits(u32 val, unsigned width, unsigned shift)
+{
+ return (val >> shift) & ((1 << width) - 1);
+}
+
+static ulong rk3399_spi_get_clk(struct rk3399_cru *cru, ulong clk_id)
+{
+ const struct spi_clkreg *spiclk = NULL;
+ u32 div, val;
+
+ switch (clk_id) {
+ case SCLK_SPI0 ... SCLK_SPI5:
+ spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
+ break;
+
+ default:
+ error("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
+
[U-Boot] [PATCH v3 3/7] rockchip: spi: rk_spi: select 198MHz input to the SPI module for the RK3399
To provide more (runtime) configuration points for the SPI data rate
at higher speeds (e.g. above 9MHz), we increase the module input rate
to 198MHz (from 99MHz) for the RK3399.
Signed-off-by: Philipp Tomsich
---
Changes in v3:
- increase the module input clock from 99MHz to 198MHz for the RK3399
(added in version 3)
Changes in v2: None
drivers/spi/rk_spi.c | 7 ---
drivers/spi/rk_spi.h | 7 +++
2 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c
index 3e44f17..63cceef 100644
--- a/drivers/spi/rk_spi.c
+++ b/drivers/spi/rk_spi.c
@@ -208,10 +208,11 @@ static int rockchip_spi_probe(struct udevice *bus)
priv->max_freq = plat->frequency;
/*
-* Use 99 MHz as our clock since it divides nicely into 594 MHz which
-* is the assumed speed for CLK_GENERAL.
+* Use 99 MHz (198MHz on the RK3399) as our clock since it
+* divides nicely into 594 MHz which is the assumed speed for
+* CLK_GENERAL.
*/
- ret = clk_set_rate(&priv->clk, 9900);
+ ret = clk_set_rate(&priv->clk, ROCKCHIP_SPI_MOD_CLK);
if (ret < 0) {
debug("%s: Failed to set clock: %d\n", __func__, ret);
return ret;
diff --git a/drivers/spi/rk_spi.h b/drivers/spi/rk_spi.h
index f1ac812..ea262ed 100644
--- a/drivers/spi/rk_spi.h
+++ b/drivers/spi/rk_spi.h
@@ -119,6 +119,13 @@ enum {
};
#define ROCKCHIP_SPI_TIMEOUT_MS1000
+
+#if defined(CONFIG_ROCKCHIP_RK3399)
+#define ROCKCHIP_SPI_MOD_CLK19800
+#define ROCKCHIP_SPI_MAX_RATE 5000
+#else
+#define ROCKCHIP_SPI_MOD_CLK9900
#define ROCKCHIP_SPI_MAX_RATE 4800
+#endif
#endif /* __RK_SPI_H */
--
1.9.1
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[U-Boot] [PATCH v3 6/7] rockchip: spi: enable support for the rk_spi driver for the RK3399
From: Jakob Unterwurzacher
The existing Rockchip SPI (rk_spi.c) driver also matches the hardware
block found in the RK3399. This has been confirmed both with SPI NOR
flashes and general SPI transfers on the RK3399-Q7 for SPI1 and SPI5.
This change adds the 'rockchip,rk3399-spi' string to its compatible
list to allow reuse of the existing driver.
X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich
Tested-by: Jakob Unterwurzacher
---
Changes in v3: None
Changes in v2: None
drivers/spi/rk_spi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c
index d518f9d..35c29b2 100644
--- a/drivers/spi/rk_spi.c
+++ b/drivers/spi/rk_spi.c
@@ -411,6 +411,7 @@ static const struct dm_spi_ops rockchip_spi_ops = {
static const struct udevice_id rockchip_spi_ids[] = {
{ .compatible = "rockchip,rk3288-spi" },
+ { .compatible = "rockchip,rk3399-spi" },
{ }
};
--
1.9.1
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[U-Boot] [PATCH v3 4/7] rockchip: spi: rk_spi: improve clocking code for the RK3399
The original code for the clock clamping did not support going up to
half the module input frequency (even when clocking the module at
99MHz), as a hard limit (of 48MHz) was used for the maximum bitrate.
This rewrites the check to allow frequencies of up to half the SPI
module rate as bitrates and then clamps to whatever the DTS allows
as a maximum (board-specific) frequency.
Signed-off-by: Philipp Tomsich
---
Changes in v3:
- change the top bitrate permissible (without generating a -EINVAL)
from 48MHz/MBit to half the input clockrate (i.e. 49.5MHz/MBit for
a 99MHz module input clock)
Changes in v2: None
drivers/spi/rk_spi.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c
index 63cceef..d518f9d 100644
--- a/drivers/spi/rk_spi.c
+++ b/drivers/spi/rk_spi.c
@@ -372,10 +372,17 @@ static int rockchip_spi_set_speed(struct udevice *bus,
uint speed)
{
struct rockchip_spi_priv *priv = dev_get_priv(bus);
- if (speed > ROCKCHIP_SPI_MAX_RATE)
+ /*
+* The minimum divider configurable is 2, so we can't exceed
+* half the input frequency for the SPI module.
+*/
+ if (speed > (priv->input_rate / 2))
return -EINVAL;
+
+ /* Clamp to the maximum frequency specified in the DTS */
if (speed > priv->max_freq)
speed = priv->max_freq;
+
priv->speed_hz = speed;
return 0;
--
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[U-Boot] [PATCH v3 7/7] rockchip: spl: rk3399: spi: enable SPL_SPI_LOAD if SPI is enabled for SPL
To include the ability to load from an SPI flash in SPL, it's not sufficient to define SPL_SPI_SUPPORT and SPL_SPI_FLASH_SUPPORT via Kconfig... so we conditionally define SPL_SPI_LOAD if SPI support is already enabled for SPL via Kconfig. Signed-off-by: Philipp Tomsich --- Changes in v3: None Changes in v2: None include/configs/rk3399_common.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index 9d22e0c..c409d95 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -18,6 +18,9 @@ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_DRIVERS_MISC_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT +#if defined(CONFIG_SPL_SPI_SUPPORT) +#define CONFIG_SPL_SPI_LOAD +#endif #define COUNTER_FREQUENCY 2400 -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 0/7] rockchip: spl: rk3399: prepare to have SPI config per-board
To support SPI flashes (via the device model) and enable loading of later-stage images from SPI in SPL, we need a few adjustments to the common configuration header for the RK3399: - enable SPL_SPI_LOAD if SPI is enabled for SPL (in rk3399_common) - move CONFIG_SPI and CONFIG_SPI_FLASH (from rk3399_common) to defconfig Changes in v3: - replaced macro-pasting with a lookup table to improve readability (as requested by Simon) - increase the module input clock from 99MHz to 198MHz for the RK3399 (added in version 3) - change the top bitrate permissible (without generating a -EINVAL) from 48MHz/MBit to half the input clockrate (i.e. 49.5MHz/MBit for a 99MHz module input clock) Changes in v2: - fixes a wrong macro usage, which caused the SPI module input clock frequency to be significantly higher than intended - frequencies have now been validated using an oscilloscope (keep in mind that all frequencies are derived from a 99MHz module input clock) at the following measurement points (assuming the other fix for the usage of DIV_RATE from the series): * 1 MHz ... 0.99 MHz * 5 MHz ... 4.95 MHz * 10 MHz ... 9.9 MHz * 30 MHz ... 33MHz * 50 MHz ... 49.5 MHz - fixes an off-by-one for the RK3399 that cause the SPI module input clock to be misstated as 84MHz (even though it was running at 99MHz) Jakob Unterwurzacher (1): rockchip: spi: enable support for the rk_spi driver for the RK3399 Philipp Tomsich (6): rockchip: clk: rk3399: add clock support for SCLK_SPI1 and SCLK_SPI5 rockchip: clk: rk3399: fix off-by one during rate calculation in i2c/spi_set_rate rockchip: spi: rk_spi: select 198MHz input to the SPI module for the RK3399 rockchip: spi: rk_spi: improve clocking code for the RK3399 rockchip: pinctrl: rk3399: add support for the SPI5 controller rockchip: spl: rk3399: spi: enable SPL_SPI_LOAD if SPI is enabled for SPL arch/arm/include/asm/arch-rockchip/grf_rk3399.h | 12 +++ arch/arm/include/asm/arch-rockchip/periph.h | 3 + drivers/clk/rockchip/clk_rk3399.c | 115 ++-- drivers/pinctrl/rockchip/pinctrl_rk3399.c | 17 drivers/spi/rk_spi.c| 17 +++- drivers/spi/rk_spi.h| 7 ++ include/configs/rk3399_common.h | 3 + 7 files changed, 163 insertions(+), 11 deletions(-) -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 3/3] spl: Makefile: include /config in the (reduced) FDT used by the SPL stage
When OF control is enabled for the SPL stage, nodes are removed from the DTB to reduce its size. While /chosen is kept, /config is removed. There's no reason why /chosen should be kept over /config (and as we would like to put properties into /config that control the SPL stage), we add '/config' to the list of nodes to be retained for the SPL stage. Signed-off-by: Philipp Tomsich --- scripts/Makefile.spl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index eb24292..182b300 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -232,7 +232,7 @@ fdtgrep_props := -b u-boot,dm-pre-reloc -b u-boot,dm-spl endif quiet_cmd_fdtgrep = FDTGREP $@ cmd_fdtgrep = $(objtree)/tools/fdtgrep $(fdtgrep_props) -RT $< \ - -n /chosen -O dtb | \ + -n /chosen -n /config -O dtb | \ $(objtree)/tools/fdtgrep -r -O dtb - -o $@ \ $(addprefix -P ,$(subst $\",,$(CONFIG_OF_SPL_REMOVE_PROPS))) -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 2/7] rockchip: clk: rk3399: fix off-by one during rate calculation in i2c/spi_set_rate
For the RK3399, i2c_set_rate (and by extension: our spi_set_rate, which had been mindlessly following the template of the i2c_set_rate implementation) miscalculates the rate returned due to a off-by-one error resulting from the following sequence of events: 1. calculates 'src_div := src_freq / target_freq' 2. stores 'src_div - 1' into the register (the actual divider applied in hardware is biased by adding 1) 3. returns the result of the DIV_RATE(src_freq, src_div) macro, which expects the (decremented) divider from the hardware-register and implictly adds 1 (i.e. 'DIV_RATE(freq, div) := freq / (div + 1)') This can be observed with the SPI driver, which sets a rate of 99MHz based on the GPLL frequency of 594MHz: the hardware generates a clock of 99MHz (src_div is 6, the bitfield in the register correctly reads 5), but reports a frequency of 84MHz (594 / 7) on return. To fix, we have two options: * either we bias (i.e. "DIV_RATE(GPLL, src_div - 1)"), which doesn't make for a particularily nice read * we simply call the i2c/spi_get_rate function (introducing additional overhead for the additional register-read), which reads the divider from the register and then passes it through the DIV_RATE macro Given that this code is not time-critical, the more readable solution (i.e. calling the appropriate get_rate function) is implemented in this change. Signed-off-by: Philipp Tomsich Tested-by: Klaus Goger --- Changes in v3: None Changes in v2: - fixes an off-by-one for the RK3399 that cause the SPI module input clock to be misstated as 84MHz (even though it was running at 99MHz) drivers/clk/rockchip/clk_rk3399.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index fab36fa..5c2d898 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -606,7 +606,7 @@ static ulong rk3399_i2c_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) return -EINVAL; } - return DIV_TO_RATE(GPLL_HZ, src_clk_div); + return rk3399_i2c_get_clk(cru, clk_id); } /* @@ -695,8 +695,7 @@ static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) ((src_clk_div << spiclk->div_shift) | (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift))); - - return DIV_TO_RATE(GPLL_HZ, src_clk_div); + return rk3399_spi_get_clk(cru, clk_id); } static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz) -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 5/7] rockchip: pinctrl: rk3399: add support for the SPI5 controller
This commit adds support for the pin-configuration of the SPI5
controller of the RK3399 through the following changes:
* grf_rk3399.h: adds definition for configuring the SPI5 pins
in the GPIO2C group
* periph.h: defines PERIPH_ID_SPI3 through PERIPH_ID_SPI5
* pinctrl_rk3399.c: adds the reverse-mapping from the IRQ# to
PERIPH_ID_SPI5; dispatches PERIPH_ID_SPI3
through SPI5 to the appropriate pin-config
function; implements the pin-configuration
for PERIPH_ID_SPI5 using the GPIO2C group
X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich
Tested-by: Jakob Unterwurzacher
---
Changes in v3: None
Changes in v2: None
arch/arm/include/asm/arch-rockchip/grf_rk3399.h | 12
arch/arm/include/asm/arch-rockchip/periph.h | 3 +++
drivers/pinctrl/rockchip/pinctrl_rk3399.c | 17 +
3 files changed, 32 insertions(+)
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
index c424753..cbcff2e 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
@@ -344,6 +344,18 @@ enum {
GRF_GPIO2C1_SEL_SHIFT = 2,
GRF_GPIO2C1_SEL_MASK= 3 << GRF_GPIO2C1_SEL_SHIFT,
GRF_UART0BT_SOUT= 1,
+ GRF_GPIO2C4_SEL_SHIFT = 8,
+ GRF_GPIO2C4_SEL_MASK= 3 << GRF_GPIO2C4_SEL_SHIFT,
+ GRF_SPI5EXPPLUS_RXD = 2,
+ GRF_GPIO2C5_SEL_SHIFT = 10,
+ GRF_GPIO2C5_SEL_MASK= 3 << GRF_GPIO2C5_SEL_SHIFT,
+ GRF_SPI5EXPPLUS_TXD = 2,
+ GRF_GPIO2C6_SEL_SHIFT = 12,
+ GRF_GPIO2C6_SEL_MASK= 3 << GRF_GPIO2C6_SEL_SHIFT,
+ GRF_SPI5EXPPLUS_CLK = 2,
+ GRF_GPIO2C7_SEL_SHIFT = 14,
+ GRF_GPIO2C7_SEL_MASK= 3 << GRF_GPIO2C7_SEL_SHIFT,
+ GRF_SPI5EXPPLUS_CSN0= 2,
/* GRF_GPIO3A_IOMUX */
GRF_GPIO3A0_SEL_SHIFT = 0,
diff --git a/arch/arm/include/asm/arch-rockchip/periph.h
b/arch/arm/include/asm/arch-rockchip/periph.h
index 239a274..8018d47 100644
--- a/arch/arm/include/asm/arch-rockchip/periph.h
+++ b/arch/arm/include/asm/arch-rockchip/periph.h
@@ -27,6 +27,9 @@ enum periph_id {
PERIPH_ID_SPI0,
PERIPH_ID_SPI1,
PERIPH_ID_SPI2,
+ PERIPH_ID_SPI3,
+ PERIPH_ID_SPI4,
+ PERIPH_ID_SPI5,
PERIPH_ID_UART0,
PERIPH_ID_UART1,
PERIPH_ID_UART2,
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3399.c
b/drivers/pinctrl/rockchip/pinctrl_rk3399.c
index 507bec4..6eb657f 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3399.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3399.c
@@ -145,7 +145,19 @@ static int pinctrl_rk3399_spi_config(struct
rk3399_grf_regs *grf,
| GRF_SPI2TPM_CLK << GRF_GPIO2B3_SEL_SHIFT
| GRF_SPI2TPM_CSN0 << GRF_GPIO2B4_SEL_SHIFT);
break;
+ case PERIPH_ID_SPI5:
+ if (cs != 0)
+ goto err;
+ rk_clrsetreg(&grf->gpio2c_iomux,
+GRF_GPIO2C4_SEL_MASK | GRF_GPIO2C5_SEL_MASK
+| GRF_GPIO2C6_SEL_MASK | GRF_GPIO2C7_SEL_MASK,
+GRF_SPI5EXPPLUS_RXD << GRF_GPIO2C4_SEL_SHIFT
+| GRF_SPI5EXPPLUS_TXD << GRF_GPIO2C5_SEL_SHIFT
+| GRF_SPI5EXPPLUS_CLK << GRF_GPIO2C6_SEL_SHIFT
+| GRF_SPI5EXPPLUS_CSN0 << GRF_GPIO2C7_SEL_SHIFT);
+ break;
default:
+ printf("%s: spi_id %d is not supported.\n", __func__, spi_id);
goto err;
}
@@ -259,6 +271,9 @@ static int rk3399_pinctrl_request(struct udevice *dev, int
func, int flags)
case PERIPH_ID_SPI0:
case PERIPH_ID_SPI1:
case PERIPH_ID_SPI2:
+ case PERIPH_ID_SPI3:
+ case PERIPH_ID_SPI4:
+ case PERIPH_ID_SPI5:
pinctrl_rk3399_spi_config(priv->grf, priv->pmugrf, func, flags);
break;
case PERIPH_ID_UART0:
@@ -307,6 +322,8 @@ static int rk3399_pinctrl_get_periph_id(struct udevice *dev,
return PERIPH_ID_SPI1;
case 52:
return PERIPH_ID_SPI2;
+ case 132:
+ return PERIPH_ID_SPI5;
case 57:
return PERIPH_ID_I2C0;
case 59: /* Note strange order */
--
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[U-Boot] [PATCH 2/3] doc: document /config/u-boot, spl-payload-offset property
This adds documentation on the u-boot,spl-payload-offset property (which overrides CONFIG_SYS_SPI_U_BOOT_OFFS during the SPI loading in the SPL stage, if present). Signed-off-by: Philipp Tomsich --- doc/device-tree-bindings/config.txt | 5 + 1 file changed, 5 insertions(+) diff --git a/doc/device-tree-bindings/config.txt b/doc/device-tree-bindings/config.txt index 5640bae..d4bc1df 100644 --- a/doc/device-tree-bindings/config.txt +++ b/doc/device-tree-bindings/config.txt @@ -20,3 +20,8 @@ u-boot,efi-partition-entries-offset is formatted. This setting will override any values configured via Kconfig. + +u-boot,spl-payload-offset + If present (and SPL is controlled by the device-tree), this allows + to override the CONFIG_SYS_SPI_U_BOOT_OFFS setting using a value + from the device-tree. -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/3] spl: spi: override CONFIG_SYS_SPI_U_BOOT_OFFS via /config-property
For the RK3399-Q7, we need some flexibility (depending on the feature
set we include in the SPL stage and how large our SPI flash is) in
positioning the SPL payload (i.e. the FIT image containing U-Boot, ATF
and the M0 payload) in our SPI flash.
To avoid having to deal with this through different U-Boot images, we
introduce a the '/config/u-boot,spl-payload-offset' property node
allow it to override the default setting.
Signed-off-by: Philipp Tomsich
---
common/spl/spl_spi.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/common/spl/spl_spi.c b/common/spl/spl_spi.c
index 925a1b1..42880d5 100644
--- a/common/spl/spl_spi.c
+++ b/common/spl/spl_spi.c
@@ -15,6 +15,8 @@
#include
#include
+DECLARE_GLOBAL_DATA_PTR;
+
#ifdef CONFIG_SPL_OS_BOOT
/*
* Load the kernel, check for a valid header we can parse, and if found load
@@ -70,6 +72,7 @@ static int spl_spi_load_image(struct spl_image_info
*spl_image,
struct spl_boot_device *bootdev)
{
int err = 0;
+ unsigned payload_offs = CONFIG_SYS_SPI_U_BOOT_OFFS;
struct spi_flash *flash;
struct image_header *header;
@@ -89,12 +92,18 @@ static int spl_spi_load_image(struct spl_image_info
*spl_image,
/* use CONFIG_SYS_TEXT_BASE as temporary storage area */
header = (struct image_header *)(CONFIG_SYS_TEXT_BASE);
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+ payload_offs = fdtdec_get_config_int(gd->fdt_blob,
+"u-boot,spl-payload-offset",
+payload_offs);
+#endif
+
#ifdef CONFIG_SPL_OS_BOOT
if (spl_start_uboot() || spi_load_image_os(spl_image, flash, header))
#endif
{
/* Load u-boot, mkimage header is 64 bytes. */
- err = spi_flash_read(flash, CONFIG_SYS_SPI_U_BOOT_OFFS, 0x40,
+ err = spi_flash_read(flash, payload_offs, 0x40,
(void *)header);
if (err) {
debug("%s: Failed to read from SPI flash (err=%d)\n",
@@ -113,13 +122,13 @@ static int spl_spi_load_image(struct spl_image_info
*spl_image,
load.bl_len = 1;
load.read = spl_spi_fit_read;
err = spl_load_simple_fit(spl_image, &load,
- CONFIG_SYS_SPI_U_BOOT_OFFS,
+ payload_offs,
header);
} else {
err = spl_parse_image_header(spl_image, header);
if (err)
return err;
- err = spi_flash_read(flash, CONFIG_SYS_SPI_U_BOOT_OFFS,
+ err = spi_flash_read(flash, payload_offs,
spl_image->size,
(void *)spl_image->load_addr);
}
--
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[U-Boot] [PATCH v1 2/8] rockchip: mkimage: rewrite padding calculation for SD/MMC and SPI images
In (first) breaking and (then) fixing the rkspi tool, I realised that
the calculation of the required padding (for the header-size and the
2K-in-every-4K SPI layout) was not as self-explainatory as it could
have been. This change rewrites the code (using new, common functions
in rkcommon.c) and adds verbose in-line comments to ensure that we
won't fall into the same pit in the future...
Tested on the RK3399 (with has a boot0-style payload) with SD/MMC and SPI.
Signed-off-by: Philipp Tomsich
---
tools/rkcommon.c | 20 ++--
tools/rkcommon.h | 10 --
tools/rksd.c | 23 ---
tools/rkspi.c| 41 +++--
4 files changed, 65 insertions(+), 29 deletions(-)
diff --git a/tools/rkcommon.c b/tools/rkcommon.c
index 6cdb749..1311d65 100644
--- a/tools/rkcommon.c
+++ b/tools/rkcommon.c
@@ -199,9 +199,13 @@ void rkcommon_rc4_encode_spl(void *buf, unsigned int
offset, unsigned int size)
}
}
-void rkcommon_vrec_header(struct image_tool_params *params,
- struct image_type_params *tparams)
+int rkcommon_vrec_header(struct image_tool_params *params,
+struct image_type_params *tparams,
+unsigned int alignment)
{
+ unsigned int unpadded_size;
+ unsigned int padded_size;
+
/*
* The SPL image looks as follows:
*
@@ -228,4 +232,16 @@ void rkcommon_vrec_header(struct image_tool_params *params,
tparams->hdr = malloc(tparams->header_size);
memset(tparams->hdr, 0, tparams->header_size);
tparams->header_size = tparams->header_size;
+
+ /*
+* If someone passed in 0 for the alignment, we'd better handle
+* it correctly...
+*/
+ if (!alignment)
+ alignment = 1;
+
+ unpadded_size = tparams->header_size + params->file_size;
+ padded_size = ROUND(unpadded_size, alignment);
+
+ return padded_size - unpadded_size;
}
diff --git a/tools/rkcommon.h b/tools/rkcommon.h
index cc161a6..a21321f 100644
--- a/tools/rkcommon.h
+++ b/tools/rkcommon.h
@@ -83,8 +83,14 @@ void rkcommon_rc4_encode_spl(void *buf, unsigned int offset,
unsigned int size);
* @params: Pointer to the tool params structure
* @tparams:Pointer tot the image type structure (for setting
* the header and header_size)
+ * @alignment: Alignment (a power of two) that the image should be
+ * padded to (e.g. 512 if we want to align with SD/MMC
+ * blocksizes or 2048 for the SPI format)
+ *
+ * @return bytes of padding required/added (does not include the header_size)
*/
-void rkcommon_vrec_header(struct image_tool_params *params,
- struct image_type_params *tparams);
+int rkcommon_vrec_header(struct image_tool_params *params,
+struct image_type_params *tparams,
+unsigned int alignment);
#endif
diff --git a/tools/rksd.c b/tools/rksd.c
index ac8a67d..6dafedf 100644
--- a/tools/rksd.c
+++ b/tools/rksd.c
@@ -29,12 +29,20 @@ static void rksd_set_header(void *buf, struct stat *sbuf,
int ifd,
unsigned int size;
int ret;
+ printf("params->file_size %d\n", params->file_size);
+ printf("params->orig_file_size %d\n", params->orig_file_size);
+
+ /*
+* We need to calculate this using 'RK_SPL_HDR_START' and not using
+* 'tparams->header_size', as the additional byte inserted when
+* 'is_boot0' is true counts towards the payload.
+*/
size = params->file_size - RK_SPL_HDR_START;
ret = rkcommon_set_header(buf, size, params);
if (ret) {
/* TODO(s...@chromium.org): This method should return an error
*/
- printf("Warning: SPL image is too large (size %#x) and will not
boot\n",
- size);
+ printf("Warning: SPL image is too large (size %#x) and will "
+ "not boot\n", size);
}
}
@@ -51,18 +59,11 @@ static int rksd_check_image_type(uint8_t type)
return EXIT_FAILURE;
}
-/* We pad the file out to a fixed size - this method returns that size */
static int rksd_vrec_header(struct image_tool_params *params,
struct image_type_params *tparams)
{
- int pad_size;
-
- rkcommon_vrec_header(params, tparams);
-
- pad_size = RK_SPL_HDR_START + rkcommon_get_spl_size(params);
- debug("pad_size %x\n", pad_size);
-
- return pad_size - params->file_size - tparams->header_size;
+ /* We don't add any additional padding after the end of the image */
+ return rkcommon_vrec_header(params, tparams, 1);
}
/*
diff --git a/tools/rkspi.c b/tools/rkspi.c
index 0a15229..87bd1a9 100644
--- a/tools/rkspi.c
+++ b/tools/rkspi.c
@@ -39,8 +39,8 @@ static void rkspi_set_header(void *buf, struct stat *sbuf,
int ifd,
debug("size %x
[U-Boot] [PATCH v1 0/8] rockchip: mkimage: refactor rksd/rkspi padding calculation and add dumpimage support
We support booting both from SD/MMC images and SPI images on the RK3399-Q7 for different use-cases (e.g. external boot in development from the SD card, internal boot from MMC or SPI depending on whether the SPI flash is populated on any given configuration option). In getting the SPI image support ready for production, we found a few areas that warranted improvements: - we had broken SPI bootstrap earlier in the changes introducting boot0-style images for the RK3399 (this needed fixing) - in fixing the broken SPI padding calculation, it became apparent that it's best to refactor and document things before we make the same mistake again in the future - with both SD/MMC and SPI images being used for various purposes by various people, the wrong image style was inadvertendly used in some tests... so we support for 'dumpimage' (i.e. verify_header and print_header) had to be added to quickly check the image type being handled Note that with the refactored calculation of the image-size, we don't pad the image to the maximum SPL size any longer, but pad SD/MMC to the next 512 byte block (RK_BLK_SIZE) and SPI to the next 2K boundary. Philipp Tomsich (8): rockchip: mkimage: rkspi: include the header sector in the SPI size calculation rockchip: mkimage: rewrite padding calculation for SD/MMC and SPI images rockchip: mkimage: Update comments for header size rockchip: mkimage: rksd: pad SD/MMC images to a full blocksize rockchip: mkimage: clarify header0 initialisation rockchip: mkimage: play nice with dumpimage rockchip: mkimage: remove placeholder functions from rkimage rockchip: mkimage: add support for verify_header/print_header tools/rkcommon.c | 195 ++- tools/rkcommon.h | 29 - tools/rkimage.c | 21 +- tools/rksd.c | 47 +- tools/rkspi.c| 62 +- 5 files changed, 255 insertions(+), 99 deletions(-) -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v1 6/8] rockchip: mkimage: play nice with dumpimage
Dumpimage (it invoked with "-T rkspi" or "-T rksd") would not work due
to check_params failing. These changes ensure that we can both be called
with an empty imagename.
Signed-off-by: Philipp Tomsich
---
tools/rkcommon.c | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/tools/rkcommon.c b/tools/rkcommon.c
index ed29ef9..773e4f6 100644
--- a/tools/rkcommon.c
+++ b/tools/rkcommon.c
@@ -85,6 +85,9 @@ static struct spl_info *rkcommon_get_spl_info(char *imagename)
{
int i;
+ if (!imagename)
+ return NULL;
+
for (i = 0; i < ARRAY_SIZE(spl_infos); i++)
if (!strncmp(imagename, spl_infos[i].imagename, 6))
return spl_infos + i;
@@ -97,17 +100,24 @@ int rkcommon_check_params(struct image_tool_params *params)
int i;
if (rkcommon_get_spl_info(params->imagename) != NULL)
- return 0;
+ return EXIT_SUCCESS;
+
+ /*
+* If this is a operation (list or extract), the don't require
+* imagename to be set.
+*/
+ if (params->lflag || params->iflag)
+ return EXIT_SUCCESS;
fprintf(stderr, "ERROR: imagename (%s) is not supported!\n",
- strlen(params->imagename) > 0 ? params->imagename : "NULL");
+ params->imagename ? params->imagename : "NULL");
fprintf(stderr, "Available imagename:");
for (i = 0; i < ARRAY_SIZE(spl_infos); i++)
fprintf(stderr, "\t%s", spl_infos[i].imagename);
fprintf(stderr, "\n");
- return -1;
+ return EXIT_FAILURE;
}
const char *rkcommon_get_spl_hdr(struct image_tool_params *params)
--
1.9.1
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[U-Boot] [PATCH v1 8/8] rockchip: mkimage: add support for verify_header/print_header
The rockchip image generation was previously missing the ability to
verify the generated header (and dump the image-type) without having
to resort to hexdump or od. Experience in our testing has showed it
to be very easy to get the rkspi and rksd images mixed up and the
lab... so we add the necessary support to have dumpimage tell us
what image type we're dealing with.
This change set adds the verify_header and print_header capability
to the rksd/rkspi image drivers (through shared code in rkcommon).
As of now, we only support images fully that are not RC4-encoded for
the SPL payload (i.e. header1 and payload). For RC4-encoded payloads,
the outer header (header0) is checked, but no detection of whether
this is a SD/MMC or SPI formatted payload takes place.
The output of dumpsys now prints the image type (spl_hdr), whether it
is a SD/MMC or SPI image, and the (padded) size of the image:
$ ./tools/dumpimage -l ./spl.img
Image Type: Rockchip RK33 (SD/MMC) boot image
^^ SD/MMC vs. SPI indication
spl_hdr indicated by the image
Data Size:79872 bytes
Signed-off-by: Philipp Tomsich
---
tools/rkcommon.c | 119 ++-
tools/rkcommon.h | 19 +
tools/rksd.c | 29 +++---
tools/rkspi.c| 21 ++
4 files changed, 146 insertions(+), 42 deletions(-)
diff --git a/tools/rkcommon.c b/tools/rkcommon.c
index 773e4f6..ae414b3 100644
--- a/tools/rkcommon.c
+++ b/tools/rkcommon.c
@@ -2,6 +2,8 @@
* (C) Copyright 2015 Google, Inc
* Written by Simon Glass
*
+ * (C) 2017 Theobroma Systems Design und Consulting GmbH
+ *
* SPDX-License-Identifier:GPL-2.0+
*
* Helper functions for Rockchip images
@@ -200,7 +202,7 @@ int rkcommon_set_header(void *buf, uint file_size,
rkcommon_set_header0(buf, file_size, params);
- /* Set up the SPL name */
+ /* Set up the SPL name (i.e. copy spl_hdr over) */
memcpy(&hdr->magic, rkcommon_get_spl_hdr(params), RK_SPL_HDR_SIZE);
if (rkcommon_need_rc4_spl(params))
@@ -210,6 +212,121 @@ int rkcommon_set_header(void *buf, uint file_size,
return 0;
}
+static inline unsigned rkcommon_offset_to_spi(unsigned offset)
+{
+ /*
+* While SD/MMC images use a flat addressing, SPI images are padded
+* to use the first 2K of every 4K sector only.
+*/
+ return ((offset & ~0x7ff) << 1) + (offset & 0x7ff);
+}
+
+static inline unsigned rkcommon_spi_to_offset(unsigned offset)
+{
+ return ((offset & ~0x7ff) >> 1) + (offset & 0x7ff);
+}
+
+static int rkcommon_parse_header(const void *buf, struct header0_info *header0,
+struct spl_info **spl_info)
+{
+ unsigned hdr1_offset;
+ struct header1_info *hdr1_sdmmc, *hdr1_spi;
+ int i;
+
+ if (spl_info)
+ *spl_info = NULL;
+
+ /*
+* The first header (hdr0) is always RC4 encoded, so try to decrypt
+* with the well-known key.
+*/
+ memcpy((void *)header0, buf, sizeof(struct header0_info));
+ rc4_encode((void *)header0, sizeof(struct header0_info), rc4_key);
+
+ if (header0->signature != RK_SIGNATURE)
+ return -FDT_ERR_BADSTRUCTURE;
+
+ /* We don't support RC4 encoded image payloads here, yet... */
+ if (header0->disable_rc4 == 0)
+ return -ENOSYS;
+
+ hdr1_offset = header0->init_offset * RK_BLK_SIZE;
+ hdr1_sdmmc = (struct header1_info *)(buf + hdr1_offset);
+ hdr1_spi = (struct header1_info *)(buf +
+ rkcommon_offset_to_spi(hdr1_offset));
+
+ for (i = 0; i < ARRAY_SIZE(spl_infos); i++) {
+ if (!memcmp(&hdr1_sdmmc->magic, spl_infos[i].spl_hdr, 4)) {
+ if (spl_info)
+ *spl_info = &spl_infos[i];
+ return IH_TYPE_RKSD;
+ } else if (!memcmp(&hdr1_spi->magic, spl_infos[i].spl_hdr, 4)) {
+ if (spl_info)
+ *spl_info = &spl_infos[i];
+ return IH_TYPE_RKSPI;
+ }
+ }
+
+ return -1;
+}
+
+int rkcommon_verify_header(unsigned char *buf, int size,
+ struct image_tool_params *params)
+{
+ struct header0_info header0;
+ struct spl_info *img_spl_info, *spl_info;
+ int ret;
+
+ ret = rkcommon_parse_header(buf, &header0, &img_spl_info);
+
+ /* If this is the (unimplemented) RC4 case, then rewrite the result */
+ if (ret == -ENOSYS)
+ return 0;
+
+ if (ret < 0)
+ return ret;
+
+ /*
+* If no 'imagename' is specified via the commandline (e.g. if this is
+* 'dumpimage -l' w/o any further constraints), we accept any spl_info.
+*/
+ if (params->imagename == NULL)
+ return 0;
+
+
[U-Boot] [PATCH v1 4/8] rockchip: mkimage: rksd: pad SD/MMC images to a full blocksize
Signed-off-by: Philipp Tomsich
---
tools/rksd.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/tools/rksd.c b/tools/rksd.c
index 6dafedf..8627b6d 100644
--- a/tools/rksd.c
+++ b/tools/rksd.c
@@ -62,8 +62,11 @@ static int rksd_check_image_type(uint8_t type)
static int rksd_vrec_header(struct image_tool_params *params,
struct image_type_params *tparams)
{
- /* We don't add any additional padding after the end of the image */
- return rkcommon_vrec_header(params, tparams, 1);
+ /*
+* Pad to the RK_BLK_SIZE (512 bytes) to be consistent with init_size
+* being encoded in RK_BLK_SIZE units in header0 (see rkcommon.c).
+*/
+ return rkcommon_vrec_header(params, tparams, RK_BLK_SIZE);
}
/*
--
1.9.1
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[U-Boot] [PATCH v1 3/8] rockchip: mkimage: Update comments for header size
The calculation of the variable header size in rkcommon_vrec_header
had been update twice in the earlier series (introducing boot0-style
images to deal with the alignment of the first instruction in 64bit
binaries). Unfortunately, I didn't update the comment twice (so it
remained out-of-date).
This change brings the comment back in-sync with what the code is
doing.
Signed-off-by: Philipp Tomsich
---
tools/rkcommon.c | 22 +-
1 file changed, 13 insertions(+), 9 deletions(-)
diff --git a/tools/rkcommon.c b/tools/rkcommon.c
index 1311d65..cfd40ac 100644
--- a/tools/rkcommon.c
+++ b/tools/rkcommon.c
@@ -176,7 +176,7 @@ int rkcommon_set_header(void *buf, uint file_size,
rkcommon_set_header0(buf, file_size, params);
- /* Set up the SPL name and add the AArch64 'nop' padding, if needed */
+ /* Set up the SPL name */
memcpy(&hdr->magic, rkcommon_get_spl_hdr(params), RK_SPL_HDR_SIZE);
if (rkcommon_need_rc4_spl(params))
@@ -211,17 +211,21 @@ int rkcommon_vrec_header(struct image_tool_params *params,
*
* 0x0header0 (see rkcommon.c)
* 0x800 spl_name ('RK30', ..., 'RK33')
+*(start of the payload for AArch64 payloads: we expect the
+*first 4 bytes to be available for overwriting with our
+*spl_name)
* 0x804 first instruction to be executed
-*(image start for AArch32, 'nop' for AArch64))
-* 0x808 second instruction to be executed
-*(image start for AArch64)
+*(start of the image/payload for 32bit payloads)
*
-* For AArch64 (ARMv8) payloads, we receive an input file that
-* needs to start on an 8-byte boundary (natural alignment), so
-* we need to put a NOP at 0x804.
+* For AArch64 (ARMv8) payloads, natural alignment (8-bytes) is
+* required for its sections (so the image we receive needs to
+* have the first 4 bytes reserved for the spl_name). Reserving
+* these 4 bytes is done using the BOOT0_HOOK infrastructure.
*
-* Depending on this, the header is either 0x804 or 0x808 bytes
-* in length.
+* Depending on this, the header is either 0x800 (if this is a
+* 'boot0'-style payload, which has reserved 4 bytes at the
+* beginning for the 'spl_name' and expects us to overwrite
+* its first 4 bytes) or 0x804 bytes in length.
*/
if (rkcommon_spl_is_boot0(params))
tparams->header_size = RK_SPL_HDR_START;
--
1.9.1
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[U-Boot] [PATCH v1 5/8] rockchip: mkimage: clarify header0 initialisation
This change set adds documentation to the header0 initialisation and
improves readability for the calculations of various offsets/lengths.
As the U-Boot SPL stage doesn't use any payload beyond what is covered
by init_size, we no longer add RK_MAX_BOOT_SIZE to init_boot_size.
Signed-off-by: Philipp Tomsich
---
tools/rkcommon.c | 20 +---
1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/tools/rkcommon.c b/tools/rkcommon.c
index cfd40ac..ed29ef9 100644
--- a/tools/rkcommon.c
+++ b/tools/rkcommon.c
@@ -13,6 +13,8 @@
#include "mkimage.h"
#include "rkcommon.h"
+#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
+
enum {
RK_SIGNATURE= 0x0ff0aa55,
};
@@ -159,9 +161,21 @@ static void rkcommon_set_header0(void *buf, uint file_size,
hdr->disable_rc4 = !rkcommon_need_rc4_spl(params);
hdr->init_offset = RK_INIT_OFFSET;
- hdr->init_size = (file_size + RK_BLK_SIZE - 1) / RK_BLK_SIZE;
- hdr->init_size = (hdr->init_size + 3) & ~3;
- hdr->init_boot_size = hdr->init_size + RK_MAX_BOOT_SIZE / RK_BLK_SIZE;
+ hdr->init_size = DIV_ROUND_UP(file_size, RK_BLK_SIZE);
+ /*
+* The init_size has to be a multiple of 4 blocks (i.e. of 2K)
+* or the BootROM will not boot the image.
+*
+* Note: To verify that this is not a legacy constraint, we
+* rechecked this against the RK3399 BootROM.
+*/
+ hdr->init_size = ROUND(hdr->init_size, 4);
+ /*
+* The images we create do not contain the stage following the SPL as
+* part of the SPL image, so the init_boot_size (which might have been
+* read by Rockchip's miniloder) should be the same as the init_size.
+*/
+ hdr->init_boot_size = hdr->init_size;
rc4_encode(buf, RK_BLK_SIZE, rc4_key);
}
--
1.9.1
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[U-Boot] [PATCH v1 1/8] rockchip: mkimage: rkspi: include the header sector in the SPI size calculation
Our earlier change broke the generation of SPI images, by excluding the
2K used for header0 from the size-calculation.
This commit makes sure that these are included before calculating the
required total size (including the padding from the 2K-from-every-4K
conversion).
Signed-off-by: Philipp Tomsich
---
tools/rkspi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tools/rkspi.c b/tools/rkspi.c
index d2d3fdd..0a15229 100644
--- a/tools/rkspi.c
+++ b/tools/rkspi.c
@@ -79,12 +79,12 @@ static int rkspi_vrec_header(struct image_tool_params
*params,
rkcommon_vrec_header(params, tparams);
- pad_size = (rkcommon_get_spl_size(params) + 0x7ff) / 0x800 * 0x800;
+ pad_size = ROUND(rkcommon_get_spl_size(params), 0x800);
params->orig_file_size = pad_size;
/* We will double the image size due to the SPI format */
- pad_size *= 2;
pad_size += RK_SPL_HDR_START;
+ pad_size *= 2;
debug("pad_size %x\n", pad_size);
return pad_size - params->file_size - tparams->header_size;
--
1.9.1
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[U-Boot] [PATCH v1 0/2] rockchip: dts: rk3399-puma: Update to use DDR3-1600 timings
With our validation having progresses to the point of tuning the DRAM interface, we can now use a DDR3-1600 timing (i.e. 800MHz base clock) as the default for the RK3399-Q7 (Puma). This series - adds a DDR3-1600 timing for the RK3399-Q7 - switches the RK3399-Q7 over to use this new timing - cleans up some graffiti (i.e. unwanted source edits) from the DDR3-1333 timing we had submitted earlier Philipp Tomsich (2): rockchip: dts: Clean up graffiti in rk3399-sdram-ddr3-1333.dtsi rockchip: dts: rk3399-puma: Add DDR3-1600 timings and use for Puma arch/arm/dts/rk3399-puma.dts |6 +- arch/arm/dts/rk3399-sdram-ddr3-1333.dtsi |8 +- arch/arm/dts/rk3399-sdram-ddr3-1600.dtsi | 1537 ++ 3 files changed, 1546 insertions(+), 5 deletions(-) create mode 100644 arch/arm/dts/rk3399-sdram-ddr3-1600.dtsi -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v1 1/2] rockchip: dts: Clean up graffiti in rk3399-sdram-ddr3-1333.dtsi
The DDR3-1333 timings for the RK3399-Q7 (Puma) has some unintended left-over comments in them. This change cleans the file up. Signed-off-by: Philipp Tomsich --- arch/arm/dts/rk3399-sdram-ddr3-1333.dtsi | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/rk3399-sdram-ddr3-1333.dtsi b/arch/arm/dts/rk3399-sdram-ddr3-1333.dtsi index bed236d..f032eec 100644 --- a/arch/arm/dts/rk3399-sdram-ddr3-1333.dtsi +++ b/arch/arm/dts/rk3399-sdram-ddr3-1333.dtsi @@ -39,22 +39,22 @@ 666 3 2 -/* 13 */ 9 + 9 1 0x0600 0x 0x 0x 0x -/* 0xaae60 */ 7 + 0x0007 0x 0x 0x -/* 0xaae60 */ 7 + 0x0007 0x 0x 0x -/* 0xaae60 */ 7 + 0x0007 0x 0x 0x0100 -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v1 7/8] rockchip: mkimage: remove placeholder functions from rkimage
The imagetool framework checks whether function pointer for the verify,
print and extract actions are available and will will handle their
absence appropriately.
This change removes the unnecessary functions and uses the driver
structure to convey available functionality to imagetool. This is in
fact better than having verify just return 0 (which previously broke
dumpimage, as dumpimage assumed that we had handled the image and did
not continue to probe further).
Signed-off-by: Philipp Tomsich
---
tools/rkimage.c | 21 +++--
1 file changed, 3 insertions(+), 18 deletions(-)
diff --git a/tools/rkimage.c b/tools/rkimage.c
index 44d098c..9880b15 100644
--- a/tools/rkimage.c
+++ b/tools/rkimage.c
@@ -13,16 +13,6 @@
static uint32_t header;
-static int rkimage_verify_header(unsigned char *buf, int size,
-struct image_tool_params *params)
-{
- return 0;
-}
-
-static void rkimage_print_header(const void *buf)
-{
-}
-
static void rkimage_set_header(void *buf, struct stat *sbuf, int ifd,
struct image_tool_params *params)
{
@@ -33,11 +23,6 @@ static void rkimage_set_header(void *buf, struct stat *sbuf,
int ifd,
rkcommon_rc4_encode_spl(buf, 4, params->file_size);
}
-static int rkimage_extract_subimage(void *buf, struct image_tool_params
*params)
-{
- return 0;
-}
-
static int rkimage_check_image_type(uint8_t type)
{
if (type == IH_TYPE_RKIMAGE)
@@ -55,10 +40,10 @@ U_BOOT_IMAGE_TYPE(
4,
&header,
rkcommon_check_params,
- rkimage_verify_header,
- rkimage_print_header,
+ NULL,
+ NULL,
rkimage_set_header,
- rkimage_extract_subimage,
+ NULL,
rkimage_check_image_type,
NULL,
NULL
--
1.9.1
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[U-Boot] [PATCH v1 2/2] rockchip: dts: rk3399-puma: Add DDR3-1600 timings and use for Puma
With the validation done for DDR3-1600 (i.e. 800 MHz bus clock), we
add the timings (rk3399-sdram-ddr3-1600.dtsi) and change rk3399-puma.dts
to use these by default.
Signed-off-by: Philipp Tomsich
---
arch/arm/dts/rk3399-puma.dts |6 +-
arch/arm/dts/rk3399-sdram-ddr3-1600.dtsi | 1537 ++
2 files changed, 1542 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/rk3399-sdram-ddr3-1600.dtsi
diff --git a/arch/arm/dts/rk3399-puma.dts b/arch/arm/dts/rk3399-puma.dts
index 301cc16..312d70e 100644
--- a/arch/arm/dts/rk3399-puma.dts
+++ b/arch/arm/dts/rk3399-puma.dts
@@ -7,12 +7,16 @@
/dts-v1/;
#include
#include "rk3399.dtsi"
-#include "rk3399-sdram-ddr3-1333.dtsi"
+#include "rk3399-sdram-ddr3-1600.dtsi"
/ {
model = "Theobroma Systems RK3399-Q7 SoM";
compatible = "tsd,puma", "rockchip,rk3399";
+ config {
+ u-boot,spl-payload-offset = <204800>;
+ };
+
chosen {
stdout-path = "serial0:115200n8";
u-boot,spl-boot-order = &spiflash, &sdhci, &sdmmc;
diff --git a/arch/arm/dts/rk3399-sdram-ddr3-1600.dtsi
b/arch/arm/dts/rk3399-sdram-ddr3-1600.dtsi
new file mode 100644
index 000..06e04e3
--- /dev/null
+++ b/arch/arm/dts/rk3399-sdram-ddr3-1600.dtsi
@@ -0,0 +1,1537 @@
+/*
+ * (C) 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+&dmc {
+rockchip,sdram-params = <
+ 0x1
+ 0xa
+ 0x3
+ 0x2
+ 0x1
+ 0x0
+ 0xf
+ 0xf
+ 1
+ 0x80151015
+ 0x14040902
+ 0x0002
+ 0x6346
+ 0x004c
+ 0x
+ 0x1
+ 0xa
+ 0x3
+ 0x2
+ 0x1
+ 0x0
+ 0xf
+ 0xf
+ 1
+ 0x80151015
+ 0x14040902
+ 0x0002
+ 0x6346
+ 0x004c
+ 0x
+ 800
+ 3
+ 2
+ 9
+ 1
+ 0x0600
+ 0x
+ 0x
+ 0x
+ 0x
+ 0x0008
+ 0x
+ 0x
+ 0x
+ 0x0008
+ 0x
+ 0x
+ 0x
+ 0x0008
+ 0x
+ 0x
+ 0x0100
+ 0x
+ 0x0101
+ 0x00020100
+ 0x00027100
+ 0x00061a80
+ 0x02000200
+ 0x08160200
+ 0x00081600
+ 0x04000816
+ 0x26050004
+ 0x1c0b061c
+ 0x1c260500
+ 0x001c0b06
+ 0x061c2605
+ 0x06001c0b
+ 0x0c04
+ 0x0400db60
+ 0x0c040605
+ 0x0400db60
+ 0x0c040605
+ 0x0400db60
+ 0x02030005
+ 0x0b0c0b00
+ 0x000c0b0c
+ 0x14000a0a
+ 0x0a0a
+ 0x0001
+ 0x03171717
+ 0x000b0b0b
+ 0x
+ 0x0301
+ 0x18580118
+ 0x18580118
+ 0x18580118
+ 0x
+ 0x00050005
+ 0x00140005
+ 0x00140014
+ 0x
+ 0x
+ 0x
+ 0x
+ 0x0200
+ 0x02000120
+ 0x02000120
+ 0x0120
+ 0x
+ 0x
+ 0x
+ 0x
+ 0x
+ 0x
+ 0x0301
+ 0x0001
+ 0x
+ 0x
+ 0x0100
+ 0x80104002
+ 0x00040003
+ 0x00040005
+ 0x0003
+ 0x00050004
+ 0x0004
+ 0x00040003
+ 0x00040005
+ 0x6160
+ 0x30b0
+ 0x30b06160
+ 0x6160
+ 0x30b0
+ 0x
+ 0x
+ 0x
+ 0x
+ 0x
+ 0x08080800
+ 0x00080808
+ 0x00030200
+ 0x00040700
+ 0x0302
+ 0x02000407
+ 0x0003
+ 0x00030f04
+ 0x00070004
+ 0x
[U-Boot] [PATCH] ehci-ppc4xx: Prepare for usage of readl()/writel() accessors
We used to have opencoded ehci_readl()/writel() which required no external functions to be called. Now with attempt to switch to generic readl()/writel() accessors we see a missing declaration of those accessors in ehci-ppc4xx. Something like that happens if applied http://patchwork.ozlabs.org/patch/726714/: >8--- CC drivers/usb/host/ehci-ppc4xx.o drivers/usb/host/ehci-ppc4xx.c: In function 'ehci_hcd_init': drivers/usb/host/ehci-ppc4xx.c:23:3: warning: implicit declaration of function 'readl' [-Wimplicit-function-declaration] HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); ^ >8--- Signed-off-by: Alexey Brodkin Cc: Tom Rini Cc: Marek Vasut Cc: Stefan Roese --- drivers/usb/host/ehci-ppc4xx.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/usb/host/ehci-ppc4xx.c b/drivers/usb/host/ehci-ppc4xx.c index 9aee3ff786cb..9d235776428e 100644 --- a/drivers/usb/host/ehci-ppc4xx.c +++ b/drivers/usb/host/ehci-ppc4xx.c @@ -8,6 +8,7 @@ */ #include #include +#include #include "ehci.h" -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] board: dra71: Fix selection of OPPs
On Sun, Apr 16, 2017 at 10:13:55AM +0530, Lokesh Vutla wrote: > As per the DM[1] Dated June 2016–Revised February 2017, Table 5-3, > DRA71 supports the following OPPs for various voltage domains: > > VDD_MPU: OPP_NOM > VDD_CORE: OPP_NOM > VDD_GPU: OPP_NOM > VDD_DSPEVE: OPP_NOM, OPP_HIGH > VDD_IVA: OPP_NOM, OPP_HIGH > > This patch add support for selection of the above OPPs instead of > using OPP_NOM for all voltage domains. > > [1] http://www.ti.com/lit/ds/symlink/dra718.pdf > > Reported-by: Vishal Mahaveer > Signed-off-by: Lokesh Vutla Reviewed-by: Tom Rini -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] configs: keystone2: Standardise U-boot prompt
On Sun, Apr 16, 2017 at 11:21:28AM +0530, Lokesh Vutla wrote: > Standardise U-Boot prompt on all keystone2 platforms > instead of platform specific prompt. > > Signed-off-by: Lokesh Vutla Reviewed-by: Tom Rini -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] drivers/usb/ehci: Use platform-specific accessors
Hi Tom, Marek, On Fri, 2017-04-14 at 16:06 -0400, Tom Rini wrote: > On Fri, Apr 14, 2017 at 05:16:11PM +, Alexey Brodkin wrote: > > > > Hi Marek, > > > > On Fri, 2017-04-14 at 16:44 +0200, Marek Vasut wrote: > > > > > > On 03/24/2017 01:56 PM, Marek Vasut wrote: > > > > > > > > > > > Even better, this patch breaks powerpc board lwmon5, so dropped. > > > > Are you sure the problem is in my patch? > > Yes, it is. Dropping this from the USB PR gets everything going again. Ok the problem was obvious missing inclusion f "asm/io.h". Fix is submitted here http://patchwork.ozlabs.org/patch/751397/ Please consider for applying. > > Maybe this PPC board just needs to UNdefine > > CONFIG_EHCI_DESC_BIG_ENDIAN or there's a problem in its either > > cpu_to_XXX() or readl()/writel()? > > > > Stefan, could you please look at what's wrong here > > if you have the board handy? > > Well, since this is your set of changes, you should have some idea > what's right/wrong here given what things are before/after. Also, for > wide changes like this, please give things a build either in travis-ci > (so that most of the world is built) or do most of the world locally > before posting, thanks! Well I tried to run a buildman locally (thanks to machine resources I have) but out of 1243 boards 154 have fatal problems if I use toolchains obtained via buildbot. Which is barely useful for capturing issues introduced by incremental patches :( -Alexey ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] drivers/usb/ehci: Use platform-specific accessors
On Mon, Apr 17, 2017 at 04:19:17PM +, Alexey Brodkin wrote: > Hi Tom, Marek, > > On Fri, 2017-04-14 at 16:06 -0400, Tom Rini wrote: > > On Fri, Apr 14, 2017 at 05:16:11PM +, Alexey Brodkin wrote: > > > > > > Hi Marek, > > > > > > On Fri, 2017-04-14 at 16:44 +0200, Marek Vasut wrote: > > > > > > > > On 03/24/2017 01:56 PM, Marek Vasut wrote: > > > > > > > > > > > > > > Even better, this patch breaks powerpc board lwmon5, so dropped. > > > > > > Are you sure the problem is in my patch? > > > > Yes, it is. Dropping this from the USB PR gets everything going again. > > Ok the problem was obvious missing inclusion f "asm/io.h". > Fix is submitted here http://patchwork.ozlabs.org/patch/751397/ > > Please consider for applying. Thanks. > > > Maybe this PPC board just needs to UNdefine > > > CONFIG_EHCI_DESC_BIG_ENDIAN or there's a problem in its either > > > cpu_to_XXX() or readl()/writel()? > > > > > > Stefan, could you please look at what's wrong here > > > if you have the board handy? > > > > Well, since this is your set of changes, you should have some idea > > what's right/wrong here given what things are before/after. Also, for > > wide changes like this, please give things a build either in travis-ci > > (so that most of the world is built) or do most of the world locally > > before posting, thanks! > > Well I tried to run a buildman locally (thanks to machine resources I have) > but out of 1243 boards 154 have fatal problems if I use toolchains obtained > via buildbot. Which is barely useful for capturing issues introduced by > incremental patches :( Did you mean buildman? If you look at .travis.yml that builds all of those boards (well, with the exception of some we need gcc-6 in order to have small enough binaries for) and that's pretty close to 1200 I think. -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 02/14] sysreset: add syscon-reboot driver
Hi Simon,
El 16/04/2017 a las 21:34, Simon Glass escribió:
> Hi Alvaro,
>
> On 15 April 2017 at 16:03, Álvaro Fernández Rojas wrote:
>> Add a new sysreset driver based on linux/drivers/power/reset/syscon-reboot.c,
>> which provides a generic driver for platforms that only require writing a
>> mask
>> to a regmap offset.
>>
>> Signed-off-by: Álvaro Fernández Rojas
>> ---
>> v2: no changes
>>
>> drivers/sysreset/Kconfig | 8 +
>> drivers/sysreset/Makefile | 1 +
>> drivers/sysreset/sysreset_syscon.c | 60
>> ++
>> 3 files changed, 69 insertions(+)
>> create mode 100644 drivers/sysreset/sysreset_syscon.c
>>
>> diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
>> index 05a37b9..0946c9d 100644
>> --- a/drivers/sysreset/Kconfig
>> +++ b/drivers/sysreset/Kconfig
>> @@ -13,4 +13,12 @@ config SYSRESET
>> to effect a reset. The uclass will try all available drivers when
>> reset_walk() is called.
>>
>> +config SYSRESET_SYSCON
>> + bool "Enable support for mfd syscon reboot driver"
>> + depends on SYSRESET
>> + select REGMAP
>> + select SYSCON
>> + help
>> + Description here.
>
> Yes please!
Sure, my fault :P
>
>> +
>> endmenu
>> diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
>> index 49b8bb6..1205f47 100644
>> --- a/drivers/sysreset/Makefile
>> +++ b/drivers/sysreset/Makefile
>> @@ -18,3 +18,4 @@ obj-$(CONFIG_ARCH_SNAPDRAGON) += sysreset_snapdragon.o
>> obj-$(CONFIG_ARCH_STI) += sysreset_sti.o
>> obj-$(CONFIG_TARGET_XTFPGA) += sysreset_xtfpga.o
>> obj-$(CONFIG_ARCH_ASPEED) += sysreset_ast.o
>> +obj-$(CONFIG_SYSRESET_SYSCON) += sysreset_syscon.o
>> diff --git a/drivers/sysreset/sysreset_syscon.c
>> b/drivers/sysreset/sysreset_syscon.c
>> new file mode 100644
>> index 000..61aeb1d
>> --- /dev/null
>> +++ b/drivers/sysreset/sysreset_syscon.c
>> @@ -0,0 +1,60 @@
>> +/*
>> + * Copyright (C) 2017 Álvaro Fernández Rojas
>> + *
>> + * Derived from linux/drivers/power/reset/syscon-reboot.c:
>> + * Copyright (C) 2013, Applied Micro Circuits Corporation
>> + * Author: Feng Kan
>> + *
>> + * SPDX-License-Identifier:GPL-2.0+
>> + */
>> +
>> +#include
>> +#include
>> +#include
>> +#include
>
> this should go at the end
I will fix it.
>
>> +#include
>> +#include
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +static int syscon_reboot_request(struct udevice *dev, enum sysreset_t type)
>> +{
>> + struct udevice *syscon;
>> + struct regmap *regmap;
>> + unsigned int offset, mask;
>> + int err;
>> +
>> + err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
>> + "regmap", &syscon);
>> + if (err) {
>> + error("unable to find syscon device\n");
>> + return err;
>> + }
>> +
>> + regmap = syscon_get_regmap(syscon);
>> + if (!regmap) {
>> + error("unable to find regmap\n");
>> + return -ENODEV;
>> + }
>> +
>> + offset = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev), "offset",
>> 0);
>> + mask = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev), "mask", 0);
>
> You should do this in ofdata_to_platdata() or probe() and store it in
> a local struct
I tried doing it in probe:
https://github.com/Noltari/u-boot/commit/37f45960f240c3e57fa70afe69d9b5782c9e6f9f
However it looks like probe is never called with my current U_BOOT_DRIVER
settings...
Then I tried doing it in bind instead of probe and it looks like the syscon
device isn't ready when syscon-reboot is binded...
Any ideas? :$
>
>
>> +
>> + return regmap_write(regmap, offset, mask);
>
> Check error here, and either return -EINPROGRESS or some other error
I will, but regmap_write returns always 0, so there's no error at all to
check...
>
>> +}
>> +
>> +static struct sysreset_ops syscon_reboot_ops = {
>> + .request= syscon_reboot_request,
>> +};
>> +
>> +static const struct udevice_id syscon_reboot_ids[] = {
>> + { .compatible = "syscon-reboot" },
>> + { /* sentinel */ }
>> +};
>> +
>> +U_BOOT_DRIVER(syscon_reboot) = {
>> + .name = "syscon_reboot",
>> + .id = UCLASS_SYSRESET,
>> + .of_match = syscon_reboot_ids,
>> + .ops= &syscon_reboot_ops,
>> +};
>> --
>> 2.1.4
>>
>
> Regards,
> Simon
>
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Re: [U-Boot] [PATCH v2 02/14] sysreset: add syscon-reboot driver
Hi Alvaro,
On 17 April 2017 at 11:38, Álvaro Fernández Rojas wrote:
>
> Hi Simon,
>
> El 16/04/2017 a las 21:34, Simon Glass escribió:
> > Hi Alvaro,
> >
> > On 15 April 2017 at 16:03, Álvaro Fernández Rojas wrote:
> >> Add a new sysreset driver based on
> >> linux/drivers/power/reset/syscon-reboot.c,
> >> which provides a generic driver for platforms that only require writing a
> >> mask
> >> to a regmap offset.
> >>
> >> Signed-off-by: Álvaro Fernández Rojas
> >> ---
> >> v2: no changes
> >>
> >> drivers/sysreset/Kconfig | 8 +
> >> drivers/sysreset/Makefile | 1 +
> >> drivers/sysreset/sysreset_syscon.c | 60
> >> ++
> >> 3 files changed, 69 insertions(+)
> >> create mode 100644 drivers/sysreset/sysreset_syscon.c
> >>
> >> diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
> >> index 05a37b9..0946c9d 100644
> >> --- a/drivers/sysreset/Kconfig
> >> +++ b/drivers/sysreset/Kconfig
> >> @@ -13,4 +13,12 @@ config SYSRESET
> >> to effect a reset. The uclass will try all available drivers when
> >> reset_walk() is called.
> >>
> >> +config SYSRESET_SYSCON
> >> + bool "Enable support for mfd syscon reboot driver"
> >> + depends on SYSRESET
> >> + select REGMAP
> >> + select SYSCON
> >> + help
> >> + Description here.
> >
> > Yes please!
> Sure, my fault :P
>
> >
> >> +
> >> endmenu
> >> diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
> >> index 49b8bb6..1205f47 100644
> >> --- a/drivers/sysreset/Makefile
> >> +++ b/drivers/sysreset/Makefile
> >> @@ -18,3 +18,4 @@ obj-$(CONFIG_ARCH_SNAPDRAGON) += sysreset_snapdragon.o
> >> obj-$(CONFIG_ARCH_STI) += sysreset_sti.o
> >> obj-$(CONFIG_TARGET_XTFPGA) += sysreset_xtfpga.o
> >> obj-$(CONFIG_ARCH_ASPEED) += sysreset_ast.o
> >> +obj-$(CONFIG_SYSRESET_SYSCON) += sysreset_syscon.o
> >> diff --git a/drivers/sysreset/sysreset_syscon.c
> >> b/drivers/sysreset/sysreset_syscon.c
> >> new file mode 100644
> >> index 000..61aeb1d
> >> --- /dev/null
> >> +++ b/drivers/sysreset/sysreset_syscon.c
> >> @@ -0,0 +1,60 @@
> >> +/*
> >> + * Copyright (C) 2017 Álvaro Fernández Rojas
> >> + *
> >> + * Derived from linux/drivers/power/reset/syscon-reboot.c:
> >> + * Copyright (C) 2013, Applied Micro Circuits Corporation
> >> + * Author: Feng Kan
> >> + *
> >> + * SPDX-License-Identifier:GPL-2.0+
> >> + */
> >> +
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >
> > this should go at the end
> I will fix it.
>
> >
> >> +#include
> >> +#include
> >> +
> >> +DECLARE_GLOBAL_DATA_PTR;
> >> +
> >> +static int syscon_reboot_request(struct udevice *dev, enum sysreset_t
> >> type)
> >> +{
> >> + struct udevice *syscon;
> >> + struct regmap *regmap;
> >> + unsigned int offset, mask;
> >> + int err;
> >> +
> >> + err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
> >> + "regmap", &syscon);
> >> + if (err) {
> >> + error("unable to find syscon device\n");
> >> + return err;
> >> + }
> >> +
> >> + regmap = syscon_get_regmap(syscon);
> >> + if (!regmap) {
> >> + error("unable to find regmap\n");
> >> + return -ENODEV;
> >> + }
> >> +
> >> + offset = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
> >> "offset", 0);
> >> + mask = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev), "mask",
> >> 0);
> >
> > You should do this in ofdata_to_platdata() or probe() and store it in
> > a local struct
> I tried doing it in probe:
> https://github.com/Noltari/u-boot/commit/37f45960f240c3e57fa70afe69d9b5782c9e6f9f
>
> However it looks like probe is never called with my current U_BOOT_DRIVER
> settings...
That is bad - you should figure out why. The
uclass_get_device_by_phandle() should call probe().
> Then I tried doing it in bind instead of probe and it looks like the syscon
> device isn't ready when syscon-reboot is binded...
> Any ideas? :$
Figure out why probe() doesn't happen.
>
> >
> >
> >> +
> >> + return regmap_write(regmap, offset, mask);
> >
> > Check error here, and either return -EINPROGRESS or some other error
> I will, but regmap_write returns always 0, so there's no error at all to
> check...
That's fine - you can return -EINPROGRESS if it returns 0, and the
error otherwise. Also please add function docs for regmap_read/write()
while you are there.
>
> >
> >> +}
> >> +
> >> +static struct sysreset_ops syscon_reboot_ops = {
> >> + .request= syscon_reboot_request,
> >> +};
> >> +
> >> +static const struct udevice_id syscon_reboot_ids[] = {
> >> + { .compatible = "syscon-reboot" },
> >> + { /* sentinel */ }
> >> +};
> >> +
> >> +U_BOOT_DRIVER(syscon_reboot) = {
> >> + .name = "syscon_reboot",
> >> + .id = UCLASS_SYSRESET,
> >> + .of_match = sysco
[U-Boot] [PATCH v1 00/15] Expand Aspeed AST2500 Support
This series expands support for Aspeed AST2500 SoC, commonly used as Board Management Controller in many servers. The main goal of this series is I2C driver, the rest are either cleanups or supporting patches. Most notable among them is addition of Watchdog uclass, so that watchdog drivers can now use Driver Model. One notable thing that is *missing* from this series is Device Tree configuration for I2C driver. The Linux Kernel I2C driver is still under review and it may affect the details of how devices need to be configured in the Device Tree. So, I decided to wait until it will show up in Linux Kernel DT and then pull it into U-Boot. I removed Network driver from this series. I will work on it separately and will make it compatible with existing Faraday devices, but that is a work better done outside of this already long series. Changes in v1: - Added link to the original version to commit message - Rename wdt_reset to wdt_expire_now - Rename wdt_restart to wdt_reset - Clarified function documentation in few cases - Add Sandbox WDT driver and unit tests - Rename reset to expire_now - Rename restart to reset - Remove unnecessary check for error in dev_get_priv - Fix comment - Rename wdt_reset call to wdt_expire_now - Rename wdt_reset call to wdt_expire_now - Style fixes Maxim Sloyko (15): aspeed: Update ast2500 Device Tree dm: Simple Watchdog uclass aspeed: Watchdog Timer Driver aspeed: Make SCU lock/unlock functions part of SCU API aspeed: Reset Driver aspeed: Device Tree configuration for Reset Driver aspeed: Refactor AST2500 RAM Driver and Sysreset Driver aspeed: AST2500 Pinctrl Driver aspeed: Enable Pinctrl Driver in AST2500 EVB aspeed: Add P-Bus clock in ast2500 clock driver aspeed: Add I2C Driver aspeed: Enable I2C in EVB defconfig aspeed: Add support for Clocks needed by MACs aspeed: Refactor SCU to use consistent mask & shift aspeed: Cleanup ast2500-u-boot.dtsi Device Tree arch/arm/dts/ast2500-evb.dts | 15 + arch/arm/dts/ast2500-u-boot.dtsi | 59 +- arch/arm/dts/ast2500.dtsi | 881 - arch/arm/include/asm/arch-aspeed/pinctrl.h | 52 ++ arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 132 +++- arch/arm/include/asm/arch-aspeed/wdt.h | 38 +- arch/arm/mach-aspeed/Kconfig | 8 +- arch/arm/mach-aspeed/ast2500/clk_ast2500.c | 15 + arch/arm/mach-aspeed/ast2500/sdram_ast2500.c | 17 +- arch/arm/mach-aspeed/ast_wdt.c | 47 +- arch/sandbox/dts/test.dts | 4 + arch/sandbox/include/asm/state.h | 9 + configs/evb-ast2500_defconfig | 6 + configs/sandbox_defconfig | 2 + drivers/clk/aspeed/clk_ast2500.c | 321 +++-- drivers/i2c/Kconfig| 9 + drivers/i2c/Makefile | 1 + drivers/i2c/ast_i2c.c | 357 ++ drivers/i2c/ast_i2c.h | 132 drivers/pinctrl/Kconfig| 9 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/aspeed/Makefile| 1 + drivers/pinctrl/aspeed/pinctrl_ast2500.c | 127 drivers/reset/Kconfig | 10 + drivers/reset/Makefile | 1 + drivers/reset/ast2500-reset.c | 106 +++ drivers/sysreset/sysreset_ast.c| 24 +- drivers/watchdog/Kconfig | 32 + drivers/watchdog/Makefile | 3 + drivers/watchdog/ast_wdt.c | 125 drivers/watchdog/sandbox_wdt.c | 76 +++ drivers/watchdog/wdt-uclass.c | 72 ++ include/dm/uclass-id.h | 1 + include/dt-bindings/clock/ast2500-scu.h| 2 + include/dt-bindings/reset/ast2500-reset.h | 45 ++ include/wdt.h | 107 +++ test/dm/Makefile | 1 + test/dm/wdt.c | 40 ++ 38 files changed, 2721 insertions(+), 167 deletions(-) create mode 100644 arch/arm/include/asm/arch-aspeed/pinctrl.h create mode 100644 drivers/i2c/ast_i2c.c create mode 100644 drivers/i2c/ast_i2c.h create mode 100644 drivers/pinctrl/aspeed/Makefile create mode 100644 drivers/pinctrl/aspeed/pinctrl_ast2500.c create mode 100644 drivers/reset/ast2500-reset.c create mode 100644 drivers/watchdog/ast_wdt.c create mode 100644 drivers/watchdog/sandbox_wdt.c create mode 100644 drivers/watchdog/wdt-uclass.c create mode 100644 include/dt-bindings/reset/ast2500-reset.h create mode 100644 include/wdt.h create mode 100644 test/dm/wdt.c -- 2.12.2.762.g0e3151a226-goog ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v1 09/15] aspeed: Enable Pinctrl Driver in AST2500 EVB
Enable Pinctrl Driver in AST2500 Eval Board's defconfig Signed-off-by: Maxim Sloyko --- Changes in v1: None configs/evb-ast2500_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig index 74808a71ee..f8ef9b779c 100644 --- a/configs/evb-ast2500_defconfig +++ b/configs/evb-ast2500_defconfig @@ -17,3 +17,4 @@ CONFIG_SYSRESET=y CONFIG_TIMER=y CONFIG_WDT=y CONFIG_DM_RESET=y +CONFIG_PINCTRL=y -- 2.12.2.762.g0e3151a226-goog ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v1 07/15] aspeed: Refactor AST2500 RAM Driver and Sysreset Driver
This change switches all existing users of ast2500 Watchdog to Driver
Model based Watchdog driver.
To perform system reset Sysreset Driver uses first Watchdog device found
via uclass_first_device call. Since the system is going to be reset
anyway it does not make much difference which watchdog is used.
Instead of using Watchdog to reset itself, SDRAM driver now uses Reset
driver to do that.
These were the only users of the old Watchdog API, so that API is
removed.
This all is done in one change to avoid having to maintain dual API for
watchdog in between.
Signed-off-by: Maxim Sloyko
---
Changes in v1:
- Rename wdt_reset call to wdt_expire_now
---
arch/arm/include/asm/arch-aspeed/wdt.h | 39 -
arch/arm/mach-aspeed/Kconfig | 8 +
arch/arm/mach-aspeed/ast2500/sdram_ast2500.c | 12 +--
arch/arm/mach-aspeed/ast_wdt.c | 51
configs/evb-ast2500_defconfig| 2 ++
drivers/sysreset/sysreset_ast.c | 24 ++---
6 files changed, 24 insertions(+), 112 deletions(-)
diff --git a/arch/arm/include/asm/arch-aspeed/wdt.h
b/arch/arm/include/asm/arch-aspeed/wdt.h
index 981fa05a56..db8ecbcbe4 100644
--- a/arch/arm/include/asm/arch-aspeed/wdt.h
+++ b/arch/arm/include/asm/arch-aspeed/wdt.h
@@ -100,45 +100,6 @@ u32 ast_reset_mask_from_flags(ulong flags);
* @reset_mask: Reset Mask
*/
ulong ast_flags_from_reset_mode_mask(u32 reset_mode, u32 reset_mask);
-
-#ifndef CONFIG_WDT
-/**
- * Stop WDT
- *
- * @wdt: watchdog to stop
- *
- * When using driver model this function has different signature
- */
-void wdt_stop(struct ast_wdt *wdt);
-
-/**
- * Stop WDT
- *
- * @wdt: watchdog to start
- * @timeoutwatchdog timeout in number of clock ticks
- *
- * When using driver model this function has different signature
- */
-void wdt_start(struct ast_wdt *wdt, u32 timeout);
-#endif /* CONFIG_WDT */
-
-/**
- * Reset peripherals specified by mask
- *
- * Note, that this is only supported by ast2500 SoC
- *
- * @wdt: watchdog to use for this reset
- * @mask: reset mask.
- */
-int ast_wdt_reset_masked(struct ast_wdt *wdt, u32 mask);
-
-/**
- * ast_get_wdt() - get a pointer to watchdog registers
- *
- * @wdt_number: 0-based WDT peripheral number
- * @return pointer to registers or -ve error on error
- */
-struct ast_wdt *ast_get_wdt(u8 wdt_number);
#endif /* __ASSEMBLY__ */
#endif /* _ASM_ARCH_WDT_H */
diff --git a/arch/arm/mach-aspeed/Kconfig b/arch/arm/mach-aspeed/Kconfig
index c5b90bd96a..4f021baa06 100644
--- a/arch/arm/mach-aspeed/Kconfig
+++ b/arch/arm/mach-aspeed/Kconfig
@@ -11,19 +11,13 @@ config SYS_TEXT_BASE
config ASPEED_AST2500
bool "Support Aspeed AST2500 SoC"
+ depends on DM_RESET
select CPU_ARM1176
help
The Aspeed AST2500 is a ARM-based SoC with arm1176 CPU.
It is used as Board Management Controller on many server boards,
which is enabled by support of LPC and eSPI peripherals.
-config WDT_NUM
- int "Number of Watchdog Timers"
- default 3 if ASPEED_AST2500
- help
- The number of Watchdot Timers on a SoC.
- AST2500 has three WDTsk earlier versions have two or fewer.
-
source "arch/arm/mach-aspeed/ast2500/Kconfig"
endif
diff --git a/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
b/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
index cb6e03fa34..efcf452b17 100644
--- a/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
+++ b/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -328,6 +329,7 @@ static void ast2500_sdrammc_lock(struct dram_info *info)
static int ast2500_sdrammc_probe(struct udevice *dev)
{
+ struct reset_ctl reset_ctl;
struct dram_info *priv = (struct dram_info *)dev_get_priv(dev);
struct ast2500_sdrammc_regs *regs = priv->regs;
int i;
@@ -345,9 +347,15 @@ static int ast2500_sdrammc_probe(struct udevice *dev)
}
clk_set_rate(&priv->ddr_clk, priv->clock_rate);
- ret = ast_wdt_reset_masked(ast_get_wdt(0), WDT_RESET_SDRAM);
+ ret = reset_get_by_index(dev, 0, &reset_ctl);
if (ret) {
- debug("%s(): SDRAM reset failed\n", __func__);
+ debug("%s(): Failed to get reset signal\n", __func__);
+ return ret;
+ }
+
+ ret = reset_assert(&reset_ctl);
+ if (ret) {
+ debug("%s(): SDRAM reset failed: %u\n", __func__, ret);
return ret;
}
diff --git a/arch/arm/mach-aspeed/ast_wdt.c b/arch/arm/mach-aspeed/ast_wdt.c
index 895fba3366..1a858b1020 100644
--- a/arch/arm/mach-aspeed/ast_wdt.c
+++ b/arch/arm/mach-aspeed/ast_wdt.c
@@ -28,54 +28,3 @@ ulong ast_flags_from_reset_mode_mask(u32 reset_mode, u32
reset_mask)
return ret;
}
-
-#ifndef CONFIG_WDT
-void wdt_stop(struct ast_wdt *wdt)
-{
- clrbits_le32(&wdt->ctrl, WDT_CTRL_EN);
-}
[U-Boot] [PATCH v1 06/15] aspeed: Device Tree configuration for Reset Driver
Add Reset Driver configuration to ast2500 SoC Device Tree and bindings
for various reset signals
Signed-off-by: Maxim Sloyko
---
Changes in v1: None
arch/arm/dts/ast2500-evb.dts | 15 +++
arch/arm/dts/ast2500-u-boot.dtsi | 10 +++
include/dt-bindings/reset/ast2500-reset.h | 45 +++
3 files changed, 70 insertions(+)
create mode 100644 include/dt-bindings/reset/ast2500-reset.h
diff --git a/arch/arm/dts/ast2500-evb.dts b/arch/arm/dts/ast2500-evb.dts
index dc13952fb8..723941ac0b 100644
--- a/arch/arm/dts/ast2500-evb.dts
+++ b/arch/arm/dts/ast2500-evb.dts
@@ -21,3 +21,18 @@
&sdrammc {
clock-frequency = <4>;
};
+
+&wdt1 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&wdt2 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&wdt3 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi
index c95a7ba835..faeeec1be4 100644
--- a/arch/arm/dts/ast2500-u-boot.dtsi
+++ b/arch/arm/dts/ast2500-u-boot.dtsi
@@ -1,4 +1,5 @@
#include
+#include
#include "ast2500.dtsi"
@@ -11,12 +12,21 @@
#reset-cells = <1>;
};
+ rst: reset-controller {
+ u-boot,dm-pre-reloc;
+ compatible = "aspeed,ast2500-reset";
+ aspeed,wdt = <&wdt1>;
+ #reset-cells = <1>;
+ };
+
sdrammc: sdrammc@1e6e {
u-boot,dm-pre-reloc;
compatible = "aspeed,ast2500-sdrammc";
reg = <0x1e6e 0x174
0x1e6e0200 0x1d4 >;
+ #reset-cells = <1>;
clocks = <&scu PLL_MPLL>;
+ resets = <&rst AST_RESET_SDRAM>;
};
ahb {
diff --git a/include/dt-bindings/reset/ast2500-reset.h
b/include/dt-bindings/reset/ast2500-reset.h
new file mode 100644
index 00..eb5e1db97b
--- /dev/null
+++ b/include/dt-bindings/reset/ast2500-reset.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright 2017 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ABI_MACH_ASPEED_AST2500_RESET_H_
+#define _ABI_MACH_ASPEED_AST2500_RESET_H_
+
+/*
+ * The values are intentionally layed out as flags in
+ * WDT reset parameter.
+ */
+
+#define AST_RESET_SOC 0
+#define AST_RESET_CHIP 1
+#define AST_RESET_CPU (1 << 1)
+#define AST_RESET_ARM (1 << 2)
+#define AST_RESET_COPROC (1 << 3)
+#define AST_RESET_SDRAM(1 << 4)
+#define AST_RESET_AHB (1 << 5)
+#define AST_RESET_I2C (1 << 6)
+#define AST_RESET_MAC1 (1 << 7)
+#define AST_RESET_MAC2 (1 << 8)
+#define AST_RESET_GCRT (1 << 9)
+#define AST_RESET_USB20(1 << 10)
+#define AST_RESET_USB11_HOST (1 << 11)
+#define AST_RESET_USB11_HID(1 << 12)
+#define AST_RESET_VIDEO(1 << 13)
+#define AST_RESET_HAC (1 << 14)
+#define AST_RESET_LPC (1 << 15)
+#define AST_RESET_SDIO (1 << 16)
+#define AST_RESET_MIC (1 << 17)
+#define AST_RESET_CRT2D(1 << 18)
+#define AST_RESET_PWM (1 << 19)
+#define AST_RESET_PECI (1 << 20)
+#define AST_RESET_JTAG (1 << 21)
+#define AST_RESET_ADC (1 << 22)
+#define AST_RESET_GPIO (1 << 23)
+#define AST_RESET_MCTP (1 << 24)
+#define AST_RESET_XDMA (1 << 25)
+#define AST_RESET_SPI (1 << 26)
+#define AST_RESET_MISC (1 << 27)
+
+#endif /* _ABI_MACH_ASPEED_AST2500_RESET_H_ */
--
2.12.2.762.g0e3151a226-goog
___
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[U-Boot] [PATCH v1 11/15] aspeed: Add I2C Driver
Add Device Model based I2C driver for ast2500/ast2400 SoCs.
The driver is very limited, it only supports master mode and
synchronous byte-by-byte reads/writes, no DMA or Pool Buffers.
Signed-off-by: Maxim Sloyko
---
Changes in v1:
- Style fixes
---
drivers/i2c/Kconfig | 9 ++
drivers/i2c/Makefile | 1 +
drivers/i2c/ast_i2c.c | 357 ++
drivers/i2c/ast_i2c.h | 132 +++
4 files changed, 499 insertions(+)
create mode 100644 drivers/i2c/ast_i2c.c
create mode 100644 drivers/i2c/ast_i2c.h
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 39f62daf5d..e661a308b0 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -100,6 +100,15 @@ config SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
enable status register. This config option can be enabled in such
cases.
+config SYS_I2C_ASPEED
+ bool "Aspeed I2C Controller"
+ depends on DM_I2C && ARCH_ASPEED
+ help
+ Say yes here to select Aspeed I2C Host Controller. The driver
+ supports AST2500 and AST2400 controllers, but is very limited.
+ Only single master mode is supported and only byte-by-byte
+ synchronous reads and writes are supported, no Pool Buffers or DMA.
+
config SYS_I2C_INTEL
bool "Intel I2C/SMBUS driver"
depends on DM_I2C
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 7c86198863..229fd476db 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o
obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
obj-$(CONFIG_SYS_I2C) += i2c_core.o
+obj-$(CONFIG_SYS_I2C_ASPEED) += ast_i2c.o
obj-$(CONFIG_SYS_I2C_AT91) += at91_i2c.o
obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o
obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o
diff --git a/drivers/i2c/ast_i2c.c b/drivers/i2c/ast_i2c.c
new file mode 100644
index 00..16dfb57066
--- /dev/null
+++ b/drivers/i2c/ast_i2c.c
@@ -0,0 +1,357 @@
+/*
+ * Copyright (C) 2012-2020 ASPEED Technology Inc.
+ * Copyright 2016 IBM Corporation
+ * Copyright 2017 Google, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "ast_i2c.h"
+
+#define I2C_TIMEOUT_US 10
+#define I2C_SLEEP_STEP_US 20
+
+#define HIGHSPEED_TTIMEOUT 3
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Device private data
+ */
+struct ast_i2c_priv {
+ /* This device's clock */
+ struct clk clk;
+ /* Device registers */
+ struct ast_i2c_regs *regs;
+ /* I2C speed in Hz */
+ int speed;
+};
+
+/*
+ * Given desired divider ratio, return the value that needs to be set
+ * in Clock and AC Timing Control register
+ */
+static u32 get_clk_reg_val(ulong divider_ratio)
+{
+ ulong inc = 0, div;
+ ulong scl_low, scl_high, data;
+
+ for (div = 0; divider_ratio >= 16; div++) {
+ inc |= (divider_ratio & 1);
+ divider_ratio >>= 1;
+ }
+ divider_ratio += inc;
+ scl_low = (divider_ratio >> 1) - 1;
+ scl_high = divider_ratio - scl_low - 2;
+ data = I2CD_CACTC_BASE
+ | (scl_high << I2CD_TCKHIGH_SHIFT)
+ | (scl_low << I2CD_TCKLOW_SHIFT)
+ | (div << I2CD_BASE_DIV_SHIFT);
+
+ return data;
+}
+
+static void ast_i2c_clear_interrupts(struct udevice *dev)
+{
+ struct ast_i2c_priv *priv = dev_get_priv(dev);
+
+ writel(~0, &priv->regs->isr);
+}
+
+static void ast_i2c_init_bus(struct udevice *dev)
+{
+ struct ast_i2c_priv *priv = dev_get_priv(dev);
+
+ /* Reset device */
+ writel(0, &priv->regs->fcr);
+ /* Enable Master Mode. Assuming single-master */
+ writel(I2CD_MASTER_EN
+ | I2CD_M_SDA_LOCK_EN
+ | I2CD_MULTI_MASTER_DIS | I2CD_M_SCL_DRIVE_EN,
+ &priv->regs->fcr);
+ /* Enable Interrupts */
+ writel(I2CD_INTR_TX_ACK
+ | I2CD_INTR_TX_NAK
+ | I2CD_INTR_RX_DONE
+ | I2CD_INTR_BUS_RECOVER_DONE
+ | I2CD_INTR_NORMAL_STOP
+ | I2CD_INTR_ABNORMAL, &priv->regs->icr);
+}
+
+static int ast_i2c_ofdata_to_platdata(struct udevice *dev)
+{
+ struct ast_i2c_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ priv->regs = dev_get_addr_ptr(dev);
+ if (IS_ERR(priv->regs))
+ return PTR_ERR(priv->regs);
+
+ ret = clk_get_by_index(dev, 0, &priv->clk);
+ if (ret < 0) {
+ debug("%s: Can't get clock for %s: %d\n", __func__, dev->name,
+ ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int ast_i2c_probe(struct udevice *dev)
+{
+ struct ast2500_scu *scu;
+
+ debug("Enabling I2C%u\n", dev->seq);
+
+ /*
+* Get all I2C devices out of Reset.
+* Only needs to be
[U-Boot] [PATCH v1 13/15] aspeed: Add support for Clocks needed by MACs
Add support for clocks needed by MACs to ast2500 clock driver.
The clocks are D2-PLL, which is used by both MACs and PCLK_MAC1 and
PCLK_MAC2 for MAC1 and MAC2 respectively.
The rate of D2-PLL is hardcoded to 250MHz -- the value used in Aspeed
SDK. It is not entirely clear from the datasheet how this clock is used
by MACs, so not clear if the rate would ever need to be different. So,
for now, hardcoding it is probably safer.
The rate of PCLK_MAC{1,2} is chosen based on MAC speed selected through
hardware strapping.
So, the network driver would only need to enable these clocks, no need
to configure the rate.
Signed-off-by: Maxim Sloyko
---
Changes in v1: None
arch/arm/dts/ast2500-u-boot.dtsi | 8 +
arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 62 +-
drivers/clk/aspeed/clk_ast2500.c | 265 ++---
include/dt-bindings/clock/ast2500-scu.h| 2 +
4 files changed, 304 insertions(+), 33 deletions(-)
diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi
index faeeec1be4..f826646095 100644
--- a/arch/arm/dts/ast2500-u-boot.dtsi
+++ b/arch/arm/dts/ast2500-u-boot.dtsi
@@ -61,3 +61,11 @@
};
};
};
+
+&mac0 {
+ clocks = <&scu PCLK_MAC1>, <&scu PLL_D2PLL>;
+};
+
+&mac1 {
+ clocks = <&scu PCLK_MAC2>, <&scu PLL_D2PLL>;
+};
diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
index 319d75e05c..fe877b5430 100644
--- a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
+++ b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
@@ -30,9 +30,36 @@
#define SCU_HPLL_POST_SHIFT13
#define SCU_HPLL_POST_MASK 0x3f
+#define SCU_MACCLK_SHIFT 16
+#define SCU_MACCLK_MASK(7 << SCU_MACCLK_SHIFT)
+
+#define SCU_MISC2_RGMII_HPLL (1 << 23)
+#define SCU_MISC2_RGMII_CLKDIV_SHIFT 20
+#define SCU_MISC2_RGMII_CLKDIV_MASK(3 << SCU_MISC2_RGMII_CLKDIV_SHIFT)
+#define SCU_MISC2_RMII_MPLL(1 << 19)
+#define SCU_MISC2_RMII_CLKDIV_SHIFT16
+#define SCU_MISC2_RMII_CLKDIV_MASK (3 << SCU_MISC2_RMII_CLKDIV_SHIFT)
#define SCU_MISC2_UARTCLK_SHIFT24
+#define SCU_MISC_D2PLL_OFF (1 << 4)
#define SCU_MISC_UARTCLK_DIV13 (1 << 12)
+#define SCU_MISC_GCRT_USB20CLK (1 << 21)
+
+#define SCU_MICDS_MAC1RGMII_TXDLY_SHIFT0
+#define SCU_MICDS_MAC1RGMII_TXDLY_MASK (0x3f\
+<< SCU_MICDS_MAC1RGMII_TXDLY_SHIFT)
+#define SCU_MICDS_MAC2RGMII_TXDLY_SHIFT6
+#define SCU_MICDS_MAC2RGMII_TXDLY_MASK (0x3f\
+<< SCU_MICDS_MAC2RGMII_TXDLY_SHIFT)
+#define SCU_MICDS_MAC1RMII_RDLY_SHIFT 12
+#define SCU_MICDS_MAC1RMII_RDLY_MASK (0x3f << SCU_MICDS_MAC1RMII_RDLY_SHIFT)
+#define SCU_MICDS_MAC2RMII_RDLY_SHIFT 18
+#define SCU_MICDS_MAC2RMII_RDLY_MASK (0x3f << SCU_MICDS_MAC2RMII_RDLY_SHIFT)
+#define SCU_MICDS_MAC1RMII_TXFALL (1 << 24)
+#define SCU_MICDS_MAC2RMII_TXFALL (1 << 25)
+#define SCU_MICDS_RMII1_RCLKEN (1 << 29)
+#define SCU_MICDS_RMII2_RCLKEN (1 << 30)
+#define SCU_MICDS_RGMIIPLL (1 << 31)
/*
* SYSRESET is actually more like a Power register,
@@ -71,14 +98,45 @@
*/
#define SCU_PIN_FUN_MAC1_MDC (1 << 30)
#define SCU_PIN_FUN_MAC1_MDIO (1 << 31)
-#define SCU_PIN_FUN_MAC1_PHY_LINK (1 << 0)
+#define SCU_PIN_FUN_MAC1_PHY_LINK (1 << 0)
#define SCU_PIN_FUN_MAC2_MDIO (1 << 2)
-#define SCU_PIN_FUN_MAC2_PHY_LINK (1 << 1)
+#define SCU_PIN_FUN_MAC2_PHY_LINK (1 << 1)
#define SCU_PIN_FUN_SCL1 (1 << 12)
#define SCU_PIN_FUN_SCL2 (1 << 14)
#define SCU_PIN_FUN_SDA1 (1 << 13)
#define SCU_PIN_FUN_SDA2 (1 << 15)
+#define SCU_CLKSTOP_MAC1 (1 << 20)
+#define SCU_CLKSTOP_MAC2 (1 << 21)
+
+#define SCU_D2PLL_EXT1_OFF (1 << 0)
+#define SCU_D2PLL_EXT1_BYPASS (1 << 1)
+#define SCU_D2PLL_EXT1_RESET (1 << 2)
+#define SCU_D2PLL_EXT1_MODE_SHIFT 3
+#define SCU_D2PLL_EXT1_MODE_MASK (3 << SCU_D2PLL_EXT1_MODE_SHIFT)
+#define SCU_D2PLL_EXT1_PARAM_SHIFT 5
+#define SCU_D2PLL_EXT1_PARAM_MASK (0x1ff << SCU_D2PLL_EXT1_PARAM_SHIFT)
+
+#define SCU_D2PLL_NUM_SHIFT0
+#define SCU_D2PLL_NUM_MASK (0xff << SCU_D2PLL_NUM_SHIFT)
+#define SCU_D2PLL_DENUM_SHIFT 8
+#define SCU_D2PLL_DENUM_MASK (0x1f << SCU_D2PLL_DENUM_SHIFT)
+#define SCU_D2PLL_POST_SHIFT 13
+#define SCU_D2PLL_POST_MASK(0x3f << SCU_D2PLL_POST_SHIFT)
+#define SCU_D2PLL_ODIV_SHIFT 19
+#define SCU_D2PLL_ODIV_MASK(7 << SCU_D2PLL_ODIV_SHIFT)
+#define SCU_D2PLL_SIC_SHIFT22
+#define SCU_D2PLL_SIC_MASK (0x1f << SCU_D2PLL_SIC_SHIFT)
+#define SCU_D2PLL_SIP_SHIFT27
+#define SCU_D2PLL_SIP_MASK
[U-Boot] [PATCH v1 15/15] aspeed: Cleanup ast2500-u-boot.dtsi Device Tree
Remove unnecessary apb and ahb nodes and just override necessary
nodes/values.
Signed-off-by: Maxim Sloyko
---
Changes in v1: None
---
arch/arm/dts/ast2500-u-boot.dtsi | 41
1 file changed, 21 insertions(+), 20 deletions(-)
diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi
index f826646095..7f80bad7d0 100644
--- a/arch/arm/dts/ast2500-u-boot.dtsi
+++ b/arch/arm/dts/ast2500-u-boot.dtsi
@@ -34,32 +34,33 @@
apb {
u-boot,dm-pre-reloc;
+ };
- timer: timer@1e782000 {
- u-boot,dm-pre-reloc;
- };
+ };
+};
- uart1: serial@1e783000 {
- clocks = <&scu PCLK_UART1>;
- };
+&uart1 {
+ clocks = <&scu PCLK_UART1>;
+};
- uart2: serial@1e78d000 {
- clocks = <&scu PCLK_UART2>;
- };
+&uart2 {
+ clocks = <&scu PCLK_UART2>;
+};
- uart3: serial@1e78e000 {
- clocks = <&scu PCLK_UART3>;
- };
+&uart3 {
+ clocks = <&scu PCLK_UART3>;
+};
- uart4: serial@1e78f000 {
- clocks = <&scu PCLK_UART4>;
- };
+&uart4 {
+ clocks = <&scu PCLK_UART4>;
+};
- uart5: serial@1e784000 {
- clocks = <&scu PCLK_UART5>;
- };
- };
- };
+&uart5 {
+ clocks = <&scu PCLK_UART5>;
+};
+
+&timer {
+ u-boot,dm-pre-reloc;
};
&mac0 {
--
2.12.2.762.g0e3151a226-goog
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[U-Boot] [PATCH v1 03/15] aspeed: Watchdog Timer Driver
This driver supports ast2500 and ast2400 SoCs.
Only ast2500 supports reset_mask and thus the option of resettting
individual peripherals using WDT.
Signed-off-by: Maxim Sloyko
---
Changes in v1:
- Rename reset to expire_now
- Rename restart to reset
---
arch/arm/include/asm/arch-aspeed/wdt.h | 53 --
arch/arm/mach-aspeed/ast_wdt.c | 40 ---
drivers/watchdog/Kconfig | 11 +++
drivers/watchdog/Makefile | 1 +
drivers/watchdog/ast_wdt.c | 125 +
5 files changed, 217 insertions(+), 13 deletions(-)
create mode 100644 drivers/watchdog/ast_wdt.c
diff --git a/arch/arm/include/asm/arch-aspeed/wdt.h
b/arch/arm/include/asm/arch-aspeed/wdt.h
index b292a0e67b..981fa05a56 100644
--- a/arch/arm/include/asm/arch-aspeed/wdt.h
+++ b/arch/arm/include/asm/arch-aspeed/wdt.h
@@ -67,15 +67,60 @@ struct ast_wdt {
u32 timeout_status;
u32 clr_timeout_status;
u32 reset_width;
-#ifdef CONFIG_ASPEED_AST2500
+ /* On pre-ast2500 SoCs this register is reserved. */
u32 reset_mask;
-#else
- u32 reserved0;
-#endif
};
+/**
+ * Given flags parameter passed to wdt_reset or wdt_start uclass functions,
+ * gets Reset Mode value from it.
+ *
+ * @flags: flags parameter passed into wdt_reset or wdt_start
+ * @return Reset Mode value
+ */
+u32 ast_reset_mode_from_flags(ulong flags);
+
+/**
+ * Given flags parameter passed to wdt_reset or wdt_start uclass functions,
+ * gets Reset Mask value from it. Reset Mask is only supported on ast2500
+ *
+ * @flags: flags parameter passed into wdt_reset or wdt_start
+ * @return Reset Mask value
+ */
+u32 ast_reset_mask_from_flags(ulong flags);
+
+/**
+ * Given Reset Mask and Reset Mode values, converts them to flags,
+ * suitable for passing into wdt_start or wdt_reset uclass functions.
+ *
+ * On ast2500 Reset Mask is 25 bits wide and Reset Mode is 2 bits wide, so they
+ * can both be packed into single 32 bits wide value.
+ *
+ * @reset_mode: Reset Mode
+ * @reset_mask: Reset Mask
+ */
+ulong ast_flags_from_reset_mode_mask(u32 reset_mode, u32 reset_mask);
+
+#ifndef CONFIG_WDT
+/**
+ * Stop WDT
+ *
+ * @wdt: watchdog to stop
+ *
+ * When using driver model this function has different signature
+ */
void wdt_stop(struct ast_wdt *wdt);
+
+/**
+ * Stop WDT
+ *
+ * @wdt: watchdog to start
+ * @timeoutwatchdog timeout in number of clock ticks
+ *
+ * When using driver model this function has different signature
+ */
void wdt_start(struct ast_wdt *wdt, u32 timeout);
+#endif /* CONFIG_WDT */
/**
* Reset peripherals specified by mask
diff --git a/arch/arm/mach-aspeed/ast_wdt.c b/arch/arm/mach-aspeed/ast_wdt.c
index 22481ab7ea..895fba3366 100644
--- a/arch/arm/mach-aspeed/ast_wdt.c
+++ b/arch/arm/mach-aspeed/ast_wdt.c
@@ -9,6 +9,27 @@
#include
#include
+u32 ast_reset_mode_from_flags(ulong flags)
+{
+ return flags & WDT_CTRL_RESET_MASK;
+}
+
+u32 ast_reset_mask_from_flags(ulong flags)
+{
+ return flags >> 2;
+}
+
+ulong ast_flags_from_reset_mode_mask(u32 reset_mode, u32 reset_mask)
+{
+ ulong ret = reset_mode & WDT_CTRL_RESET_MASK;
+
+ if (ret == WDT_CTRL_RESET_SOC)
+ ret |= (reset_mask << 2);
+
+ return ret;
+}
+
+#ifndef CONFIG_WDT
void wdt_stop(struct ast_wdt *wdt)
{
clrbits_le32(&wdt->ctrl, WDT_CTRL_EN);
@@ -26,15 +47,7 @@ void wdt_start(struct ast_wdt *wdt, u32 timeout)
setbits_le32(&wdt->ctrl,
WDT_CTRL_EN | WDT_CTRL_RESET | WDT_CTRL_CLK1MHZ);
}
-
-struct ast_wdt *ast_get_wdt(u8 wdt_number)
-{
- if (wdt_number > CONFIG_WDT_NUM - 1)
- return ERR_PTR(-EINVAL);
-
- return (struct ast_wdt *)(WDT_BASE +
- sizeof(struct ast_wdt) * wdt_number);
-}
+#endif /* CONFIG_WDT */
int ast_wdt_reset_masked(struct ast_wdt *wdt, u32 mask)
{
@@ -57,3 +70,12 @@ int ast_wdt_reset_masked(struct ast_wdt *wdt, u32 mask)
return -EINVAL;
#endif
}
+
+struct ast_wdt *ast_get_wdt(u8 wdt_number)
+{
+ if (wdt_number > CONFIG_WDT_NUM - 1)
+ return ERR_PTR(-EINVAL);
+
+ return (struct ast_wdt *)(WDT_BASE +
+ sizeof(struct ast_wdt) * wdt_number);
+}
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 7a725f1e6d..fab8dc9034 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -18,4 +18,15 @@ config WDT_SANDBOX
can be probed and supports all of the methods of WDT, but does
not
really do anything.
+config WDT_ASPEED
+ bool "Aspeed ast2400/ast2500 watchdog timer support"
+ depends on WDT
+ default y if ARCH_ASPEED
+ help
+ Select this to enable watchdog timer for Aspeed ast2500/ast2400
devices.
+ The watchdog timer is stopped when initialized. It performs reset,
either
+ full SoC reset or CPU or just some peripherals, based on the flags.
+
[U-Boot] [PATCH v1 02/15] dm: Simple Watchdog uclass
This is a simple uclass for Watchdog Timers. It has four operations:
start, restart, reset, stop. Drivers must implement start, restart and
stop operations, while implementing reset is optional: It's default
implementation expires watchdog timer in one clock tick.
Signed-off-by: Maxim Sloyko
---
Changes in v1:
- Rename wdt_reset to wdt_expire_now
- Rename wdt_restart to wdt_reset
- Clarified function documentation in few cases
- Add Sandbox WDT driver and unit tests
---
arch/sandbox/dts/test.dts| 4 ++
arch/sandbox/include/asm/state.h | 9
configs/sandbox_defconfig| 2 +
drivers/watchdog/Kconfig | 21
drivers/watchdog/Makefile| 2 +
drivers/watchdog/sandbox_wdt.c | 76 +++
drivers/watchdog/wdt-uclass.c| 72 ++
include/dm/uclass-id.h | 1 +
include/wdt.h| 107 +++
test/dm/Makefile | 1 +
test/dm/wdt.c| 40 +++
11 files changed, 335 insertions(+)
create mode 100644 drivers/watchdog/sandbox_wdt.c
create mode 100644 drivers/watchdog/wdt-uclass.c
create mode 100644 include/wdt.h
create mode 100644 test/dm/wdt.c
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index fff175d1b7..e04ecc64cc 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -418,6 +418,10 @@
};
};
};
+
+ wdt0: wdt@0 {
+ compatible = "sandbox,wdt";
+ };
};
#include "sandbox_pmic.dtsi"
diff --git a/arch/sandbox/include/asm/state.h b/arch/sandbox/include/asm/state.h
index 149f28d873..987cc7b49d 100644
--- a/arch/sandbox/include/asm/state.h
+++ b/arch/sandbox/include/asm/state.h
@@ -39,6 +39,12 @@ struct sandbox_spi_info {
struct udevice *emul;
};
+struct sandbox_wdt_info {
+ unsigned long long counter;
+ uint reset_count;
+ bool running;
+};
+
/* The complete state of the test system */
struct sandbox_state {
const char *cmd;/* Command to execute */
@@ -69,6 +75,9 @@ struct sandbox_state {
/* Pointer to information for each SPI bus/cs */
struct sandbox_spi_info spi[CONFIG_SANDBOX_SPI_MAX_BUS]
[CONFIG_SANDBOX_SPI_MAX_CS];
+
+ /* Information about Watchdog */
+ struct sandbox_wdt_info wdt;
};
/* Minimum space we guarantee in the state FDT when calling read/write*/
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 01f6f5d5c6..a5f63e027f 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -171,3 +171,5 @@ CONFIG_UNIT_TEST=y
CONFIG_UT_TIME=y
CONFIG_UT_DM=y
CONFIG_UT_ENV=y
+CONFIG_WDT=y
+CONFIG_WDT_SANDBOX=y
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index e69de29bb2..7a725f1e6d 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -0,0 +1,21 @@
+menu "Watchdog Timer Support"
+
+config WDT
+ bool "Enable driver model for watchdog timer drivers"
+ depends on DM
+ help
+ Enable driver model for watchdog timer. At the moment the API
+ is very simple and only supports four operations:
+ start, restart, stop and reset (expire immediately).
+ What exactly happens when the timer expires is up to a particular
+ device/driver.
+
+config WDT_SANDBOX
+ bool "Enable Watchdog Timer support for Sandbox"
+ depends on SANDBOX && WDT
+ help
+ Enable Watchdog Timer support in Sandbox. This is a dummy
device that
+ can be probed and supports all of the methods of WDT, but does
not
+ really do anything.
+
+endmenu
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index a007ae8234..f523d34d57 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -15,3 +15,5 @@ obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o
obj-$(CONFIG_BFIN_WATCHDOG) += bfin_wdt.o
obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o
obj-$(CONFIG_DESIGNWARE_WATCHDOG) += designware_wdt.o
+obj-$(CONFIG_WDT) += wdt-uclass.o
+obj-$(CONFIG_WDT_SANDBOX) += sandbox_wdt.o
diff --git a/drivers/watchdog/sandbox_wdt.c b/drivers/watchdog/sandbox_wdt.c
new file mode 100644
index 00..34d90bee7e
--- /dev/null
+++ b/drivers/watchdog/sandbox_wdt.c
@@ -0,0 +1,76 @@
+/*
+ * Copyright 2017 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int sandbox_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
+{
+ struct sandbox_state *state = state_get_current();
+
+ state->wdt.counter = timeout;
+ state->wdt.running = true;
+
+ return 0;
+}
+
+static int sandbox_wdt_stop(struct udevice *dev)
+{
+ struct sandbox_state *state = state_get_current();
+
+ state->wdt.running = false;
[U-Boot] [PATCH v1 01/15] aspeed: Update ast2500 Device Tree
Pull in the Device Tree for ast2500 from the mainline Linux kernel.
The file is copied from
https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi
Signed-off-by: Maxim Sloyko
---
Changes in v1:
- Added link to the original version to commit message
---
arch/arm/dts/ast2500.dtsi | 881 +-
1 file changed, 880 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/ast2500.dtsi b/arch/arm/dts/ast2500.dtsi
index 97fac69d11..7e0ad3a41a 100644
--- a/arch/arm/dts/ast2500.dtsi
+++ b/arch/arm/dts/ast2500.dtsi
@@ -1,6 +1,6 @@
/*
* This device tree is copied from
- * https://raw.githubusercontent.com/torvalds/linux/02440622/arch/arm/boot/dts/
+ *
https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi
*/
#include "skeleton.dtsi"
@@ -36,6 +36,22 @@
reg = <0x1e6c0080 0x80>;
};
+ mac0: ethernet@1e66 {
+ compatible = "faraday,ftgmac100";
+ reg = <0x1e66 0x180>;
+ interrupts = <2>;
+ no-hw-checksum;
+ status = "disabled";
+ };
+
+ mac1: ethernet@1e68 {
+ compatible = "faraday,ftgmac100";
+ reg = <0x1e68 0x180>;
+ interrupts = <3>;
+ no-hw-checksum;
+ status = "disabled";
+ };
+
apb {
compatible = "simple-bus";
#address-cells = <1>;
@@ -48,6 +64,822 @@
reg = <0x1e6e2070 0x04>;
};
+ syscon: syscon@1e6e2000 {
+ compatible = "aspeed,g5-scu", "syscon",
"simple-mfd";
+ reg = <0x1e6e2000 0x1a8>;
+
+ pinctrl: pinctrl {
+ compatible = "aspeed,g5-pinctrl";
+ aspeed,external-nodes = <&gfx &lhc>;
+
+ pinctrl_acpi_default: acpi_default {
+ function = "ACPI";
+ groups = "ACPI";
+ };
+
+ pinctrl_adc0_default: adc0_default {
+ function = "ADC0";
+ groups = "ADC0";
+ };
+
+ pinctrl_adc1_default: adc1_default {
+ function = "ADC1";
+ groups = "ADC1";
+ };
+
+ pinctrl_adc10_default: adc10_default {
+ function = "ADC10";
+ groups = "ADC10";
+ };
+
+ pinctrl_adc11_default: adc11_default {
+ function = "ADC11";
+ groups = "ADC11";
+ };
+
+ pinctrl_adc12_default: adc12_default {
+ function = "ADC12";
+ groups = "ADC12";
+ };
+
+ pinctrl_adc13_default: adc13_default {
+ function = "ADC13";
+ groups = "ADC13";
+ };
+
+ pinctrl_adc14_default: adc14_default {
+ function = "ADC14";
+ groups = "ADC14";
+ };
+
+ pinctrl_adc15_default: adc15_default {
+ function = "ADC15";
+ groups = "ADC15";
+ };
+
+ pinctrl_adc2_default: adc2_default {
+ function = "ADC2";
+ groups = "ADC2";
+ };
+
+ pinctrl_adc3_default: adc3_default {
+ function = "ADC3";
+ groups = "ADC3";
+ };
+
+
[U-Boot] [PATCH v1 12/15] aspeed: Enable I2C in EVB defconfig
Enable I2C driver in ast2500 Eval Board defconfig. Also enable i2c command. Signed-off-by: Maxim Sloyko --- Changes in v1: None configs/evb-ast2500_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig index f8ef9b779c..08b5f85a34 100644 --- a/configs/evb-ast2500_defconfig +++ b/configs/evb-ast2500_defconfig @@ -18,3 +18,6 @@ CONFIG_TIMER=y CONFIG_WDT=y CONFIG_DM_RESET=y CONFIG_PINCTRL=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_ASPEED=y +CONFIG_CMD_I2C=y -- 2.12.2.762.g0e3151a226-goog ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v1 04/15] aspeed: Make SCU lock/unlock functions part of SCU API
Make functions for locking and unlocking SCU part of SCU API.
Many drivers need to modify settings in SCU and thus need to unlock it
first. This change makes it possible.
Signed-off-by: Maxim Sloyko
---
Changes in v1: None
arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 14 ++
arch/arm/mach-aspeed/ast2500/clk_ast2500.c | 15 +++
drivers/clk/aspeed/clk_ast2500.c | 18 ++
3 files changed, 31 insertions(+), 16 deletions(-)
diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
index fc0c01ae33..0fa3ecb9b9 100644
--- a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
+++ b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
@@ -120,6 +120,20 @@ int ast_get_clk(struct udevice **devp);
*/
void *ast_get_scu(void);
+/**
+ * ast_scu_unlock() - unlock protected registers
+ *
+ * @scu, pointer to ast2500_scu
+ */
+void ast_scu_unlock(struct ast2500_scu *scu);
+
+/**
+ * ast_scu_lock() - lock protected registers
+ *
+ * @scu, pointer to ast2500_scu
+ */
+void ast_scu_lock(struct ast2500_scu *scu);
+
#endif /* __ASSEMBLY__ */
#endif /* _ASM_ARCH_SCU_AST2500_H */
diff --git a/arch/arm/mach-aspeed/ast2500/clk_ast2500.c
b/arch/arm/mach-aspeed/ast2500/clk_ast2500.c
index 079909fa64..30cfac1af0 100644
--- a/arch/arm/mach-aspeed/ast2500/clk_ast2500.c
+++ b/arch/arm/mach-aspeed/ast2500/clk_ast2500.c
@@ -6,6 +6,7 @@
#include
#include
+#include
#include
int ast_get_clk(struct udevice **devp)
@@ -28,3 +29,17 @@ void *ast_get_scu(void)
return priv->scu;
}
+
+void ast_scu_unlock(struct ast2500_scu *scu)
+{
+ writel(SCU_UNLOCK_VALUE, &scu->protection_key);
+ while (!readl(&scu->protection_key))
+ ;
+}
+
+void ast_scu_lock(struct ast2500_scu *scu)
+{
+ writel(~SCU_UNLOCK_VALUE, &scu->protection_key);
+ while (readl(&scu->protection_key))
+ ;
+}
diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c
index 26a5e58221..504731271c 100644
--- a/drivers/clk/aspeed/clk_ast2500.c
+++ b/drivers/clk/aspeed/clk_ast2500.c
@@ -132,20 +132,6 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
return rate;
}
-static void ast2500_scu_unlock(struct ast2500_scu *scu)
-{
- writel(SCU_UNLOCK_VALUE, &scu->protection_key);
- while (!readl(&scu->protection_key))
- ;
-}
-
-static void ast2500_scu_lock(struct ast2500_scu *scu)
-{
- writel(~SCU_UNLOCK_VALUE, &scu->protection_key);
- while (readl(&scu->protection_key))
- ;
-}
-
static ulong ast2500_configure_ddr(struct ast2500_scu *scu, ulong rate)
{
ulong clkin = ast2500_get_clkin(scu);
@@ -197,9 +183,9 @@ static ulong ast2500_configure_ddr(struct ast2500_scu *scu,
ulong rate)
| (best_num << SCU_MPLL_NUM_SHIFT)
| (best_denum << SCU_MPLL_DENUM_SHIFT);
- ast2500_scu_unlock(scu);
+ ast_scu_unlock(scu);
writel(mpll_reg, &scu->m_pll_param);
- ast2500_scu_lock(scu);
+ ast_scu_lock(scu);
return ast2500_get_mpll_rate(clkin, mpll_reg);
}
--
2.12.2.762.g0e3151a226-goog
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] Add ARM errata workaround 852421 and 852423 for Cortex-A17
On Sun, Apr 16, 2017 at 7:50 PM, Nisal Menuka wrote: > ARM errata 852421 and 852423 applies to r1p0, r1p1 and r1p2 > revisions of Cortex-A17 processors. These workarounds > exist in Linux kernel and I thought it would be better > to add them in to U-Boot. > > Signed-off-by: Nisal Menuka > --- > arch/arm/cpu/armv7/start.S | 12 > 1 file changed, 12 insertions(+) > > diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S > index 1a6aee9..f06fd28 100644 > --- a/arch/arm/cpu/armv7/start.S > +++ b/arch/arm/cpu/armv7/start.S > @@ -283,6 +283,18 @@ skip_errata_621766: > skip_errata_725233: > #endif > > +#ifdef CONFIG_ARM_ERRATA_852421 > + mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register > + orr r0, r0, #1 << 24@ set bit #24 > + mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register > +#endif No entries to arch/arm/Kconfig ? ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v1 08/15] aspeed: AST2500 Pinctrl Driver
This driver uses Generic Pinctrl framework and is compatible with
the Linux driver for ast2500: it uses the same device tree
configuration.
Not all pins are supported by the driver at the moment, so it actually
compatible with ast2400. In general, however, there are differences that
in the future would be easier to maintain separately.
Signed-off-by: Maxim Sloyko
---
Changes in v1: None
arch/arm/include/asm/arch-aspeed/pinctrl.h | 52 ++
arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 19
drivers/pinctrl/Kconfig| 9 ++
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/aspeed/Makefile| 1 +
drivers/pinctrl/aspeed/pinctrl_ast2500.c | 127 +
6 files changed, 209 insertions(+)
create mode 100644 arch/arm/include/asm/arch-aspeed/pinctrl.h
create mode 100644 drivers/pinctrl/aspeed/Makefile
create mode 100644 drivers/pinctrl/aspeed/pinctrl_ast2500.c
diff --git a/arch/arm/include/asm/arch-aspeed/pinctrl.h
b/arch/arm/include/asm/arch-aspeed/pinctrl.h
new file mode 100644
index 00..365dc21dbc
--- /dev/null
+++ b/arch/arm/include/asm/arch-aspeed/pinctrl.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2017 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#ifndef _ASM_ARCH_PERIPH_H
+#define _ASM_ARCH_PERIPH_H
+
+/*
+ * Peripherals supported by the hardware.
+ * These are used to specify pinctrl settings.
+ */
+
+enum periph_id {
+ PERIPH_ID_UART1,
+ PERIPH_ID_UART2,
+ PERIPH_ID_UART3,
+ PERIPH_ID_UART4,
+ PERIPH_ID_LPC,
+ PERIPH_ID_PWM0,
+ PERIPH_ID_PWM1,
+ PERIPH_ID_PWM2,
+ PERIPH_ID_PWM3,
+ PERIPH_ID_PWM4,
+ PERIPH_ID_PWM5,
+ PERIPH_ID_PWM6,
+ PERIPH_ID_PWM7,
+ PERIPH_ID_PWM8,
+ PERIPH_ID_MAC1,
+ PERIPH_ID_MAC2,
+ PERIPH_ID_VIDEO,
+ PERIPH_ID_SPI1,
+ PERIPH_ID_SPI2,
+ PERIPH_ID_I2C1,
+ PERIPH_ID_I2C2,
+ PERIPH_ID_I2C3,
+ PERIPH_ID_I2C4,
+ PERIPH_ID_I2C5,
+ PERIPH_ID_I2C6,
+ PERIPH_ID_I2C7,
+ PERIPH_ID_I2C8,
+ PERIPH_ID_I2C9,
+ PERIPH_ID_I2C10,
+ PERIPH_ID_I2C11,
+ PERIPH_ID_I2C12,
+ PERIPH_ID_I2C13,
+ PERIPH_ID_I2C14,
+ PERIPH_ID_SD1,
+ PERIPH_ID_SD2,
+};
+
+#endif /* _ASM_ARCH_SCU_AST2500_H */
diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
index e2556f920d..1cdd3b9198 100644
--- a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
+++ b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
@@ -10,6 +10,8 @@
#define SCU_HWSTRAP_VGAMEM_MASK3
#define SCU_HWSTRAP_VGAMEM_SHIFT 2
+#define SCU_HWSTRAP_MAC1_RGMII (1 << 6)
+#define SCU_HWSTRAP_MAC2_RGMII (1 << 7)
#define SCU_HWSTRAP_DDR4 (1 << 24)
#define SCU_HWSTRAP_CLKIN_25MHZ(1 << 23)
@@ -59,6 +61,23 @@
#define SCU_SYSRESET_AHB (1 << 1)
#define SCU_SYSRESET_SDRAM_WDT (1 << 0)
+/* Bits 16-27 in the register control pin functions for I2C devices 3-14 */
+#define SCU_PINMUX_CTRL5_I2C (1 << 16)
+
+/*
+ * The values are grouped by function, not by register.
+ * They are actually scattered across multiple loosely related registers.
+ */
+#define SCU_PIN_FUN_MAC1_MDC (1 << 30)
+#define SCU_PIN_FUN_MAC1_MDIO (1 << 31)
+#define SCU_PIN_FUN_MAC1_PHY_LINK (1 << 0)
+#define SCU_PIN_FUN_MAC2_MDIO (1 << 2)
+#define SCU_PIN_FUN_MAC2_PHY_LINK (1 << 1)
+#define SCU_PIN_FUN_SCL1 (1 << 12)
+#define SCU_PIN_FUN_SCL2 (1 << 14)
+#define SCU_PIN_FUN_SDA1 (1 << 13)
+#define SCU_PIN_FUN_SDA2 (1 << 15)
+
#ifndef __ASSEMBLY__
struct ast2500_clk_priv {
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index efcb4c0003..3b7dd5f0c5 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -175,6 +175,15 @@ config PIC32_PINCTRL
by a device tree node which contains both GPIO defintion and pin
control
functions.
+config ASPEED_AST2500_PINCTRL
+ bool "Aspeed AST2500 pin control driver"
+ depends on DM && PINCTRL_GENERIC && ASPEED_AST2500
+ default y
+ help
+Support pin multiplexing control on Aspeed ast2500 SoC. The driver uses
+ Generic Pinctrl framework and is compatible with the Linux driver,
+ i.e. it uses the same device tree configuration.
+
endif
source "drivers/pinctrl/meson/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 512112af64..5392c3ed45 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -16,3 +16,4 @@ obj-$(CONFIG_PIC32_PINCTRL) += pinctrl_pic32.o
obj-$(CONFIG_PINCTRL_EXYNOS) += exynos/
obj-$(CONFIG_PINCTRL_MESON)+= meson/
obj-$(CONFIG_PINCTRL_MVEBU)+= mvebu/
+obj-$(CONFIG_ARCH_ASPEED) += aspeed/
diff --git a/drivers/pinctrl/aspeed/M
[U-Boot] [PATCH v1 05/15] aspeed: Reset Driver
Add Reset Driver for ast2500 SoC. This driver uses Watchdog Timer to
perform resets and thus depends on it. The actual Watchdog device used
needs to be configured in Device Tree using "aspeed,wdt" property, which
must be WDT phandle, for example:
rst: reset-controller {
compatible = "aspeed,ast2500-reset";
aspeed,wdt = <&wdt1>;
}
Signed-off-by: Maxim Sloyko
---
Changes in v1:
- Remove unnecessary check for error in dev_get_priv
- Fix comment
- Rename wdt_reset call to wdt_expire_now
---
arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 28 +++
drivers/reset/Kconfig | 10 +++
drivers/reset/Makefile | 1 +
drivers/reset/ast2500-reset.c | 106 +
4 files changed, 145 insertions(+)
create mode 100644 drivers/reset/ast2500-reset.c
diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
index 0fa3ecb9b9..e2556f920d 100644
--- a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
+++ b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
@@ -31,6 +31,34 @@
#define SCU_MISC_UARTCLK_DIV13 (1 << 12)
+/*
+ * SYSRESET is actually more like a Power register,
+ * except that corresponding bit set to 1 means that
+ * the peripheral is off.
+ */
+#define SCU_SYSRESET_XDMA (1 << 25)
+#define SCU_SYSRESET_MCTP (1 << 24)
+#define SCU_SYSRESET_ADC (1 << 23)
+#define SCU_SYSRESET_JTAG (1 << 22)
+#define SCU_SYSRESET_MIC (1 << 18)
+#define SCU_SYSRESET_SDIO (1 << 16)
+#define SCU_SYSRESET_USB11HOST (1 << 15)
+#define SCU_SYSRESET_USBHUB(1 << 14)
+#define SCU_SYSRESET_CRT (1 << 13)
+#define SCU_SYSRESET_MAC2 (1 << 12)
+#define SCU_SYSRESET_MAC1 (1 << 11)
+#define SCU_SYSRESET_PECI (1 << 10)
+#define SCU_SYSRESET_PWM (1 << 9)
+#define SCU_SYSRESET_PCI_VGA (1 << 8)
+#define SCU_SYSRESET_2D(1 << 7)
+#define SCU_SYSRESET_VIDEO (1 << 6)
+#define SCU_SYSRESET_LPC (1 << 5)
+#define SCU_SYSRESET_HAC (1 << 4)
+#define SCU_SYSRESET_USBHID(1 << 3)
+#define SCU_SYSRESET_I2C (1 << 2)
+#define SCU_SYSRESET_AHB (1 << 1)
+#define SCU_SYSRESET_SDRAM_WDT (1 << 0)
+
#ifndef __ASSEMBLY__
struct ast2500_clk_priv {
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index c42b0bcf0e..eb54189d4b 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -43,4 +43,14 @@ config RESET_UNIPHIER
Say Y if you want to control reset signals provided by System Control
block, Media I/O block, Peripheral Block.
+config AST2500_RESET
+ bool "Reset controller driver for AST2500 SoCs"
+ depends on DM_RESET && WDT_ASPEED
+ default y if ASPEED_AST2500
+ help
+ Support for reset controller on AST2500 SoC. This controller uses
+ watchdog to reset different peripherals and thus only supports
+ resets that are supported by watchdog. The main limitation though
+ is that some reset signals, like I2C or MISC reset multiple devices.
+
endmenu
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 5c4305cc1d..16ad7eed5b 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset-test.o
obj-$(CONFIG_TEGRA_CAR_RESET) += tegra-car-reset.o
obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o
obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
+obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o
diff --git a/drivers/reset/ast2500-reset.c b/drivers/reset/ast2500-reset.c
new file mode 100644
index 00..b2c89e1f1e
--- /dev/null
+++ b/drivers/reset/ast2500-reset.c
@@ -0,0 +1,106 @@
+/*
+ * Copyright 2017 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct ast2500_reset_priv {
+ /* WDT used to perform resets. */
+ struct udevice *wdt;
+ struct ast2500_scu *scu;
+};
+
+static int ast2500_ofdata_to_platdata(struct udevice *dev)
+{
+ struct ast2500_reset_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = uclass_get_device_by_phandle(UCLASS_WDT, dev, "aspeed,wdt",
+ &priv->wdt);
+ if (ret) {
+ debug("%s: can't find WDT for reset controller", __func__);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int ast2500_reset_assert(struct reset_ctl *reset_ctl)
+{
+ struct ast2500_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+ u32 reset_mode, reset_mask;
+ bool reset_sdram;
+ int ret;
+
+ /*
+* To reset SDRAM, a specifal flag in SYSRESET register
+* needs to be enabled
[U-Boot] [PATCH v1 14/15] aspeed: Refactor SCU to use consistent mask & shift
Refactor SCU header to use consistent Mask & Shift values.
Now, consistently, to read value from SCU register, mask needs
to be applied before shift.
Signed-off-by: Maxim Sloyko
---
Changes in v1: None
arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 12
arch/arm/mach-aspeed/ast2500/sdram_ast2500.c | 5 ++--
drivers/clk/aspeed/clk_ast2500.c | 39 +-
3 files changed, 27 insertions(+), 29 deletions(-)
diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
index fe877b5430..590aed2f6c 100644
--- a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
+++ b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
@@ -8,8 +8,8 @@
#define SCU_UNLOCK_VALUE 0x1688a8a8
-#define SCU_HWSTRAP_VGAMEM_MASK3
#define SCU_HWSTRAP_VGAMEM_SHIFT 2
+#define SCU_HWSTRAP_VGAMEM_MASK(3 << SCU_HWSTRAP_VGAMEM_SHIFT)
#define SCU_HWSTRAP_MAC1_RGMII (1 << 6)
#define SCU_HWSTRAP_MAC2_RGMII (1 << 7)
#define SCU_HWSTRAP_DDR4 (1 << 24)
@@ -18,17 +18,17 @@
#define SCU_MPLL_DENUM_SHIFT 0
#define SCU_MPLL_DENUM_MASK0x1f
#define SCU_MPLL_NUM_SHIFT 5
-#define SCU_MPLL_NUM_MASK 0xff
+#define SCU_MPLL_NUM_MASK (0xff << SCU_MPLL_NUM_SHIFT)
#define SCU_MPLL_POST_SHIFT13
-#define SCU_MPLL_POST_MASK 0x3f
+#define SCU_MPLL_POST_MASK (0x3f << SCU_MPLL_POST_SHIFT)
#define SCU_PCLK_DIV_SHIFT 23
-#define SCU_PCLK_DIV_MASK 7
+#define SCU_PCLK_DIV_MASK (7 << SCU_PCLK_DIV_SHIFT)
#define SCU_HPLL_DENUM_SHIFT 0
#define SCU_HPLL_DENUM_MASK0x1f
#define SCU_HPLL_NUM_SHIFT 5
-#define SCU_HPLL_NUM_MASK 0xff
+#define SCU_HPLL_NUM_MASK (0xff << SCU_HPLL_NUM_SHIFT)
#define SCU_HPLL_POST_SHIFT13
-#define SCU_HPLL_POST_MASK 0x3f
+#define SCU_HPLL_POST_MASK (0x3f << SCU_HPLL_POST_SHIFT)
#define SCU_MACCLK_SHIFT 16
#define SCU_MACCLK_MASK(7 << SCU_MACCLK_SHIFT)
diff --git a/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
b/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
index efcf452b17..6383f727f2 100644
--- a/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
+++ b/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
@@ -183,9 +183,8 @@ static int ast2500_sdrammc_ddr4_calibrate_vref(struct
dram_info *info)
static size_t ast2500_sdrammc_get_vga_mem_size(struct dram_info *info)
{
size_t vga_mem_size_base = 8 * 1024 * 1024;
- u32 vga_hwconf = (readl(&info->scu->hwstrap)
- >> SCU_HWSTRAP_VGAMEM_SHIFT)
- & SCU_HWSTRAP_VGAMEM_MASK;
+ u32 vga_hwconf = (readl(&info->scu->hwstrap) & SCU_HWSTRAP_VGAMEM_MASK)
+ >> SCU_HWSTRAP_VGAMEM_SHIFT;
return vga_mem_size_base << vga_hwconf;
}
diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c
index 7b4b5c64ac..ccf47a1da1 100644
--- a/drivers/clk/aspeed/clk_ast2500.c
+++ b/drivers/clk/aspeed/clk_ast2500.c
@@ -52,11 +52,11 @@ struct ast2500_div_config {
*/
static ulong ast2500_get_mpll_rate(ulong clkin, u32 mpll_reg)
{
- const ulong num = (mpll_reg >> SCU_MPLL_NUM_SHIFT) & SCU_MPLL_NUM_MASK;
- const ulong denum = (mpll_reg >> SCU_MPLL_DENUM_SHIFT)
- & SCU_MPLL_DENUM_MASK;
- const ulong post_div = (mpll_reg >> SCU_MPLL_POST_SHIFT)
- & SCU_MPLL_POST_MASK;
+ const ulong num = (mpll_reg & SCU_MPLL_NUM_MASK) >> SCU_MPLL_NUM_SHIFT;
+ const ulong denum = (mpll_reg & SCU_MPLL_DENUM_MASK)
+ >> SCU_MPLL_DENUM_SHIFT;
+ const ulong post_div = (mpll_reg & SCU_MPLL_POST_MASK)
+ >> SCU_MPLL_POST_SHIFT;
return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1);
}
@@ -67,11 +67,11 @@ static ulong ast2500_get_mpll_rate(ulong clkin, u32
mpll_reg)
*/
static ulong ast2500_get_hpll_rate(ulong clkin, u32 hpll_reg)
{
- const ulong num = (hpll_reg >> SCU_HPLL_NUM_SHIFT) & SCU_HPLL_NUM_MASK;
- const ulong denum = (hpll_reg >> SCU_HPLL_DENUM_SHIFT)
- & SCU_HPLL_DENUM_MASK;
- const ulong post_div = (hpll_reg >> SCU_HPLL_POST_SHIFT)
- & SCU_HPLL_POST_MASK;
+ const ulong num = (hpll_reg & SCU_HPLL_NUM_MASK) >> SCU_HPLL_NUM_SHIFT;
+ const ulong denum = (hpll_reg & SCU_HPLL_DENUM_MASK)
+ >> SCU_HPLL_DENUM_SHIFT;
+ const ulong post_div = (hpll_reg & SCU_HPLL_POST_MASK)
+ >> SCU_HPLL_POST_SHIFT;
return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1);
}
@@ -136,11 +136,11 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
case BCLK_PCLK:
{
ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1
