[U-Boot] [PATCH] configs: imx6: Select missing BOARD_LATE_INIT

2017-03-23 Thread Jagan Teki
From: Jagan Teki 

Select missing BOARD_LATE_INIT from configs/ to
respective targets on arch area for Engicam imx6 boards.

Cc: Tom Rini 
Cc: Stefano Babic 
Cc: Michael Trimarchi 
Signed-off-by: Jagan Teki 
---
 arch/arm/cpu/armv7/mx6/Kconfig | 2 ++
 configs/imx6dl_icore_rqs_mmc_defconfig | 1 -
 configs/imx6q_icore_rqs_mmc_defconfig  | 1 -
 configs/imx6ul_isiot_emmc_defconfig| 1 -
 configs/imx6ul_isiot_mmc_defconfig | 1 -
 configs/imx6ul_isiot_nand_defconfig| 1 -
 6 files changed, 2 insertions(+), 5 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index 190e5c6..9174136 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -172,6 +172,7 @@ config TARGET_MX6Q_ICORE
 
 config TARGET_MX6Q_ICORE_RQS
bool "Support Engicam i.Core RQS"
+   select BOARD_LATE_INIT
select MX6QDL
select OF_CONTROL
select DM
@@ -253,6 +254,7 @@ config TARGET_MX6UL_GEAM
select SUPPORT_SPL
 config TARGET_MX6UL_ISIOT
bool "Support Engicam Is.IoT MX6UL"
+   select BOARD_LATE_INIT
select MX6UL
select OF_CONTROL
select DM
diff --git a/configs/imx6dl_icore_rqs_mmc_defconfig 
b/configs/imx6dl_icore_rqs_mmc_defconfig
index f521292..64fa2ec 100644
--- a/configs/imx6dl_icore_rqs_mmc_defconfig
+++ b/configs/imx6dl_icore_rqs_mmc_defconfig
@@ -38,4 +38,3 @@ CONFIG_FEC_MXC=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
 CONFIG_MXC_UART=y
-CONFIG_BOARD_LATE_INIT=y
diff --git a/configs/imx6q_icore_rqs_mmc_defconfig 
b/configs/imx6q_icore_rqs_mmc_defconfig
index 6bd3387..6bbdfa8 100644
--- a/configs/imx6q_icore_rqs_mmc_defconfig
+++ b/configs/imx6q_icore_rqs_mmc_defconfig
@@ -38,4 +38,3 @@ CONFIG_FEC_MXC=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
 CONFIG_MXC_UART=y
-CONFIG_BOARD_LATE_INIT=y
diff --git a/configs/imx6ul_isiot_emmc_defconfig 
b/configs/imx6ul_isiot_emmc_defconfig
index 4c3664f..94fe808 100644
--- a/configs/imx6ul_isiot_emmc_defconfig
+++ b/configs/imx6ul_isiot_emmc_defconfig
@@ -37,4 +37,3 @@ CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
 CONFIG_MXC_UART=y
 CONFIG_IMX_THERMAL=y
-CONFIG_BOARD_LATE_INIT=y
diff --git a/configs/imx6ul_isiot_mmc_defconfig 
b/configs/imx6ul_isiot_mmc_defconfig
index ea2d378..8ecdd8e 100644
--- a/configs/imx6ul_isiot_mmc_defconfig
+++ b/configs/imx6ul_isiot_mmc_defconfig
@@ -39,4 +39,3 @@ CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
 CONFIG_MXC_UART=y
 CONFIG_IMX_THERMAL=y
-CONFIG_BOARD_LATE_INIT=y
diff --git a/configs/imx6ul_isiot_nand_defconfig 
b/configs/imx6ul_isiot_nand_defconfig
index f02a2ac..6f1a054 100644
--- a/configs/imx6ul_isiot_nand_defconfig
+++ b/configs/imx6ul_isiot_nand_defconfig
@@ -40,4 +40,3 @@ CONFIG_PINCTRL_IMX6=y
 CONFIG_SYS_I2C_MXC=y
 CONFIG_MXC_UART=y
 CONFIG_IMX_THERMAL=y
-CONFIG_BOARD_LATE_INIT=y
-- 
1.9.1

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Re: [U-Boot] [PATCH 05/21] phy: Add STi phy usb support

2017-03-23 Thread Patrice CHOTARD
Hi Simon

On 03/22/2017 02:06 PM, Simon Glass wrote:
> Hi,
>
> On 17 March 2017 at 10:25,   wrote:
>> From: Patrice Chotard 
>>
>> This is the generic phy driver for the picoPHY ports
>> used by USB2 and USB3 Host controllers available on
>> STiH407 SoC families.
>>
>> Signed-off-by: Patrice Chotard 
>> ---
>>  configs/stih410-b2260_defconfig |   1 +
>>  drivers/usb/Kconfig |   4 +
>>  drivers/usb/phy/Kconfig |  11 +++
>>  drivers/usb/phy/Makefile|   1 +
>>  drivers/usb/phy/sti_phy_usb.c   | 158 
>> 
>>  5 files changed, 175 insertions(+)
>>  create mode 100644 drivers/usb/phy/Kconfig
>>  create mode 100644 drivers/usb/phy/sti_phy_usb.c
>
> Really we should have a UCLASS_USB_PHY for this. Can you work up a
> simple implementation as a starting point?

Yes, no problem, i will add a usb phy implementation in my next series

Patrice

>
> Regards,
> Simon
>
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[U-Boot] [PATCH 1/7] SECURE BOOT: Add header address of PPA in kconfig

2017-03-23 Thread Sumit Garg
From: Vinitha Pillai-B57223 

The header address of PPA defined in Kconfig.

Signed-off-by: Vinitha Pillai 
Signed-off-by: Sumit Garg 
---
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 11 +++
 arch/arm/cpu/armv8/fsl-layerscape/ppa.c   |  2 +-
 arch/arm/include/asm/fsl_secure_boot.h| 12 ++--
 3 files changed, 14 insertions(+), 11 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index a99b1c6..10efb8c 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -154,6 +154,17 @@ config SYS_LS_PPA_FW_ADDR
  QSPI flash, this address is a directly memory-mapped.
  If it is in a serial accessed flash, such as NAND and SD
  card, it is a byte offset.
+
+config SYS_LS_PPA_ESBC_ADDR
+   hex "hdr address of PPA firmware loading from"
+   depends on FSL_LS_PPA && CHAIN_OF_TRUST
+   default 0x600c if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A
+   help
+ If the PPA header firmware locate at XIP flash, such as NOR or
+ QSPI flash, this address is a directly memory-mapped.
+ If it is in a serial accessed flash, such as NAND and SD
+ card, it is a byte offset.
+
 endmenu
 
 config SYS_FSL_ERRATUM_A010315
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c 
b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
index b68e87d..cb16925 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
@@ -42,7 +42,7 @@ int ppa_init(void)
ppa_img_addr = (uintptr_t)ppa_fit_addr;
if (fsl_check_boot_mode_secure() != 0) {
ret = fsl_secboot_validate(ppa_esbc_hdr,
-  CONFIG_PPA_KEY_HASH,
+  PPA_KEY_HASH,
   &ppa_img_addr);
if (ret != 0)
printf("PPA validation failed\n");
diff --git a/arch/arm/include/asm/fsl_secure_boot.h 
b/arch/arm/include/asm/fsl_secure_boot.h
index fd627c0..a1a3004 100644
--- a/arch/arm/include/asm/fsl_secure_boot.h
+++ b/arch/arm/include/asm/fsl_secure_boot.h
@@ -109,21 +109,13 @@
 #endif
 
 #ifdef CONFIG_FSL_LS_PPA
-#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
-#ifdef CONFIG_LS1043A
-#define CONFIG_SYS_LS_PPA_ESBC_ADDR0x600c
-#endif
-#else
-#error "No CONFIG_SYS_LS_PPA_FW_IN_xxx defined"
-#endif /* ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP */
-
 /* Define the key hash here if SRK used for signing PPA image is
  * different from SRK hash put in SFP used for U-Boot.
  * Example
  * #define CONFIG_PPA_KEY_HASH \
- * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b"
+ * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b"
  */
-#define CONFIG_PPA_KEY_HASHNULL
+#define PPA_KEY_HASHNULL
 #endif /* ifdef CONFIG_FSL_LS_PPA */
 
 #include 
-- 
1.9.1

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[U-Boot] [PATCH 0/7] Add LS1046 and LS1012 secure boot targets

2017-03-23 Thread Sumit Garg
Purpose of patchset:

1. This consolidated patchset supersedes earlier patchset for LS1046
   and LS1012 secure boot target addition patchsets as they have inter-
   dependency.
2. Rebased and incorporated review comments.
3. Enabling PPA in secure boot via Kconfig option similar to non-secure
   boot for LS1043, LS1012 and LS1046.

Following are patchwork links of earlier patchset:

LS1046 secure boot targets (v3 patchset):
-
https://patchwork.ozlabs.org/patch/711699/
https://patchwork.ozlabs.org/patch/711698/
https://patchwork.ozlabs.org/patch/711701/

LS1012 secure boot target (v1 patchset):
-
https://patchwork.ozlabs.org/patch/691306/
https://patchwork.ozlabs.org/patch/691305/

Also this patchset include patches to enable PPA in secure boot for
LS1043 via Kconfig option.

  SECURE BOOT: Add header address of PPA in kconfig
  LS1043ARDB: Enable PPA in Secure boot defconfig
  SECURE_BOOT: Enable chain of trust on LS1046A platform
  LS1046AQDS: Add NOR Secure Boot Target
  LS1046ARDB: Add QSPI Secure Boot target
  SECURE_BOOT: Enable chain of trust on LS1012A platform
  LS1012ARDB: Add QSPI Secure Boot target

 arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 13 ++
 arch/arm/cpu/armv8/fsl-layerscape/ppa.c   |  2 +-
 arch/arm/include/asm/arch-fsl-layerscape/config.h |  9 -
 arch/arm/include/asm/fsl_secure_boot.h| 33 +---
 board/freescale/ls1012ardb/MAINTAINERS|  4 ++
 board/freescale/ls1012ardb/ls1012ardb.c   |  5 +++
 board/freescale/ls1046aqds/MAINTAINERS|  4 ++
 board/freescale/ls1046aqds/ls1046aqds.c   | 19 +
 board/freescale/ls1046ardb/Kconfig|  2 +-
 board/freescale/ls1046ardb/MAINTAINERS|  4 ++
 board/freescale/ls1046ardb/ls1046ardb.c   | 19 +
 configs/ls1012ardb_qspi_SECURE_BOOT_defconfig | 48 +++
 configs/ls1043ardb_SECURE_BOOT_defconfig  |  1 +
 configs/ls1046aqds_SECURE_BOOT_defconfig  | 39 ++
 configs/ls1046ardb_qspi_SECURE_BOOT_defconfig | 37 +
 include/configs/ls1012a_common.h  |  2 -
 include/configs/ls1012ardb.h  |  3 ++
 include/configs/ls1046ardb.h  |  2 +
 18 files changed, 226 insertions(+), 20 deletions(-)
 create mode 100644 configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
 create mode 100644 configs/ls1046aqds_SECURE_BOOT_defconfig
 create mode 100644 configs/ls1046ardb_qspi_SECURE_BOOT_defconfig

-- 
1.9.1

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[U-Boot] [PATCH 3/7] SECURE_BOOT: Enable chain of trust on LS1046A platform

2017-03-23 Thread Sumit Garg
From: Vinitha Pillai-B57223 

Define bootscript and its header addresses for QSPI target. Also
define PPA header address to enable PPA validation.

Signed-off-by: Vinitha Pillai 
Signed-off-by: Sumit Garg 
---
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig |  1 +
 arch/arm/include/asm/arch-fsl-layerscape/config.h |  2 +-
 arch/arm/include/asm/fsl_secure_boot.h| 18 ++
 3 files changed, 16 insertions(+), 5 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 10efb8c..fbb6642 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -159,6 +159,7 @@ config SYS_LS_PPA_ESBC_ADDR
hex "hdr address of PPA firmware loading from"
depends on FSL_LS_PPA && CHAIN_OF_TRUST
default 0x600c if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A
+   default 0x4074 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A
help
  If the PPA header firmware locate at XIP flash, such as NOR or
  QSPI flash, this address is a directly memory-mapped.
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h 
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index b5b08aa..1f22afd 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -199,7 +199,7 @@
 
 #define CONFIG_SYS_FSL_IFC_BE
 #define CONFIG_SYS_FSL_SFP_VER_3_2
-#define CONFIG_SYS_FSL_SNVS_LE
+#define CONFIG_SYS_FSL_SEC_MON_BE
 #define CONFIG_SYS_FSL_SFP_BE
 #define CONFIG_SYS_FSL_SRK_LE
 #define CONFIG_KEY_REVOCATION
diff --git a/arch/arm/include/asm/fsl_secure_boot.h 
b/arch/arm/include/asm/fsl_secure_boot.h
index a1a3004..423c2c4 100644
--- a/arch/arm/include/asm/fsl_secure_boot.h
+++ b/arch/arm/include/asm/fsl_secure_boot.h
@@ -46,9 +46,10 @@
 
 #endif
 
-#if defined(CONFIG_LS1043A) || defined(CONFIG_LS2080A)
-/* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit
- * Similiarly for LS2080
+#if defined(CONFIG_FSL_LAYERSCAPE)
+/*
+ * For fsl layerscape based platforms, ESBC image Address in Header
+ * is 64 bit.
  */
 #define CONFIG_ESBC_ADDR_64BIT
 #endif
@@ -90,12 +91,21 @@
 #define CONFIG_BS_ADDR_DEVICE  0x0940
 #define CONFIG_BS_HDR_SIZE 0x0010
 #define CONFIG_BS_SIZE 0x0008
+#elif defined(CONFIG_QSPI_BOOT)
+#ifdef CONFIG_ARCH_LS1046A
+#define CONFIG_BS_HDR_ADDR_DEVICE  0x4078
+#define CONFIG_BS_ADDR_DEVICE  0x4080
 #else
+#error "Platform not supported"
+#endif
+#define CONFIG_BS_HDR_SIZE 0x2000
+#define CONFIG_BS_SIZE 0x1000
+#else /* Default NOR Boot */
 #define CONFIG_BS_HDR_ADDR_DEVICE  0x600a
 #define CONFIG_BS_ADDR_DEVICE  0x6006
 #define CONFIG_BS_HDR_SIZE 0x2000
 #define CONFIG_BS_SIZE 0x1000
-#endif /* #ifdef CONFIG_SD_BOOT */
+#endif
 #define CONFIG_BS_HDR_ADDR_RAM 0x8100
 #define CONFIG_BS_ADDR_RAM 0x8102
 #endif
-- 
1.9.1

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[U-Boot] [PATCH 2/7] LS1043ARDB: Enable PPA in Secure boot defconfig

2017-03-23 Thread Sumit Garg
From: Vinitha Pillai-B57223 

Enable PPA in secure boot by defining FSL_LS_PPA macro in its defconfig
file.

Signed-off-by: Vinitha Pillai 
Signed-off-by: Sumit Garg 
---
 configs/ls1043ardb_SECURE_BOOT_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig 
b/configs/ls1043ardb_SECURE_BOOT_defconfig
index 6f86877..861d49b 100644
--- a/configs/ls1043ardb_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_SECURE_BOOT_defconfig
@@ -3,6 +3,7 @@ CONFIG_TARGET_LS1043ARDB=y
 CONFIG_SECURE_BOOT=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
 CONFIG_FIT=y
+CONFIG_FSL_LS_PPA=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_BOOTDELAY=10
-- 
1.9.1

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[U-Boot] [PATCH 4/7] LS1046AQDS: Add NOR Secure Boot Target

2017-03-23 Thread Sumit Garg
Add NOR secure boot target. Also enable sec init.

Signed-off-by: Vinitha Pillai 
Signed-off-by: Sumit Garg 
---
 board/freescale/ls1046aqds/MAINTAINERS   |  4 
 board/freescale/ls1046aqds/ls1046aqds.c  | 19 
 configs/ls1046aqds_SECURE_BOOT_defconfig | 39 
 3 files changed, 62 insertions(+)
 create mode 100644 configs/ls1046aqds_SECURE_BOOT_defconfig

diff --git a/board/freescale/ls1046aqds/MAINTAINERS 
b/board/freescale/ls1046aqds/MAINTAINERS
index b4549ae..6737d55 100644
--- a/board/freescale/ls1046aqds/MAINTAINERS
+++ b/board/freescale/ls1046aqds/MAINTAINERS
@@ -8,3 +8,7 @@ F:  configs/ls1046aqds_nand_defconfig
 F: configs/ls1046aqds_sdcard_ifc_defconfig
 F: configs/ls1046aqds_sdcard_qspi_defconfig
 F: configs/ls1046aqds_qspi_defconfig
+
+M: Sumit Garg 
+S: Maintained
+F: configs/ls1046aqds_SECURE_BOOT_defconfig
diff --git a/board/freescale/ls1046aqds/ls1046aqds.c 
b/board/freescale/ls1046aqds/ls1046aqds.c
index af3f70a..8def6e6 100644
--- a/board/freescale/ls1046aqds/ls1046aqds.c
+++ b/board/freescale/ls1046aqds/ls1046aqds.c
@@ -21,6 +21,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #include "../common/vid.h"
@@ -265,6 +266,24 @@ int board_init(void)
if (adjust_vdd(0))
printf("Warning: Adjusting core voltage failed.\n");
 
+#ifdef CONFIG_SECURE_BOOT
+   /*
+* In case of Secure Boot, the IBR configures the SMMU
+* to allow only Secure transactions.
+* SMMU must be reset in bypass mode.
+* Set the ClientPD bit and Clear the USFCFG Bit
+*/
+   u32 val;
+   val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
+   out_le32(SMMU_SCR0, val);
+   val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
+   out_le32(SMMU_NSCR0, val);
+#endif
+
+#ifdef CONFIG_FSL_CAAM
+   sec_init();
+#endif
+
return 0;
 }
 
diff --git a/configs/ls1046aqds_SECURE_BOOT_defconfig 
b/configs/ls1046aqds_SECURE_BOOT_defconfig
new file mode 100644
index 000..dc16fa0
--- /dev/null
+++ b/configs/ls1046aqds_SECURE_BOOT_defconfig
@@ -0,0 +1,39 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1046AQDS=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_SECURE_BOOT=y
+CONFIG_BOOTDELAY=10
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_RSA=y
-- 
1.9.1

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[U-Boot] [PATCH 5/7] LS1046ARDB: Add QSPI Secure Boot target

2017-03-23 Thread Sumit Garg
From: Vinitha Pillai-B57223 

Add QSPI Secure Boot target. Also enable sec init.

Signed-off-by: Vinitha Pillai 
Signed-off-by: Sumit Garg 
---
 board/freescale/ls1046ardb/Kconfig|  2 +-
 board/freescale/ls1046ardb/MAINTAINERS|  4 +++
 board/freescale/ls1046ardb/ls1046ardb.c   | 19 ++
 configs/ls1046ardb_qspi_SECURE_BOOT_defconfig | 37 +++
 include/configs/ls1046ardb.h  |  2 ++
 5 files changed, 63 insertions(+), 1 deletion(-)
 create mode 100644 configs/ls1046ardb_qspi_SECURE_BOOT_defconfig

diff --git a/board/freescale/ls1046ardb/Kconfig 
b/board/freescale/ls1046ardb/Kconfig
index a62255c..b9f2ed7 100644
--- a/board/freescale/ls1046ardb/Kconfig
+++ b/board/freescale/ls1046ardb/Kconfig
@@ -12,5 +12,5 @@ config SYS_SOC
 
 config SYS_CONFIG_NAME
default "ls1046ardb"
-
+source "board/freescale/common/Kconfig"
 endif
diff --git a/board/freescale/ls1046ardb/MAINTAINERS 
b/board/freescale/ls1046ardb/MAINTAINERS
index ff42bef..758ff9d 100644
--- a/board/freescale/ls1046ardb/MAINTAINERS
+++ b/board/freescale/ls1046ardb/MAINTAINERS
@@ -7,3 +7,7 @@ F:  include/configs/ls1046ardb.h
 F: configs/ls1046ardb_qspi_defconfig
 F: configs/ls1046ardb_sdcard_defconfig
 F: configs/ls1046ardb_emmc_defconfig
+
+M: Sumit Garg 
+S: Maintained
+F: configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
diff --git a/board/freescale/ls1046ardb/ls1046ardb.c 
b/board/freescale/ls1046ardb/ls1046ardb.c
index 02b6c4c..df69dcf 100644
--- a/board/freescale/ls1046ardb/ls1046ardb.c
+++ b/board/freescale/ls1046ardb/ls1046ardb.c
@@ -21,6 +21,7 @@
 #include 
 #include 
 #include "cpld.h"
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -71,6 +72,24 @@ int board_init(void)
enable_layerscape_ns_access();
 #endif
 
+#ifdef CONFIG_SECURE_BOOT
+   /*
+* In case of Secure Boot, the IBR configures the SMMU
+* to allow only Secure transactions.
+* SMMU must be reset in bypass mode.
+* Set the ClientPD bit and Clear the USFCFG Bit
+*/
+   u32 val;
+   val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
+   out_le32(SMMU_SCR0, val);
+   val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
+   out_le32(SMMU_NSCR0, val);
+#endif
+
+#ifdef CONFIG_FSL_CAAM
+   sec_init();
+#endif
+
 #ifdef CONFIG_FSL_LS_PPA
ppa_init();
 #endif
diff --git a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig 
b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
new file mode 100644
index 000..af14e19
--- /dev/null
+++ b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
@@ -0,0 +1,37 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1046ARDB=y
+CONFIG_FSL_LS_PPA=y
+CONFIG_QSPI_AHB_INIT=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_QSPI_BOOT=y
+CONFIG_SECURE_BOOT=y
+CONFIG_BOOTDELAY=10
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_RSA=y
diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h
index 2141b82..196db81 100644
--- a/include/configs/ls1046ardb.h
+++ b/include/configs/ls1046ardb.h
@@ -239,4 +239,6 @@
"7e80.flash:16m(nand_uboot)," \
"48m(nand_kernel),448m(nand_free)"
 
+#include 
+
 #endif /* __LS1046ARDB_H__ */
-- 
1.9.1

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[U-Boot] [PATCH 7/7] LS1012ARDB: Add QSPI Secure Boot target

2017-03-23 Thread Sumit Garg
From: Vinitha Pillai-B57223 

Add QSPI Secure Boot target to enable chain of trust

Signed-off-by: Sumit Garg 
Signed-off-by: Vinitha Pillai 
Reviewed-by: Ruchika Gupta 
---
 board/freescale/ls1012ardb/MAINTAINERS|  4 +++
 board/freescale/ls1012ardb/ls1012ardb.c   |  5 +++
 configs/ls1012ardb_qspi_SECURE_BOOT_defconfig | 48 +++
 include/configs/ls1012a_common.h  |  2 --
 include/configs/ls1012ardb.h  |  3 ++
 5 files changed, 60 insertions(+), 2 deletions(-)
 create mode 100644 configs/ls1012ardb_qspi_SECURE_BOOT_defconfig

diff --git a/board/freescale/ls1012ardb/MAINTAINERS 
b/board/freescale/ls1012ardb/MAINTAINERS
index 79a2a7d..2cb38e7 100644
--- a/board/freescale/ls1012ardb/MAINTAINERS
+++ b/board/freescale/ls1012ardb/MAINTAINERS
@@ -4,3 +4,7 @@ S:  Maintained
 F: board/freescale/ls1012ardb/
 F: include/configs/ls1012ardb.h
 F: configs/ls1012ardb_qspi_defconfig
+
+M: Sumit Garg 
+S: Maintained
+F: configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
diff --git a/board/freescale/ls1012ardb/ls1012ardb.c 
b/board/freescale/ls1012ardb/ls1012ardb.c
index a23a23b..a21e4c4 100644
--- a/board/freescale/ls1012ardb/ls1012ardb.c
+++ b/board/freescale/ls1012ardb/ls1012ardb.c
@@ -22,6 +22,7 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -118,6 +119,10 @@ int board_init(void)
gd->env_addr = (ulong)&default_environment[0];
 #endif
 
+#ifdef CONFIG_FSL_CAAM
+   sec_init();
+#endif
+
 #ifdef CONFIG_FSL_LS_PPA
ppa_init();
 #endif
diff --git a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig 
b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
new file mode 100644
index 000..97f49d5
--- /dev/null
+++ b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
@@ -0,0 +1,48 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1012ARDB=y
+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+# CONFIG_CMD_IMLS is not set
+CONFIG_SYS_NS16550=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
+CONFIG_FSL_LS_PPA=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SECURE_BOOT=y
+CONFIG_QSPI_BOOT=y
+CONFIG_BOOTDELAY=10
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_STORAGE=y
+CONFIG_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
index af07672..c36736f 100644
--- a/include/configs/ls1012a_common.h
+++ b/include/configs/ls1012a_common.h
@@ -122,6 +122,4 @@
 #define CONFIG_PANIC_HANG
 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)  /* Increase max gunzip size */
 
-#include 
-
 #endif /* __LS1012A_COMMON_H */
diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
index 70d3a71..276fe10 100644
--- a/include/configs/ls1012ardb.h
+++ b/include/configs/ls1012ardb.h
@@ -74,4 +74,7 @@
 #define CONFIG_SYS_MEMTEST_START   0x8000
 #define CONFIG_SYS_MEMTEST_END 0x9fff
 
+
+#include 
+
 #endif /* __LS1012ARDB_H__ */
-- 
1.9.1

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[U-Boot] [PATCH 6/7] SECURE_BOOT: Enable chain of trust on LS1012A platform

2017-03-23 Thread Sumit Garg
From: Vinitha Pillai-B57223 

Define bootscript and its header addresses for QSPI target
Also add PPA header address in Kconfig

Signed-off-by: Vinitha Pillai 
Signed-off-by: Sumit Garg 
---
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 1 +
 arch/arm/include/asm/arch-fsl-layerscape/config.h | 7 ++-
 arch/arm/include/asm/fsl_secure_boot.h| 3 +++
 3 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index fbb6642..03bc9ea 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -160,6 +160,7 @@ config SYS_LS_PPA_ESBC_ADDR
depends on FSL_LS_PPA && CHAIN_OF_TRUST
default 0x600c if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A
default 0x4074 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A
+   default 0x4048 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A
help
  If the PPA header firmware locate at XIP flash, such as NOR or
  QSPI flash, this address is a directly memory-mapped.
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h 
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 1f22afd..4db11b6 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -185,7 +185,12 @@
 #elif defined(CONFIG_ARCH_LS1012A)
 #define GICD_BASE  0x01401000
 #define GICC_BASE  0x01402000
-
+#define CONFIG_SYS_FSL_SFP_VER_3_2
+#define CONFIG_SYS_FSL_SEC_MON_BE
+#define CONFIG_SYS_FSL_SFP_BE
+#define CONFIG_SYS_FSL_SRK_LE
+#define CONFIG_KEY_REVOCATION
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC   1
 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
 #define CONFIG_MAX_MEM_MAPPED  CONFIG_SYS_DDR_BLOCK1_SIZE
 
diff --git a/arch/arm/include/asm/fsl_secure_boot.h 
b/arch/arm/include/asm/fsl_secure_boot.h
index 423c2c4..69cd35d 100644
--- a/arch/arm/include/asm/fsl_secure_boot.h
+++ b/arch/arm/include/asm/fsl_secure_boot.h
@@ -95,6 +95,9 @@
 #ifdef CONFIG_ARCH_LS1046A
 #define CONFIG_BS_HDR_ADDR_DEVICE  0x4078
 #define CONFIG_BS_ADDR_DEVICE  0x4080
+#elif defined(CONFIG_ARCH_LS1012A)
+#define CONFIG_BS_HDR_ADDR_DEVICE  0x400c
+#define CONFIG_BS_ADDR_DEVICE  0x4006
 #else
 #error "Platform not supported"
 #endif
-- 
1.9.1

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Re: [U-Boot] [PATCH v2 17/20] arm: socfpga: Convert Altera ddr driver to use Kconfig

2017-03-23 Thread Marek Vasut
On 03/23/2017 06:36 AM, Ley Foon Tan wrote:
> On Wed, Mar 22, 2017 at 10:26 PM, Marek Vasut  wrote:
>> On 03/22/2017 10:45 AM, Ley Foon Tan wrote:
>>> On Fri, Mar 10, 2017 at 9:53 AM, Marek Vasut  wrote:
 On 03/09/2017 01:26 AM, Ley Foon Tan wrote:
> Convert Altera ddr driver to use Kconfig method. Enable ALTERA_SDRAM
> by default if it is on Gen5 target. Arria 10 will have different driver.
>
> Signed-off-by: Tien Fong Chee 
> Signed-off-by: Ley Foon Tan 
> ---
>  drivers/Kconfig  | 2 ++
>  drivers/ddr/Kconfig  | 1 +
>  drivers/ddr/altera/Kconfig   | 6 ++
>  include/configs/socfpga_common.h | 5 -
>  4 files changed, 9 insertions(+), 5 deletions(-)
>  create mode 100644 drivers/ddr/Kconfig
>  create mode 100644 drivers/ddr/altera/Kconfig
>
> diff --git a/drivers/Kconfig b/drivers/Kconfig
> index 0e5d97d..3e6bbac 100644
> --- a/drivers/Kconfig
> +++ b/drivers/Kconfig
> @@ -14,6 +14,8 @@ source "drivers/cpu/Kconfig"
>
>  source "drivers/crypto/Kconfig"
>
> +source "drivers/ddr/Kconfig"
> +
>  source "drivers/demo/Kconfig"
>
>  source "drivers/ddr/fsl/Kconfig"
> diff --git a/drivers/ddr/Kconfig b/drivers/ddr/Kconfig
> new file mode 100644
> index 000..b764add
> --- /dev/null
> +++ b/drivers/ddr/Kconfig
> @@ -0,0 +1 @@
> +source "drivers/ddr/altera/Kconfig"
> diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig
> new file mode 100644
> index 000..9554da7
> --- /dev/null
> +++ b/drivers/ddr/altera/Kconfig
> @@ -0,0 +1,6 @@
> +config ALTERA_SDRAM
> + bool "SoCFPGA SDRAM for Arria5/Cyclone5 devices"

 Does this controller even support SDRAM ? :)
>>> The existing DDR driver is for Gen5 only. We will have new DDR driver
>>> for Arria 10 in later patchset.
>>
>> I was asking about the SDRAM support in Gen5 controller though :)
> Yes, it support for double data rate 2 (DDR2), DDR3, and low-power
> DDR2 (LPDDR2) SDRAM.

Ah, so a misnomer . I'd prefer to have something like "SoCFPGA DRAM
controller ... or SoCFPGA DDR SDRAM controller" in the Kconfig option to
make it clear.

-- 
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH v2] spl: add support to booting with ATF

2017-03-23 Thread Andre Przywara
Hi Kever,

I was wondering if we really need to copy in all those ATF definitions.
I think this is really an *interface* between the loader (SPL or BL2)
and the runtime services (BL31), so it's supposed to be stable and we
wouldn't need to pull in all those headers.

So given that, can't we simply model the data structure, which at the
end of the day is just a bunch of simple data types:

struct param_header_t {
uint8_t type;   /* type of the structure */
uint8_t version;/* version of this structure */
uint16_t size;  /* size of this structure in bytes */
uint32_t attr;  /* attributes: unused bits SBZ */

struct entry_point_info_t {
struct param_header_t h;
uintptr_t pc;
uint32_t spsr;
unsigned long args[8]; /* struct aapcs64_params_t args; */

struct atf_image_info_t {
struct param_header_t h;
uintptr_t image_base;   /* physical address of base of image */
uint32_t image_size;/* bytes read from image file */


struct bl31_params_t {
struct param_header_t h;
struct atf_image_info_t *bl31_image_info;
struct entry_point_info_t *bl32_ep_info;
.

Whenever this gets changed we are in trouble anyway (because we break
compatibility).

So what are the opinions on this? Pull in the ATF source or define our
own and mark it as an ATF copy?

Cheers,
Andre.

On 23/03/17 03:00, Kever Yang wrote:
> ATF(ARM Trusted Firmware) is used by ARM arch64 SoCs, find more infomation
> about ATF at: https://github.com/ARM-software/arm-trusted-firmware
> 
> SPL is considered as BL2 in ATF terminology, it needs to load other parts
> of ATF binary like BL31, BL32, SCP-BL30, and BL33(U-Boot). And needs to
> prepare the parameter for BL31 which including entry and image information
> for all other images. Then the SPL handle PC to BL31 with the parameter,
> the BL31 will do the rest of work and at last get into U-Boot(BL33).
> 
> Signed-off-by: Kever Yang 
> ---
> 
> Changes in v2:
> - Kconfig comment update with Simon's suggestion
> - including file ordering,
> - update function comment format,
> - use 'if' instead of '#ifdef' for bl31_entry
> - add ATF Kconfig option depend on ARM64
> Series-changes: 1
> - license update
> - split out as separate patch
> 
>  common/spl/Kconfig   |  14 +++
>  common/spl/Makefile  |   1 +
>  common/spl/spl.c |   3 +
>  common/spl/spl_atf.c |  96 ++
>  include/atf_common.h | 276 
> +++
>  include/spl.h|   1 +
>  6 files changed, 391 insertions(+)
>  create mode 100644 common/spl/spl_atf.c
>  create mode 100644 include/atf_common.h
> 
> diff --git a/common/spl/Kconfig b/common/spl/Kconfig
> index 60ae60c..1b7fb8d 100644
> --- a/common/spl/Kconfig
> +++ b/common/spl/Kconfig
> @@ -670,6 +670,20 @@ config SPL_YMODEM_SUPPORT
> means of transmitting U-Boot over a serial line for using in SPL,
> with a checksum to ensure correctness.
>  
> +config SPL_ATF_SUPPORT
> + bool "Support ARM Trusted Firmware"
> + depends on SPL && ARM64
> + help
> +   ATF(ARM Trusted Firmware) is a component for ARM arch64 which which
> +   is loaded by SPL(which is considered as BL2 in ATF terminology).
> +   More detail at: https://github.com/ARM-software/arm-trusted-firmware
> +
> +config SPL_ATF_TEXT_BASE
> + depends on SPL_ATF_SUPPORT
> + hex "ATF TEXT BASE addr"
> + help
> +   This is the base address in memory for ATF text and entry point.
> +
>  config TPL_ENV_SUPPORT
>   bool "Support an environment"
>   depends on TPL
> diff --git a/common/spl/Makefile b/common/spl/Makefile
> index 1933cbd..b3b34d6 100644
> --- a/common/spl/Makefile
> +++ b/common/spl/Makefile
> @@ -20,6 +20,7 @@ endif
>  obj-$(CONFIG_SPL_UBI) += spl_ubi.o
>  obj-$(CONFIG_SPL_NET_SUPPORT) += spl_net.o
>  obj-$(CONFIG_SPL_MMC_SUPPORT) += spl_mmc.o
> +obj-$(CONFIG_SPL_ATF_SUPPORT) += spl_atf.o
>  obj-$(CONFIG_SPL_USB_SUPPORT) += spl_usb.o
>  obj-$(CONFIG_SPL_FAT_SUPPORT) += spl_fat.o
>  obj-$(CONFIG_SPL_EXT_SUPPORT) += spl_ext.o
> diff --git a/common/spl/spl.c b/common/spl/spl.c
> index 26bc9ef..7041e1b 100644
> --- a/common/spl/spl.c
> +++ b/common/spl/spl.c
> @@ -374,6 +374,9 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
> gd->malloc_ptr / 1024);
>  #endif
>  
> + if (IS_ENABLED(CONFIG_SPL_ATF_SUPPORT))
> + bl31_entry();
> +
>   debug("loaded - jumping to U-Boot...\n");
>   spl_board_prepare_for_boot();
>   jump_to_image_no_args(&spl_image);
> diff --git a/common/spl/spl_atf.c b/common/spl/spl_atf.c
> new file mode 100644
> index 000..38753d7
> --- /dev/null
> +++ b/common/spl/spl_atf.c
> @@ -0,0 +1,96 @@
> +/*
> + * Reference to the ARM TF Project,
> + * plat/arm/common/arm_bl2_setup.c
> + * Portions copyright (c) 2013-2016, ARM Limited and Contributors. All rights
> + * reserved.
> + * Copyright (C) 2016 Rockchip Electronic Co.,

Re: [U-Boot] [PATCH 3/3 v3] controlcenterdc: Make secure boot available

2017-03-23 Thread Stefan Roese
Hi Mario,

On 22.02.2017 16:07, Mario Six wrote:
> Make secure booting available for the controlcenterdc
> board.
> 
> Signed-off-by: Reinhard Pfau 
> Signed-off-by: Mario Six 
> ---
> Changes in v3:
> 
> * Added secure boot options to config to enable secure boot by default
> 
> Changes in v2:
> 
> * Moved definition and interpretation of SECURED_MODE_IMAGE and
>   SECURED_MODE_CSK_INDEX to previous patch

When trying to compile with these patches applied, I get this
error:

[stefan@stefan-work u-boot-marvell (master)]$ make -s -j10
Couldn't open RSA private key: './kwb_csk.key': No such file or directory
Failed to load CSK
Could not create image
Makefile:982: recipe for target 'u-boot-spl.kwb' failed

We need to find a way, to compile for this board without such errors.
Perhaps by providing a "default key"? Any ideas?

Thanks,
Stefan
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Re: [U-Boot] [PATCH 3/3 v3] controlcenterdc: Make secure boot available

2017-03-23 Thread Mario Six
On Thu, Mar 23, 2017 at 10:31 AM, Stefan Roese  wrote:
> Hi Mario,
>
> On 22.02.2017 16:07, Mario Six wrote:
>> Make secure booting available for the controlcenterdc
>> board.
>>
>> Signed-off-by: Reinhard Pfau 
>> Signed-off-by: Mario Six 
>> ---
>> Changes in v3:
>>
>> * Added secure boot options to config to enable secure boot by default
>>
>> Changes in v2:
>>
>> * Moved definition and interpretation of SECURED_MODE_IMAGE and
>>   SECURED_MODE_CSK_INDEX to previous patch
>
> When trying to compile with these patches applied, I get this
> error:
>
> [stefan@stefan-work u-boot-marvell (master)]$ make -s -j10
> Couldn't open RSA private key: './kwb_csk.key': No such file or directory
> Failed to load CSK
> Could not create image
> Makefile:982: recipe for target 'u-boot-spl.kwb' failed
>
> We need to find a way, to compile for this board without such errors.
> Perhaps by providing a "default key"? Any ideas?
>
> Thanks,
> Stefan
>

Hi Stefan,

Hm, yes, for automatic building, the need to put the KAK and CSK keys somewhere
is problematic; didn't consider that, sorry.

The easiest way would probably be to have some Makefile check for the existence
of kwb_kak.key and kwb_csk.key in the root directory, and create them if they
don't exists, using

openssl genrsa -out kwb_kak.key 2048 openssl genrsa -out kwb_csk.key 2048

But I am not quite sure where to put those checks/instructions in a
non-disruptive manner.

Best regards,

Mario
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Re: [U-Boot] [PATCH v2 17/20] arm: socfpga: Convert Altera ddr driver to use Kconfig

2017-03-23 Thread Ley Foon Tan
On Thu, Mar 23, 2017 at 3:39 PM, Marek Vasut  wrote:
> On 03/23/2017 06:36 AM, Ley Foon Tan wrote:
>> On Wed, Mar 22, 2017 at 10:26 PM, Marek Vasut  wrote:
>>> On 03/22/2017 10:45 AM, Ley Foon Tan wrote:
 On Fri, Mar 10, 2017 at 9:53 AM, Marek Vasut  wrote:
> On 03/09/2017 01:26 AM, Ley Foon Tan wrote:
>> Convert Altera ddr driver to use Kconfig method. Enable ALTERA_SDRAM
>> by default if it is on Gen5 target. Arria 10 will have different driver.
>>
>> Signed-off-by: Tien Fong Chee 
>> Signed-off-by: Ley Foon Tan 
>> ---
>>  drivers/Kconfig  | 2 ++
>>  drivers/ddr/Kconfig  | 1 +
>>  drivers/ddr/altera/Kconfig   | 6 ++
>>  include/configs/socfpga_common.h | 5 -
>>  4 files changed, 9 insertions(+), 5 deletions(-)
>>  create mode 100644 drivers/ddr/Kconfig
>>  create mode 100644 drivers/ddr/altera/Kconfig
>>
>> diff --git a/drivers/Kconfig b/drivers/Kconfig
>> index 0e5d97d..3e6bbac 100644
>> --- a/drivers/Kconfig
>> +++ b/drivers/Kconfig
>> @@ -14,6 +14,8 @@ source "drivers/cpu/Kconfig"
>>
>>  source "drivers/crypto/Kconfig"
>>
>> +source "drivers/ddr/Kconfig"
>> +
>>  source "drivers/demo/Kconfig"
>>
>>  source "drivers/ddr/fsl/Kconfig"
>> diff --git a/drivers/ddr/Kconfig b/drivers/ddr/Kconfig
>> new file mode 100644
>> index 000..b764add
>> --- /dev/null
>> +++ b/drivers/ddr/Kconfig
>> @@ -0,0 +1 @@
>> +source "drivers/ddr/altera/Kconfig"
>> diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig
>> new file mode 100644
>> index 000..9554da7
>> --- /dev/null
>> +++ b/drivers/ddr/altera/Kconfig
>> @@ -0,0 +1,6 @@
>> +config ALTERA_SDRAM
>> + bool "SoCFPGA SDRAM for Arria5/Cyclone5 devices"
>
> Does this controller even support SDRAM ? :)
 The existing DDR driver is for Gen5 only. We will have new DDR driver
 for Arria 10 in later patchset.
>>>
>>> I was asking about the SDRAM support in Gen5 controller though :)
>> Yes, it support for double data rate 2 (DDR2), DDR3, and low-power
>> DDR2 (LPDDR2) SDRAM.
>
> Ah, so a misnomer . I'd prefer to have something like "SoCFPGA DRAM
> controller ... or SoCFPGA DDR SDRAM controller" in the Kconfig option to
> make it clear.
>
Okay, will change it to "SoCFPGA DDR SDRAM controller".

Thanks.

Regards
Ley Foon
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Re: [U-Boot] [PATCH 06/21] usb: ehci: Add STi ehci support

2017-03-23 Thread Patrice CHOTARD
Hi Simon

On 03/22/2017 02:05 PM, Simon Glass wrote:
> Hi,
>
> On 17 March 2017 at 10:25,   wrote:
>> From: Patrice Chotard 
>>
>> Add support for on-chip ehci controller available
>> on STMicrolectronics SoCs.
>> ehci support will be then available on both type A
>> USB 2.0 connectors.
>>
>> Signed-off-by: Patrice Chotard 
>> ---
>>  drivers/usb/host/Kconfig|  9 +
>>  drivers/usb/host/Makefile   |  1 +
>>  drivers/usb/host/ehci-sti.c | 91 
>> +
>>  3 files changed, 101 insertions(+)
>>  create mode 100644 drivers/usb/host/ehci-sti.c
>>
>> diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
>> index 5129a57..d66f49e 100644
>> --- a/drivers/usb/host/Kconfig
>> +++ b/drivers/usb/host/Kconfig
>> @@ -120,6 +120,15 @@ config USB_EHCI_MSM
>>   This driver supports combination of Chipidea USB controller
>>   and Synapsys USB PHY in host mode only.
>>
>> +config USB_EHCI_STI
>> +   bool "Support for STMicroelectronics on-chip EHCI USB controller"
>> +   depends on ARCH_STI
>> +   select STI_PHY_USB
>> +   default y
>> +   ---help---
>> + Enables support for the on-chip EHCI controller on
>> + STMicroelectronics SoCs.
>> +
>>  config USB_EHCI_ZYNQ
>> bool "Support for Xilinx Zynq on-chip EHCI USB controller"
>> depends on ARCH_ZYNQ
>> diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
>> index 58c0cf5..303aa32 100644
>> --- a/drivers/usb/host/Makefile
>> +++ b/drivers/usb/host/Makefile
>> @@ -46,6 +46,7 @@ obj-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o
>>  obj-$(CONFIG_USB_EHCI_MSM) += ehci-msm.o
>>  obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
>>  obj-$(CONFIG_USB_EHCI_SPEAR) += ehci-spear.o
>> +obj-$(CONFIG_USB_EHCI_STI) += ehci-sti.o
>>  obj-$(CONFIG_USB_EHCI_SUNXI) += ehci-sunxi.o
>>  obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
>>  obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
>> diff --git a/drivers/usb/host/ehci-sti.c b/drivers/usb/host/ehci-sti.c
>> new file mode 100644
>> index 000..89ca66a
>> --- /dev/null
>> +++ b/drivers/usb/host/ehci-sti.c
>> @@ -0,0 +1,91 @@
>> +/*
>> + * Copyright (c) 2017
>> + * Patrice Chotard 
>> + *
>> + * SPDX-License-Identifier:GPL-2.0+
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include "ehci.h"
>> +#include 
>> +#include 
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +struct sti_ehci_priv {
>> +   struct ehci_ctrl ctrl;
>> +   struct reset_ctl power_ctl;
>> +   struct reset_ctl softreset_ctl;
>> +};
>> +
>> +static int sti_ehci_probe(struct udevice *dev)
>> +{
>> +   struct sti_ehci_priv *priv = dev_get_priv(dev);
>> +   struct ehci_hccr *hccr = priv->ctrl.hccr;
>> +   struct ehci_hcor *hcor;
>> +   struct udevice *dev_phy;
>> +   int ret, phy_node;
>> +
>> +   hccr = (struct ehci_hccr *)dev_get_addr(dev);
>> +
>> +   if (hccr == (void *)FDT_ADDR_T_NONE)
>> +   return -EINVAL;
>> +
>> +   ret = reset_get_by_name(dev, "power", &priv->power_ctl);
>
> This is OK, but can you instead access it via a phandle in the device's node?

Sorry i didn't get your point. Why getting it using a phandle ?

>
>> +   if (ret) {
>> +   error("can't get power reset for %s (%d)", dev->name, ret);
>> +   return ret;
>> +   }
>> +
>> +   ret = reset_get_by_name(dev, "softreset", &priv->softreset_ctl);
>> +   if (ret) {
>> +   error("can't get soft reset for %s (%d)", dev->name, ret);
>> +   return ret;
>> +   }
>> +
>> +   ret = reset_deassert(&priv->power_ctl);
>> +   if (ret < 0) {
>> +   error("EHCI power reset deassert failed: %d", ret);
>> +   return ret;
>> +   }
>> +
>> +   ret = reset_deassert(&priv->softreset_ctl);
>> +   if (ret < 0) {
>> +   error("EHCI soft reset deassert failed: %d", ret);
>> +   return ret;
>> +   }
>> +
>> +   /* get phy node */
>> +   phy_node = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset, 
>> "phys");
>> +   if (phy_node <= 0) {
>> +   error("Not found usb phy device\n");
>> +   return -ENODEV;
>> +   }
>> +
>> +   /* probe associated phy */
>> +   ret = uclass_get_device_by_of_offset(UCLASS_MISC, phy_node, 
>> &dev_phy);
>
> Instead of the above two calls, can you use uclass_get_device_by_phandle()?

Yes, agree, i will also apply this to ohci-sti.c and xhci-sti.c which 
are similar .

Thanks

Patrice

>
>> +
>> +   hcor = (struct ehci_hcor *)((phys_addr_t)hccr +
>> +   HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));
>> +
>> +   return ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST);
>> +}
>> +
>> +static const struct udevice_id sti_usb_ids[] = {
>> +   { .compatible = "st,st-ehci-300x" },
>> +   { }
>> +};
>> +
>> +U_BOOT_DRIVER(ehci_sti) = {
>> +   .name = "ehci_sti",
>> +   .id = UCLASS_USB,
>> + 

Re: [U-Boot] [PATCH 3/3 v3] controlcenterdc: Make secure boot available

2017-03-23 Thread Stefan Roese

On 23.03.2017 10:45, Mario Six wrote:

On Thu, Mar 23, 2017 at 10:31 AM, Stefan Roese  wrote:

Hi Mario,

On 22.02.2017 16:07, Mario Six wrote:

Make secure booting available for the controlcenterdc
board.

Signed-off-by: Reinhard Pfau 
Signed-off-by: Mario Six 
---
Changes in v3:

* Added secure boot options to config to enable secure boot by default

Changes in v2:

* Moved definition and interpretation of SECURED_MODE_IMAGE and
  SECURED_MODE_CSK_INDEX to previous patch


When trying to compile with these patches applied, I get this
error:

[stefan@stefan-work u-boot-marvell (master)]$ make -s -j10
Couldn't open RSA private key: './kwb_csk.key': No such file or directory
Failed to load CSK
Could not create image
Makefile:982: recipe for target 'u-boot-spl.kwb' failed

We need to find a way, to compile for this board without such errors.
Perhaps by providing a "default key"? Any ideas?

Thanks,
Stefan



Hi Stefan,

Hm, yes, for automatic building, the need to put the KAK and CSK keys somewhere
is problematic; didn't consider that, sorry.

The easiest way would probably be to have some Makefile check for the existence
of kwb_kak.key and kwb_csk.key in the root directory, and create them if they
don't exists, using

openssl genrsa -out kwb_kak.key 2048 openssl genrsa -out kwb_csk.key 2048


Sounds like a doable solution.


But I am not quite sure where to put those checks/instructions in a
non-disruptive manner.


Perhaps its better, to place those files into the board directory,
for cases, where multiple targets with different keys are being
built?

I'm currently busy with collecting most pending mvebu patches for
a pull request now. To get this going, I'll probably drop this
last patch from you (patch 3/3) for now, to get the remaining
stuff into mainline.

This way, you will have a bit more time to figure this out in an
acceptable way.

Thanks,
Stefan
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Re: [U-Boot] [PATCH 3/3 v3] controlcenterdc: Make secure boot available

2017-03-23 Thread Mario Six
On Thu, Mar 23, 2017 at 11:04 AM, Stefan Roese  wrote:
> On 23.03.2017 10:45, Mario Six wrote:
>>
>> On Thu, Mar 23, 2017 at 10:31 AM, Stefan Roese  wrote:
>>>
>>> Hi Mario,
>>>
>>> On 22.02.2017 16:07, Mario Six wrote:

 Make secure booting available for the controlcenterdc
 board.

 Signed-off-by: Reinhard Pfau 
 Signed-off-by: Mario Six 
 ---
 Changes in v3:

 * Added secure boot options to config to enable secure boot by default

 Changes in v2:

 * Moved definition and interpretation of SECURED_MODE_IMAGE and
   SECURED_MODE_CSK_INDEX to previous patch
>>>
>>>
>>> When trying to compile with these patches applied, I get this
>>> error:
>>>
>>> [stefan@stefan-work u-boot-marvell (master)]$ make -s -j10
>>> Couldn't open RSA private key: './kwb_csk.key': No such file or directory
>>> Failed to load CSK
>>> Could not create image
>>> Makefile:982: recipe for target 'u-boot-spl.kwb' failed
>>>
>>> We need to find a way, to compile for this board without such errors.
>>> Perhaps by providing a "default key"? Any ideas?
>>>
>>> Thanks,
>>> Stefan
>>>
>>
>> Hi Stefan,
>>
>> Hm, yes, for automatic building, the need to put the KAK and CSK keys
>> somewhere
>> is problematic; didn't consider that, sorry.
>>
>> The easiest way would probably be to have some Makefile check for the
>> existence
>> of kwb_kak.key and kwb_csk.key in the root directory, and create them if
>> they
>> don't exists, using
>>
>> openssl genrsa -out kwb_kak.key 2048 openssl genrsa -out kwb_csk.key 2048
>
>
> Sounds like a doable solution.
>
>> But I am not quite sure where to put those checks/instructions in a
>> non-disruptive manner.
>
>
> Perhaps its better, to place those files into the board directory,
> for cases, where multiple targets with different keys are being
> built?
>
> I'm currently busy with collecting most pending mvebu patches for
> a pull request now. To get this going, I'll probably drop this
> last patch from you (patch 3/3) for now, to get the remaining
> stuff into mainline.
>
> This way, you will have a bit more time to figure this out in an
> acceptable way.
>
>
> Thanks,
> Stefan
>

OK, that's fine with me. Thanks for testing!

Best regards,

Mario
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[U-Boot] [PATCH] arm64/ls1046a: Enable ERRATUM_A008850 for ls1046a SoC

2017-03-23 Thread Shengzhou Liu
Signed-off-by: Shengzhou Liu 
---
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index a99b1c6..25588c8 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -36,6 +36,7 @@ config ARCH_LS1046A
select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A008336
select SYS_FSL_ERRATUM_A008511
+   select SYS_FSL_ERRATUM_A008850
select SYS_FSL_ERRATUM_A009801
select SYS_FSL_ERRATUM_A009803
select SYS_FSL_ERRATUM_A009942
-- 
2.1.0.27.g96db324

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Re: [U-Boot] [PATCH v3 0/6] board: sama5d3: convert boards to support DM/DT

2017-03-23 Thread Andy Pont
Wenyou Yang wrote...

> The purpose of patch set is to convert the board to support device
> tree and driver model, and enable the early debug UART as well.
> It is based on the patch set:
>   [PATCH v8 0/2] pinctrl: at91: Add pinctrl driver
>   https://lists.denx.de/pipermail/u-boot/2017-March/284577.html

I was going to test these out on my SAMA5D31EK but it appears to be bricked as 
the only output I get at power-on is a single "RomBOOT" and SAM-BA doesn't seem 
to want to connect.

Is there any way I can de-brick the board so I can test these patches?

Thanks,

Andy.



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Re: [U-Boot] [PATCH 3/7] i2c: lpc32xx: Factor out i2c_adapter parameter

2017-03-23 Thread Heiko Schocher

Hello Sylvain,

Am 14.03.2017 um 16:24 schrieb Sylvain Lemieux:

From: Liam Beguin 

This is part of the prep work for the migration to the driver model.
It will enable the driver to support DM and non-DM configurations
using the same functions.

Signed-off-by: Liam Beguin 
Signed-off-by: Sylvain Lemieux 
---
  drivers/i2c/lpc32xx_i2c.c | 107 +++---
  1 file changed, 53 insertions(+), 54 deletions(-)


I am fine with this patch, but checkpatch says:

CHECK: Alignment should match open parenthesis
#270: FILE: drivers/i2c/lpc32xx_i2c.c:248:
+   __i2c_init(lpc32xx_i2c[adap->hwadapnr], requested_speed, slaveadd,
+   adap->hwadapnr);

Could you fix this please?

bye,
Heiko


diff --git a/drivers/i2c/lpc32xx_i2c.c b/drivers/i2c/lpc32xx_i2c.c
index e5dfdfe1df..62d2d7eee5 100644
--- a/drivers/i2c/lpc32xx_i2c.c
+++ b/drivers/i2c/lpc32xx_i2c.c
@@ -29,7 +29,7 @@
  #endif

  /* i2c register set */
-struct lpc32xx_i2c_registers {
+struct lpc32xx_i2c_base {
union {
u32 rx;
u32 tx;
@@ -61,15 +61,15 @@ struct lpc32xx_i2c_registers {
  #define LPC32XX_I2C_STAT_NAI  0x0004
  #define LPC32XX_I2C_STAT_TDI  0x0001

-static struct lpc32xx_i2c_registers *lpc32xx_i2c[] = {
-   (struct lpc32xx_i2c_registers *)I2C1_BASE,
-   (struct lpc32xx_i2c_registers *)I2C2_BASE,
-   (struct lpc32xx_i2c_registers *)(USB_BASE + 0x300)
+static struct lpc32xx_i2c_base *lpc32xx_i2c[] = {
+   (struct lpc32xx_i2c_base *)I2C1_BASE,
+   (struct lpc32xx_i2c_base *)I2C2_BASE,
+   (struct lpc32xx_i2c_base *)(USB_BASE + 0x300)
  };

  /* Set I2C bus speed */
-static unsigned int __i2c_set_bus_speed(struct i2c_adapter *adap,
-   unsigned int speed)
+static unsigned int __i2c_set_bus_speed(struct lpc32xx_i2c_base *base,
+   unsigned int speed, unsigned int chip)
  {
int half_period;

@@ -77,7 +77,7 @@ static unsigned int __i2c_set_bus_speed(struct i2c_adapter 
*adap,
return -EINVAL;

/* OTG I2C clock source and CLK registers are different */
-   if (adap->hwadapnr == 2) {
+   if (chip == 2) {
half_period = (get_periph_clk_rate() / speed) / 2;
if (half_period > 0xFF)
return -EINVAL;
@@ -87,38 +87,35 @@ static unsigned int __i2c_set_bus_speed(struct i2c_adapter 
*adap,
return -EINVAL;
}

-   writel(half_period, &lpc32xx_i2c[adap->hwadapnr]->clk_hi);
-   writel(half_period, &lpc32xx_i2c[adap->hwadapnr]->clk_lo);
+   writel(half_period, &base->clk_hi);
+   writel(half_period, &base->clk_lo);
return 0;
  }

  /* I2C init called by cmd_i2c when doing 'i2c reset'. */
-static void __i2c_init(struct i2c_adapter *adap,
-   int requested_speed, int slaveadd)
+static void __i2c_init(struct lpc32xx_i2c_base *base,
+  int requested_speed, int slaveadd, unsigned int chip)
  {
-   struct lpc32xx_i2c_registers *i2c = lpc32xx_i2c[adap->hwadapnr];
-
/* soft reset (auto-clears) */
-   writel(LPC32XX_I2C_SOFT_RESET, &i2c->ctrl);
+   writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
/* set HI and LO periods for half of the default speed */
-   __i2c_set_bus_speed(adap, requested_speed);
+   __i2c_set_bus_speed(base, requested_speed, chip);
  }

  /* I2C probe called by cmd_i2c when doing 'i2c probe'. */
-static int __i2c_probe_chip(struct i2c_adapter *adap, u8 dev)
+static int __i2c_probe_chip(struct lpc32xx_i2c_base *base, u8 dev)
  {
-   struct lpc32xx_i2c_registers *i2c = lpc32xx_i2c[adap->hwadapnr];
int stat;

/* Soft-reset the controller */
-   writel(LPC32XX_I2C_SOFT_RESET, &i2c->ctrl);
-   while (readl(&i2c->ctrl) & LPC32XX_I2C_SOFT_RESET)
+   writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
+   while (readl(&base->ctrl) & LPC32XX_I2C_SOFT_RESET)
;
/* Addre slave for write with start before and stop after */
writel((dev<<1) | LPC32XX_I2C_TX_START | LPC32XX_I2C_TX_STOP,
-  &i2c->tx);
+  &base->tx);
/* wait for end of transation */
-   while (!((stat = readl(&i2c->stat)) & LPC32XX_I2C_STAT_TDI))
+   while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
;
/* was there no acknowledge? */
return (stat & LPC32XX_I2C_STAT_NAI) ? -1 : 0;
@@ -128,20 +125,19 @@ static int __i2c_probe_chip(struct i2c_adapter *adap, u8 
dev)
   * I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c
   * Begin write, send address byte(s), begin read, receive data bytes, end.
   */
-static int __i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
-int alen, u8 *data, int length)
+static int __i2c_read(struct lpc32xx_i2c_base *base, u8 dev, uint addr,
+ int alen, u8 *data, int length)
  {
-

Re: [U-Boot] [PATCH 4/7] i2c: lpc32xx: Add DM for lpc32xx I2C

2017-03-23 Thread Heiko Schocher

Hello Sylvain,

Am 14.03.2017 um 16:24 schrieb Sylvain Lemieux:

From: Liam Beguin 

Adding DM specific wrapper functions and definitions.

Signed-off-by: Liam Beguin 
Signed-off-by: Sylvain Lemieux 
---
  drivers/i2c/lpc32xx_i2c.c | 91 +++
  1 file changed, 91 insertions(+)


Checkpatch says:

ERROR: code indent should use tabs where possible
#88: FILE: drivers/i2c/lpc32xx_i2c.c:320:
+^I^I  u32 chip_flags)$

total: 1 errors, 0 warnings, 0 checks, 122 lines checked

Could you please fix, thanks!

bye,
Heiko


diff --git a/drivers/i2c/lpc32xx_i2c.c b/drivers/i2c/lpc32xx_i2c.c
index 62d2d7eee5..17e8b744e5 100644
--- a/drivers/i2c/lpc32xx_i2c.c
+++ b/drivers/i2c/lpc32xx_i2c.c
@@ -15,6 +15,8 @@
  #include 
  #include 
  #include 
+#include 
+#include 

  /*
   * Provide default speed and slave if target did not
@@ -47,6 +49,14 @@ struct lpc32xx_i2c_base {
u32 stxfl;
  };

+#ifdef CONFIG_DM_I2C
+struct lpc32xx_i2c_dev {
+   struct lpc32xx_i2c_base *base;
+   int index;
+   uint speed;
+};
+#endif /* CONFIG_DM_I2C */
+
  /* TX register fields */
  #define LPC32XX_I2C_TX_START  0x0100
  #define LPC32XX_I2C_TX_STOP   0x0200
@@ -61,11 +71,13 @@ struct lpc32xx_i2c_base {
  #define LPC32XX_I2C_STAT_NAI  0x0004
  #define LPC32XX_I2C_STAT_TDI  0x0001

+#ifndef CONFIG_DM_I2C
  static struct lpc32xx_i2c_base *lpc32xx_i2c[] = {
(struct lpc32xx_i2c_base *)I2C1_BASE,
(struct lpc32xx_i2c_base *)I2C2_BASE,
(struct lpc32xx_i2c_base *)(USB_BASE + 0x300)
  };
+#endif

  /* Set I2C bus speed */
  static unsigned int __i2c_set_bus_speed(struct lpc32xx_i2c_base *base,
@@ -241,6 +253,7 @@ static int __i2c_write(struct lpc32xx_i2c_base *base, u8 
dev, uint addr,
return 0;
  }

+#ifndef CONFIG_DM_I2C
  static void lpc32xx_i2c_init(struct i2c_adapter *adap,
 int requested_speed, int slaveadd)
  {
@@ -294,3 +307,80 @@ U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_2, lpc32xx_i2c_init, NULL,
 10,
 0,
 2)
+#else /* CONFIG_DM_I2C */
+static int lpc32xx_i2c_probe(struct udevice *bus)
+{
+   struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
+
+   __i2c_init(dev->base, dev->speed, 0, dev->index);
+   return 0;
+}
+
+static int lpc32xx_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
+ u32 chip_flags)
+{
+   struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
+   return __i2c_probe_chip(dev->base, chip_addr);
+}
+
+static int lpc32xx_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
+   int nmsgs)
+{
+   struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
+   struct i2c_msg *dmsg, *omsg, dummy;
+   uint i = 0, address = 0;
+
+   memset(&dummy, 0, sizeof(struct i2c_msg));
+
+   /* We expect either two messages (one with an offset and one with the
+* actual data) or one message (just data)
+*/
+   if (nmsgs > 2 || nmsgs == 0) {
+   debug("%s: Only one or two messages are supported.", __func__);
+   return -1;
+   }
+
+   omsg = nmsgs == 1 ? &dummy : msg;
+   dmsg = nmsgs == 1 ? msg : msg + 1;
+
+   /* the address is expected to be a uint, not a array. */
+   address = omsg->buf[0];
+   for (i = 1; i < omsg->len; i++)
+   address = (address << 8) + omsg->buf[i];
+
+   if (dmsg->flags & I2C_M_RD)
+   return __i2c_read(dev->base, dmsg->addr, address,
+ omsg->len, dmsg->buf, dmsg->len);
+   else
+   return __i2c_write(dev->base, dmsg->addr, address,
+  omsg->len, dmsg->buf, dmsg->len);
+}
+
+static int lpc32xx_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
+{
+   struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
+   return __i2c_set_bus_speed(dev->base, speed, dev->index);
+}
+
+static int lpc32xx_i2c_reset(struct udevice *bus)
+{
+   struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
+
+   __i2c_init(dev->base, dev->speed, 0, dev->index);
+   return 0;
+}
+
+static const struct dm_i2c_ops lpc32xx_i2c_ops = {
+   .xfer  = lpc32xx_i2c_xfer,
+   .probe_chip= lpc32xx_i2c_probe_chip,
+   .deblock   = lpc32xx_i2c_reset,
+   .set_bus_speed = lpc32xx_i2c_set_bus_speed,
+};
+
+U_BOOT_DRIVER(i2c_lpc32xx) = {
+   .id   = UCLASS_I2C,
+   .name = "i2c_lpc32xx",
+   .probe= lpc32xx_i2c_probe,
+   .ops  = &lpc32xx_i2c_ops,
+};
+#endif /* CONFIG_DM_I2C */



--
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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[U-Boot] fatls returncode

2017-03-23 Thread Mirza Krak
Hi.

I am running U-boot 2015.04 and experiencing some issues with "fatls" command.

We use the "fatls" command to detect if there is an USB storage device
plugged in the port during boot (might be better ways of doing this).
So on boot we have:

   fatls usb 0:1 && 

Normally "fatls" returns "0" when it does a successful list. But we
have found a case where it does not even though everything seems to
work fine. Below is a log with debug enabled (obfuscated filenames
since I got this flash drive from a customer).

MX-4 C61 # fatls usb 0:1
VFAT Support enabled
FAT32, fat_sect: 1146, fatlength: 7619
Rootdir begins at cluster: 2, sector: 16384, offset: 80
Data begins at: 16368
Sector size: 512, cluster size: 8
FAT read(sect=16384, cnt:8), clust_size=8, DIRENTSPERBLOCK=16
system volume information/
bin/
boot/
etc/
i4m/
lib/
sbin/
share/
 1530   file1.sh
15542   file2.sh
 1745   file3.sh
 4609   file4.sh
END LOOP: buffer_blk_cnt=0   clust_size=8
 1547   file5.sh
22361   file6.sh
   385078   file7.sh
33279   file8.sh
  1152054   file9.sh
   158132   file10.sh
 1473   file11.sh
 9739   file12.sh
   318780   file13.sh
END LOOP: buffer_blk_cnt=1   clust_size=8
 34027520   file14.sh
 1246   file15.sh
 1246   file16.sh
END LOOP: buffer_blk_cnt=2   clust_size=8
END LOOP: buffer_blk_cnt=3   clust_size=8
END LOOP: buffer_blk_cnt=4   clust_size=8
END LOOP: buffer_blk_cnt=5   clust_size=8
END LOOP: buffer_blk_cnt=6   clust_size=8
END LOOP: buffer_blk_cnt=7   clust_size=8
FAT32: entry: 0x0002 = 2, offset: 0x0002 = 2
FAT32: ret: 0fff, offset: 0002

16 file(s), 8 dir(s)

MX-4 C61 # echo $?
1

Even though the file list seems to be OK, the return code indicates an error.

I am wondering if we need to set "ret = 0" in below code-path (which
the exit path in above output)

fs/fat/fat.c:

1139 /* If end of rootdir reached */
1140 if (rootdir_end) {
1141 if (dols == LS_ROOT) {
1142 printf("\n%d file(s), %d dir(s)\n\n",
1143files, dirs);
1144 *size = 0;
1145 }
1146 goto exit;
1147 }

-- 
Med Vänliga Hälsningar / Best Regards

***
Mirza Krak
Host Mobility AB
mirza.k...@hostmobility.com
Anders Personsgatan 12, 416 64 Göteborg
Sweden
http://www.hostmobility.com
Direct: +46 31 31 32 704
Phone: +46 31 31 32 700
Fax: +46 31 80 67 51
Mobile: +46 730 28 06 22
***
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[U-Boot] [PATCH 0/7] *** SUBJECT HERE ***

2017-03-23 Thread make
From: Ken Ma 

*** BLURB HERE ***
1. Move base, max_lun and max_id such scsi generic data from platdata to uclass 
plat data;
2. Make scsi compatible for legacy SCSI devices and new SAS controller
   - Introduce scsi bus DT node, scsi work as bus and scsi disks, scsi scanner 
and sata are
 its children scsi device; this is similar to the case that spi bus manages 
spi flashes;
 In such case, scsi bus probe should probe its children devices 
automatically;
   - SAS controller can also be a scsi node as current.
3. Example with mvebu armada 3700 scsi bus node

Ken Ma (7):
  scsi: move base, max_lun and max_id to uclass plat data
  scsi: add children devices binding
  scsi: call children devices' probe functions automatically
  scsi: dt-bindings: add scsi device tree bindings
  scsi: mvebu: add scsi driver
  scsi: a3700: enable mvebu scsi driver
  scsi: dts: a3700: add scsi node

 arch/arm/dts/armada-3720-db.dts|  4 ++
 arch/arm/dts/armada-37xx.dtsi  | 16 +--
 common/scsi.c  |  2 +-
 configs/mvebu_db-88f3720_defconfig |  2 +
 .../scsi/marvell,mvebu-scsi.txt| 29 
 doc/device-tree-bindings/scsi/scsi-bus.txt | 22 +
 drivers/block/Kconfig  | 10 
 drivers/block/Makefile |  1 +
 drivers/block/ahci.c   |  2 +-
 drivers/block/mvebu_scsi.c | 31 +
 drivers/block/scsi-uclass.c| 54 +-
 11 files changed, 165 insertions(+), 8 deletions(-)
 create mode 100644 doc/device-tree-bindings/scsi/marvell,mvebu-scsi.txt
 create mode 100644 doc/device-tree-bindings/scsi/scsi-bus.txt
 create mode 100644 drivers/block/mvebu_scsi.c

-- 
1.9.1

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[U-Boot] [PATCH 1/7] scsi: move base, max_lun and max_id to uclass plat data

2017-03-23 Thread make
From: Ken Ma 

- The members in scsi_platdata(base, max_lun and max_id) are generic,
  so now they are taken from fdt by the uclass_platdata instead of
  platdata code upon call to post bind callback.

Signed-off-by: Ken Ma 
Cc: Simon Glass 
Cc: Stefan Roese 
Cc: Michal Simek 
Reviewed-on: http://vgitil04.il.marvell.com:8080/35304
Tested-by: iSoC Platform CI 
Reviewed-by: Omri Itach 
Reviewed-by: Kostya Porotchkin 
---
 common/scsi.c   |  2 +-
 drivers/block/ahci.c|  2 +-
 drivers/block/scsi-uclass.c | 29 +
 3 files changed, 31 insertions(+), 2 deletions(-)

diff --git a/common/scsi.c b/common/scsi.c
index fb5b407..117c682 100644
--- a/common/scsi.c
+++ b/common/scsi.c
@@ -574,7 +574,7 @@ int scsi_scan(int mode)
return ret;
 
/* Get controller platdata */
-   plat = dev_get_platdata(dev);
+   plat = dev_get_uclass_platdata(dev);
 
for (i = 0; i < plat->max_id; i++) {
for (lun = 0; lun < plat->max_lun; lun++) {
diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c
index 3fa14a7..368816e 100644
--- a/drivers/block/ahci.c
+++ b/drivers/block/ahci.c
@@ -479,7 +479,7 @@ static int ahci_init_one(pci_dev_t dev)
pci_write_config_byte(dev, 0x41, 0xa1);
 #endif
 #else
-   struct scsi_platdata *plat = dev_get_platdata(dev);
+   struct scsi_platdata *plat = dev_get_uclass_platdata(dev);
probe_ent->mmio_base = (void *)plat->base;
 #endif
 
diff --git a/drivers/block/scsi-uclass.c b/drivers/block/scsi-uclass.c
index 05da6cd..3bf026b 100644
--- a/drivers/block/scsi-uclass.c
+++ b/drivers/block/scsi-uclass.c
@@ -11,8 +11,11 @@
 
 #include 
 #include 
+#include 
 #include 
 
+DECLARE_GLOBAL_DATA_PTR;
+
 static int scsi_post_probe(struct udevice *dev)
 {
debug("%s: device %p\n", __func__, dev);
@@ -20,8 +23,34 @@ static int scsi_post_probe(struct udevice *dev)
return 0;
 }
 
+static void scsi_ofdata_to_uclass_platdata(struct udevice *dev)
+{
+   struct scsi_platdata *plat = dev_get_uclass_platdata(dev);
+   const void *blob = gd->fdt_blob;
+   int node = dev->of_offset;
+
+   plat->base = (unsigned long)dev_get_addr_ptr(dev);
+   plat->max_id = fdtdec_get_uint(blob,
+  node,
+  "max-id",
+  CONFIG_SYS_SCSI_MAX_SCSI_ID);
+   plat->max_lun = fdtdec_get_uint(blob,
+   node,
+   "max-lun",
+   CONFIG_SYS_SCSI_MAX_LUN);
+   return;
+}
+
+static int scsi_post_bind(struct udevice *dev)
+{
+   /* Get uclass plat data from fdt */
+   scsi_ofdata_to_uclass_platdata(dev);
+}
+
 UCLASS_DRIVER(scsi) = {
.id = UCLASS_SCSI,
.name   = "scsi",
+   .post_bind  = scsi_post_bind,
.post_probe  = scsi_post_probe,
+   .per_device_platdata_auto_alloc_size = sizeof(struct scsi_platdata),
 };
-- 
1.9.1

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[U-Boot] [PATCH 3/7] scsi: call children devices' probe functions automatically

2017-03-23 Thread make
From: Ken Ma 

- For the purpose of accessing peripheral devices through SCSI, the
  peripheral devices need to be probed to finish low level
  initialization, for example, ahci controller needs to do the ahci
  initialization;
- scsi_low_level_init() calling is removed since the detailed scsi low
  level initialization work is up to the peripheral scsi devices, for
  example, sata controller may do AHCI initialization while scanner
  controller may do ISIS initialization; the work should be done in
  children devices probe when scsi controller acts as bus or be done
  in the pure SAS controller's probe when SCSI controller is a SAS
  and works as an on-board component on the motherboard;
- Since u-boot initialization does not probe devices by default, SCSI
  children devices can be probed automatically in SCSI post probe
  function when SCSI controller acts as a bus.

Signed-off-by: Ken Ma 
Cc: Simon Glass 
Cc: Stefan Roese 
Cc: Michal Simek 
Reviewed-on: http://vgitil04.il.marvell.com:8080/35426
Tested-by: iSoC Platform CI 
Reviewed-by: Omri Itach 
Reviewed-by: Kostya Porotchkin 
---
 drivers/block/scsi-uclass.c | 22 --
 1 file changed, 20 insertions(+), 2 deletions(-)

diff --git a/drivers/block/scsi-uclass.c b/drivers/block/scsi-uclass.c
index 86eddfc..119ba53 100644
--- a/drivers/block/scsi-uclass.c
+++ b/drivers/block/scsi-uclass.c
@@ -18,8 +18,26 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static int scsi_post_probe(struct udevice *dev)
 {
+   struct udevice *child_dev;
+   int ret;
+
debug("%s: device %p\n", __func__, dev);
-   scsi_low_level_init(0, dev);
+
+   /*
+* For the purpose of accessing peripheral devices through SCSI, the
+* peripheral devices need to be probed to finish low level
+* initialization, for example, ahci controller needs to do the ahci
+* initialization;
+* Since u-boot initialization does not probe devices by default, SCSI
+* children devices can be probed automatically in SCSI post probe
+* function when SCSI controller acts as a bus.
+*/
+   list_for_each_entry(child_dev, &dev->child_head, sibling_node) {
+   ret = device_probe(child_dev);
+   if (ret)
+   return ret;
+   }
+
return 0;
 }
 
@@ -54,6 +72,6 @@ UCLASS_DRIVER(scsi) = {
.id = UCLASS_SCSI,
.name   = "scsi",
.post_bind  = scsi_post_bind,
-   .post_probe  = scsi_post_probe,
+   .post_probe = scsi_post_probe,
.per_device_platdata_auto_alloc_size = sizeof(struct scsi_platdata),
 };
-- 
1.9.1

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[U-Boot] [PATCH 4/7] scsi: dt-bindings: add scsi device tree bindings

2017-03-23 Thread make
From: Ken Ma 

- Add generic scsi device tree bindings doc, the doc includes:
  - Brief introduction for scsi;
  - Scsi's properties' introduction;
- Add marvell mvebu scsi binding doc with the example of armada3700
  SCSI controller.

Signed-off-by: Ken Ma 
Cc: Simon Glass 
Cc: Stefan Roese 
Cc: Michal Simek 
Reviewed-on: http://vgitil04.il.marvell.com:8080/35427
Tested-by: iSoC Platform CI 
Reviewed-by: Omri Itach 
Reviewed-by: Kostya Porotchkin 
---
 .../scsi/marvell,mvebu-scsi.txt| 29 ++
 doc/device-tree-bindings/scsi/scsi-bus.txt | 22 
 2 files changed, 51 insertions(+)
 create mode 100644 doc/device-tree-bindings/scsi/marvell,mvebu-scsi.txt
 create mode 100644 doc/device-tree-bindings/scsi/scsi-bus.txt

diff --git a/doc/device-tree-bindings/scsi/marvell,mvebu-scsi.txt 
b/doc/device-tree-bindings/scsi/marvell,mvebu-scsi.txt
new file mode 100644
index 000..b3d06af
--- /dev/null
+++ b/doc/device-tree-bindings/scsi/marvell,mvebu-scsi.txt
@@ -0,0 +1,29 @@
+Binding for marvell mvebu SCSI controller
+
+Required properties:
+- #address-cells  - the number of cells used to represent physical base 
addresses
+- #size-cells - the number of cells used to represent the size of an 
address
+- compatible  - the name of mvebu SCSI bus controller, supported value 
"marvell,mvebu-scsi",
+covers the following Marvell SoC families: armada3700, 
armada70x0 and armada80x0
+
+Optional property:
+- max-id  - maximum number of scsi target ids, the default value is 
CONFIG_SYS_SCSI_MAX_SCSI_ID
+- max-lun - maximum number of scsi logical units, the default value is 
CONFIG_SYS_SCSI_MAX_LUN
+
+Example for armada3700 SCSI controller which is SAS and acts as an add-on host 
bus adapter without the
+base register:
+- Armada3700 has only 1 SATA interface, so the property "max-id" is 1;
+- Armada3700 max logical units number is 1, so the property "max-lun" is 1.
+
+   scsi: scsi {
+   compatible = "marvell,mvebu-scsi";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   max-id = <1>;
+   max-lun = <1>;
+   sata: sata@e {
+   compatible = "marvell,armada-3700-ahci";
+   reg = <0xe 0x2000>;
+   interrupts = ;
+   };
+   };
diff --git a/doc/device-tree-bindings/scsi/scsi-bus.txt 
b/doc/device-tree-bindings/scsi/scsi-bus.txt
new file mode 100644
index 000..01aee06
--- /dev/null
+++ b/doc/device-tree-bindings/scsi/scsi-bus.txt
@@ -0,0 +1,22 @@
+SCSI (Small Computer System Interface) busses
+
+SCSI busses can be described with a node for the SCSI controller device
+and a set of child nodes for each SCSI devices on the bus. An SCSI controller
+node can also be a Serial Attached SCSI (SAS) controller, which can act as an
+add-on host bus adapter or work as a pure controller as an on-board component
+on the motherboard, to offer compatibility with SATA devices.
+
+The SCSI controller node requires the following properties:
+- #address-cells  - the number of cells used to represent physical base 
addresses
+- #size-cells - the number of cells used to represent the size of an 
address
+- compatible  - the name of SCSI bus controller following generic names 
recommended practice
+
+No other properties are required in the SCSI bus node.  It is assumed
+that a driver for an SCSI bus device will understand that it is an SCSI bus.
+
+Optional property:
+- base- scsi register base address
+- max-id  - maximum number of scsi target ids, the default value is 
CONFIG_SYS_SCSI_MAX_SCSI_ID
+- max-lun - maximum number of scsi logical units, the default value is 
CONFIG_SYS_SCSI_MAX_LUN
+
+SCSI device nodes must be children of the SCSI controller node.
\ No newline at end of file
-- 
1.9.1

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[U-Boot] [PATCH 7/7] scsi: dts: a3700: add scsi node

2017-03-23 Thread make
From: Ken Ma 

- Add scsi node which acts as a bus for scsi devices, armada3700 has
  only 1 scsi interface, so max-id is 1, and the logic unit number is
  also 1 for armada3700;
- Since a3700's scsi is sas(serial attached scsi) which is compatible
  for sata and sata hard disk is a sas device, so move sata node to be
  under scsi node.

Signed-off-by: Ken Ma 
Cc: Simon Glass 
Cc: Stefan Roese 
Cc: Michal Simek 
Reviewed-on: http://vgitil04.il.marvell.com:8080/35303
Tested-by: iSoC Platform CI 
Reviewed-by: Kostya Porotchkin 
Reviewed-by: Omri Itach 
---
 arch/arm/dts/armada-3720-db.dts |  4 
 arch/arm/dts/armada-37xx.dtsi   | 16 
 2 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/arch/arm/dts/armada-3720-db.dts b/arch/arm/dts/armada-3720-db.dts
index 85761af..9fc60f6 100644
--- a/arch/arm/dts/armada-3720-db.dts
+++ b/arch/arm/dts/armada-3720-db.dts
@@ -89,6 +89,10 @@
status = "okay";
 };
 
+&scsi {
+   status = "okay";
+};
+
 /* CON3 */
 &sata {
status = "okay";
diff --git a/arch/arm/dts/armada-37xx.dtsi b/arch/arm/dts/armada-37xx.dtsi
index 062f2a6..de5d3a1 100644
--- a/arch/arm/dts/armada-37xx.dtsi
+++ b/arch/arm/dts/armada-37xx.dtsi
@@ -149,11 +149,19 @@
status = "disabled";
};
 
-   sata: sata@e {
-   compatible = "marvell,armada-3700-ahci";
-   reg = <0xe 0x2000>;
-   interrupts = ;
+   scsi: scsi {
+   compatible = "marvell,mvebu-scsi";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   max-id = <1>;
+   max-lun = <1>;
status = "disabled";
+   sata: sata@e {
+   compatible = "marvell,armada-3700-ahci";
+   reg = <0xe 0x2000>;
+   interrupts = ;
+   status = "disabled";
+   };
};
 
gic: interrupt-controller@1d0 {
-- 
1.9.1

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[U-Boot] [PATCH 5/7] scsi: mvebu: add scsi driver

2017-03-23 Thread make
From: Ken Ma 

- Add mvebu scsi driver which is based on scsi uclass so that
  scsi command can work when driver model is enabled for scsi;
- Mvebu scsi is serial attached scsi and act as an add-on host
  bus adapter.

Signed-off-by: Ken Ma 
Cc: Simon Glass 
Cc: Stefan Roese 
Cc: Michal Simek 
Reviewed-on: http://vgitil04.il.marvell.com:8080/35301
Reviewed-by: Omri Itach 
Reviewed-by: Kostya Porotchkin 
Tested-by: iSoC Platform CI 
---
 drivers/block/Kconfig  | 10 ++
 drivers/block/Makefile |  1 +
 drivers/block/mvebu_scsi.c | 31 +++
 3 files changed, 42 insertions(+)
 create mode 100644 drivers/block/mvebu_scsi.c

diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig
index 88e66e2..bb27a7f 100644
--- a/drivers/block/Kconfig
+++ b/drivers/block/Kconfig
@@ -28,6 +28,16 @@ config DM_SCSI
  (IDs/LUNs) a block device is created with RAW read/write and
  filesystem support.
 
+config MVEBU_SCSI
+   bool "Marvell MVEBU SCSI driver"
+   depends on DM_SCSI
+   default n
+   help
+ Say yes here to support Marvell MVEBU SCSI.
+ Marvell MVEBU SCSI supports serial attached SCSI(SAS),
+ which offers backward compatibility with SATA, versions 2 and later.
+ It allows for SATA drives to be connected to SAS backplanes.
+
 config BLOCK_CACHE
bool "Use block device cache"
default n
diff --git a/drivers/block/Makefile b/drivers/block/Makefile
index a72feec..88fe17d 100644
--- a/drivers/block/Makefile
+++ b/drivers/block/Makefile
@@ -29,5 +29,6 @@ obj-$(CONFIG_SATA_SIL) += sata_sil.o
 obj-$(CONFIG_IDE_SIL680) += sil680.o
 obj-$(CONFIG_SANDBOX) += sandbox.o sandbox_scsi.o sata_sandbox.o
 obj-$(CONFIG_SCSI_SYM53C8XX) += sym53c8xx.o
+obj-$(CONFIG_MVEBU_SCSI) += mvebu_scsi.o
 obj-$(CONFIG_SYSTEMACE) += systemace.o
 obj-$(CONFIG_BLOCK_CACHE) += blkcache.o
diff --git a/drivers/block/mvebu_scsi.c b/drivers/block/mvebu_scsi.c
new file mode 100644
index 000..0151edcb
--- /dev/null
+++ b/drivers/block/mvebu_scsi.c
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2016 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ * https://spdx.org/licenses
+ */
+
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int mvebu_scsi_probe(struct udevice *bus)
+{
+   /* Do nothing */
+   return 0;
+}
+
+static const struct udevice_id mvebu_scsi_ids[] = {
+   { .compatible = "marvell,mvebu-scsi" },
+   { }
+};
+
+U_BOOT_DRIVER(scsi_mvebu_drv) = {
+   .name   = "scsi_mvebu",
+   .id = UCLASS_SCSI,
+   .of_match   = mvebu_scsi_ids,
+   .probe  = mvebu_scsi_probe,
+};
+
-- 
1.9.1

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[U-Boot] [PATCH 2/7] scsi: add children devices binding

2017-03-23 Thread make
From: Ken Ma 

- When scsi controller acts as a bus, we need to bind its children
  scsi devices(scsi hdd, cd, dvd, scanner) to their drivers as spi
  controller binds spi flashes, so scsi-uclass's post bind function
  calls dm_scan_fdt_dev() to bind scsi subnode devices;
- When scsi controller is a Serial Attached SCSI, it can also work as
  a pure controller as an on-board component on the motherboard, it may
  has no subnodes in fdt, then dm_scan_fdt_dev() does nothing and has
  no effect.

Signed-off-by: Ken Ma 
Cc: Simon Glass 
Cc: Stefan Roese 
Cc: Michal Simek 
Reviewed-on: http://vgitil04.il.marvell.com:8080/35425
Tested-by: iSoC Platform CI 
Reviewed-by: Omri Itach 
Reviewed-by: Kostya Porotchkin 
---
 drivers/block/scsi-uclass.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/block/scsi-uclass.c b/drivers/block/scsi-uclass.c
index 3bf026b..86eddfc 100644
--- a/drivers/block/scsi-uclass.c
+++ b/drivers/block/scsi-uclass.c
@@ -45,6 +45,9 @@ static int scsi_post_bind(struct udevice *dev)
 {
/* Get uclass plat data from fdt */
scsi_ofdata_to_uclass_platdata(dev);
+
+   /* bind subnode devices */
+   return dm_scan_fdt_dev(dev);
 }
 
 UCLASS_DRIVER(scsi) = {
-- 
1.9.1

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[U-Boot] [PATCH 6/7] scsi: a3700: enable mvebu scsi driver

2017-03-23 Thread make
From: Ken Ma 

- Enable SCSI support in Armada-3700 DB default configuration.

Reviewed-on: http://vgitil04.il.marvell.com:8080/35302
Reviewed-by: Omri Itach 
Tested-by: iSoC Platform CI 
Reviewed-by: Kostya Porotchkin 
Signed-off-by: Ken Ma 
Cc: Simon Glass 
Cc: Stefan Roese 
Cc: Michal Simek 
---
 configs/mvebu_db-88f3720_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/configs/mvebu_db-88f3720_defconfig 
b/configs/mvebu_db-88f3720_defconfig
index 80f2599..53b3c38 100644
--- a/configs/mvebu_db-88f3720_defconfig
+++ b/configs/mvebu_db-88f3720_defconfig
@@ -33,6 +33,8 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_MAC_PARTITION=y
 CONFIG_ISO_PARTITION=y
 CONFIG_EFI_PARTITION=y
+CONFIG_DM_SCSI=y
+CONFIG_MVEBU_SCSI=y
 CONFIG_BLOCK_CACHE=y
 CONFIG_DM_I2C=y
 CONFIG_DM_I2C_COMPAT=y
-- 
1.9.1

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Re: [U-Boot] [PATCH 7/7] scsi: dts: a3700: add scsi node

2017-03-23 Thread Stefan Roese

Hi Ken,

On 23.03.2017 10:29, m...@marvell.com wrote:

From: Ken Ma 

- Add scsi node which acts as a bus for scsi devices, armada3700 has
  only 1 scsi interface, so max-id is 1, and the logic unit number is
  also 1 for armada3700;
- Since a3700's scsi is sas(serial attached scsi) which is compatible
  for sata and sata hard disk is a sas device, so move sata node to be
  under scsi node.

Signed-off-by: Ken Ma 
Cc: Simon Glass 
Cc: Stefan Roese 
Cc: Michal Simek 
Reviewed-on: http://vgitil04.il.marvell.com:8080/35303
Tested-by: iSoC Platform CI 
Reviewed-by: Kostya Porotchkin 
Reviewed-by: Omri Itach 
---
 arch/arm/dts/armada-3720-db.dts |  4 
 arch/arm/dts/armada-37xx.dtsi   | 16 
 2 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/arch/arm/dts/armada-3720-db.dts b/arch/arm/dts/armada-3720-db.dts
index 85761af..9fc60f6 100644
--- a/arch/arm/dts/armada-3720-db.dts
+++ b/arch/arm/dts/armada-3720-db.dts
@@ -89,6 +89,10 @@
status = "okay";
 };

+&scsi {
+   status = "okay";
+};
+
 /* CON3 */
 &sata {
status = "okay";
diff --git a/arch/arm/dts/armada-37xx.dtsi b/arch/arm/dts/armada-37xx.dtsi
index 062f2a6..de5d3a1 100644
--- a/arch/arm/dts/armada-37xx.dtsi
+++ b/arch/arm/dts/armada-37xx.dtsi
@@ -149,11 +149,19 @@
status = "disabled";
};

-   sata: sata@e {
-   compatible = "marvell,armada-3700-ahci";
-   reg = <0xe 0x2000>;
-   interrupts = ;
+   scsi: scsi {
+   compatible = "marvell,mvebu-scsi";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   max-id = <1>;
+   max-lun = <1>;
status = "disabled";
+   sata: sata@e {
+   compatible = "marvell,armada-3700-ahci";
+   reg = <0xe 0x2000>;
+   interrupts = ;
+   status = "disabled";
+   };
};

gic: interrupt-controller@1d0 {



I see that you introduce a "scsi" DT node and move the SATA controller
one "level up". I'm not sure if such a change is acceptable as we try
to re-use the DT from Linux. Or thinking more about this, I'm pretty
sure that such a change is not acceptable in general.

Can't you use the existing DT layout and use the
"marvell,armada-3700-ahci" (and other perhaps?) compatible property
instead for driver probing? Not sure how to handle the "max-id" and
"max-lun" properties though. We definitely can't just add some ad-hoc
properties here in U-Boot which have no chance for Linux upstream
acceptance.

Thanks,
Stefan
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Re: [U-Boot] [PATCH v4] drivers/net/phy: add fixed-phy / fixed-link support

2017-03-23 Thread Christian Gmeiner
Hi

> +int fixedphy_probe(struct phy_device *phydev)
> +{
> +   struct fixed_link *priv;
> +   int ofnode = phydev->addr;
> +   u32 val;
> +
> +   /* check for mandatory properties within fixed-link node */
> +   val = fdt_getprop_u32_default_node(gd->fdt_blob,
> +  ofnode, 0, "speed", 0);
> +   if (val != SPEED_10 && val != SPEED_1000 && val != SPEED_1000) {


Still wrong - SPEED_100 is missing.

  if (val != SPEED_10 && val != SPEED_100 && val != SPEED_1000) {


> +   printf("ERROR: no/invalid speed given in fixed-link node!");
> +   return -EINVAL;
> +   }
> +
> +   priv = malloc(sizeof(*priv));
> +   if (!priv)
> +   return -ENOMEM;
> +   memset(priv, 0, sizeof(*priv));
> +
> +   phydev->priv = priv;
> +   phydev->addr = 0;
> +
> +   priv->link_speed = val;
> +   priv->duplex = fdtdec_get_bool(gd->fdt_blob, ofnode, "full-duplex");
> +   priv->pause = fdtdec_get_bool(gd->fdt_blob, ofnode, "pause");
> +   priv->asym_pause = fdtdec_get_bool(gd->fdt_blob, ofnode, 
> "asym-pause");
> +
> +   /* fixed-link phy must not be reset by core phy code */
> +   phydev->flags |= PHY_FLAG_BROKEN_RESET;
> +
> +   return 0;
> +}
> +


Greets
--
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https://www.youtube.com/user/AloryOFFICIAL
https://soundcloud.com/christian-gmeiner
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Re: [U-Boot] [PATCH v4] drivers/net/phy: add fixed-phy / fixed-link support

2017-03-23 Thread Hannes Schmelzer



On 23.03.2017 15:03, Christian Gmeiner wrote:

Hi

Hi Christian,



+int fixedphy_probe(struct phy_device *phydev)
+{
+   struct fixed_link *priv;
+   int ofnode = phydev->addr;
+   u32 val;
+
+   /* check for mandatory properties within fixed-link node */
+   val = fdt_getprop_u32_default_node(gd->fdt_blob,
+  ofnode, 0, "speed", 0);
+   if (val != SPEED_10 && val != SPEED_1000 && val != SPEED_1000) {


Still wrong - SPEED_100 is missing.

   if (val != SPEED_10 && val != SPEED_100 && val != SPEED_1000) {

What a mess ... looked 100 times to it ...
Sending now a v5. Many thanks.

cheers,
Hannes

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[U-Boot] [PATCH v5] drivers/net/phy: add fixed-phy / fixed-link support

2017-03-23 Thread Hannes Schmelzer
From: Hannes Schmelzer 

This patch adds support for having a "fixed-link" to some other MAC
(like some embedded switch-device).

For this purpose we introduce a new phy-driver, called "Fixed PHY".

Fixed PHY works only with CONFIG_DM_ETH enabled, since the fixed-link is
described with a subnode below ethernet interface.

Most ethernet drivers (unfortunately not all are following same scheme
for searching/attaching phys) are calling "phy_connect(...)" for getting
a phy-device.
At this point we link in, we search here for a subnode called "fixed-
link", once found we start phy_device_create(...) with the special phy-
id PHY_FIXED_ID (0xa5a55a5a).

During init the "Fixed PHY" driver has registered with this id and now
gets probed, during probe we get all the details about fixed-link out of
dts, later on the phy reports this values.

Signed-off-by: Hannes Schmelzer 

Signed-off-by: Hannes Schmelzer 
---

Changes in v5:
- fix speed-check (regarding) 100MBit/s

Changes in v4:
- be more precise in comment regarding setting PHY_FLAG_BROKEN_RESET
  flag.

Changes in v3:
- better handling dependency on DM_ETH
- replace -1 error return code with more meaningful -EINVAL

Changes in v2:
- drop unary debug prints
- simplify 'speed-property' check
- make fixed-phy selectable trough Kconfig
- add doc/device-tree-bindings/net/fixed-link.txt from linux kernel

 doc/device-tree-bindings/net/fixed-link.txt | 30 +++
 drivers/net/phy/Kconfig | 10 
 drivers/net/phy/Makefile|  1 +
 drivers/net/phy/fixed.c | 82 +
 drivers/net/phy/phy.c   | 23 ++--
 include/phy.h   |  3 ++
 6 files changed, 146 insertions(+), 3 deletions(-)
 create mode 100644 doc/device-tree-bindings/net/fixed-link.txt
 create mode 100644 drivers/net/phy/fixed.c

diff --git a/doc/device-tree-bindings/net/fixed-link.txt 
b/doc/device-tree-bindings/net/fixed-link.txt
new file mode 100644
index 000..5829bd8
--- /dev/null
+++ b/doc/device-tree-bindings/net/fixed-link.txt
@@ -0,0 +1,30 @@
+Fixed link Device Tree binding
+--
+
+Some Ethernet MACs have a "fixed link", and are not connected to a
+normal MDIO-managed PHY device. For those situations, a Device Tree
+binding allows to describe a "fixed link".
+
+Such a fixed link situation is described by creating a 'fixed-link'
+sub-node of the Ethernet MAC device node, with the following
+properties:
+
+* 'speed' (integer, mandatory), to indicate the link speed. Accepted
+  values are 10, 100 and 1000
+* 'full-duplex' (boolean, optional), to indicate that full duplex is
+  used. When absent, half duplex is assumed.
+* 'pause' (boolean, optional), to indicate that pause should be
+  enabled.
+* 'asym-pause' (boolean, optional), to indicate that asym_pause should
+  be enabled.
+
+Examples:
+
+ethernet@0 {
+   ...
+   fixed-link {
+ speed = <1000>;
+ full-duplex;
+   };
+   ...
+};
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 1d514e9..e562a8a 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -90,4 +90,14 @@ config PHY_VITESSE
 config PHY_XILINX
bool "Xilinx Ethernet PHYs support"
 
+config PHY_FIXED
+   bool "Fixed-Link PHY"
+   depends on DM_ETH
+   help
+ Fixed PHY is used for having a 'fixed-link' to another MAC with a 
direct
+ connection (MII, RGMII, ...).
+ There is nothing like autoneogation and so
+ on, the link is always up with fixed speed and fixed duplex-setting.
+ More information: doc/device-tree-bindings/net/fixed-link.txt
+
 endif #PHYLIB
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index d372971..88c00a5 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -28,3 +28,4 @@ obj-$(CONFIG_PHY_TI) += ti.o
 obj-$(CONFIG_PHY_XILINX) += xilinx_phy.o
 obj-$(CONFIG_PHY_VITESSE) += vitesse.o
 obj-$(CONFIG_PHY_MSCC) += mscc.o
+obj-$(CONFIG_PHY_FIXED) += fixed.o
diff --git a/drivers/net/phy/fixed.c b/drivers/net/phy/fixed.c
new file mode 100644
index 000..df82356
--- /dev/null
+++ b/drivers/net/phy/fixed.c
@@ -0,0 +1,82 @@
+/*
+ * Fixed-Link phy
+ *
+ * Copyright 2017 Bernecker & Rainer Industrieelektronik GmbH
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int fixedphy_probe(struct phy_device *phydev)
+{
+   struct fixed_link *priv;
+   int ofnode = phydev->addr;
+   u32 val;
+
+   /* check for mandatory properties within fixed-link node */
+   val = fdt_getprop_u32_default_node(gd->fdt_blob,
+  ofnode, 0, "speed", 0);
+   if (val != SPEED_10 && val != SPEED_100 && val != SPEED_1000) {
+   printf("ERROR: no/invalid speed given in fixed-link node!");
+   return -EINVAL;
+   }
+

Re: [U-Boot] fatls returncode

2017-03-23 Thread Wolfgang Denk
Dear Mirza,

In message  
you wrote:
> 
> I am running U-boot 2015.04 and experiencing some issues with "fatls" command.
...
> Normally "fatls" returns "0" when it does a successful list. But we
> have found a case where it does not even though everything seems to
> work fine. Below is a log with debug enabled (obfuscated filenames
> since I got this flash drive from a customer).

Please update to a recent versionof the code.  The return code
handling has probably been fixed by this commit:

0a04ed8   2015-09-11 17:15:21 -0400   FIX: fat: Provide correct return code 
from disk_{read|write} to upper layers


Best regards,

Wolfgang Denk

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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
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 data encryption standard and they came up with ...
Student: EBCDIC!
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[U-Boot] Please pull u-boot-dm

2017-03-23 Thread Simon Glass
Hi Tom,

Here are the patches that survived testing so far. More to come next week.


The following changes since commit 5877d8f398de26617be6f1f57bc30c49e9f90ebb:

  Merge branch 'master' of git://git.denx.de/u-boot-mmc (2017-03-21
14:10:15 -0400)

are available in the git repository at:

  git://git.denx.de/u-boot-dm.git

for you to fetch changes up to 55bc080e799ac18802a791bd5ce5d83a136da6e3:

  dtoc: make ScanTree recurse into subnodes (2017-03-22 07:27:19 -0600)


Jean-Jacques Hiblot (2):
  regmap: use fdt address translation
  drivers: ti_qspi: use syscon to get the address ctrl_mod_mmap register

Lokesh Vutla (1):
  dm: core: Fix Handling of global_data moving in SPL

Philipp Tomsich (1):
  dtoc: make ScanTree recurse into subnodes

 drivers/core/regmap.c | 14 --
 drivers/core/root.c   |  6 --
 drivers/spi/ti_qspi.c | 47 ++-
 tools/dtoc/dtoc.py| 19 ++-
 4 files changed, 72 insertions(+), 14 deletions(-)

Regards,
Simon
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[U-Boot] [PATCH v2 00/45] Add PPv2.2 support to the mvpp2 ethernet driver and enable it for A7k/8k

2017-03-23 Thread Stefan Roese

This patchset does the following things:

- It brings the latest Linux changes from the mvpp2 ethernet driver done
  by Thomas Petazzoni to the U-Boot version of this driver. This enables
  the usage of this driver on the new Marvell Armada 7k / 8k ARMv8 SoCs.

- This driver is enabled for the currently available Armada 7k / 8k
  boards and the necessary configuration is done to the config header.

v2 status:
The GoP / NetC patch has been split into multiple smaller patches for
easier review. The code for untested / unsupported interfaces (like
QSGMII, XAUI and RXAUI) has been removed for now.

Thanks,
Stefan

Changes in v2:
- Added Reviewed-by from Tom and Joe
- Added Acked-by from Joe
- Rebased on latest patchset version from Thomas available in net-next,
  mostly smaller changes, making checkpatch happy.
- New patch
- Fixed small typo in commit text

Stefan Roese (22):
  bitops.h: Include bitsperlong.h as needed for GENMASK_ULL
  net: mvpp2: Round up top tx buffer boundaries for dcache ops
  net: mvpp2: enable building on 64-bit platforms (more U-Boot specific)
  net: mvpp2: Add MDIO support for PPv2.2
  net: mvpp2: Move probe function from MISC to ETH DM driver
  net: mvpp2.c: Clear all buffer / descriptor areas before usage
  net: mvpp2: Enable compilation for Armada 7K/8K platforms
  arm64: mvebu: armada-7k/8k: Enable MVPP2 ethernet driver
  net: mvpp2: Handle eth device naming in multi-CP case correctly
  net: mvpp2: Add remove function that is called before the OS is
started
  net: mvpp2: Add RX and TX FIFO configuration for PPv2.2
  net: include/phy.h: Add new PHY interface modes
  net: mvpp2: Restructure probe / init functions
  net: mvpp2: Read phy-speed from DT to select between 1GB and 2.5GB
SGMII
  net: mvpp2: Add GoP and NetC support for ports 2 & 3 (RGMII & SGMII)
  net: mvpp2: Add GoP and NetC support for port 0 (SFI)
  net: mvpp2: Add missing PHY_INTERFACE_MODE_RGMII_ID
  net: mvpp2: Enable PHY polling mode on PPv2.2
  net: mvpp2: Configure SMI PHY address needed for PHY polling
  net: mvpp2: Remove unreferenced in_use_thresh from struct
mvpp2_bm_pool
  arm64: mvebu: armada-7040-db.dts: Change eth1 speed from 2.5G to 1G
  arm64: mvebu: Enable CONFIG_PHY_MARVELL in Armada7k/8k-DB defconfig

Thomas Petazzoni (23):
  net: mvpp2: simplify mvpp2_bm_bufs_add()
  net: mvpp2: remove unused register definitions
  net: mvpp2: fix indentation of MVPP2_EXT_GLOBAL_CTRL_DEFAULT
  net: mvpp2: simplify MVPP2_PRS_RI_* definitions
  net: mvpp2: enable building on 64-bit platforms
  net: mvpp2: use "dma" instead of "phys" where appropriate
  net: mvpp2: remove support for buffer header
  net: mvpp2: store physical address of buffer in rx_desc->buf_cookie
  net: mvpp2: add and use accessors for TX/RX descriptors
  net: mvpp2: add hw_version field in "struct mvpp2"
  net: mvpp2: introduce an intermediate union for the TX/RX descriptors
  net: mvpp2: introduce PPv2.2 HW descriptors and adapt accessors
  net: mvpp2: adjust the allocation/free of BM pools for PPv2.2
  net: mvpp2: adapt the mvpp2_rxq_*_pool_set functions to PPv2.2
  net: mvpp2: adapt mvpp2_defaults_set() to PPv2.2
  net: mvpp2: adjust mvpp2_{rxq,txq}_init for PPv2.2
  net: mvpp2: handle register mapping and access for PPv2.2
  net: mvpp2: handle misc PPv2.1/PPv2.2 differences
  net: mvpp2: add AXI bridge initialization for PPv2.2
  net: mvpp2: rework RXQ interrupt group initialization for PPv2.2
  net: mvpp2: adapt rxq distribution to PPv2.2
  net: mvpp2: finally add the PPv2.2 compatible string
  arm64: marvell: dts: add PPv2.2 description to Armada 7K/8K

 arch/arm/dts/armada-7040-db.dts   |   27 +-
 arch/arm/dts/armada-8040-db.dts   |   16 +
 arch/arm/dts/armada-cp110-master.dtsi |   37 +
 arch/arm/dts/armada-cp110-slave.dtsi  |   37 +
 configs/mvebu_db-88f7040_defconfig|3 +-
 configs/mvebu_db-88f8040_defconfig|3 +-
 drivers/net/Kconfig   |6 +-
 drivers/net/mvpp2.c   | 2045 -
 include/configs/mvebu_armada-8k.h |8 +
 include/linux/bitops.h|1 +
 include/phy.h |6 +
 11 files changed, 1873 insertions(+), 316 deletions(-)

-- 
2.12.1

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[U-Boot] [PATCH v2 02/45] net: mvpp2: Round up top tx buffer boundaries for dcache ops

2017-03-23 Thread Stefan Roese
check_cache_range() warns that the top boundaries are not properly
aligned when flushing or invalidating the buffers and make these
operations fail.

This gets rid of the warnings:
CACHE: Misaligned operation at range ...

Signed-off-by: Stefan Roese 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 88e88b903b..93eb1f2dd4 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -3972,7 +3972,8 @@ static int mvpp2_send(struct udevice *dev, void *packet, 
int length)
| MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC;
 
/* Flush tx data */
-   flush_dcache_range((u32)packet, (u32)packet + length);
+   flush_dcache_range((unsigned long)packet,
+  (unsigned long)packet + ALIGN(length, PKTALIGN));
 
/* Enable transmit */
mb();
-- 
2.12.1

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[U-Boot] [PATCH v2 11/45] net: mvpp2: store physical address of buffer in rx_desc->buf_cookie

2017-03-23 Thread Stefan Roese
From: Thomas Petazzoni 

Signed-off-by: Thomas Petazzoni 
Signed-off-by: Stefan Roese 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 13 +
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 90ab6d718b..17ce0e9f7d 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -2352,20 +2352,25 @@ static inline int mvpp2_bm_cookie_pool_get(unsigned 
long cookie)
 /* Release buffer to BM */
 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
 dma_addr_t buf_dma_addr,
-unsigned long buf_virt_addr)
+unsigned long buf_phys_addr)
 {
-   mvpp2_write(port->priv, MVPP2_BM_VIRT_RLS_REG, buf_virt_addr);
+   /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply
+* returned in the "cookie" field of the RX
+* descriptor. Instead of storing the virtual address, we
+* store the physical address
+*/
+   mvpp2_write(port->priv, MVPP2_BM_VIRT_RLS_REG, buf_phys_addr);
mvpp2_write(port->priv, MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr);
 }
 
 /* Refill BM pool */
 static void mvpp2_pool_refill(struct mvpp2_port *port, u32 bm,
  dma_addr_t dma_addr,
- u32 cookie)
+ phys_addr_t phys_addr)
 {
int pool = mvpp2_bm_cookie_pool_get(bm);
 
-   mvpp2_bm_pool_put(port, pool, dma_addr, cookie);
+   mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
 }
 
 /* Allocate buffers for the pool */
-- 
2.12.1

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[U-Boot] [PATCH v2 15/45] net: mvpp2: introduce PPv2.2 HW descriptors and adapt accessors

2017-03-23 Thread Stefan Roese
From: Thomas Petazzoni 

This commit adds the definition of the PPv2.2 HW descriptors, adjusts
the mvpp2_tx_desc and mvpp2_rx_desc structures accordingly, and adapts
the accessors to work on both PPv2.1 and PPv2.2.

Signed-off-by: Thomas Petazzoni 
Signed-off-by: Stefan Roese 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe
- Rebased on latest patchset version from Thomas available in net-next,
  mostly smaller changes, making checkpatch happy.

 drivers/net/mvpp2.c | 73 ++---
 1 file changed, 64 insertions(+), 9 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index f063b04e43..605c8bcd70 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -825,18 +825,42 @@ struct mvpp21_rx_desc {
u32 reserved8;
 };
 
+/* HW TX descriptor for PPv2.2 */
+struct mvpp22_tx_desc {
+   u32 command;
+   u8  packet_offset;
+   u8  phys_txq;
+   u16 data_size;
+   u64 reserved1;
+   u64 buf_dma_addr_ptp;
+   u64 buf_cookie_misc;
+};
+
+/* HW RX descriptor for PPv2.2 */
+struct mvpp22_rx_desc {
+   u32 status;
+   u16 reserved1;
+   u16 data_size;
+   u32 reserved2;
+   u32 reserved3;
+   u64 buf_dma_addr_key_hash;
+   u64 buf_cookie_misc;
+};
+
 /* Opaque type used by the driver to manipulate the HW TX and RX
  * descriptors
  */
 struct mvpp2_tx_desc {
union {
struct mvpp21_tx_desc pp21;
+   struct mvpp22_tx_desc pp22;
};
 };
 
 struct mvpp2_rx_desc {
union {
struct mvpp21_rx_desc pp21;
+   struct mvpp22_rx_desc pp22;
};
 };
 
@@ -1040,59 +1064,90 @@ static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port 
*port,
  struct mvpp2_tx_desc *tx_desc,
  dma_addr_t dma_addr)
 {
-   tx_desc->pp21.buf_dma_addr = dma_addr;
+   if (port->priv->hw_version == MVPP21) {
+   tx_desc->pp21.buf_dma_addr = dma_addr;
+   } else {
+   u64 val = (u64)dma_addr;
+
+   tx_desc->pp22.buf_dma_addr_ptp &= ~GENMASK_ULL(40, 0);
+   tx_desc->pp22.buf_dma_addr_ptp |= val;
+   }
 }
 
 static void mvpp2_txdesc_size_set(struct mvpp2_port *port,
  struct mvpp2_tx_desc *tx_desc,
  size_t size)
 {
-   tx_desc->pp21.data_size = size;
+   if (port->priv->hw_version == MVPP21)
+   tx_desc->pp21.data_size = size;
+   else
+   tx_desc->pp22.data_size = size;
 }
 
 static void mvpp2_txdesc_txq_set(struct mvpp2_port *port,
 struct mvpp2_tx_desc *tx_desc,
 unsigned int txq)
 {
-   tx_desc->pp21.phys_txq = txq;
+   if (port->priv->hw_version == MVPP21)
+   tx_desc->pp21.phys_txq = txq;
+   else
+   tx_desc->pp22.phys_txq = txq;
 }
 
 static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port,
 struct mvpp2_tx_desc *tx_desc,
 unsigned int command)
 {
-   tx_desc->pp21.command = command;
+   if (port->priv->hw_version == MVPP21)
+   tx_desc->pp21.command = command;
+   else
+   tx_desc->pp22.command = command;
 }
 
 static void mvpp2_txdesc_offset_set(struct mvpp2_port *port,
struct mvpp2_tx_desc *tx_desc,
unsigned int offset)
 {
-   tx_desc->pp21.packet_offset = offset;
+   if (port->priv->hw_version == MVPP21)
+   tx_desc->pp21.packet_offset = offset;
+   else
+   tx_desc->pp22.packet_offset = offset;
 }
 
 static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port,
struct mvpp2_rx_desc *rx_desc)
 {
-   return rx_desc->pp21.buf_dma_addr;
+   if (port->priv->hw_version == MVPP21)
+   return rx_desc->pp21.buf_dma_addr;
+   else
+   return rx_desc->pp22.buf_dma_addr_key_hash & GENMASK_ULL(40, 0);
 }
 
 static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port,
 struct mvpp2_rx_desc *rx_desc)
 {
-   return rx_desc->pp21.buf_cookie;
+   if (port->priv->hw_version == MVPP21)
+   return rx_desc->pp21.buf_cookie;
+   else
+   return rx_desc->pp22.buf_cookie_misc & GENMASK_ULL(40, 0);
 }
 
 static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port,
struct mvpp2_rx_desc *rx_desc)
 {
-   return rx_desc->pp21.data_size;
+   if (port->priv->hw_version == MVPP21)
+   return rx_desc->pp21.data_size;
+   else
+   return rx_desc->pp22.data_size;
 }
 
 static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port,
   struct mvpp2_

[U-Boot] [PATCH v2 08/45] net: mvpp2: enable building on 64-bit platforms (more U-Boot specific)

2017-03-23 Thread Stefan Roese
Some more U-Boot specific 64bit support changes, mostly changing u32
to unsigned long.

Signed-off-by: Stefan Roese 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 25 +++--
 1 file changed, 15 insertions(+), 10 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index d5085909e4..82d3ff9c35 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -959,7 +959,7 @@ struct mvpp2_bm_pool {
int pkt_size;
 
/* BPPE virtual base address */
-   u32 *virt_addr;
+   unsigned long *virt_addr;
/* BPPE physical base address */
dma_addr_t phys_addr;
 
@@ -1003,8 +1003,8 @@ struct buffer_location {
struct mvpp2_tx_desc *aggr_tx_descs;
struct mvpp2_tx_desc *tx_descs;
struct mvpp2_rx_desc *rx_descs;
-   u32 *bm_pool[MVPP2_BM_POOLS_NUM];
-   u32 *rx_buffer[MVPP2_BM_LONG_BUF_NUM];
+   unsigned long *bm_pool[MVPP2_BM_POOLS_NUM];
+   unsigned long *rx_buffer[MVPP2_BM_LONG_BUF_NUM];
int first_rxq;
 };
 
@@ -3963,8 +3963,8 @@ static int mvpp2_send(struct udevice *dev, void *packet, 
int length)
tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
tx_desc->phys_txq = txq->id;
tx_desc->data_size = length;
-   tx_desc->packet_offset = (u32)packet & MVPP2_TX_DESC_ALIGN;
-   tx_desc->buf_phys_addr = (u32)packet & ~MVPP2_TX_DESC_ALIGN;
+   tx_desc->packet_offset = (unsigned long)packet & MVPP2_TX_DESC_ALIGN;
+   tx_desc->buf_phys_addr = (unsigned long)packet & ~MVPP2_TX_DESC_ALIGN;
/* First and Last descriptor */
tx_desc->command = MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE
| MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC;
@@ -4088,24 +4088,29 @@ static int mvpp2_base_probe(struct udevice *dev)
 
/* Align buffer area for descs and rx_buffers to 1MiB */
bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
-   mmu_set_region_dcache_behaviour((u32)bd_space, BD_SPACE, DCACHE_OFF);
+   mmu_set_region_dcache_behaviour((unsigned long)bd_space,
+   BD_SPACE, DCACHE_OFF);
 
buffer_loc.aggr_tx_descs = (struct mvpp2_tx_desc *)bd_space;
size += MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE;
 
-   buffer_loc.tx_descs = (struct mvpp2_tx_desc *)((u32)bd_space + size);
+   buffer_loc.tx_descs =
+   (struct mvpp2_tx_desc *)((unsigned long)bd_space + size);
size += MVPP2_MAX_TXD * MVPP2_DESC_ALIGNED_SIZE;
 
-   buffer_loc.rx_descs = (struct mvpp2_rx_desc *)((u32)bd_space + size);
+   buffer_loc.rx_descs =
+   (struct mvpp2_rx_desc *)((unsigned long)bd_space + size);
size += MVPP2_MAX_RXD * MVPP2_DESC_ALIGNED_SIZE;
 
for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
-   buffer_loc.bm_pool[i] = (u32 *)((u32)bd_space + size);
+   buffer_loc.bm_pool[i] =
+   (unsigned long *)((unsigned long)bd_space + size);
size += MVPP2_BM_POOL_SIZE_MAX * sizeof(u32);
}
 
for (i = 0; i < MVPP2_BM_LONG_BUF_NUM; i++) {
-   buffer_loc.rx_buffer[i] = (u32 *)((u32)bd_space + size);
+   buffer_loc.rx_buffer[i] =
+   (unsigned long *)((unsigned long)bd_space + size);
size += RX_BUFFER_SIZE;
}
 
-- 
2.12.1

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[U-Boot] [PATCH v2 09/45] net: mvpp2: use "dma" instead of "phys" where appropriate

2017-03-23 Thread Stefan Roese
From: Thomas Petazzoni 

As indicated by Russell King, the mvpp2 driver currently uses a lot
"phys" or "phys_addr" to store what really is a DMA address. This commit
clarifies this by using "dma" or "dma_addr" where appropriate.

This is especially important as we are going to introduce more changes
where the distinction between physical address and DMA address will be
key.

Signed-off-by: Thomas Petazzoni 
Signed-off-by: Stefan Roese 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 61 +++--
 1 file changed, 31 insertions(+), 30 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 82d3ff9c35..53ddb330e9 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -799,7 +799,7 @@ struct mvpp2_tx_desc {
u8  packet_offset;  /* the offset from the buffer beginning */
u8  phys_txq;   /* destination queue ID */
u16 data_size;  /* data size of transmitted packet in bytes */
-   u32 buf_phys_addr;  /* physical addr of transmitted buffer  */
+   u32 buf_dma_addr;   /* physical addr of transmitted buffer  */
u32 buf_cookie; /* cookie for access to TX buffer in tx path */
u32 reserved1[3];   /* hw_cmd (for future use, BM, PON, PNC) */
u32 reserved2;  /* reserved (for future use)*/
@@ -809,7 +809,7 @@ struct mvpp2_rx_desc {
u32 status; /* info about received packet   */
u16 reserved1;  /* parser_info (for future use, PnC)*/
u16 data_size;  /* size of received packet in bytes */
-   u32 buf_phys_addr;  /* physical address of the buffer   */
+   u32 buf_dma_addr;   /* physical address of the buffer   */
u32 buf_cookie; /* cookie for access to RX buffer in rx path */
u16 reserved2;  /* gem_port_id (for future use, PON)*/
u16 reserved3;  /* csum_l4 (for future use, PnC)*/
@@ -864,7 +864,7 @@ struct mvpp2_tx_queue {
struct mvpp2_tx_desc *descs;
 
/* DMA address of the Tx DMA descriptors array */
-   dma_addr_t descs_phys;
+   dma_addr_t descs_dma;
 
/* Index of the last Tx DMA descriptor */
int last_desc;
@@ -887,7 +887,7 @@ struct mvpp2_rx_queue {
struct mvpp2_rx_desc *descs;
 
/* DMA address of the RX DMA descriptors array */
-   dma_addr_t descs_phys;
+   dma_addr_t descs_dma;
 
/* Index of the last RX DMA descriptor */
int last_desc;
@@ -960,8 +960,8 @@ struct mvpp2_bm_pool {
 
/* BPPE virtual base address */
unsigned long *virt_addr;
-   /* BPPE physical base address */
-   dma_addr_t phys_addr;
+   /* BPPE DMA base address */
+   dma_addr_t dma_addr;
 
/* Ports using BM pool */
u32 port_map;
@@ -971,7 +971,7 @@ struct mvpp2_bm_pool {
 };
 
 struct mvpp2_buff_hdr {
-   u32 next_buff_phys_addr;
+   u32 next_buff_dma_addr;
u32 next_buff_virt_addr;
u16 byte_count;
u16 info;
@@ -2215,7 +2215,7 @@ static int mvpp2_bm_pool_create(struct udevice *dev,
u32 val;
 
bm_pool->virt_addr = buffer_loc.bm_pool[bm_pool->id];
-   bm_pool->phys_addr = (dma_addr_t)buffer_loc.bm_pool[bm_pool->id];
+   bm_pool->dma_addr = (dma_addr_t)buffer_loc.bm_pool[bm_pool->id];
if (!bm_pool->virt_addr)
return -ENOMEM;
 
@@ -2227,7 +2227,7 @@ static int mvpp2_bm_pool_create(struct udevice *dev,
}
 
mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),
-   bm_pool->phys_addr);
+   bm_pool->dma_addr);
mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);
 
val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
@@ -2367,20 +2367,21 @@ static inline int mvpp2_bm_cookie_pool_get(unsigned 
long cookie)
 
 /* Release buffer to BM */
 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
-dma_addr_t buf_phys_addr,
+dma_addr_t buf_dma_addr,
 unsigned long buf_virt_addr)
 {
mvpp2_write(port->priv, MVPP2_BM_VIRT_RLS_REG, buf_virt_addr);
-   mvpp2_write(port->priv, MVPP2_BM_PHY_RLS_REG(pool), buf_phys_addr);
+   mvpp2_write(port->priv, MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr);
 }
 
 /* Refill BM pool */
 static void mvpp2_pool_refill(struct mvpp2_port *port, u32 bm,
- u32 phys_addr, u32 cookie)
+ dma_addr_t dma_addr,
+ u32 cookie)
 {
int pool = mvpp2_bm_cookie_pool_get(bm);
 
-   mvpp2_bm_pool_put(port, pool, phys_addr, cookie);
+   mvpp2_bm_pool_put(port, pool, dma_addr, cookie);
 }
 
 /* Allocate buffers for the pool */
@@ -2944,7 +2945,7 @@ st

[U-Boot] [PATCH v2 37/45] net: mvpp2: Read phy-speed from DT to select between 1GB and 2.5GB SGMII

2017-03-23 Thread Stefan Roese
Read the "phy-speed" DT property to differentiate between 1 and 2.5GB
SGMII operations. Please note that its unclear right now, if this
DT property will be accepted in mainline Linux. If not, we need to
revisit this code and change it to use the accepted property.

Signed-off-by: Stefan Roese 
Cc: Joe Hershberger 

---

Changes in v2:
- New patch

 drivers/net/mvpp2.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index ecefa21097..6f9a4137f8 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -839,6 +839,8 @@ struct mvpp2_port {
unsigned int duplex;
unsigned int speed;
 
+   unsigned int phy_speed; /* SGMII 1Gbps vs 2.5Gbps */
+
struct mvpp2_bm_pool *pool_long;
struct mvpp2_bm_pool *pool_short;
 
@@ -3859,6 +3861,15 @@ static int phy_info_parse(struct udevice *dev, struct 
mvpp2_port *port)
return -EINVAL;
}
 
+   /*
+* ToDo:
+* Not sure if this DT property "phy-speed" will get accepted, so
+* this might change later
+*/
+   /* Get phy-speed for SGMII 2.5Gbps vs 1Gbps setup */
+   port->phy_speed = fdtdec_get_int(gd->fdt_blob, port_node,
+"phy-speed", 1000);
+
phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node, "reg", 0);
 
port->id = id;
-- 
2.12.1

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[U-Boot] [PATCH v2 10/45] net: mvpp2: remove support for buffer header

2017-03-23 Thread Stefan Roese
From: Thomas Petazzoni 

Signed-off-by: Thomas Petazzoni 
Signed-off-by: Stefan Roese 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe
- Rebased on latest patchset version from Thomas available in net-next,
  mostly smaller changes, making checkpatch happy.

 drivers/net/mvpp2.c | 20 
 1 file changed, 20 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 53ddb330e9..90ab6d718b 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -970,22 +970,6 @@ struct mvpp2_bm_pool {
int in_use_thresh;
 };
 
-struct mvpp2_buff_hdr {
-   u32 next_buff_dma_addr;
-   u32 next_buff_virt_addr;
-   u16 byte_count;
-   u16 info;
-   u8  reserved1;  /* bm_qset (for future use, BM) */
-};
-
-/* Buffer header info bits */
-#define MVPP2_B_HDR_INFO_MC_ID_MASK0xfff
-#define MVPP2_B_HDR_INFO_MC_ID(info)   ((info) & MVPP2_B_HDR_INFO_MC_ID_MASK)
-#define MVPP2_B_HDR_INFO_LAST_OFFS 12
-#define MVPP2_B_HDR_INFO_LAST_MASK BIT(12)
-#define MVPP2_B_HDR_INFO_IS_LAST(info) \
-  ((info & MVPP2_B_HDR_INFO_LAST_MASK) >> MVPP2_B_HDR_INFO_LAST_OFFS)
-
 /* Static declaractions */
 
 /* Number of RXQs used by single port */
@@ -3892,10 +3876,6 @@ static int mvpp2_recv(struct udevice *dev, int flags, 
uchar **packetp)
pool = mvpp2_bm_cookie_pool_get(bm);
bm_pool = &port->priv->bm_pools[pool];
 
-   /* Check if buffer header is used */
-   if (rx_status & MVPP2_RXD_BUF_HDR)
-   return 0;
-
/* In case of an error, release the requested buffer pointer
 * to the Buffer Manager. This request process is controlled
 * by the hardware, and the information about the buffer is
-- 
2.12.1

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[U-Boot] [PATCH v2 32/45] net: mvpp2: Handle eth device naming in multi-CP case correctly

2017-03-23 Thread Stefan Roese
Currently, the naming of the ethernet ports is not handled correctly in
the multi-CP (Communication Processor) case. On Armada 8k, the slave-CP
also instantiates an ethernet controller with the same device ID's.
This patch now takes this into account and adds the required base-id
so that the slave-CP ethernet devices will be named "mvpp2-3 ...".

This patch also updates my Copyright notice to include 2017 as well.

Signed-off-by: Stefan Roese 
Cc: Stefan Chulski 
Cc: Kostya Porotchkin 
Cc: Nadav Haklai 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 11 ++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index b9e0fdcc82..2328c25850 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -6,7 +6,7 @@
  * Marcin Wojtas 
  *
  * U-Boot version:
- * Copyright (C) 2016 Stefan Roese 
+ * Copyright (C) 2016-2017 Stefan Roese 
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2. This program is licensed "as is" without any
@@ -1090,6 +1090,8 @@ static int rxq_number = MVPP2_DEFAULT_RXQ;
 /* Number of TXQs used by single port */
 static int txq_number = MVPP2_DEFAULT_TXQ;
 
+static int base_id;
+
 #define MVPP2_DRIVER_NAME "mvpp2"
 #define MVPP2_DRIVER_VERSION "1.0"
 
@@ -4523,6 +4525,7 @@ static int mvpp2_base_bind(struct udevice *parent)
char *name;
int subnode;
u32 id;
+   int base_id_add;
 
/* Lookup eth driver */
drv = lists_uclass_lookup(UCLASS_ETH);
@@ -4531,7 +4534,12 @@ static int mvpp2_base_bind(struct udevice *parent)
return -ENOENT;
}
 
+   base_id_add = base_id;
+
fdt_for_each_subnode(subnode, blob, node) {
+   /* Increment base_id for all subnodes, also the disabled ones */
+   base_id++;
+
/* Skip disabled ports */
if (!fdtdec_get_is_enabled(blob, subnode))
continue;
@@ -4541,6 +4549,7 @@ static int mvpp2_base_bind(struct udevice *parent)
return -ENOMEM;
 
id = fdtdec_get_int(blob, subnode, "port-id", -1);
+   id += base_id_add;
 
name = calloc(1, 16);
sprintf(name, "mvpp2-%d", id);
-- 
2.12.1

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[U-Boot] [PATCH v2 34/45] net: mvpp2: Add RX and TX FIFO configuration for PPv2.2

2017-03-23 Thread Stefan Roese
This patch adds the PPv2.2 specific FIFO configuration to the mvpp2
driver. The RX FIFO packet data size is changed to the recommended
FIFO sizes. The TX FIFO configuration is newly added.

Signed-off-by: Stefan Roese 
Cc: Stefan Chulski 
Cc: Kostya Porotchkin 
Cc: Nadav Haklai 
---

Changes in v2: None

 drivers/net/mvpp2.c | 75 -
 1 file changed, 68 insertions(+), 7 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index e13a679e33..4863336985 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -482,9 +482,23 @@ do {   
\
 #define MVPP2_TX_DESC_ALIGN(MVPP2_DESC_ALIGNED_SIZE - 1)
 
 /* RX FIFO constants */
-#define MVPP2_RX_FIFO_PORT_DATA_SIZE   0x2000
-#define MVPP2_RX_FIFO_PORT_ATTR_SIZE   0x80
-#define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80
+#define MVPP21_RX_FIFO_PORT_DATA_SIZE  0x2000
+#define MVPP21_RX_FIFO_PORT_ATTR_SIZE  0x80
+#define MVPP22_RX_FIFO_10GB_PORT_DATA_SIZE 0x8000
+#define MVPP22_RX_FIFO_2_5GB_PORT_DATA_SIZE0x2000
+#define MVPP22_RX_FIFO_1GB_PORT_DATA_SIZE  0x1000
+#define MVPP22_RX_FIFO_10GB_PORT_ATTR_SIZE 0x200
+#define MVPP22_RX_FIFO_2_5GB_PORT_ATTR_SIZE0x80
+#define MVPP22_RX_FIFO_1GB_PORT_ATTR_SIZE  0x40
+#define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80
+
+/* TX general registers */
+#define MVPP22_TX_FIFO_SIZE_REG(eth_tx_port)   (0x8860 + ((eth_tx_port) << 2))
+#define MVPP22_TX_FIFO_SIZE_MASK   0xf
+
+/* TX FIFO constants */
+#define MVPP2_TX_FIFO_DATA_SIZE_10KB   0xa
+#define MVPP2_TX_FIFO_DATA_SIZE_3KB0x3
 
 /* RX buffer constants */
 #define MVPP2_SKB_SHINFO_SIZE \
@@ -3934,10 +3948,35 @@ static void mvpp2_rx_fifo_init(struct mvpp2 *priv)
int port;
 
for (port = 0; port < MVPP2_MAX_PORTS; port++) {
-   mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
-   MVPP2_RX_FIFO_PORT_DATA_SIZE);
-   mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
-   MVPP2_RX_FIFO_PORT_ATTR_SIZE);
+   if (priv->hw_version == MVPP22) {
+   if (port == 0) {
+   mvpp2_write(priv,
+   MVPP2_RX_DATA_FIFO_SIZE_REG(port),
+   MVPP22_RX_FIFO_10GB_PORT_DATA_SIZE);
+   mvpp2_write(priv,
+   MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
+   MVPP22_RX_FIFO_10GB_PORT_ATTR_SIZE);
+   } else if (port == 1) {
+   mvpp2_write(priv,
+   MVPP2_RX_DATA_FIFO_SIZE_REG(port),
+   
MVPP22_RX_FIFO_2_5GB_PORT_DATA_SIZE);
+   mvpp2_write(priv,
+   MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
+   
MVPP22_RX_FIFO_2_5GB_PORT_ATTR_SIZE);
+   } else {
+   mvpp2_write(priv,
+   MVPP2_RX_DATA_FIFO_SIZE_REG(port),
+   MVPP22_RX_FIFO_1GB_PORT_DATA_SIZE);
+   mvpp2_write(priv,
+   MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
+   MVPP22_RX_FIFO_1GB_PORT_ATTR_SIZE);
+   }
+   } else {
+   mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
+   MVPP21_RX_FIFO_PORT_DATA_SIZE);
+   mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
+   MVPP21_RX_FIFO_PORT_ATTR_SIZE);
+   }
}
 
mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
@@ -3945,6 +3984,24 @@ static void mvpp2_rx_fifo_init(struct mvpp2 *priv)
mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
 }
 
+/* Initialize Tx FIFO's */
+static void mvpp2_tx_fifo_init(struct mvpp2 *priv)
+{
+   int port, val;
+
+   for (port = 0; port < MVPP2_MAX_PORTS; port++) {
+   /* Port 0 supports 10KB TX FIFO */
+   if (port == 0) {
+   val = MVPP2_TX_FIFO_DATA_SIZE_10KB &
+   MVPP22_TX_FIFO_SIZE_MASK;
+   } else {
+   val = MVPP2_TX_FIFO_DATA_SIZE_3KB &
+   MVPP22_TX_FIFO_SIZE_MASK;
+   }
+   mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), val);
+   }
+}
+
 static void mvpp2_axi_init(struct mvpp2 *priv)
 {
u32 val, rdval, wrval;
@@ -4051,6 +4108,10 @@ static int mvpp2_init(struct udevice *dev, struct mvpp2 
*priv)
/* Rx Fifo Init */
mvpp2_rx_fifo_init(priv);

[U-Boot] [PATCH v2 12/45] net: mvpp2: add and use accessors for TX/RX descriptors

2017-03-23 Thread Stefan Roese
From: Thomas Petazzoni 

The PPv2.2 IP has a different TX and RX descriptor layout compared to
PPv2.1. In order to prepare for the introduction of PPv2.2 support in
mvpp2, this commit adds accessors for the different fields of the TX
and RX descriptors, and changes the code to use them.

For now, the mvpp2_port argument passed to the accessors is not used,
but it will be used in follow-up to update the descriptor according to
the version of the IP being used.

Apart from the mechanical changes to use the newly introduced
accessors, a few other changes, needed to use the accessors, are made:

- The mvpp2_txq_inc_put() function now takes a mvpp2_port as first
  argument, as it is needed to use the accessors.

- Similarly, the mvpp2_bm_cookie_build() gains a mvpp2_port first
  argument, for the same reason.

- In mvpp2_rx_error(), instead of accessing the RX descriptor in each
  case of the switch, we introduce a local variable to store the
  packet size.

- Similarly, in mvpp2_buff_hdr_rx(), we introduce a local "cookie"
  variable to store the RX descriptor cookie, rather than accessing
  it from the descriptor each time.

- In mvpp2_tx_frag_process() and mvpp2_tx() instead of accessing the
  packet size from the TX descriptor, we use the actual value
  available in the function, which is used to set the TX descriptor
  packet size a few lines before.

Signed-off-by: Thomas Petazzoni 
Signed-off-by: Stefan Roese 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 118 +---
 1 file changed, 93 insertions(+), 25 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 17ce0e9f7d..d199eafe30 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -1016,6 +1016,65 @@ static u32 mvpp2_read(struct mvpp2 *priv, u32 offset)
return readl(priv->base + offset);
 }
 
+static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port,
+ struct mvpp2_tx_desc *tx_desc,
+ dma_addr_t dma_addr)
+{
+   tx_desc->buf_dma_addr = dma_addr;
+}
+
+static void mvpp2_txdesc_size_set(struct mvpp2_port *port,
+ struct mvpp2_tx_desc *tx_desc,
+ size_t size)
+{
+   tx_desc->data_size = size;
+}
+
+static void mvpp2_txdesc_txq_set(struct mvpp2_port *port,
+struct mvpp2_tx_desc *tx_desc,
+unsigned int txq)
+{
+   tx_desc->phys_txq = txq;
+}
+
+static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port,
+struct mvpp2_tx_desc *tx_desc,
+unsigned int command)
+{
+   tx_desc->command = command;
+}
+
+static void mvpp2_txdesc_offset_set(struct mvpp2_port *port,
+   struct mvpp2_tx_desc *tx_desc,
+   unsigned int offset)
+{
+   tx_desc->packet_offset = offset;
+}
+
+static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port,
+   struct mvpp2_rx_desc *rx_desc)
+{
+   return rx_desc->buf_dma_addr;
+}
+
+static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port,
+struct mvpp2_rx_desc *rx_desc)
+{
+   return rx_desc->buf_cookie;
+}
+
+static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port,
+   struct mvpp2_rx_desc *rx_desc)
+{
+   return rx_desc->data_size;
+}
+
+static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port,
+  struct mvpp2_rx_desc *rx_desc)
+{
+   return rx_desc->status;
+}
+
 static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu)
 {
txq_pcpu->txq_get_index++;
@@ -2779,11 +2838,15 @@ static void mvpp2_rxq_offset_set(struct mvpp2_port 
*port,
 }
 
 /* Obtain BM cookie information from descriptor */
-static u32 mvpp2_bm_cookie_build(struct mvpp2_rx_desc *rx_desc)
+static u32 mvpp2_bm_cookie_build(struct mvpp2_port *port,
+struct mvpp2_rx_desc *rx_desc)
 {
-   int pool = (rx_desc->status & MVPP2_RXD_BM_POOL_ID_MASK) >>
-  MVPP2_RXD_BM_POOL_ID_OFFS;
int cpu = smp_processor_id();
+   int pool;
+
+   pool = (mvpp2_rxdesc_status_get(port, rx_desc) &
+   MVPP2_RXD_BM_POOL_ID_MASK) >>
+   MVPP2_RXD_BM_POOL_ID_OFFS;
 
return ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS) |
   ((cpu & 0xFF) << MVPP2_BM_COOKIE_CPU_OFFS);
@@ -3005,10 +3068,11 @@ static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port,
 
for (i = 0; i < rx_received; i++) {
struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
-   u32 bm = mvpp2_bm_cookie_build(rx_desc);
+   u32 bm = mvpp2_bm_cookie_build(port, rx_desc);
 
-   mvpp2_pool_refill(por

[U-Boot] [PATCH v2 06/45] net: mvpp2: simplify MVPP2_PRS_RI_* definitions

2017-03-23 Thread Stefan Roese
From: Thomas Petazzoni 

Some of the MVPP2_PRS_RI_* definitions use the ~(value) syntax, which
doesn't compile nicely on 64-bit. Moreover, those definitions are in
fact unneeded, since they are always used in combination with a bit
mask that ensures only the appropriate bits are modified.

Therefore, such definitions should just be set to 0x0. In addition, as
suggested by Russell King, we change the _MASK definitions to also use
the BIT() macro so that it is clear they are related to the values
defined afterwards.

For example:

 #define MVPP2_PRS_RI_L2_CAST_MASK  0x600
 #define MVPP2_PRS_RI_L2_UCAST  ~(BIT(9) | BIT(10))
 #define MVPP2_PRS_RI_L2_MCAST  BIT(9)
 #define MVPP2_PRS_RI_L2_BCAST  BIT(10)

becomes

 #define MVPP2_PRS_RI_L2_CAST_MASK  (BIT(9) | BIT(10))
 #define MVPP2_PRS_RI_L2_UCAST  0x0
 #define MVPP2_PRS_RI_L2_MCAST  BIT(9)
 #define MVPP2_PRS_RI_L2_BCAST  BIT(10)

Because the values (MVPP2_PRS_RI_L2_UCAST, MVPP2_PRS_RI_L2_MCAST and
MVPP2_PRS_RI_L2_BCAST) are always applied with
MVPP2_PRS_RI_L2_CAST_MASK, and therefore there is no need for
MVPP2_PRS_RI_L2_UCAST to be defined as ~(BIT(9) | BIT(10)).

It fixes the following warnings when building the driver on a 64-bit
platform (which is not possible as of this commit, but will be enabled
in a follow-up commit):

drivers/net/ethernet/marvell/mvpp2.c: In function ‘mvpp2_prs_mac_promisc_set’:
drivers/net/ethernet/marvell/mvpp2.c:524:33: warning: large integer implicitly 
truncated to unsigned type [-Woverflow]
 #define MVPP2_PRS_RI_L2_UCAST   ~(BIT(9) | BIT(10))
  ^
drivers/net/ethernet/marvell/mvpp2.c:1459:33: note: in expansion of macro 
‘MVPP2_PRS_RI_L2_UCAST’
 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_UCAST,

Signed-off-by: Thomas Petazzoni 
Signed-off-by: Stefan Roese 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 74ae1a2d2a..769680ac45 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -572,28 +572,28 @@ enum mvpp2_tag_type {
 /* Sram result info bits assignment */
 #define MVPP2_PRS_RI_MAC_ME_MASK   0x1
 #define MVPP2_PRS_RI_DSA_MASK  0x2
-#define MVPP2_PRS_RI_VLAN_MASK 0xc
-#define MVPP2_PRS_RI_VLAN_NONE ~(BIT(2) | BIT(3))
+#define MVPP2_PRS_RI_VLAN_MASK (BIT(2) | BIT(3))
+#define MVPP2_PRS_RI_VLAN_NONE 0x0
 #define MVPP2_PRS_RI_VLAN_SINGLE   BIT(2)
 #define MVPP2_PRS_RI_VLAN_DOUBLE   BIT(3)
 #define MVPP2_PRS_RI_VLAN_TRIPLE   (BIT(2) | BIT(3))
 #define MVPP2_PRS_RI_CPU_CODE_MASK 0x70
 #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC  BIT(4)
-#define MVPP2_PRS_RI_L2_CAST_MASK  0x600
-#define MVPP2_PRS_RI_L2_UCAST  ~(BIT(9) | BIT(10))
+#define MVPP2_PRS_RI_L2_CAST_MASK  (BIT(9) | BIT(10))
+#define MVPP2_PRS_RI_L2_UCAST  0x0
 #define MVPP2_PRS_RI_L2_MCAST  BIT(9)
 #define MVPP2_PRS_RI_L2_BCAST  BIT(10)
 #define MVPP2_PRS_RI_PPPOE_MASK0x800
-#define MVPP2_PRS_RI_L3_PROTO_MASK 0x7000
-#define MVPP2_PRS_RI_L3_UN ~(BIT(12) | BIT(13) | BIT(14))
+#define MVPP2_PRS_RI_L3_PROTO_MASK (BIT(12) | BIT(13) | BIT(14))
+#define MVPP2_PRS_RI_L3_UN 0x0
 #define MVPP2_PRS_RI_L3_IP4BIT(12)
 #define MVPP2_PRS_RI_L3_IP4_OPTBIT(13)
 #define MVPP2_PRS_RI_L3_IP4_OTHER  (BIT(12) | BIT(13))
 #define MVPP2_PRS_RI_L3_IP6BIT(14)
 #define MVPP2_PRS_RI_L3_IP6_EXT(BIT(12) | BIT(14))
 #define MVPP2_PRS_RI_L3_ARP(BIT(13) | BIT(14))
-#define MVPP2_PRS_RI_L3_ADDR_MASK  0x18000
-#define MVPP2_PRS_RI_L3_UCAST  ~(BIT(15) | BIT(16))
+#define MVPP2_PRS_RI_L3_ADDR_MASK  (BIT(15) | BIT(16))
+#define MVPP2_PRS_RI_L3_UCAST  0x0
 #define MVPP2_PRS_RI_L3_MCAST  BIT(15)
 #define MVPP2_PRS_RI_L3_BCAST  (BIT(15) | BIT(16))
 #define MVPP2_PRS_RI_IP_FRAG_MASK  0x2
-- 
2.12.1

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[U-Boot] [PATCH v2 23/45] net: mvpp2: rework RXQ interrupt group initialization for PPv2.2

2017-03-23 Thread Stefan Roese
From: Thomas Petazzoni 

This commit adjusts how the MVPP2_ISR_RXQ_GROUP_REG register is
configured, since it changed between PPv2.1 and PPv2.2.

Signed-off-by: Thomas Petazzoni 
Signed-off-by: Stefan Roese 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe
- Rebased on latest patchset version from Thomas available in net-next,
  mostly smaller changes, making checkpatch happy.

 drivers/net/mvpp2.c | 50 +-
 1 file changed, 45 insertions(+), 5 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index b56af82f92..16a9c75cf0 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -228,7 +228,21 @@ do {   
\
 
 /* Interrupt Cause and Mask registers */
 #define MVPP2_ISR_RX_THRESHOLD_REG(rxq)(0x5200 + 4 * (rxq))
-#define MVPP2_ISR_RXQ_GROUP_REG(rxq)   (0x5400 + 4 * (rxq))
+#define MVPP21_ISR_RXQ_GROUP_REG(rxq)  (0x5400 + 4 * (rxq))
+
+#define MVPP22_ISR_RXQ_GROUP_INDEX_REG  0x5400
+#define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
+#define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK   0x380
+#define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET 7
+
+#define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
+#define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK   0x380
+
+#define MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG 0x5404
+#define MVPP22_ISR_RXQ_SUB_GROUP_STARTQ_MASK0x1f
+#define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_MASK  0xf00
+#define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET8
+
 #define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port))
 #define MVPP2_ISR_ENABLE_INTERRUPT(mask)   ((mask) & 0x)
 #define MVPP2_ISR_DISABLE_INTERRUPT(mask)  (((mask) << 16) & 0x)
@@ -3747,7 +3761,19 @@ static int mvpp2_port_init(struct udevice *dev, struct 
mvpp2_port *port)
}
 
/* Configure Rx queue group interrupt for this port */
-   mvpp2_write(priv, MVPP2_ISR_RXQ_GROUP_REG(port->id), CONFIG_MV_ETH_RXQ);
+   if (priv->hw_version == MVPP21) {
+   mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id),
+   CONFIG_MV_ETH_RXQ);
+   } else {
+   u32 val;
+
+   val = (port->id << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET);
+   mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val);
+
+   val = (CONFIG_MV_ETH_RXQ <<
+  MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET);
+   mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val);
+   }
 
/* Create Rx descriptor rings */
for (queue = 0; queue < rxq_number; queue++) {
@@ -4013,9 +4039,23 @@ static int mvpp2_init(struct udevice *dev, struct mvpp2 
*priv)
mvpp2_rx_fifo_init(priv);
 
/* Reset Rx queue group interrupt configuration */
-   for (i = 0; i < MVPP2_MAX_PORTS; i++)
-   mvpp2_write(priv, MVPP2_ISR_RXQ_GROUP_REG(i),
-   CONFIG_MV_ETH_RXQ);
+   for (i = 0; i < MVPP2_MAX_PORTS; i++) {
+   if (priv->hw_version == MVPP21) {
+   mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(i),
+   CONFIG_MV_ETH_RXQ);
+   continue;
+   } else {
+   u32 val;
+
+   val = (i << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET);
+   mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val);
+
+   val = (CONFIG_MV_ETH_RXQ <<
+  MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET);
+   mvpp2_write(priv,
+   MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val);
+   }
+   }
 
if (priv->hw_version == MVPP21)
writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
-- 
2.12.1

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[U-Boot] [PATCH v2 14/45] net: mvpp2: introduce an intermediate union for the TX/RX descriptors

2017-03-23 Thread Stefan Roese
From: Thomas Petazzoni 

Since the format of the HW descriptors is different between PPv2.1 and
PPv2.2, this commit introduces an intermediate union, with for now
only the PPv2.1 descriptors. The bulk of the driver code only
manipulates opaque mvpp2_tx_desc and mvpp2_rx_desc pointers, and the
descriptors can only be accessed and modified through the accessor
functions. A follow-up commit will add the descriptor definitions for
PPv2.2.

Signed-off-by: Thomas Petazzoni 
Signed-off-by: Stefan Roese 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 39 ---
 1 file changed, 28 insertions(+), 11 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 9683439d23..f063b04e43 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -797,7 +797,8 @@ struct mvpp2_port {
 #define MVPP2_RXD_L3_IP6   BIT(30)
 #define MVPP2_RXD_BUF_HDR  BIT(31)
 
-struct mvpp2_tx_desc {
+/* HW TX descriptor for PPv2.1 */
+struct mvpp21_tx_desc {
u32 command;/* Options used by HW for packet transmitting.*/
u8  packet_offset;  /* the offset from the buffer beginning */
u8  phys_txq;   /* destination queue ID */
@@ -808,7 +809,8 @@ struct mvpp2_tx_desc {
u32 reserved2;  /* reserved (for future use)*/
 };
 
-struct mvpp2_rx_desc {
+/* HW RX descriptor for PPv2.1 */
+struct mvpp21_rx_desc {
u32 status; /* info about received packet   */
u16 reserved1;  /* parser_info (for future use, PnC)*/
u16 data_size;  /* size of received packet in bytes */
@@ -823,6 +825,21 @@ struct mvpp2_rx_desc {
u32 reserved8;
 };
 
+/* Opaque type used by the driver to manipulate the HW TX and RX
+ * descriptors
+ */
+struct mvpp2_tx_desc {
+   union {
+   struct mvpp21_tx_desc pp21;
+   };
+};
+
+struct mvpp2_rx_desc {
+   union {
+   struct mvpp21_rx_desc pp21;
+   };
+};
+
 /* Per-CPU Tx queue control */
 struct mvpp2_txq_pcpu {
int cpu;
@@ -1023,59 +1040,59 @@ static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port 
*port,
  struct mvpp2_tx_desc *tx_desc,
  dma_addr_t dma_addr)
 {
-   tx_desc->buf_dma_addr = dma_addr;
+   tx_desc->pp21.buf_dma_addr = dma_addr;
 }
 
 static void mvpp2_txdesc_size_set(struct mvpp2_port *port,
  struct mvpp2_tx_desc *tx_desc,
  size_t size)
 {
-   tx_desc->data_size = size;
+   tx_desc->pp21.data_size = size;
 }
 
 static void mvpp2_txdesc_txq_set(struct mvpp2_port *port,
 struct mvpp2_tx_desc *tx_desc,
 unsigned int txq)
 {
-   tx_desc->phys_txq = txq;
+   tx_desc->pp21.phys_txq = txq;
 }
 
 static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port,
 struct mvpp2_tx_desc *tx_desc,
 unsigned int command)
 {
-   tx_desc->command = command;
+   tx_desc->pp21.command = command;
 }
 
 static void mvpp2_txdesc_offset_set(struct mvpp2_port *port,
struct mvpp2_tx_desc *tx_desc,
unsigned int offset)
 {
-   tx_desc->packet_offset = offset;
+   tx_desc->pp21.packet_offset = offset;
 }
 
 static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port,
struct mvpp2_rx_desc *rx_desc)
 {
-   return rx_desc->buf_dma_addr;
+   return rx_desc->pp21.buf_dma_addr;
 }
 
 static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port,
 struct mvpp2_rx_desc *rx_desc)
 {
-   return rx_desc->buf_cookie;
+   return rx_desc->pp21.buf_cookie;
 }
 
 static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port,
struct mvpp2_rx_desc *rx_desc)
 {
-   return rx_desc->data_size;
+   return rx_desc->pp21.data_size;
 }
 
 static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port,
   struct mvpp2_rx_desc *rx_desc)
 {
-   return rx_desc->status;
+   return rx_desc->pp21.status;
 }
 
 static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu)
-- 
2.12.1

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[U-Boot] [PATCH v2 41/45] net: mvpp2: Enable PHY polling mode on PPv2.2

2017-03-23 Thread Stefan Roese
Testing shows, that PHY polling needs to be enabled on Armada 7k/8k.
Otherwise ethernet transfers will not work correctly. PHY polling
is enabled per default after reset, so we do not need to specifically
enable it, but this makes it clearer.

Signed-off-by: Stefan Roese 
Cc: Stefan Chulski 
Cc: Kostya Porotchkin 
Cc: Nadav Haklai 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index d20d82e017..cc6d42255c 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -4966,14 +4966,15 @@ static int mvpp2_init(struct udevice *dev, struct mvpp2 
*priv)
if (priv->hw_version == MVPP22)
mvpp2_axi_init(priv);
 
-   /* Disable HW PHY polling */
if (priv->hw_version == MVPP21) {
+   /* Disable HW PHY polling */
val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
} else {
+   /* Enable HW PHY polling */
val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
-   val &= ~MVPP22_SMI_POLLING_EN;
+   val |= MVPP22_SMI_POLLING_EN;
writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
}
 
-- 
2.12.1

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[U-Boot] [PATCH v2 19/45] net: mvpp2: adjust mvpp2_{rxq, txq}_init for PPv2.2

2017-03-23 Thread Stefan Roese
From: Thomas Petazzoni 

In PPv2.2, the MVPP2_RXQ_DESC_ADDR_REG and MVPP2_TXQ_DESC_ADDR_REG
registers have a slightly different layout, because they need to contain
a 64-bit address for the RX and TX descriptor arrays. This commit
adjusts those functions accordingly.

Signed-off-by: Thomas Petazzoni 
Signed-off-by: Stefan Roese 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 26 +-
 1 file changed, 21 insertions(+), 5 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index e75979b37a..5e888e7394 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -143,6 +143,7 @@ do {
\
 /* Descriptor Manager Top Registers */
 #define MVPP2_RXQ_NUM_REG  0x2040
 #define MVPP2_RXQ_DESC_ADDR_REG0x2044
+#define MVPP22_DESC_ADDR_OFFS  8
 #define MVPP2_RXQ_DESC_SIZE_REG0x2048
 #define MVPP2_RXQ_DESC_SIZE_MASK   0x3ff0
 #define MVPP2_RXQ_STATUS_UPDATE_REG(rxq)   (0x3000 + 4 * (rxq))
@@ -184,6 +185,7 @@ do {
\
 #define MVPP2_TXQ_RSVD_CLR_REG 0x20b8
 #define MVPP2_TXQ_RSVD_CLR_OFFSET  16
 #define MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu)  (0x2100 + 4 * (cpu))
+#define MVPP22_AGGR_TXQ_DESC_ADDR_OFFS 8
 #define MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu)  (0x2140 + 4 * (cpu))
 #define MVPP2_AGGR_TXQ_DESC_SIZE_MASK  0x3ff0
 #define MVPP2_AGGR_TXQ_STATUS_REG(cpu) (0x2180 + 4 * (cpu))
@@ -3107,6 +3109,8 @@ static int mvpp2_aggr_txq_init(struct udevice *dev,
   int desc_num, int cpu,
   struct mvpp2 *priv)
 {
+   u32 txq_dma;
+
/* Allocate memory for TX descriptors */
aggr_txq->descs = buffer_loc.aggr_tx_descs;
aggr_txq->descs_dma = (dma_addr_t)buffer_loc.aggr_tx_descs;
@@ -3123,10 +3127,16 @@ static int mvpp2_aggr_txq_init(struct udevice *dev,
aggr_txq->next_desc_to_proc = mvpp2_read(priv,
 MVPP2_AGGR_TXQ_INDEX_REG(cpu));
 
-   /* Set Tx descriptors queue starting address */
-   /* indirect access */
-   mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu),
-   aggr_txq->descs_dma);
+   /* Set Tx descriptors queue starting address indirect
+* access
+*/
+   if (priv->hw_version == MVPP21)
+   txq_dma = aggr_txq->descs_dma;
+   else
+   txq_dma = aggr_txq->descs_dma >>
+   MVPP22_AGGR_TXQ_DESC_ADDR_OFFS;
+
+   mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu), txq_dma);
mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu), desc_num);
 
return 0;
@@ -3137,6 +3147,8 @@ static int mvpp2_rxq_init(struct mvpp2_port *port,
  struct mvpp2_rx_queue *rxq)
 
 {
+   u32 rxq_dma;
+
rxq->size = port->rx_ring_size;
 
/* Allocate memory for RX descriptors */
@@ -3155,7 +3167,11 @@ static int mvpp2_rxq_init(struct mvpp2_port *port,
 
/* Set Rx descriptors queue starting address - indirect access */
mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
-   mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, rxq->descs_dma);
+   if (port->priv->hw_version == MVPP21)
+   rxq_dma = rxq->descs_dma;
+   else
+   rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS;
+   mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma);
mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, rxq->size);
mvpp2_write(port->priv, MVPP2_RXQ_INDEX_REG, 0);
 
-- 
2.12.1

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[U-Boot] [PATCH v2 31/45] arm64: mvebu: armada-7k/8k: Enable MVPP2 ethernet driver

2017-03-23 Thread Stefan Roese
Since we've now integrated the A7k/8k support in the mvpp2 ethernet
driver, lets enable the support for both Marvell developments boards.

Signed-off-by: Stefan Roese 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 configs/mvebu_db-88f7040_defconfig | 2 +-
 configs/mvebu_db-88f8040_defconfig | 2 +-
 include/configs/mvebu_armada-8k.h  | 8 
 3 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/configs/mvebu_db-88f7040_defconfig 
b/configs/mvebu_db-88f7040_defconfig
index f20158a117..fdafeb6607 100644
--- a/configs/mvebu_db-88f7040_defconfig
+++ b/configs/mvebu_db-88f7040_defconfig
@@ -47,7 +47,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
+CONFIG_MVPP2=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_PCIE_DW_MVEBU=y
diff --git a/configs/mvebu_db-88f8040_defconfig 
b/configs/mvebu_db-88f8040_defconfig
index 3611b845fe..9866e19778 100644
--- a/configs/mvebu_db-88f8040_defconfig
+++ b/configs/mvebu_db-88f8040_defconfig
@@ -47,7 +47,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
+CONFIG_MVPP2=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_PCIE_DW_MVEBU=y
diff --git a/include/configs/mvebu_armada-8k.h 
b/include/configs/mvebu_armada-8k.h
index a8a9d15b5e..8ee5f27a97 100644
--- a/include/configs/mvebu_armada-8k.h
+++ b/include/configs/mvebu_armada-8k.h
@@ -81,6 +81,14 @@
 #define CONFIG_ENV_SIZE(64 << 10) /* 64KiB */
 #define CONFIG_ENV_SECT_SIZE   (64 << 10) /* 64KiB sectors */
 
+/*
+ * Ethernet Driver configuration
+ */
+#define CONFIG_ENV_OVERWRITE   /* ethaddr can be reprogrammed */
+#define CONFIG_PHY_GIGE/* GbE speed/duplex detect */
+#define CONFIG_ARP_TIMEOUT 200
+#define CONFIG_NET_RETRY_COUNT 50
+
 /* USB 2.0 */
 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
 
-- 
2.12.1

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[U-Boot] [PATCH v2 29/45] net: mvpp2: Enable compilation for Armada 7K/8K platforms

2017-03-23 Thread Stefan Roese
Since Armada 7K/8K is also equipped with a newer version of the MVPP2
ethernet controller, lets enable compilation of this driver for these
platforms.

Signed-off-by: Stefan Roese 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/Kconfig | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 70e36611ea..8aa92790f4 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -124,12 +124,12 @@ config FEC_MXC
  NXP i.MX processors.
 
 config MVPP2
-   bool "Marvell Armada 375 network interface support"
-   depends on ARMADA_375
+   bool "Marvell Armada 375/7K/8K network interface support"
+   depends on ARMADA_375 || ARMADA_8K
select PHYLIB
help
  This driver supports the network interface units in the
- Marvell ARMADA 375 SoC.
+ Marvell ARMADA 375, 7K and 8K SoCs.
 
 config MACB
bool "Cadence MACB/GEM Ethernet Interface"
-- 
2.12.1

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[U-Boot] [PATCH v2 04/45] net: mvpp2: remove unused register definitions

2017-03-23 Thread Stefan Roese
From: Thomas Petazzoni 

Signed-off-by: Thomas Petazzoni 
Signed-off-by: Stefan Roese 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 4 
 1 file changed, 4 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 365180d456..42df1b7e02 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -294,10 +294,6 @@ do {   
\
 #define MVPP2_SRC_ADDR_HIGH0x28
 #define MVPP2_PHY_AN_CFG0_REG  0x34
 #define MVPP2_PHY_AN_STOP_SMI0_MASKBIT(7)
-#define MVPP2_MIB_COUNTERS_BASE(port)  (0x1000 + ((port) >> 1) * \
-   0x400 + (port) * 0x400)
-#define MVPP2_MIB_LATE_COLLISION   0x7c
-#define MVPP2_ISR_SUM_MASK_REG 0x220c
 #define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG 0x305c
 #define MVPP2_EXT_GLOBAL_CTRL_DEFAULT  0x27
 
-- 
2.12.1

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[U-Boot] [PATCH v2 27/45] net: mvpp2: Move probe function from MISC to ETH DM driver

2017-03-23 Thread Stefan Roese
This patch moves the base_probe function mvpp2_base_probe() from the
MISC driver to the ETH driver. When integrated in the MISC driver,
probe is called too early before the U-Boot ethernet infrastructure
(especially the MDIO / PHY interface) has been initialized. Resulting
in errors in mdio_register().

Signed-off-by: Stefan Roese 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 80 -
 1 file changed, 43 insertions(+), 37 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 8751ee85e3..06909e6a3c 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -773,6 +773,8 @@ struct mvpp2 {
unsigned int max_port_rxqs;
 
struct mii_dev *bus;
+
+   int probe_done;
 };
 
 struct mvpp2_pcpu_stats {
@@ -4377,42 +4379,6 @@ static void mvpp2_stop(struct udevice *dev)
mvpp2_cleanup_txqs(port);
 }
 
-static int mvpp2_probe(struct udevice *dev)
-{
-   struct mvpp2_port *port = dev_get_priv(dev);
-   struct mvpp2 *priv = dev_get_priv(dev->parent);
-   int err;
-
-   /* Initialize network controller */
-   err = mvpp2_init(dev, priv);
-   if (err < 0) {
-   dev_err(&pdev->dev, "failed to initialize controller\n");
-   return err;
-   }
-
-   return mvpp2_port_probe(dev, port, dev_of_offset(dev), priv);
-}
-
-static const struct eth_ops mvpp2_ops = {
-   .start  = mvpp2_start,
-   .send   = mvpp2_send,
-   .recv   = mvpp2_recv,
-   .stop   = mvpp2_stop,
-};
-
-static struct driver mvpp2_driver = {
-   .name   = "mvpp2",
-   .id = UCLASS_ETH,
-   .probe  = mvpp2_probe,
-   .ops= &mvpp2_ops,
-   .priv_auto_alloc_size = sizeof(struct mvpp2_port),
-   .platdata_auto_alloc_size = sizeof(struct eth_pdata),
-};
-
-/*
- * Use a MISC device to bind the n instances (child nodes) of the
- * network base controller in UCLASS_ETH.
- */
 static int mvpp2_base_probe(struct udevice *dev)
 {
struct mvpp2 *priv = dev_get_priv(dev);
@@ -4503,6 +4469,47 @@ static int mvpp2_base_probe(struct udevice *dev)
return mdio_register(bus);
 }
 
+static int mvpp2_probe(struct udevice *dev)
+{
+   struct mvpp2_port *port = dev_get_priv(dev);
+   struct mvpp2 *priv = dev_get_priv(dev->parent);
+   int err;
+
+   /* Only call the probe function for the parent once */
+   if (!priv->probe_done) {
+   err = mvpp2_base_probe(dev->parent);
+   priv->probe_done = 1;
+   }
+   /* Initialize network controller */
+   err = mvpp2_init(dev, priv);
+   if (err < 0) {
+   dev_err(&pdev->dev, "failed to initialize controller\n");
+   return err;
+   }
+
+   return mvpp2_port_probe(dev, port, dev_of_offset(dev), priv);
+}
+
+static const struct eth_ops mvpp2_ops = {
+   .start  = mvpp2_start,
+   .send   = mvpp2_send,
+   .recv   = mvpp2_recv,
+   .stop   = mvpp2_stop,
+};
+
+static struct driver mvpp2_driver = {
+   .name   = "mvpp2",
+   .id = UCLASS_ETH,
+   .probe  = mvpp2_probe,
+   .ops= &mvpp2_ops,
+   .priv_auto_alloc_size = sizeof(struct mvpp2_port),
+   .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+};
+
+/*
+ * Use a MISC device to bind the n instances (child nodes) of the
+ * network base controller in UCLASS_ETH.
+ */
 static int mvpp2_base_bind(struct udevice *parent)
 {
const void *blob = gd->fdt_blob;
@@ -4560,6 +4567,5 @@ U_BOOT_DRIVER(mvpp2_base) = {
.id = UCLASS_MISC,
.of_match = mvpp2_ids,
.bind   = mvpp2_base_bind,
-   .probe  = mvpp2_base_probe,
.priv_auto_alloc_size = sizeof(struct mvpp2),
 };
-- 
2.12.1

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[U-Boot] [PATCH v2 07/45] net: mvpp2: enable building on 64-bit platforms

2017-03-23 Thread Stefan Roese
From: Thomas Petazzoni 

The mvpp2 is going to be extended to support the Marvell Armada 7K/8K
platform, which is ARM64. As a preparation to this work, this commit
enables building the mvpp2 driver on ARM64, by:

 - Adjusting the Kconfig dependency

 - Fixing the types used in the driver so that they are 32/64-bits
   compliant. We use dma_addr_t for DMA addresses, and unsigned long
   for virtual addresses.

It is worth mentioning that after this commit, the driver is for now
still only used on 32-bits platforms, and will only work on 32-bits
platforms.

Changed by Stefan for U-Boot:
Removed the Kconfig change as it does not apply to U-Boot this way.

Signed-off-by: Thomas Petazzoni 
Signed-off-by: Stefan Roese 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 14 --
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 769680ac45..d5085909e4 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -2219,7 +2219,8 @@ static int mvpp2_bm_pool_create(struct udevice *dev,
if (!bm_pool->virt_addr)
return -ENOMEM;
 
-   if (!IS_ALIGNED((u32)bm_pool->virt_addr, MVPP2_BM_POOL_PTR_ALIGN)) {
+   if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr,
+   MVPP2_BM_POOL_PTR_ALIGN)) {
dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n",
bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN);
return -ENOMEM;
@@ -2359,14 +2360,15 @@ static inline u32 mvpp2_bm_cookie_pool_set(u32 cookie, 
int pool)
 }
 
 /* Get pool number from a BM cookie */
-static inline int mvpp2_bm_cookie_pool_get(u32 cookie)
+static inline int mvpp2_bm_cookie_pool_get(unsigned long cookie)
 {
return (cookie >> MVPP2_BM_COOKIE_POOL_OFFS) & 0xFF;
 }
 
 /* Release buffer to BM */
 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
-u32 buf_phys_addr, u32 buf_virt_addr)
+dma_addr_t buf_phys_addr,
+unsigned long buf_virt_addr)
 {
mvpp2_write(port->priv, MVPP2_BM_VIRT_RLS_REG, buf_virt_addr);
mvpp2_write(port->priv, MVPP2_BM_PHY_RLS_REG(pool), buf_phys_addr);
@@ -2397,8 +2399,8 @@ static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
 
for (i = 0; i < buf_num; i++) {
mvpp2_bm_pool_put(port, bm_pool->id,
- (u32)buffer_loc.rx_buffer[i],
- (u32)buffer_loc.rx_buffer[i]);
+ (dma_addr_t)buffer_loc.rx_buffer[i],
+ (unsigned long)buffer_loc.rx_buffer[i]);
 
}
 
@@ -,7 +3335,7 @@ static int mvpp2_rx_refill(struct mvpp2_port *port,
   struct mvpp2_bm_pool *bm_pool,
   u32 bm, u32 phys_addr)
 {
-   mvpp2_pool_refill(port, bm, phys_addr, phys_addr);
+   mvpp2_pool_refill(port, bm, phys_addr, (unsigned long)phys_addr);
return 0;
 }
 
-- 
2.12.1

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[U-Boot] [PATCH v2 05/45] net: mvpp2: fix indentation of MVPP2_EXT_GLOBAL_CTRL_DEFAULT

2017-03-23 Thread Stefan Roese
From: Thomas Petazzoni 

Signed-off-by: Thomas Petazzoni 
Signed-off-by: Stefan Roese 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 42df1b7e02..74ae1a2d2a 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -295,7 +295,7 @@ do {
\
 #define MVPP2_PHY_AN_CFG0_REG  0x34
 #define MVPP2_PHY_AN_STOP_SMI0_MASKBIT(7)
 #define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG 0x305c
-#define MVPP2_EXT_GLOBAL_CTRL_DEFAULT  0x27
+#define MVPP2_EXT_GLOBAL_CTRL_DEFAULT  0x27
 
 /* Per-port registers */
 #define MVPP2_GMAC_CTRL_0_REG  0x0
-- 
2.12.1

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Re: [U-Boot] [PATCH v4 19/20] rockchip: rk3188: Add Radxa Rock board

2017-03-23 Thread Simon Glass
Hi Heiko,

On 21 February 2017 at 13:35, Simon Glass  wrote:
> On 18 February 2017 at 11:46, Heiko Stuebner  wrote:
>> The Rock is a RK3188 based single board computer by Radxa.
>> Currently it still relies on the proprietary DDR init and
>> cannot use the generic SPL, but at least is able to boot
>> a linux kernel and system up to a regular login prompt.
>>
>> Signed-off-by: Heiko Stuebner 
>> Reviewed-by: Simon Glass 
>> Tested-by: Kever Yang 
>> ---
>>  arch/arm/dts/Makefile |   1 +
>>  arch/arm/dts/rk3188-radxarock.dts | 382 
>> ++
>>  arch/arm/mach-rockchip/rk3188/Kconfig |  11 +
>>  board/radxa/rock/Kconfig  |  15 ++
>>  board/radxa/rock/MAINTAINERS  |   6 +
>>  board/radxa/rock/Makefile |   7 +
>>  board/radxa/rock/rock.c   |   7 +
>>  configs/rock_defconfig|  56 +
>>  include/configs/rock.h|  30 +++
>>  9 files changed, 515 insertions(+)
>>  create mode 100644 arch/arm/dts/rk3188-radxarock.dts
>>  create mode 100644 board/radxa/rock/Kconfig
>>  create mode 100644 board/radxa/rock/MAINTAINERS
>>  create mode 100644 board/radxa/rock/Makefile
>>  create mode 100644 board/radxa/rock/rock.c
>>  create mode 100644 configs/rock_defconfig
>>  create mode 100644 include/configs/rock.h
>
> Applied to u-boot-rockchip, thanks!

Just a reminder that I had to drop this patch as it does not build.
Can you please resend this one? I have also reverted the README patch
but can apply that myself once this board is enabled.

Regards,
Simon
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[U-Boot] [PATCH v2 01/45] bitops.h: Include bitsperlong.h as needed for GENMASK_ULL

2017-03-23 Thread Stefan Roese
The macro GENMASK_ULL needs the BITS_PER_LONG_LONG macro which is
defined in the bitsperlong.h header. Lets include this header as
the upcoming A7k/8k support in the Marvell mvpp2 ethernet driver
uses this macro.

Signed-off-by: Stefan Roese 
Reviewed-by: Tom Rini 
Reviewed-by: Joe Hershberger 

---

Changes in v2:
- Added Reviewed-by from Tom and Joe

 include/linux/bitops.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/linux/bitops.h b/include/linux/bitops.h
index 1b2e4915a0..576b15dc53 100644
--- a/include/linux/bitops.h
+++ b/include/linux/bitops.h
@@ -2,6 +2,7 @@
 #define _LINUX_BITOPS_H
 
 #include 
+#include 
 #include 
 
 #define BIT(nr)(1UL << (nr))
-- 
2.12.1

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[U-Boot] [PATCH v2 20/45] net: mvpp2: handle register mapping and access for PPv2.2

2017-03-23 Thread Stefan Roese
From: Thomas Petazzoni 

This commit adjusts the mvpp2 driver register mapping and access logic
to support PPv2.2, to handle a number of differences.

Due to how the registers are laid out in memory, the Device Tree binding
for the "reg" property is different:

- On PPv2.1, we had a first area for the common registers, and then one
  area per port.

- On PPv2.2, we have a first area for the common registers, and a
  second area for all the per-ports registers.

In addition, on PPv2.2, the area for the common registers is split into
so-called "address spaces" of 64 KB each. They allow to access the same
registers, but from different CPUs. Hence the introduction of cpu_base[]
in 'struct mvpp2', and the modification of the mvpp2_write() and
mvpp2_read() register accessors. For PPv2.1, the compatibility is
preserved by using an "address space" size of 0.

Changed by Stefan for U-Boot:
Since we don't support multiple CPUs in U-Boot, I've removed all the
code, macros and variables introduced in the Linux patch version for this.

Signed-off-by: Thomas Petazzoni 
Signed-off-by: Stefan Roese 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe
- Rebased on latest patchset version from Thomas available in net-next,
  mostly smaller changes, making checkpatch happy.

 drivers/net/mvpp2.c | 46 +-
 1 file changed, 37 insertions(+), 9 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 5e888e7394..645a818df6 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -342,6 +342,9 @@ do {
\
 #define  MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \
MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK)
 
+#define MVPP22_PORT_BASE   0x30e00
+#define MVPP22_PORT_OFFSET 0x1000
+
 #define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
 
 /* Descriptor ring Macros */
@@ -702,6 +705,7 @@ struct mvpp2 {
/* Shared registers' base addresses */
void __iomem *base;
void __iomem *lms_base;
+   void __iomem *iface_base;
 
/* List of pointers to port structures */
struct mvpp2_port **port_list;
@@ -736,6 +740,11 @@ struct mvpp2_pcpu_stats {
 struct mvpp2_port {
u8 id;
 
+   /* Index of the port from the "group of ports" complex point
+* of view
+*/
+   int gop_id;
+
int irq;
 
struct mvpp2 *priv;
@@ -3270,7 +3279,7 @@ static int mvpp2_txq_init(struct mvpp2_port *port,
 
mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG,
MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 |
-   MVPP2_PREF_BUF_THRESH(desc_per_txq/2));
+   MVPP2_PREF_BUF_THRESH(desc_per_txq / 2));
 
/* WRR / EJP configuration - indirect access */
tx_port_num = mvpp2_egress_port(port);
@@ -3779,11 +3788,24 @@ static int mvpp2_port_probe(struct udevice *dev,
port->phy_interface = phy_mode;
port->phyaddr = phyaddr;
 
-   port->base = (void __iomem *)dev_get_addr_index(dev->parent,
-   priv_common_regs_num
-   + id);
-   if (IS_ERR(port->base))
-   return PTR_ERR(port->base);
+   if (priv->hw_version == MVPP21) {
+   port->base = (void __iomem *)dev_get_addr_index(
+   dev->parent, priv_common_regs_num + id);
+   if (IS_ERR(port->base))
+   return PTR_ERR(port->base);
+   } else {
+   u32 gop_id;
+
+   gop_id = fdtdec_get_int(gd->fdt_blob, port_node,
+   "gop-port-id", -1);
+   if (id == -1) {
+   dev_err(&pdev->dev, "missing gop-port-id value\n");
+   return -EINVAL;
+   }
+
+   port->base = priv->iface_base + MVPP22_PORT_BASE +
+   gop_id * MVPP22_PORT_OFFSET;
+   }
 
port->tx_ring_size = MVPP2_MAX_TXD;
port->rx_ring_size = MVPP2_MAX_RXD;
@@ -4307,9 +4329,15 @@ static int mvpp2_base_probe(struct udevice *dev)
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);
 
-   priv->lms_base = (void *)dev_get_addr_index(dev, 1);
-   if (IS_ERR(priv->lms_base))
-   return PTR_ERR(priv->lms_base);
+   if (priv->hw_version == MVPP21) {
+   priv->lms_base = (void *)dev_get_addr_index(dev, 1);
+   if (IS_ERR(priv->lms_base))
+   return PTR_ERR(priv->lms_base);
+   } else {
+   priv->iface_base = (void *)dev_get_addr_index(dev, 1);
+   if (IS_ERR(priv->iface_base))
+   return PTR_ERR(priv->iface_base);
+   }
 
/* Finally create and register the MDIO bus driver */
bus = 

[U-Boot] [PATCH v2 35/45] net: include/phy.h: Add new PHY interface modes

2017-03-23 Thread Stefan Roese
This patch adds the new PHY interface modes XAUI, RXAUI and SFI that will
be used by the PPv2.2 support in the Marvell mvpp2 ethernet driver.

Signed-off-by: Stefan Roese 
Cc: Stefan Chulski 
Cc: Kostya Porotchkin 
Cc: Nadav Haklai 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 include/phy.h | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/include/phy.h b/include/phy.h
index 5477496e0e..8e507cd7a6 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -61,6 +61,9 @@ typedef enum {
PHY_INTERFACE_MODE_RGMII_TXID,
PHY_INTERFACE_MODE_RTBI,
PHY_INTERFACE_MODE_XGMII,
+   PHY_INTERFACE_MODE_XAUI,
+   PHY_INTERFACE_MODE_RXAUI,
+   PHY_INTERFACE_MODE_SFI,
PHY_INTERFACE_MODE_NONE,/* Must be last */
 
PHY_INTERFACE_MODE_COUNT,
@@ -80,6 +83,9 @@ static const char *phy_interface_strings[] = {
[PHY_INTERFACE_MODE_RGMII_TXID] = "rgmii-txid",
[PHY_INTERFACE_MODE_RTBI]   = "rtbi",
[PHY_INTERFACE_MODE_XGMII]  = "xgmii",
+   [PHY_INTERFACE_MODE_XAUI]   = "xaui",
+   [PHY_INTERFACE_MODE_RXAUI]  = "rxaui",
+   [PHY_INTERFACE_MODE_SFI]= "sfi",
[PHY_INTERFACE_MODE_NONE]   = "",
 };
 
-- 
2.12.1

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[U-Boot] [PATCH v2 13/45] net: mvpp2: add hw_version field in "struct mvpp2"

2017-03-23 Thread Stefan Roese
From: Thomas Petazzoni 

In preparation to the introduction for the support of PPv2.2 in the
mvpp2 driver, this commit adds a hw_version field to the struct
mvpp2, and uses the .data field of the DT match table to fill it in.

Having the MVPP21 and MVPP22 definitions available will allow to start
adding the necessary conditional code to support PPv2.2.

Signed-off-by: Thomas Petazzoni 
Signed-off-by: Stefan Roese 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 11 ++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index d199eafe30..9683439d23 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -707,6 +707,9 @@ struct mvpp2 {
/* Tclk value */
u32 tclk;
 
+   /* HW version */
+   enum { MVPP21, MVPP22 } hw_version;
+
struct mii_dev *bus;
 };
 
@@ -4132,6 +4135,9 @@ static int mvpp2_base_probe(struct udevice *dev)
u32 size = 0;
int i;
 
+   /* Save hw-version */
+   priv->hw_version = dev_get_driver_data(dev);
+
/*
 * U-Boot special buffer handling:
 *
@@ -4234,7 +4240,10 @@ static int mvpp2_base_bind(struct udevice *parent)
 }
 
 static const struct udevice_id mvpp2_ids[] = {
-   { .compatible = "marvell,armada-375-pp2" },
+   {
+   .compatible = "marvell,armada-375-pp2",
+   .data = MVPP21,
+   },
{ }
 };
 
-- 
2.12.1

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[U-Boot] [PATCH v2 22/45] net: mvpp2: add AXI bridge initialization for PPv2.2

2017-03-23 Thread Stefan Roese
From: Thomas Petazzoni 

The PPv2.2 unit is connected to an AXI bus on Armada 7K/8K, so this
commit adds the necessary initialization of the AXI bridge.

Signed-off-by: Thomas Petazzoni 
Signed-off-by: Stefan Roese 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 85 +
 1 file changed, 85 insertions(+)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 51922c06aa..b56af82f92 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -198,6 +198,34 @@ do {   
\
 #define MVPP2_WIN_REMAP(w) (0x4040 + ((w) << 2))
 #define MVPP2_BASE_ADDR_ENABLE 0x4060
 
+/* AXI Bridge Registers */
+#define MVPP22_AXI_BM_WR_ATTR_REG  0x4100
+#define MVPP22_AXI_BM_RD_ATTR_REG  0x4104
+#define MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG 0x4110
+#define MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG   0x4114
+#define MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG   0x4118
+#define MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG   0x411c
+#define MVPP22_AXI_RX_DATA_WR_ATTR_REG 0x4120
+#define MVPP22_AXI_TX_DATA_RD_ATTR_REG 0x4130
+#define MVPP22_AXI_RD_NORMAL_CODE_REG  0x4150
+#define MVPP22_AXI_RD_SNOOP_CODE_REG   0x4154
+#define MVPP22_AXI_WR_NORMAL_CODE_REG  0x4160
+#define MVPP22_AXI_WR_SNOOP_CODE_REG   0x4164
+
+/* Values for AXI Bridge registers */
+#define MVPP22_AXI_ATTR_CACHE_OFFS 0
+#define MVPP22_AXI_ATTR_DOMAIN_OFFS12
+
+#define MVPP22_AXI_CODE_CACHE_OFFS 0
+#define MVPP22_AXI_CODE_DOMAIN_OFFS4
+
+#define MVPP22_AXI_CODE_CACHE_NON_CACHE0x3
+#define MVPP22_AXI_CODE_CACHE_WR_CACHE 0x7
+#define MVPP22_AXI_CODE_CACHE_RD_CACHE 0xb
+
+#define MVPP22_AXI_CODE_DOMAIN_OUTER_DOM   2
+#define MVPP22_AXI_CODE_DOMAIN_SYSTEM  3
+
 /* Interrupt Cause and Mask registers */
 #define MVPP2_ISR_RX_THRESHOLD_REG(rxq)(0x5200 + 4 * (rxq))
 #define MVPP2_ISR_RXQ_GROUP_REG(rxq)   (0x5400 + 4 * (rxq))
@@ -3879,6 +3907,60 @@ static void mvpp2_rx_fifo_init(struct mvpp2 *priv)
mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
 }
 
+static void mvpp2_axi_init(struct mvpp2 *priv)
+{
+   u32 val, rdval, wrval;
+
+   mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0);
+
+   /* AXI Bridge Configuration */
+
+   rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE
+   << MVPP22_AXI_ATTR_CACHE_OFFS;
+   rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
+   << MVPP22_AXI_ATTR_DOMAIN_OFFS;
+
+   wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE
+   << MVPP22_AXI_ATTR_CACHE_OFFS;
+   wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
+   << MVPP22_AXI_ATTR_DOMAIN_OFFS;
+
+   /* BM */
+   mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval);
+   mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval);
+
+   /* Descriptors */
+   mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval);
+   mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval);
+   mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval);
+   mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval);
+
+   /* Buffer Data */
+   mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval);
+   mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval);
+
+   val = MVPP22_AXI_CODE_CACHE_NON_CACHE
+   << MVPP22_AXI_CODE_CACHE_OFFS;
+   val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM
+   << MVPP22_AXI_CODE_DOMAIN_OFFS;
+   mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val);
+   mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val);
+
+   val = MVPP22_AXI_CODE_CACHE_RD_CACHE
+   << MVPP22_AXI_CODE_CACHE_OFFS;
+   val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
+   << MVPP22_AXI_CODE_DOMAIN_OFFS;
+
+   mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val);
+
+   val = MVPP22_AXI_CODE_CACHE_WR_CACHE
+   << MVPP22_AXI_CODE_CACHE_OFFS;
+   val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
+   << MVPP22_AXI_CODE_DOMAIN_OFFS;
+
+   mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val);
+}
+
 /* Initialize network controller common part HW */
 static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv)
 {
@@ -3897,6 +3979,9 @@ static int mvpp2_init(struct udevice *dev, struct mvpp2 
*priv)
if (dram_target_info)
mvpp2_conf_mbus_windows(dram_target_info, priv);
 
+   if (priv->hw_version == MVPP22)
+   mvpp2_axi_init(priv);
+
/* Disable HW PHY polling */
if (priv->hw_version == MVPP21) {
val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
-- 
2.12.1

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[U-Boot] [PATCH v2 03/45] net: mvpp2: simplify mvpp2_bm_bufs_add()

2017-03-23 Thread Stefan Roese
From: Thomas Petazzoni 

The mvpp2_bm_bufs_add() currently creates a fake cookie by calling
mvpp2_bm_cookie_pool_set(), just to be able to call
mvpp2_pool_refill(). But all what mvpp2_pool_refill() does is extract
the pool ID from the cookie, and call mvpp2_bm_pool_put() with this ID.

Instead of doing this convoluted thing, just call mvpp2_bm_pool_put()
directly, since we have the BM pool ID.

Signed-off-by: Thomas Petazzoni 
Signed-off-by: Stefan Roese 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 93eb1f2dd4..365180d456 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -2390,7 +2390,6 @@ static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
 struct mvpp2_bm_pool *bm_pool, int buf_num)
 {
int i;
-   u32 bm;
 
if (buf_num < 0 ||
(buf_num + bm_pool->buf_num > bm_pool->size)) {
@@ -2400,10 +2399,11 @@ static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
return 0;
}
 
-   bm = mvpp2_bm_cookie_pool_set(0, bm_pool->id);
for (i = 0; i < buf_num; i++) {
-   mvpp2_pool_refill(port, bm, (u32)buffer_loc.rx_buffer[i],
+   mvpp2_bm_pool_put(port, bm_pool->id,
+ (u32)buffer_loc.rx_buffer[i],
  (u32)buffer_loc.rx_buffer[i]);
+
}
 
/* Update BM driver with number of buffers added to pool */
-- 
2.12.1

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[U-Boot] [PATCH v2 17/45] net: mvpp2: adapt the mvpp2_rxq_*_pool_set functions to PPv2.2

2017-03-23 Thread Stefan Roese
From: Thomas Petazzoni 

The MVPP2_RXQ_CONFIG_REG register has a slightly different layout
between PPv2.1 and PPv2.2, so this commit adapts the functions modifying
this register to accommodate for both the PPv2.1 and PPv2.2 cases.

Signed-off-by: Thomas Petazzoni 
Signed-off-by: Stefan Roese 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 19 ---
 1 file changed, 12 insertions(+), 7 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 4f4e6749dc..e5b42b9e66 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -91,9 +91,11 @@ do { 
\
 #define MVPP2_SNOOP_PKT_SIZE_MASK  0x1ff
 #define MVPP2_SNOOP_BUF_HDR_MASK   BIT(9)
 #define MVPP2_RXQ_POOL_SHORT_OFFS  20
-#define MVPP2_RXQ_POOL_SHORT_MASK  0x70
+#define MVPP21_RXQ_POOL_SHORT_MASK 0x70
+#define MVPP22_RXQ_POOL_SHORT_MASK 0xf0
 #define MVPP2_RXQ_POOL_LONG_OFFS   24
-#define MVPP2_RXQ_POOL_LONG_MASK   0x700
+#define MVPP21_RXQ_POOL_LONG_MASK  0x700
+#define MVPP22_RXQ_POOL_LONG_MASK  0xf00
 #define MVPP2_RXQ_PACKET_OFFSET_OFFS   28
 #define MVPP2_RXQ_PACKET_OFFSET_MASK   0x7000
 #define MVPP2_RXQ_DISABLE_MASK BIT(31)
@@ -2467,17 +2469,20 @@ static int mvpp2_bm_init(struct udevice *dev, struct 
mvpp2 *priv)
 static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port,
int lrxq, int long_pool)
 {
-   u32 val;
+   u32 val, mask;
int prxq;
 
/* Get queue physical ID */
prxq = port->rxqs[lrxq]->id;
 
-   val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
-   val &= ~MVPP2_RXQ_POOL_LONG_MASK;
-   val |= ((long_pool << MVPP2_RXQ_POOL_LONG_OFFS) &
-   MVPP2_RXQ_POOL_LONG_MASK);
+   if (port->priv->hw_version == MVPP21)
+   mask = MVPP21_RXQ_POOL_LONG_MASK;
+   else
+   mask = MVPP22_RXQ_POOL_LONG_MASK;
 
+   val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
+   val &= ~mask;
+   val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask;
mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
 }
 
-- 
2.12.1

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[U-Boot] [PATCH v2 21/45] net: mvpp2: handle misc PPv2.1/PPv2.2 differences

2017-03-23 Thread Stefan Roese
From: Thomas Petazzoni 

This commit handles a few miscellaneous differences between PPv2.1 and
PPv2.2 in different areas, where code done for PPv2.1 doesn't apply for
PPv2.2 or needs to be adjusted (getting the MAC address, disabling PHY
polling, etc.).

Changed by Stefan for U-Boot:
Since mvpp2_port_power_up() has multiple callers in U-Boot, the U-Boot
version of this patch does not remove this function but simply adds the
check for MVPP21 before the mvpp2_port_fc_adv_enable() call.

Signed-off-by: Thomas Petazzoni 
Signed-off-by: Stefan Roese 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 25 +++--
 1 file changed, 19 insertions(+), 6 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 645a818df6..51922c06aa 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -342,6 +342,9 @@ do {
\
 #define  MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \
MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK)
 
+#define MVPP22_SMI_MISC_CFG_REG0x1204
+#define  MVPP22_SMI_POLLING_EN BIT(10)
+
 #define MVPP22_PORT_BASE   0x30e00
 #define MVPP22_PORT_OFFSET 0x1000
 
@@ -3639,9 +3642,12 @@ static int mvpp2_open(struct udevice *dev, struct 
mvpp2_port *port)
 
 static void mvpp2_port_power_up(struct mvpp2_port *port)
 {
+   struct mvpp2 *priv = port->priv;
+
mvpp2_port_mii_set(port);
mvpp2_port_periodic_xon_disable(port);
-   mvpp2_port_fc_adv_enable(port);
+   if (priv->hw_version == MVPP21)
+   mvpp2_port_fc_adv_enable(port);
mvpp2_port_reset(port);
 }
 
@@ -3892,9 +3898,15 @@ static int mvpp2_init(struct udevice *dev, struct mvpp2 
*priv)
mvpp2_conf_mbus_windows(dram_target_info, priv);
 
/* Disable HW PHY polling */
-   val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
-   val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
-   writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
+   if (priv->hw_version == MVPP21) {
+   val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
+   val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
+   writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
+   } else {
+   val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
+   val &= ~MVPP22_SMI_POLLING_EN;
+   writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
+   }
 
/* Allocate and initialize aggregated TXQs */
priv->aggr_txqs = devm_kcalloc(dev, num_present_cpus(),
@@ -3920,8 +3932,9 @@ static int mvpp2_init(struct udevice *dev, struct mvpp2 
*priv)
mvpp2_write(priv, MVPP2_ISR_RXQ_GROUP_REG(i),
CONFIG_MV_ETH_RXQ);
 
-   writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
-  priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
+   if (priv->hw_version == MVPP21)
+   writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
+  priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
 
/* Allow cache snoop when transmiting packets */
mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1);
-- 
2.12.1

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[U-Boot] [PATCH v2 16/45] net: mvpp2: adjust the allocation/free of BM pools for PPv2.2

2017-03-23 Thread Stefan Roese
From: Thomas Petazzoni 

This commit adjusts the allocation and freeing of BM pools to support
PPv2.2. This involves:

- Checking that the number of buffer pointers is a multiple of 16, as
  required by the hardware.

- Adjusting the size of the DMA coherent area allocated for buffer
  pointers. Indeed, PPv2.2 needs space for 2 pointers of 64-bits per
  buffer, as opposed to 2 pointers of 32-bits per buffer in
  PPv2.1. The size in bytes is now stored in a new field of the
  mvpp2_bm_pool structure.

- On PPv2.2, getting the physical and virtual address of each buffer
  requires reading the MVPP2_BM_ADDR_HIGH_ALLOC to get the high order
  bits of those addresses. A new utility function
  mvpp2_bm_bufs_get_addrs() is introduced to handle this.

- On PPv2.2, releasing a buffer requires writing the high order 32 bits
  of the physical address to MVPP2_BM_PHY_VIRT_HIGH_RLS_REG. We no
  longer need to write the virtual address to MVPP2_BM_VIRT_RLS_REG.

Signed-off-by: Thomas Petazzoni 
Signed-off-by: Stefan Roese 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 39 ---
 1 file changed, 36 insertions(+), 3 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 605c8bcd70..4f4e6749dc 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -251,14 +251,23 @@ do {  
\
 #define MVPP2_BM_PHY_ALLOC_REG(pool)   (0x6400 + ((pool) * 4))
 #define MVPP2_BM_PHY_ALLOC_GRNTD_MASK  BIT(0)
 #define MVPP2_BM_VIRT_ALLOC_REG0x6440
+#define MVPP2_BM_ADDR_HIGH_ALLOC   0x6444
+#define MVPP2_BM_ADDR_HIGH_PHYS_MASK   0xff
+#define MVPP2_BM_ADDR_HIGH_VIRT_MASK   0xff00
+#define MVPP2_BM_ADDR_HIGH_VIRT_SHIFT  8
 #define MVPP2_BM_PHY_RLS_REG(pool) (0x6480 + ((pool) * 4))
 #define MVPP2_BM_PHY_RLS_MC_BUFF_MASK  BIT(0)
 #define MVPP2_BM_PHY_RLS_PRIO_EN_MASK  BIT(1)
 #define MVPP2_BM_PHY_RLS_GRNTD_MASKBIT(2)
 #define MVPP2_BM_VIRT_RLS_REG  0x64c0
-#define MVPP2_BM_MC_RLS_REG0x64c4
+#define MVPP21_BM_MC_RLS_REG   0x64c4
 #define MVPP2_BM_MC_ID_MASK0xfff
 #define MVPP2_BM_FORCE_RELEASE_MASKBIT(12)
+#define MVPP22_BM_ADDR_HIGH_RLS_REG0x64c4
+#define MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK  0xff
+#defineMVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK   0xff00
+#define MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT 8
+#define MVPP22_BM_MC_RLS_REG   0x64d4
 
 /* TX Scheduler registers */
 #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000
@@ -2332,6 +2341,12 @@ static int mvpp2_bm_pool_create(struct udevice *dev,
 {
u32 val;
 
+   /* Number of buffer pointers must be a multiple of 16, as per
+* hardware constraints
+*/
+   if (!IS_ALIGNED(size, 16))
+   return -EINVAL;
+
bm_pool->virt_addr = buffer_loc.bm_pool[bm_pool->id];
bm_pool->dma_addr = (dma_addr_t)buffer_loc.bm_pool[bm_pool->id];
if (!bm_pool->virt_addr)
@@ -2345,7 +2360,7 @@ static int mvpp2_bm_pool_create(struct udevice *dev,
}
 
mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),
-   bm_pool->dma_addr);
+   lower_32_bits(bm_pool->dma_addr));
mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);
 
val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
@@ -2488,6 +2503,21 @@ static inline void mvpp2_bm_pool_put(struct mvpp2_port 
*port, int pool,
 dma_addr_t buf_dma_addr,
 unsigned long buf_phys_addr)
 {
+   if (port->priv->hw_version == MVPP22) {
+   u32 val = 0;
+
+   if (sizeof(dma_addr_t) == 8)
+   val |= upper_32_bits(buf_dma_addr) &
+   MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK;
+
+   if (sizeof(phys_addr_t) == 8)
+   val |= (upper_32_bits(buf_phys_addr)
+   << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) &
+   MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK;
+
+   mvpp2_write(port->priv, MVPP22_BM_ADDR_HIGH_RLS_REG, val);
+   }
+
/* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply
 * returned in the "cookie" field of the RX
 * descriptor. Instead of storing the virtual address, we
@@ -4237,7 +4267,10 @@ static int mvpp2_base_probe(struct udevice *dev)
for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
buffer_loc.bm_pool[i] =
(unsigned long *)((unsigned long)bd_space + size);
-   size += MVPP2_BM_POOL_SIZE_MAX * sizeof(u32);
+   if (priv->hw_version == MVPP21)
+   size += MVPP2_BM_POOL_SIZE

[U-Boot] [PATCH v2 38/45] net: mvpp2: Add GoP and NetC support for ports 2 & 3 (RGMII & SGMII)

2017-03-23 Thread Stefan Roese
This patch adds the GoP (Group of Ports) and NetC (Net Complex) setup to
the Marvell mvpp2 ethernet driver. This code is mostly copied from the
Marvell U-Boot version and was written by Stefan Chulski. Please
note that only RGMII and SGMII support have been added, as these are
the only interfaces that this code has been tested with.

Signed-off-by: Stefan Roese 
Cc: Stefan Chulski 
Cc: Kostya Porotchkin 
Cc: Nadav Haklai 
Cc: Joe Hershberger 

---

Changes in v2:
- New patch

 drivers/net/mvpp2.c | 766 +++-
 1 file changed, 758 insertions(+), 8 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 6f9a4137f8..76370faff0 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -355,6 +355,7 @@ do {
\
 /* Per-port registers */
 #define MVPP2_GMAC_CTRL_0_REG  0x0
 #define  MVPP2_GMAC_PORT_EN_MASK   BIT(0)
+#define  MVPP2_GMAC_PORT_TYPE_MASK BIT(1)
 #define  MVPP2_GMAC_MAX_RX_SIZE_OFFS   2
 #define  MVPP2_GMAC_MAX_RX_SIZE_MASK   0x7ffc
 #define  MVPP2_GMAC_MIB_CNTR_EN_MASK   BIT(15)
@@ -366,29 +367,131 @@ do { 
\
 #define  MVPP2_GMAC_SA_LOW_OFFS7
 #define MVPP2_GMAC_CTRL_2_REG  0x8
 #define  MVPP2_GMAC_INBAND_AN_MASK BIT(0)
+#define  MVPP2_GMAC_SGMII_MODE_MASKBIT(0)
 #define  MVPP2_GMAC_PCS_ENABLE_MASKBIT(3)
 #define  MVPP2_GMAC_PORT_RGMII_MASKBIT(4)
+#define  MVPP2_GMAC_PORT_DIS_PADING_MASK   BIT(5)
 #define  MVPP2_GMAC_PORT_RESET_MASKBIT(6)
+#define  MVPP2_GMAC_CLK_125_BYPS_EN_MASK   BIT(9)
 #define MVPP2_GMAC_AUTONEG_CONFIG  0xc
 #define  MVPP2_GMAC_FORCE_LINK_DOWNBIT(0)
 #define  MVPP2_GMAC_FORCE_LINK_PASSBIT(1)
+#define  MVPP2_GMAC_EN_PCS_AN  BIT(2)
+#define  MVPP2_GMAC_AN_BYPASS_EN   BIT(3)
 #define  MVPP2_GMAC_CONFIG_MII_SPEED   BIT(5)
 #define  MVPP2_GMAC_CONFIG_GMII_SPEED  BIT(6)
 #define  MVPP2_GMAC_AN_SPEED_ENBIT(7)
 #define  MVPP2_GMAC_FC_ADV_EN  BIT(9)
+#define  MVPP2_GMAC_EN_FC_AN   BIT(11)
 #define  MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12)
 #define  MVPP2_GMAC_AN_DUPLEX_EN   BIT(13)
+#define  MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIGBIT(15)
 #define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c
 #define  MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS6
 #define  MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK0x1fc0
 #define  MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \
MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK)
+#define MVPP2_GMAC_CTRL_4_REG  0x90
+#define  MVPP2_GMAC_CTRL4_EXT_PIN_GMII_SEL_MASKBIT(0)
+#define  MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK  BIT(5)
+#define  MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK BIT(6)
+#define  MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASKBIT(7)
 
-#define MVPP22_SMI_MISC_CFG_REG0x1204
+/*
+ * Per-port XGMAC registers. PPv2.2 only, only for GOP port 0,
+ * relative to port->base.
+ */
+
+/* Port Mac Control0 */
+#define MVPP22_XLG_CTRL0_REG   0x100
+#define  MVPP22_XLG_PORT_ENBIT(0)
+#define  MVPP22_XLG_MAC_RESETN BIT(1)
+#define  MVPP22_XLG_RX_FC_EN   BIT(7)
+#define  MVPP22_XLG_MIBCNT_DIS BIT(13)
+/* Port Mac Control1 */
+#define MVPP22_XLG_CTRL1_REG   0x104
+#define  MVPP22_XLG_MAX_RX_SIZE_OFFS   0
+#define  MVPP22_XLG_MAX_RX_SIZE_MASK   0x1fff
+/* Port Interrupt Mask */
+#define MVPP22_XLG_INTERRUPT_MASK_REG  0x118
+#define  MVPP22_XLG_INTERRUPT_LINK_CHANGE  BIT(1)
+/* Port Mac Control3 */
+#define MVPP22_XLG_CTRL3_REG   0x11c
+#define  MVPP22_XLG_CTRL3_MACMODESELECT_MASK   (7 << 13)
+#define  MVPP22_XLG_CTRL3_MACMODESELECT_GMAC   (0 << 13)
+#define  MVPP22_XLG_CTRL3_MACMODESELECT_10GMAC (1 << 13)
+/* Port Mac Control4 */
+#define MVPP22_XLG_CTRL4_REG   0x184
+#define  MVPP22_XLG_FORWARD_802_3X_FC_EN   BIT(5)
+#define  MVPP22_XLG_FORWARD_PFC_EN BIT(6)
+#define  MVPP22_XLG_MODE_DMA_1GBIT(12)
+#define  MVPP22_XLG_EN_IDLE_CHECK_FOR_LINK BIT(14)
+
+/* XPCS registers */
+
+/* Global Configuration 0 */
+#define MVPP22_XPCS_GLOBAL_CFG_0_REG   0x0
+#define  MVPP22_XPCS_PCSRESET  BIT(0)
+#define  MVPP22_XPCS_PCSMODE_OFFS  3
+#define  MVPP22_XPCS_PCSMODE_MASK  (0x3 << \
+MVPP22_XPCS_PCSMODE_OFFS)
+#define  MVPP22_XPCS_LANEACTIVE_OFFS   5
+#define  MVPP22_XPCS_LANEACTIVE_MASK   (0x3 << \
+ 

[U-Boot] [PATCH v2 18/45] net: mvpp2: adapt mvpp2_defaults_set() to PPv2.2

2017-03-23 Thread Stefan Roese
From: Thomas Petazzoni 

This commit modifies the mvpp2_defaults_set() function to not do the
loopback and FIFO threshold initialization, which are not needed for
PPv2.2.

Signed-off-by: Thomas Petazzoni 
Signed-off-by: Stefan Roese 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 22 --
 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index e5b42b9e66..e75979b37a 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -2755,16 +2755,18 @@ static void mvpp2_defaults_set(struct mvpp2_port *port)
 {
int tx_port_num, val, queue, ptxq, lrxq;
 
-   /* Configure port to loopback if needed */
-   if (port->flags & MVPP2_F_LOOPBACK)
-   mvpp2_port_loopback_set(port);
-
-   /* Update TX FIFO MIN Threshold */
-   val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
-   val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
-   /* Min. TX threshold must be less than minimal packet length */
-   val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2);
-   writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
+   if (port->priv->hw_version == MVPP21) {
+   /* Configure port to loopback if needed */
+   if (port->flags & MVPP2_F_LOOPBACK)
+   mvpp2_port_loopback_set(port);
+
+   /* Update TX FIFO MIN Threshold */
+   val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
+   val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
+   /* Min. TX threshold must be less than minimal packet length */
+   val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2);
+   writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
+   }
 
/* Disable Legacy WRR, Disable EJP, Release from reset */
tx_port_num = mvpp2_egress_port(port);
-- 
2.12.1

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[U-Boot] [PATCH v2 39/45] net: mvpp2: Add GoP and NetC support for port 0 (SFI)

2017-03-23 Thread Stefan Roese
This patch adds the GoP (Group of Ports) and NetC (Net Complex) setup to
the Marvell mvpp2 ethernet driver for the missing port 0. This code is
mostly copied from the Marvell U-Boot version and was written by Stefan
Chulski. Please note that only SFI support have been added, as this
is the only interface that this code has been tested with. XAUI and
RXAUI support might follow at a later stage.

Signed-off-by: Stefan Roese 
Cc: Stefan Chulski 
Cc: Kostya Porotchkin 
Cc: Nadav Haklai 
Cc: Joe Hershberger 

---

Changes in v2:
- New patch

 drivers/net/mvpp2.c | 161 
 1 file changed, 161 insertions(+)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 76370faff0..7b4f7a22bd 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -3234,6 +3234,130 @@ static int gop_gpcs_reset(struct mvpp2_port *port, enum 
mv_reset act)
return 0;
 }
 
+/* Set the internal mux's to the required PCS in the PI */
+static int gop_xpcs_mode(struct mvpp2_port *port, int num_of_lanes)
+{
+   u32 val;
+   int lane;
+
+   switch (num_of_lanes) {
+   case 1:
+   lane = 0;
+   break;
+   case 2:
+   lane = 1;
+   break;
+   case 4:
+   lane = 2;
+   break;
+   default:
+   return -1;
+   }
+
+   /* configure XG MAC mode */
+   val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
+   val &= ~MVPP22_XPCS_PCSMODE_OFFS;
+   val &= ~MVPP22_XPCS_LANEACTIVE_MASK;
+   val |= (2 * lane) << MVPP22_XPCS_LANEACTIVE_OFFS;
+   writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
+
+   return 0;
+}
+
+static int gop_mpcs_mode(struct mvpp2_port *port)
+{
+   u32 val;
+
+   /* configure PCS40G COMMON CONTROL */
+   val = readl(port->priv->mpcs_base + PCS40G_COMMON_CONTROL);
+   val &= ~FORWARD_ERROR_CORRECTION_MASK;
+   writel(val, port->priv->mpcs_base + PCS40G_COMMON_CONTROL);
+
+   /* configure PCS CLOCK RESET */
+   val = readl(port->priv->mpcs_base + PCS_CLOCK_RESET);
+   val &= ~CLK_DIVISION_RATIO_MASK;
+   val |= 1 << CLK_DIVISION_RATIO_OFFS;
+   writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET);
+
+   val &= ~CLK_DIV_PHASE_SET_MASK;
+   val |= MAC_CLK_RESET_MASK;
+   val |= RX_SD_CLK_RESET_MASK;
+   val |= TX_SD_CLK_RESET_MASK;
+   writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET);
+
+   return 0;
+}
+
+/* Set the internal mux's to the required MAC in the GOP */
+static int gop_xlg_mac_mode_cfg(struct mvpp2_port *port, int num_of_act_lanes)
+{
+   u32 val;
+
+   /* configure 10G MAC mode */
+   val = readl(port->base + MVPP22_XLG_CTRL0_REG);
+   val |= MVPP22_XLG_RX_FC_EN;
+   writel(val, port->base + MVPP22_XLG_CTRL0_REG);
+
+   val = readl(port->base + MVPP22_XLG_CTRL3_REG);
+   val &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
+   val |= MVPP22_XLG_CTRL3_MACMODESELECT_10GMAC;
+   writel(val, port->base + MVPP22_XLG_CTRL3_REG);
+
+   /* read - modify - write */
+   val = readl(port->base + MVPP22_XLG_CTRL4_REG);
+   val &= ~MVPP22_XLG_MODE_DMA_1G;
+   val |= MVPP22_XLG_FORWARD_PFC_EN;
+   val |= MVPP22_XLG_FORWARD_802_3X_FC_EN;
+   val &= ~MVPP22_XLG_EN_IDLE_CHECK_FOR_LINK;
+   writel(val, port->base + MVPP22_XLG_CTRL4_REG);
+
+   /* Jumbo frame support: 0x1400 * 2 = 0x2800 bytes */
+   val = readl(port->base + MVPP22_XLG_CTRL1_REG);
+   val &= ~MVPP22_XLG_MAX_RX_SIZE_MASK;
+   val |= 0x1400 << MVPP22_XLG_MAX_RX_SIZE_OFFS;
+   writel(val, port->base + MVPP22_XLG_CTRL1_REG);
+
+   /* unmask link change interrupt */
+   val = readl(port->base + MVPP22_XLG_INTERRUPT_MASK_REG);
+   val |= MVPP22_XLG_INTERRUPT_LINK_CHANGE;
+   val |= 1; /* unmask summary bit */
+   writel(val, port->base + MVPP22_XLG_INTERRUPT_MASK_REG);
+
+   return 0;
+}
+
+/* Set PCS to reset or exit from reset */
+static int gop_xpcs_reset(struct mvpp2_port *port, enum mv_reset reset)
+{
+   u32 val;
+
+   /* read - modify - write */
+   val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
+   if (reset == RESET)
+   val &= ~MVPP22_XPCS_PCSRESET;
+   else
+   val |= MVPP22_XPCS_PCSRESET;
+   writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
+
+   return 0;
+}
+
+/* Set the MAC to reset or exit from reset */
+static int gop_xlg_mac_reset(struct mvpp2_port *port, enum mv_reset reset)
+{
+   u32 val;
+
+   /* read - modify - write */
+   val = readl(port->base + MVPP22_XLG_CTRL0_REG);
+   if (reset == RESET)
+   val &= ~MVPP22_XLG_MAC_RESETN;
+   else
+   val |= MVPP22_XLG_MAC_RESETN;
+   writel(val, port->base + MVPP22_XLG_CTRL0_REG);
+
+   return 0;
+}
+
 /*
  * gop_port_init
  *
@@ -3245,6 +3369,7 @@ static int gop_gpcs_reset(struct

[U-Boot] [PATCH v2 24/45] net: mvpp2: adapt rxq distribution to PPv2.2

2017-03-23 Thread Stefan Roese
From: Thomas Petazzoni 

In PPv2.1, we have a maximum of 8 RXQs per port, with a default of 4
RXQs per port, and we were assigning RXQs 0->3 to the first port, 4->7
to the second port, 8->11 to the third port, etc.

In PPv2.2, we have a maximum of 32 RXQs per port, and we must allocate
RXQs from the range of 32 RXQs available for each port. So port 0 must
use RXQs in the range 0->31, port 1 in the range 32->63, etc.

This commit adapts the mvpp2 to this difference between PPv2.1 and
PPv2.2:

- The constant definition MVPP2_MAX_RXQ is replaced by a new field
  'max_port_rxqs' in 'struct mvpp2', which stores the maximum number of
  RXQs per port. This field is initialized during ->probe() depending
  on the IP version.

- MVPP2_RXQ_TOTAL_NUM is removed, and instead we calculate the total
  number of RXQs by multiplying the number of ports by the maximum of
  RXQs per port. This was anyway used in only one place.

- In mvpp2_port_probe(), the calculation of port->first_rxq is adjusted
  to cope with the different allocation strategy between PPv2.1 and
  PPv2.2. Due to this change, the 'next_first_rxq' argument of this
  function is no longer needed and is removed.

Signed-off-by: Thomas Petazzoni 
Signed-off-by: Stefan Roese 
---

Changes in v2: None

 drivers/net/mvpp2.c | 33 ++---
 1 file changed, 18 insertions(+), 15 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 16a9c75cf0..c683fff53f 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -454,9 +454,6 @@ do {
\
 /* Maximum number of TXQs used by single port */
 #define MVPP2_MAX_TXQ  8
 
-/* Maximum number of RXQs used by single port */
-#define MVPP2_MAX_RXQ  8
-
 /* Default number of TXQs in use */
 #define MVPP2_DEFAULT_TXQ  1
 
@@ -464,9 +461,6 @@ do {
\
 #define MVPP2_DEFAULT_RXQ  1
 #define CONFIG_MV_ETH_RXQ  8   /* increment by 8 */
 
-/* Total number of RXQs available to all ports */
-#define MVPP2_RXQ_TOTAL_NUM(MVPP2_MAX_PORTS * MVPP2_MAX_RXQ)
-
 /* Max number of Rx descriptors */
 #define MVPP2_MAX_RXD  16
 
@@ -772,6 +766,9 @@ struct mvpp2 {
/* HW version */
enum { MVPP21, MVPP22 } hw_version;
 
+   /* Maximum number of RXQs per port */
+   unsigned int max_port_rxqs;
+
struct mii_dev *bus;
 };
 
@@ -3700,7 +3697,8 @@ static int mvpp2_port_init(struct udevice *dev, struct 
mvpp2_port *port)
struct mvpp2_txq_pcpu *txq_pcpu;
int queue, cpu, err;
 
-   if (port->first_rxq + rxq_number > MVPP2_RXQ_TOTAL_NUM)
+   if (port->first_rxq + rxq_number >
+   MVPP2_MAX_PORTS * priv->max_port_rxqs)
return -EINVAL;
 
/* Disable port */
@@ -3808,8 +3806,7 @@ static int mvpp2_port_init(struct udevice *dev, struct 
mvpp2_port *port)
 static int mvpp2_port_probe(struct udevice *dev,
struct mvpp2_port *port,
int port_node,
-   struct mvpp2 *priv,
-   int *next_first_rxq)
+   struct mvpp2 *priv)
 {
int phy_node;
u32 id;
@@ -3843,7 +3840,10 @@ static int mvpp2_port_probe(struct udevice *dev,
 
port->priv = priv;
port->id = id;
-   port->first_rxq = *next_first_rxq;
+   if (priv->hw_version == MVPP21)
+   port->first_rxq = port->id * rxq_number;
+   else
+   port->first_rxq = port->id * priv->max_port_rxqs;
port->phy_node = phy_node;
port->phy_interface = phy_mode;
port->phyaddr = phyaddr;
@@ -3877,8 +3877,6 @@ static int mvpp2_port_probe(struct udevice *dev,
}
mvpp2_port_power_up(port);
 
-   /* Increment the first Rx queue number to be used by the next port */
-   *next_first_rxq += CONFIG_MV_ETH_RXQ;
priv->port_list[id] = port;
return 0;
 }
@@ -3995,7 +3993,8 @@ static int mvpp2_init(struct udevice *dev, struct mvpp2 
*priv)
u32 val;
 
/* Checks for hardware constraints (U-Boot uses only one rxq) */
-   if ((rxq_number > MVPP2_MAX_RXQ) || (txq_number > MVPP2_MAX_TXQ)) {
+   if ((rxq_number > priv->max_port_rxqs) ||
+   (txq_number > MVPP2_MAX_TXQ)) {
dev_err(&pdev->dev, "invalid queue size parameter\n");
return -EINVAL;
}
@@ -4388,8 +4387,7 @@ static int mvpp2_probe(struct udevice *dev)
return err;
}
 
-   return mvpp2_port_probe(dev, port, dev_of_offset(dev), priv,
-   &buffer_loc.first_rxq);
+   return mvpp2_port_probe(dev, port, dev_of_offset(dev), priv);
 }
 
 static const struct eth_ops mvpp2_ops = {
@@ -4477,6 +4475,11 @@ static int mvpp2_base_probe(struct udevice *dev)
   

[U-Boot] [PATCH v2 26/45] net: mvpp2: Add MDIO support for PPv2.2

2017-03-23 Thread Stefan Roese
In U-Boot the MDIO / SMI support is integrated in the mvpp2 driver,
currently only supporting the 32bit platforms (Armada 37x). This patch
now adds the A7k/8k PPv2.2 MDIO support to that the phy / mii IF
can be used as well on these platforms.

Signed-off-by: Stefan Roese 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 19 +--
 1 file changed, 13 insertions(+), 6 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 16da28de69..8751ee85e3 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -397,7 +397,9 @@ do {
\
(((index) < (q)->last_desc) ? ((index) + 1) : 0)
 
 /* SMI: 0xc0054 -> offset 0x54 to lms_base */
-#define MVPP2_SMI  0x0054
+#define MVPP21_SMI 0x0054
+/* PP2.2: SMI: 0x12a200 -> offset 0x1200 to iface_base */
+#define MVPP22_SMI 0x1200
 #define MVPP2_PHY_REG_MASK 0x1f
 /* SMI register fields */
 #define MVPP2_SMI_DATA_OFFS0   /* Data */
@@ -745,6 +747,7 @@ struct mvpp2 {
void __iomem *base;
void __iomem *lms_base;
void __iomem *iface_base;
+   void __iomem *mdio_base;
 
/* List of pointers to port structures */
struct mvpp2_port **port_list;
@@ -4089,7 +4092,7 @@ static int smi_wait_ready(struct mvpp2 *priv)
/* wait till the SMI is not busy */
do {
/* read smi register */
-   smi_reg = readl(priv->lms_base + MVPP2_SMI);
+   smi_reg = readl(priv->mdio_base);
if (timeout-- == 0) {
printf("Error: SMI busy timeout\n");
return -EFAULT;
@@ -4131,14 +4134,14 @@ static int mpp2_mdio_read(struct mii_dev *bus, int 
addr, int devad, int reg)
| MVPP2_SMI_OPCODE_READ;
 
/* write the smi register */
-   writel(smi_reg, priv->lms_base + MVPP2_SMI);
+   writel(smi_reg, priv->mdio_base);
 
/* wait till read value is ready */
timeout = MVPP2_SMI_TIMEOUT;
 
do {
/* read smi register */
-   smi_reg = readl(priv->lms_base + MVPP2_SMI);
+   smi_reg = readl(priv->mdio_base);
if (timeout-- == 0) {
printf("Err: SMI read ready timeout\n");
return -EFAULT;
@@ -4149,7 +4152,7 @@ static int mpp2_mdio_read(struct mii_dev *bus, int addr, 
int devad, int reg)
for (timeout = 0; timeout < MVPP2_SMI_TIMEOUT; timeout++)
;
 
-   return readl(priv->lms_base + MVPP2_SMI) & MVPP2_SMI_DATA_MASK;
+   return readl(priv->mdio_base) & MVPP2_SMI_DATA_MASK;
 }
 
 /*
@@ -4186,7 +4189,7 @@ static int mpp2_mdio_write(struct mii_dev *bus, int addr, 
int devad, int reg,
smi_reg &= ~MVPP2_SMI_OPCODE_READ;
 
/* write the smi register */
-   writel(smi_reg, priv->lms_base + MVPP2_SMI);
+   writel(smi_reg, priv->mdio_base);
 
return 0;
 }
@@ -4469,10 +4472,14 @@ static int mvpp2_base_probe(struct udevice *dev)
priv->lms_base = (void *)dev_get_addr_index(dev, 1);
if (IS_ERR(priv->lms_base))
return PTR_ERR(priv->lms_base);
+
+   priv->mdio_base = priv->lms_base + MVPP21_SMI;
} else {
priv->iface_base = (void *)dev_get_addr_index(dev, 1);
if (IS_ERR(priv->iface_base))
return PTR_ERR(priv->iface_base);
+
+   priv->mdio_base = priv->iface_base + MVPP22_SMI;
}
 
if (priv->hw_version == MVPP21)
-- 
2.12.1

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[U-Boot] [PATCH v2 44/45] arm64: mvebu: armada-7040-db.dts: Change eth1 speed from 2.5G to 1G

2017-03-23 Thread Stefan Roese
The default configuration for the COMPHY-0 port should be 1G, as its
used as 1G SGMII connection. This change is necessary to get the
MAC2 port (SGMII) working on this DB.

Signed-off-by: Stefan Roese 
Cc: Stefan Chulski 
Cc: Kostya Porotchkin 
Cc: Nadav Haklai 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 arch/arm/dts/armada-7040-db.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/dts/armada-7040-db.dts b/arch/arm/dts/armada-7040-db.dts
index 776bc7831d..84e0dbdc3d 100644
--- a/arch/arm/dts/armada-7040-db.dts
+++ b/arch/arm/dts/armada-7040-db.dts
@@ -159,7 +159,7 @@
 &cpm_comphy {
phy0 {
phy-type = ;
-   phy-speed = ;
+   phy-speed = ;
};
 
phy1 {
-- 
2.12.1

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[U-Boot] [PATCH v2 28/45] net: mvpp2.c: Clear all buffer / descriptor areas before usage

2017-03-23 Thread Stefan Roese
This fixes problems noticed with the PPv2.2 A7k/8k port, when not all
elements of the descriptors had been cleared before use.

Signed-off-by: Stefan Roese 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 06909e6a3c..b9e0fdcc82 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -4429,6 +4429,9 @@ static int mvpp2_base_probe(struct udevice *dev)
size += RX_BUFFER_SIZE;
}
 
+   /* Clear the complete area so that all descriptors are cleared */
+   memset(bd_space, 0, size);
+
/* Save base addresses for later use */
priv->base = (void *)dev_get_addr_index(dev, 0);
if (IS_ERR(priv->base))
-- 
2.12.1

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[U-Boot] [PATCH v2 45/45] arm64: mvebu: Enable CONFIG_PHY_MARVELL in Armada7k/8k-DB defconfig

2017-03-23 Thread Stefan Roese
The Marvell PHY support is needed espescially for the A7040-DB with the
SGMII port (port 2). As without the marvell PHY driver configuration
for SGMII, ethernet won't work.

Signed-off-by: Stefan Roese 
Cc: Stefan Chulski 
Cc: Kostya Porotchkin 
Cc: Nadav Haklai 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 configs/mvebu_db-88f7040_defconfig | 1 +
 configs/mvebu_db-88f8040_defconfig | 1 +
 2 files changed, 2 insertions(+)

diff --git a/configs/mvebu_db-88f7040_defconfig 
b/configs/mvebu_db-88f7040_defconfig
index fdafeb6607..797eabbfab 100644
--- a/configs/mvebu_db-88f7040_defconfig
+++ b/configs/mvebu_db-88f7040_defconfig
@@ -47,6 +47,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_MARVELL=y
 CONFIG_MVPP2=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
diff --git a/configs/mvebu_db-88f8040_defconfig 
b/configs/mvebu_db-88f8040_defconfig
index 9866e19778..046da09786 100644
--- a/configs/mvebu_db-88f8040_defconfig
+++ b/configs/mvebu_db-88f8040_defconfig
@@ -47,6 +47,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_MARVELL=y
 CONFIG_MVPP2=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
-- 
2.12.1

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[U-Boot] [PATCH v2 43/45] net: mvpp2: Remove unreferenced in_use_thresh from struct mvpp2_bm_pool

2017-03-23 Thread Stefan Roese
As pointed out by Stefan Chulski, this variable is unused and should be
removed.

Signed-off-by: Stefan Roese 
Cc: Stefan Chulski 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe
- Fixed small typo in commit text

 drivers/net/mvpp2.c | 4 
 1 file changed, 4 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 086ce32851..ec985977ba 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -1247,9 +1247,6 @@ struct mvpp2_bm_pool {
 
/* Ports using BM pool */
u32 port_map;
-
-   /* Occupied buffers indicator */
-   int in_use_thresh;
 };
 
 /* Static declaractions */
@@ -2801,7 +2798,6 @@ static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
 
/* Update BM driver with number of buffers added to pool */
bm_pool->buf_num += i;
-   bm_pool->in_use_thresh = bm_pool->buf_num / 4;
 
return i;
 }
-- 
2.12.1

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[U-Boot] [PATCH v2 33/45] net: mvpp2: Add remove function that is called before the OS is started

2017-03-23 Thread Stefan Roese
This patch adds a remove function to the mvpp2 ethernet driver which is
called before the OS is started, doing:

- Allocate the used buffers back from the buffer manager
- Stop the BM activity

Signed-off-by: Stefan Roese 
Cc: Stefan Chulski 
Cc: Kostya Porotchkin 
Cc: Nadav Haklai 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 24 
 1 file changed, 24 insertions(+)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 2328c25850..e13a679e33 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -2454,6 +2454,13 @@ static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv,
 static void mvpp2_bm_bufs_free(struct udevice *dev, struct mvpp2 *priv,
   struct mvpp2_bm_pool *bm_pool)
 {
+   int i;
+
+   for (i = 0; i < bm_pool->buf_num; i++) {
+   /* Allocate buffer back from the buffer manager */
+   mvpp2_read(priv, MVPP2_BM_PHY_ALLOC_REG(bm_pool->id));
+   }
+
bm_pool->buf_num = 0;
 }
 
@@ -4495,6 +4502,21 @@ static int mvpp2_probe(struct udevice *dev)
return mvpp2_port_probe(dev, port, dev_of_offset(dev), priv);
 }
 
+/*
+ * Empty BM pool and stop its activity before the OS is started
+ */
+static int mvpp2_remove(struct udevice *dev)
+{
+   struct mvpp2_port *port = dev_get_priv(dev);
+   struct mvpp2 *priv = port->priv;
+   int i;
+
+   for (i = 0; i < MVPP2_BM_POOLS_NUM; i++)
+   mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]);
+
+   return 0;
+}
+
 static const struct eth_ops mvpp2_ops = {
.start  = mvpp2_start,
.send   = mvpp2_send,
@@ -4506,9 +4528,11 @@ static struct driver mvpp2_driver = {
.name   = "mvpp2",
.id = UCLASS_ETH,
.probe  = mvpp2_probe,
+   .remove = mvpp2_remove,
.ops= &mvpp2_ops,
.priv_auto_alloc_size = sizeof(struct mvpp2_port),
.platdata_auto_alloc_size = sizeof(struct eth_pdata),
+   .flags  = DM_FLAG_ACTIVE_DMA,
 };
 
 /*
-- 
2.12.1

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[U-Boot] [PATCH v2 25/45] net: mvpp2: finally add the PPv2.2 compatible string

2017-03-23 Thread Stefan Roese
From: Thomas Petazzoni 

Now that the mvpp2 driver has been modified to accommodate the support
for PPv2.2, we can finally advertise this support by adding the
appropriate compatible string.

Signed-off-by: Thomas Petazzoni 
Signed-off-by: Stefan Roese 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index c683fff53f..16da28de69 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -4541,6 +4541,10 @@ static const struct udevice_id mvpp2_ids[] = {
.compatible = "marvell,armada-375-pp2",
.data = MVPP21,
},
+   {
+   .compatible = "marvell,armada-7k-pp22",
+   .data = MVPP22,
+   },
{ }
 };
 
-- 
2.12.1

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[U-Boot] [PATCH v2 42/45] net: mvpp2: Configure SMI PHY address needed for PHY polling

2017-03-23 Thread Stefan Roese
On PPv2.2 we enable PHY polling, so we also need to configure the PHY
address in the specific PHY address rgisters.

Signed-off-by: Stefan Roese 
Cc: Stefan Chulski 
Cc: Kostya Porotchkin 
Cc: Nadav Haklai 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index cc6d42255c..086ce32851 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -5338,6 +5338,14 @@ static void mvpp2_stop(struct udevice *dev)
mvpp2_cleanup_txqs(port);
 }
 
+static int mvpp22_smi_phy_addr_cfg(struct mvpp2_port *port)
+{
+   writel(port->phyaddr, port->priv->iface_base +
+  MVPP22_SMI_PHY_ADDR_REG(port->gop_id));
+
+   return 0;
+}
+
 static int mvpp2_base_probe(struct udevice *dev)
 {
struct mvpp2 *priv = dev_get_priv(dev);
@@ -5476,6 +5484,9 @@ static int mvpp2_probe(struct udevice *dev)
port->base = priv->iface_base + MVPP22_PORT_BASE +
port->gop_id * MVPP22_PORT_OFFSET;
 
+   /* Set phy address of the port */
+   mvpp22_smi_phy_addr_cfg(port);
+
/* GoP Init */
gop_port_init(port);
}
-- 
2.12.1

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[U-Boot] [PATCH v2 36/45] net: mvpp2: Restructure probe / init functions

2017-03-23 Thread Stefan Roese
This patch does a bit of restructuring of the probe / init functions,
mainly to allow earlier register access as it is needed for the upcoming
GoP (Group of Ports) and NetC (Net Complex) code.

Signed-off-by: Stefan Roese 
Cc: Joe Hershberger 

---

Changes in v2:
- New patch

 drivers/net/mvpp2.c | 76 -
 1 file changed, 46 insertions(+), 30 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 4863336985..ecefa21097 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -3830,19 +3830,14 @@ static int mvpp2_port_init(struct udevice *dev, struct 
mvpp2_port *port)
return 0;
 }
 
-/* Ports initialization */
-static int mvpp2_port_probe(struct udevice *dev,
-   struct mvpp2_port *port,
-   int port_node,
-   struct mvpp2 *priv)
+static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port)
 {
+   int port_node = dev_of_offset(dev);
+   const char *phy_mode_str;
int phy_node;
u32 id;
u32 phyaddr;
-   const char *phy_mode_str;
int phy_mode = -1;
-   int priv_common_regs_num = 2;
-   int err;
 
phy_node = fdtdec_lookup_phandle(gd->fdt_blob, port_node, "phy");
if (phy_node < 0) {
@@ -3866,46 +3861,37 @@ static int mvpp2_port_probe(struct udevice *dev,
 
phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node, "reg", 0);
 
-   port->priv = priv;
port->id = id;
-   if (priv->hw_version == MVPP21)
+   if (port->priv->hw_version == MVPP21)
port->first_rxq = port->id * rxq_number;
else
-   port->first_rxq = port->id * priv->max_port_rxqs;
+   port->first_rxq = port->id * port->priv->max_port_rxqs;
port->phy_node = phy_node;
port->phy_interface = phy_mode;
port->phyaddr = phyaddr;
 
-   if (priv->hw_version == MVPP21) {
-   port->base = (void __iomem *)dev_get_addr_index(
-   dev->parent, priv_common_regs_num + id);
-   if (IS_ERR(port->base))
-   return PTR_ERR(port->base);
-   } else {
-   u32 gop_id;
-
-   gop_id = fdtdec_get_int(gd->fdt_blob, port_node,
-   "gop-port-id", -1);
-   if (id == -1) {
-   dev_err(&pdev->dev, "missing gop-port-id value\n");
-   return -EINVAL;
-   }
+   return 0;
+}
 
-   port->base = priv->iface_base + MVPP22_PORT_BASE +
-   gop_id * MVPP22_PORT_OFFSET;
-   }
+/* Ports initialization */
+static int mvpp2_port_probe(struct udevice *dev,
+   struct mvpp2_port *port,
+   int port_node,
+   struct mvpp2 *priv)
+{
+   int err;
 
port->tx_ring_size = MVPP2_MAX_TXD;
port->rx_ring_size = MVPP2_MAX_RXD;
 
err = mvpp2_port_init(dev, port);
if (err < 0) {
-   dev_err(&pdev->dev, "failed to init port %d\n", id);
+   dev_err(&pdev->dev, "failed to init port %d\n", port->id);
return err;
}
mvpp2_port_power_up(port);
 
-   priv->port_list[id] = port;
+   priv->port_list[port->id] = port;
return 0;
 }
 
@@ -4553,6 +4539,36 @@ static int mvpp2_probe(struct udevice *dev)
err = mvpp2_base_probe(dev->parent);
priv->probe_done = 1;
}
+
+   port->priv = dev_get_priv(dev->parent);
+
+   err = phy_info_parse(dev, port);
+   if (err)
+   return err;
+
+   /*
+* We need the port specific io base addresses at this stage, since
+* gop_port_init() accesses these registers
+*/
+   if (priv->hw_version == MVPP21) {
+   int priv_common_regs_num = 2;
+
+   port->base = (void __iomem *)dev_get_addr_index(
+   dev->parent, priv_common_regs_num + port->id);
+   if (IS_ERR(port->base))
+   return PTR_ERR(port->base);
+   } else {
+   port->gop_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+ "gop-port-id", -1);
+   if (port->id == -1) {
+   dev_err(&pdev->dev, "missing gop-port-id value\n");
+   return -EINVAL;
+   }
+
+   port->base = priv->iface_base + MVPP22_PORT_BASE +
+   port->gop_id * MVPP22_PORT_OFFSET;
+   }
+
/* Initialize network controller */
err = mvpp2_init(dev, priv);
if (err < 0) {
-- 
2.12.1

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[U-Boot] [PATCH v2 30/45] arm64: marvell: dts: add PPv2.2 description to Armada 7K/8K

2017-03-23 Thread Stefan Roese
From: Thomas Petazzoni 

This commit adds the description of the PPv2.2 hardware block for the
Marvell Armada 7K and Armada 8K processors, and their corresponding Armada
7040 and 8040 Development boards.

Signed-off-by: Thomas Petazzoni 
Signed-off-by: Stefan Roese 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 arch/arm/dts/armada-7040-db.dts   | 25 +++
 arch/arm/dts/armada-8040-db.dts   | 16 +++
 arch/arm/dts/armada-cp110-master.dtsi | 37 +++
 arch/arm/dts/armada-cp110-slave.dtsi  | 37 +++
 4 files changed, 115 insertions(+)

diff --git a/arch/arm/dts/armada-7040-db.dts b/arch/arm/dts/armada-7040-db.dts
index 63442df8f3..776bc7831d 100644
--- a/arch/arm/dts/armada-7040-db.dts
+++ b/arch/arm/dts/armada-7040-db.dts
@@ -209,3 +209,28 @@
no-1-8-v;
non-removable;
 };
+
+&cpm_mdio {
+   phy0: ethernet-phy@0 {
+   reg = <0>;
+   };
+   phy1: ethernet-phy@1 {
+   reg = <1>;
+   };
+};
+
+&cpm_ethernet {
+   status = "okay";
+};
+
+&cpm_eth1 {
+   status = "okay";
+   phy = <&phy0>;
+   phy-mode = "sgmii";
+};
+
+&cpm_eth2 {
+   status = "okay";
+   phy = <&phy1>;
+   phy-mode = "rgmii-id";
+};
diff --git a/arch/arm/dts/armada-8040-db.dts b/arch/arm/dts/armada-8040-db.dts
index 40def9d6cd..f1f196f563 100644
--- a/arch/arm/dts/armada-8040-db.dts
+++ b/arch/arm/dts/armada-8040-db.dts
@@ -283,3 +283,19 @@
 &cps_utmi0 {
status = "okay";
 };
+
+&cpm_mdio {
+   phy1: ethernet-phy@1 {
+   reg = <1>;
+   };
+};
+
+&cpm_ethernet {
+   status = "okay";
+};
+
+&cpm_eth2 {
+   status = "okay";
+   phy = <&phy1>;
+   phy-mode = "rgmii-id";
+};
diff --git a/arch/arm/dts/armada-cp110-master.dtsi 
b/arch/arm/dts/armada-cp110-master.dtsi
index 661a69679e..a450f3fd7c 100644
--- a/arch/arm/dts/armada-cp110-master.dtsi
+++ b/arch/arm/dts/armada-cp110-master.dtsi
@@ -61,6 +61,43 @@
interrupt-parent = <&gic>;
ranges = <0x0 0x0 0xf200 0x200>;
 
+   cpm_ethernet: ethernet@0 {
+   compatible = "marvell,armada-7k-pp22";
+   reg = <0x0 0x10>, <0x129000 0xb000>;
+   clocks = <&cpm_syscon0 1 3>, <&cpm_syscon0 1 
9>, <&cpm_syscon0 1 5>;
+   clock-names = "pp_clk", "gop_clk", "mg_clk";
+   status = "disabled";
+   dma-coherent;
+
+   cpm_eth0: eth0 {
+   interrupts = ;
+   port-id = <0>;
+   gop-port-id = <0>;
+   status = "disabled";
+   };
+
+   cpm_eth1: eth1 {
+   interrupts = ;
+   port-id = <1>;
+   gop-port-id = <2>;
+   status = "disabled";
+   };
+
+   cpm_eth2: eth2 {
+   interrupts = ;
+   port-id = <2>;
+   gop-port-id = <3>;
+   status = "disabled";
+   };
+   };
+
+   cpm_mdio: mdio@12a200 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "marvell,orion-mdio";
+   reg = <0x12a200 0x10>;
+   };
+
cpm_syscon0: system-controller@44 {
compatible = "marvell,cp110-system-controller0",
 "syscon";
diff --git a/arch/arm/dts/armada-cp110-slave.dtsi 
b/arch/arm/dts/armada-cp110-slave.dtsi
index 92ef55cf26..50898a8da6 100644
--- a/arch/arm/dts/armada-cp110-slave.dtsi
+++ b/arch/arm/dts/armada-cp110-slave.dtsi
@@ -61,6 +61,43 @@
interrupt-parent = <&gic>;
ranges = <0x0 0x0 0xf400 0x200>;
 
+   cps_ethernet: ethernet@0 {
+   compatible = "marvell,armada-7k-pp22";
+   reg = <0x0 0x10>, <0x129000 0xb000>;
+   clocks = <&cps_syscon0 1 3>, <&cps_syscon0 1 
9>, <&cps_syscon0 1 5>;
+   clock-names = "pp_clk", "gop_clk", "mg_clk";
+   status = "disabled";
+   dma-coherent;
+
+   cps_eth0: eth0 {
+   

Re: [U-Boot] [PATCH v4 19/20] rockchip: rk3188: Add Radxa Rock board

2017-03-23 Thread Heiko Stübner
Hi Simon,

Am Donnerstag, 23. März 2017, 10:18:31 CET schrieb Simon Glass:
> On 21 February 2017 at 13:35, Simon Glass  wrote:
> > On 18 February 2017 at 11:46, Heiko Stuebner  wrote:
> >> The Rock is a RK3188 based single board computer by Radxa.
> >> Currently it still relies on the proprietary DDR init and
> >> cannot use the generic SPL, but at least is able to boot
> >> a linux kernel and system up to a regular login prompt.
> >> 
> >> Signed-off-by: Heiko Stuebner 
> >> Reviewed-by: Simon Glass 
> >> Tested-by: Kever Yang 
> >> ---
> >> 
> >>  arch/arm/dts/Makefile |   1 +
> >>  arch/arm/dts/rk3188-radxarock.dts | 382
> >>  ++
> >>  arch/arm/mach-rockchip/rk3188/Kconfig |  11 +
> >>  board/radxa/rock/Kconfig  |  15 ++
> >>  board/radxa/rock/MAINTAINERS  |   6 +
> >>  board/radxa/rock/Makefile |   7 +
> >>  board/radxa/rock/rock.c   |   7 +
> >>  configs/rock_defconfig|  56 +
> >>  include/configs/rock.h|  30 +++
> >>  9 files changed, 515 insertions(+)
> >>  create mode 100644 arch/arm/dts/rk3188-radxarock.dts
> >>  create mode 100644 board/radxa/rock/Kconfig
> >>  create mode 100644 board/radxa/rock/MAINTAINERS
> >>  create mode 100644 board/radxa/rock/Makefile
> >>  create mode 100644 board/radxa/rock/rock.c
> >>  create mode 100644 configs/rock_defconfig
> >>  create mode 100644 include/configs/rock.h
> > 
> > Applied to u-boot-rockchip, thanks!
> 
> Just a reminder that I had to drop this patch as it does not build.
> Can you please resend this one? I have also reverted the README patch
> but can apply that myself once this board is enabled.

ah, I should probably fold the patch fixing the build issue into this one. I'll 
create a new series and collect all the different sets flying around.


Heiko
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[U-Boot] [PATCH v2 40/45] net: mvpp2: Add missing PHY_INTERFACE_MODE_RGMII_ID

2017-03-23 Thread Stefan Roese
Add a missing occurrance of PHY_INTERFACE_MODE_RGMII_ID, which should
be handled identical to PHY_INTERFACE_MODE_RGMII.

Signed-off-by: Stefan Roese 
Cc: Stefan Chulski 
Cc: Kostya Porotchkin 
Cc: Nadav Haklai 
Cc: Joe Hershberger 

---

Changes in v2:
- New patch

 drivers/net/mvpp2.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 7b4f7a22bd..d20d82e017 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -2895,6 +2895,7 @@ static void mvpp2_port_mii_set(struct mvpp2_port *port)
val |= MVPP2_GMAC_INBAND_AN_MASK;
break;
case PHY_INTERFACE_MODE_RGMII:
+   case PHY_INTERFACE_MODE_RGMII_ID:
val |= MVPP2_GMAC_PORT_RGMII_MASK;
default:
val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
-- 
2.12.1

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[U-Boot] [PATCH] Remove extra fdt_fixup_ethernet() call

2017-03-23 Thread Joakim Tjernlund
ft_cpu_setup() already calls fdt_fixup_ethernet(), calling it
in image_setup_libfdt() is both redundant and breaks any modifications
done by ft_board_setup(). Restore the old behavior by removing
the call in image_setup_libfdt()

Signed-off-by: Joakim Tjernlund 
---
 common/image-fdt.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/common/image-fdt.c b/common/image-fdt.c
index 80e3e63..b8f5654 100644
--- a/common/image-fdt.c
+++ b/common/image-fdt.c
@@ -498,7 +498,6 @@ int image_setup_libfdt(bootm_headers_t *images, void *blob,
goto err;
}
}
-   fdt_fixup_ethernet(blob);
 
/* Delete the old LMB reservation */
lmb_free(lmb, (phys_addr_t)(u32)(uintptr_t)blob,
-- 
2.10.2

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Re: [U-Boot] uboot information

2017-03-23 Thread Sébastien Basset
2017-03-23 3:19 GMT+01:00 Simon Glass :

> Hi,
>
> On 22 March 2017 at 10:35, Sébastien Basset  wrote:
> > 1/ No, As i am stuck on the mmc (pci controller internal soc),
> > 2/ Now i try to boot on usb key, but i don't see controller usb
> > Sorry, these are two different problems.
>
> It is better to post at the bottom that the top, for mailing lists.
>
> I think PCI XHCI has some problems. I'm not sure of its status.
>
> MMC seems to work well on Minnowboard Max (baytrail) but I am not sure
> about braswell. Is it perhaps a slightly different chip?
>
> Regards,
> Simon
>
>
For PCI XHCI, i see controller usb and root hub, but cannot reset port:

portstatus 711, change 0, 5 Gb/s
STAT_C_CONNECTION = 0 STAT_CONNECTION = 1  USB_PORT_STAT_ENABLE 0
portstatus 711, change 10, 5 Gb/s
STAT_C_CONNECTION = 0 STAT_CONNECTION = 1  USB_PORT_STAT_ENABLE 0
portstatus 711, change 10, 5 Gb/s
STAT_C_CONNECTION = 0 STAT_CONNECTION = 1  USB_PORT_STAT_ENABLE 0
portstatus 711, change 10, 5 Gb/s
STAT_C_CONNECTION = 0 STAT_CONNECTION = 1  USB_PORT_STAT_ENABLE 0
portstatus 711, change 10, 5 Gb/s
STAT_C_CONNECTION = 0 STAT_CONNECTION = 1  USB_PORT_STAT_ENABLE 0
Cannot enable port 10 after 5 retries, disabling port.
Maybe the USB cable is bad?
cannot reset port 10!?

do you have an idea,why reset port is break down ?

For MMC, braswell n3160 is dedicated for embedded iot, maybe for security.
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Re: [U-Boot] uboot information

2017-03-23 Thread Simon Glass
Hi,

On 23 March 2017 at 12:36, Sébastien Basset  wrote:
>
>
>
> 2017-03-23 3:19 GMT+01:00 Simon Glass :
>>
>> Hi,
>>
>> On 22 March 2017 at 10:35, Sébastien Basset  wrote:
>> > 1/ No, As i am stuck on the mmc (pci controller internal soc),
>> > 2/ Now i try to boot on usb key, but i don't see controller usb
>> > Sorry, these are two different problems.
>>
>> It is better to post at the bottom that the top, for mailing lists.
>>
>> I think PCI XHCI has some problems. I'm not sure of its status.
>>
>> MMC seems to work well on Minnowboard Max (baytrail) but I am not sure
>> about braswell. Is it perhaps a slightly different chip?
>>
>> Regards,
>> Simon
>>
>
> For PCI XHCI, i see controller usb and root hub, but cannot reset port:
>
> portstatus 711, change 0, 5 Gb/s
> STAT_C_CONNECTION = 0 STAT_CONNECTION = 1  USB_PORT_STAT_ENABLE 0
> portstatus 711, change 10, 5 Gb/s
> STAT_C_CONNECTION = 0 STAT_CONNECTION = 1  USB_PORT_STAT_ENABLE 0
> portstatus 711, change 10, 5 Gb/s
> STAT_C_CONNECTION = 0 STAT_CONNECTION = 1  USB_PORT_STAT_ENABLE 0
> portstatus 711, change 10, 5 Gb/s
> STAT_C_CONNECTION = 0 STAT_CONNECTION = 1  USB_PORT_STAT_ENABLE 0
> portstatus 711, change 10, 5 Gb/s
> STAT_C_CONNECTION = 0 STAT_CONNECTION = 1  USB_PORT_STAT_ENABLE 0
> Cannot enable port 10 after 5 retries, disabling port.
> Maybe the USB cable is bad?
> cannot reset port 10!?
>
> do you have an idea,why reset port is break down ?

No I am not sure. It could possibly be a driver problem, or perhaps
the port is not enabled in the FSP config?

>
> For MMC, braswell n3160 is dedicated for embedded iot, maybe for security.
>

Do you mean that you cannot use MMC on this chip?

Regards,
Simon
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Re: [U-Boot] [ PATCH 2/2] net: move Broadcom SF2 driver to Kconfig

2017-03-23 Thread Joe Hershberger
On Thu, Mar 23, 2017 at 12:32 PM, Suji Velupillai
 wrote:
> Thank you Joe for your time and feedback,
> Please see the answers inline.
> Suji
>
>
> On Tue, Mar 21, 2017 at 11:53 AM, Joe Hershberger
>  wrote:
>>
>> On Fri, Mar 3, 2017 at 7:06 PM, Steve Rae  wrote:
>> > From: Suji Velupillai 
>> >
>> > move to Kconfig:
>> > CONFIG_BCM_SF2_ETH
>> > CONFIG_BCM_SF2_ETH_GMAC
>> >
>> > Also modified defconfigs of all platforms that use these configs.
>> >
>> > Signed-off-by: Suji Velupillai 
>> > Tested-by: Suji Velupillai 
>> > Reviewed-by: JD Zheng 
>> > Reviewed-by: Scott Branden 
>> > Signed-off-by: Steve Rae 
>> > ---
>> >
>> >  arch/arm/include/asm/arch-bcmcygnus/configs.h |  6 +-
>> >  configs/bcm28155_w1d_defconfig|  5 +++--
>> >  configs/bcm911360_entphn-ns_defconfig |  3 +++
>> >  configs/bcm911360_entphn_defconfig|  3 +++
>> >  configs/bcm911360k_defconfig  |  3 +++
>> >  configs/bcm958300k-ns_defconfig   |  3 +++
>> >  configs/bcm958300k_defconfig  |  3 +++
>> >  configs/bcm958305k_defconfig  |  3 +++
>> >  drivers/net/Kconfig   | 15 +++
>> >  scripts/config_whitelist.txt  |  2 --
>> >  10 files changed, 37 insertions(+), 9 deletions(-)
>> >
>> > diff --git a/arch/arm/include/asm/arch-bcmcygnus/configs.h
>> > b/arch/arm/include/asm/arch-bcmcygnus/configs.h
>> > index af7f3bf..92b1c5e 100644
>> > --- a/arch/arm/include/asm/arch-bcmcygnus/configs.h
>> > +++ b/arch/arm/include/asm/arch-bcmcygnus/configs.h
>> > @@ -1,5 +1,5 @@
>> >  /*
>> > - * Copyright 2014 Broadcom Corporation.
>> > + * Copyright 2014-2017 Broadcom.
>> >   *
>> >   * SPDX-License-Identifier:GPL-2.0+
>> >   */
>> > @@ -23,10 +23,6 @@
>> >  #define CONFIG_SYS_NS16550_COM30x18023000
>> >
>> >  /* Ethernet */
>> > -#define CONFIG_BCM_SF2_ETH
>> > -#define CONFIG_BCM_SF2_ETH_GMAC
>> > -
>> > -#define CONFIG_PHYLIB
>> >  #define CONFIG_PHY_BROADCOM
>> >  #define CONFIG_PHY_RESET_DELAY 1 /* PHY reset delay in us*/
>> >
>> > diff --git a/configs/bcm28155_w1d_defconfig
>> > b/configs/bcm28155_w1d_defconfig
>> > index aa5216e..4adbce6 100644
>> > --- a/configs/bcm28155_w1d_defconfig
>> > +++ b/configs/bcm28155_w1d_defconfig
>> > @@ -1,7 +1,6 @@
>> >  CONFIG_ARM=y
>> >  CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
>> >  CONFIG_TARGET_BCM28155_AP=y
>> > -CONFIG_SYS_EXTRA_OPTIONS="BCM_SF2_ETH,BCM_SF2_ETH_GMAC"
>> >  CONFIG_VERSION_VARIABLE=y
>> >  # CONFIG_DISPLAY_CPUINFO is not set
>> >  # CONFIG_DISPLAY_BOARDINFO is not set
>> > @@ -15,7 +14,6 @@ CONFIG_CMD_MMC=y
>> >  CONFIG_CMD_I2C=y
>> >  CONFIG_CMD_GPIO=y
>> >  # CONFIG_CMD_SETEXPR is not set
>> > -# CONFIG_CMD_NET is not set
>> >  # CONFIG_CMD_NFS is not set
>> >  CONFIG_CMD_CACHE=y
>> >  CONFIG_CMD_FAT=y
>> > @@ -33,3 +31,6 @@ CONFIG_USB_GADGET_DOWNLOAD=y
>> >  CONFIG_G_DNL_MANUFACTURER="Broadcom Corporation"
>> >  CONFIG_G_DNL_VENDOR_NUM=0x18d1
>> >  CONFIG_G_DNL_PRODUCT_NUM=0x0d02
>> > +CONFIG_NETDEVICES=y
>> > +CONFIG_BCM_SF2_ETH=y
>> > +CONFIG_BCM_SF2_ETH_GMAC=y
>> > diff --git a/configs/bcm911360_entphn-ns_defconfig
>> > b/configs/bcm911360_entphn-ns_defconfig
>> > index adcc152..f1df78a 100644
>> > --- a/configs/bcm911360_entphn-ns_defconfig
>> > +++ b/configs/bcm911360_entphn-ns_defconfig
>> > @@ -19,3 +19,6 @@ CONFIG_CMD_TIME=y
>> >  CONFIG_CMD_FAT=y
>> >  CONFIG_SYS_NS16550=y
>> >  CONFIG_OF_LIBFDT=y
>> > +CONFIG_NETDEVICES=y
>> > +CONFIG_BCM_SF2_ETH=y
>> > +CONFIG_BCM_SF2_ETH_GMAC=y
>> > diff --git a/configs/bcm911360_entphn_defconfig
>> > b/configs/bcm911360_entphn_defconfig
>> > index e49071d..22da69e 100644
>> > --- a/configs/bcm911360_entphn_defconfig
>> > +++ b/configs/bcm911360_entphn_defconfig
>> > @@ -19,3 +19,6 @@ CONFIG_CMD_TIME=y
>> >  CONFIG_CMD_FAT=y
>> >  CONFIG_SYS_NS16550=y
>> >  CONFIG_OF_LIBFDT=y
>> > +CONFIG_NETDEVICES=y
>> > +CONFIG_BCM_SF2_ETH=y
>> > +CONFIG_BCM_SF2_ETH_GMAC=y
>> > diff --git a/configs/bcm911360k_defconfig b/configs/bcm911360k_defconfig
>> > index 8077c4a..0281fc8 100644
>> > --- a/configs/bcm911360k_defconfig
>> > +++ b/configs/bcm911360k_defconfig
>> > @@ -19,3 +19,6 @@ CONFIG_CMD_TIME=y
>> >  CONFIG_CMD_FAT=y
>> >  CONFIG_SYS_NS16550=y
>> >  CONFIG_OF_LIBFDT=y
>> > +CONFIG_NETDEVICES=y
>> > +CONFIG_BCM_SF2_ETH=y
>> > +CONFIG_BCM_SF2_ETH_GMAC=y
>> > diff --git a/configs/bcm958300k-ns_defconfig
>> > b/configs/bcm958300k-ns_defconfig
>> > index 26d0b0b..c837721 100644
>> > --- a/configs/bcm958300k-ns_defconfig
>> > +++ b/configs/bcm958300k-ns_defconfig
>> > @@ -19,3 +19,6 @@ CONFIG_CMD_TIME=y
>> >  CONFIG_CMD_FAT=y
>> >  CONFIG_SYS_NS16550=y
>> >  CONFIG_OF_LIBFDT=y
>> > +CONFIG_NETDEVICES=y
>> > +CONFIG_BCM_SF2_ETH=y
>> > +CONFIG_BCM_SF2_ETH_GMAC=y
>> > diff --git a/configs/bcm958300k_defconfig b/configs/bcm958300k_defconfig
>> > index 8077c4a..0281fc8 100644
>> > --- a/configs/bcm958300k_defconfig
>> > +++ b/configs/bcm958300k_defconfig
>> > @@ -19,3 +19,6 @@ CON

[U-Boot] [PATCH v2 1/2] rockchip: rk3399: spl: add UART0 support for SPL

2017-03-23 Thread Philipp Tomsich
The RK3399-Q7 ("Puma") SoM exposes UART0 as the Qseven UART (i.e. the
serial line available via standardised pins on the edge connector and
available on a RS232 connector).

To support boards (such as the RK3399-Q7) that require UART0 as a
debug console, we match CONFIG_DEBUG_UART_BASE and add the appropriate
iomux setup to the rk3399 SPL code.

As we are already touching this code, we also move the board-specific
UART setup (i.e. iomux setup) into board_debug_uart_init(). This will
be called from the debug UART init when CONFIG_DEBUG_UART_BOARD_INIT
is set.

Signed-off-by: Philipp Tomsich 
---

Changes in v2:
- Changed hex constant to lowercase

 arch/arm/include/asm/arch-rockchip/grf_rk3399.h |  8 +++
 arch/arm/mach-rockchip/rk3399-board-spl.c   | 29 ++---
 2 files changed, 29 insertions(+), 8 deletions(-)

diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h 
b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
index 62d8496..4701cfb 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
@@ -333,6 +333,14 @@ enum {
GRF_GPIO2B4_SEL_MASK= 3 << GRF_GPIO2B4_SEL_SHIFT,
GRF_SPI2TPM_CSN0= 1,
 
+   /* GRF_GPIO2C_IOMUX */
+   GRF_GPIO2C0_SEL_SHIFT   = 0,
+   GRF_GPIO2C0_SEL_MASK= 3 << GRF_GPIO2C0_SEL_SHIFT,
+   GRF_UART0BT_SIN = 1,
+   GRF_GPIO2C1_SEL_SHIFT   = 2,
+   GRF_GPIO2C1_SEL_MASK= 3 << GRF_GPIO2C1_SEL_SHIFT,
+   GRF_UART0BT_SOUT= 1,
+
/* GRF_GPIO3A_IOMUX */
GRF_GPIO3A4_SEL_SHIFT   = 8,
GRF_GPIO3A4_SEL_MASK= 3 << GRF_GPIO3A4_SEL_SHIFT,
diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c 
b/arch/arm/mach-rockchip/rk3399-board-spl.c
index 7b4e0a1..c212143 100644
--- a/arch/arm/mach-rockchip/rk3399-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3399-board-spl.c
@@ -57,19 +57,22 @@ void secure_timer_init(void)
writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG);
 }
 
-#define GRF_EMMCCORE_CON11 0xff77f02c
-void board_init_f(ulong dummy)
+void board_debug_uart_init(void)
 {
-   struct udevice *pinctrl;
-   struct udevice *dev;
-   int ret;
-
-   /* Example code showing how to enable the debug UART on RK3288 */
 #include 
-   /* Enable early UART2 channel C on the RK3399 */
 #define GRF_BASE   0xff77
struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
 
+#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff18)
+   /* Enable early UART0 on the RK3399 */
+   rk_clrsetreg(&grf->gpio2c_iomux,
+GRF_GPIO2C0_SEL_MASK,
+GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT);
+   rk_clrsetreg(&grf->gpio2c_iomux,
+GRF_GPIO2C1_SEL_MASK,
+GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
+#else
+   /* Enable early UART2 channel C on the RK3399 */
rk_clrsetreg(&grf->gpio4c_iomux,
 GRF_GPIO4C3_SEL_MASK,
 GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
@@ -80,6 +83,16 @@ void board_init_f(ulong dummy)
rk_clrsetreg(&grf->soc_con7,
 GRF_UART_DBG_SEL_MASK,
 GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT);
+#endif
+}
+
+#define GRF_EMMCCORE_CON11 0xff77f02c
+void board_init_f(ulong dummy)
+{
+   struct udevice *pinctrl;
+   struct udevice *dev;
+   int ret;
+
 #define EARLY_UART
 #ifdef EARLY_UART
/*
-- 
1.9.1

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[U-Boot] [PATCH v2 0/2] rockchip: rk3399: spl: Make baudrate and UART configurable

2017-03-23 Thread Philipp Tomsich

The default configuration for debug output from the RK3399 SPL is
UART2 at 1.5MBaud. While this works reasonably well for the EVB,
custom boards may want to change these settings.

To simplify the enablement (i.e. to use the RS232 connector on our
baseboard and to improve the compatibility with commonly available
RS232-to-UART dongles) for the RK3399-Q7 SoM, we need to make both
the UART and the baudrate configurable.

This patch-series makes CONFIG_BAUDRATE a first-class citizen within
the Kconfig framework (so we can set it via defconfig) and adds the
required iomux support for UART0 in the RK3399 SPL.

Changes in v2:
- Changed hex constant to lowercase

Philipp Tomsich (2):
  rockchip: rk3399: spl: add UART0 support for SPL
  rockchip: config: rk3399: update defconfigs and rk3399_common

 arch/arm/include/asm/arch-rockchip/grf_rk3399.h |  8 +++
 arch/arm/mach-rockchip/rk3399-board-spl.c   | 29 ++---
 configs/evb-rk3399_defconfig|  2 ++
 configs/puma_defconfig  |  4 +++-
 include/configs/rk3399_common.h |  1 -
 5 files changed, 34 insertions(+), 10 deletions(-)

-- 
1.9.1

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[U-Boot] [PATCH v2 2/2] rockchip: config: rk3399: update defconfigs and rk3399_common

2017-03-23 Thread Philipp Tomsich
With everything set up to define CONFIG_BAUDRATE via defconfig and
with to have the SPL debug UART either on UART0 or UART2, the configs
for the RK3399 EVB and for the RK3399-Q7 can be updated.

Signed-off-by: Philipp Tomsich 

---

Changes in v2: None

 configs/evb-rk3399_defconfig| 2 ++
 configs/puma_defconfig  | 4 +++-
 include/configs/rk3399_common.h | 1 -
 3 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
index 22405ce..7a82869 100644
--- a/configs/evb-rk3399_defconfig
+++ b/configs/evb-rk3399_defconfig
@@ -43,7 +43,9 @@ CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_PWM_ROCKCHIP=y
 CONFIG_RAM=y
 CONFIG_SPL_RAM=y
+CONFIG_BAUDRATE=150
 CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xFF1A
 CONFIG_DEBUG_UART_CLOCK=2400
 CONFIG_DEBUG_UART_SHIFT=2
diff --git a/configs/puma_defconfig b/configs/puma_defconfig
index 515185e..8e29d96 100644
--- a/configs/puma_defconfig
+++ b/configs/puma_defconfig
@@ -43,8 +43,10 @@ CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_PWM_ROCKCHIP=y
 CONFIG_RAM=y
 CONFIG_SPL_RAM=y
+CONFIG_BAUDRATE=115200
 CONFIG_DEBUG_UART=y
-CONFIG_DEBUG_UART_BASE=0xFF1A
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_BASE=0xFF18
 CONFIG_DEBUG_UART_CLOCK=2400
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550=y
diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h
index bc91eb6..c1ea616 100644
--- a/include/configs/rk3399_common.h
+++ b/include/configs/rk3399_common.h
@@ -12,7 +12,6 @@
 #define CONFIG_NR_DRAM_BANKS   1
 #define CONFIG_ENV_SIZE0x2000
 #define CONFIG_SYS_MAXARGS 16
-#define CONFIG_BAUDRATE150
 #define CONFIG_SYS_MALLOC_LEN  (32 << 20)
 #define CONFIG_SYS_CBSIZE  1024
 #define CONFIG_SKIP_LOWLEVEL_INIT
-- 
1.9.1

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[U-Boot] [PATCH] ti: clocks: Fix do_enable_clocks() to accept NULL pointers as input parameters

2017-03-23 Thread Lukasz Majewski
Up till this commit passing NULL as input parameter was allowed, but not
handled properly.

When one passed NULL to one of this function parameters, the code was
executed causing data abort.

However, what is more interesting, the abort was not caught because of code
execution in HYP mode with masked CPSR A bit ("Imprecise Data Abort mask bit).
The TI's AM57xx SoC switch to HYP mode with A bit masked in lowlevel_init.S
due to SMC call. Such operation (by default) is performed in SoC ROM code.

The problem would pop up when one:
- Switch back to SVC mode after disabling LPAE support
- Somebody enables A bit (by executing cpsie a asm instruction)

and then the previously described exception would be caught.

Signed-off-by: Lukasz Majewski 
---
 arch/arm/cpu/armv7/omap-common/clocks-common.c | 10 ++
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c 
b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index 097b8e3..157155a 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -822,27 +822,29 @@ void do_enable_clocks(u32 const *clk_domains,
u32 i, max = 100;
 
/* Put the clock domains in SW_WKUP mode */
-   for (i = 0; (i < max) && clk_domains[i]; i++) {
+   for (i = 0; (i < max) && clk_domains && clk_domains[i]; i++) {
enable_clock_domain(clk_domains[i],
CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
}
 
/* Clock modules that need to be put in HW_AUTO */
-   for (i = 0; (i < max) && clk_modules_hw_auto[i]; i++) {
+   for (i = 0; (i < max) && clk_modules_hw_auto &&
+clk_modules_hw_auto[i]; i++) {
enable_clock_module(clk_modules_hw_auto[i],
MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
wait_for_enable);
};
 
/* Clock modules that need to be put in SW_EXPLICIT_EN mode */
-   for (i = 0; (i < max) && clk_modules_explicit_en[i]; i++) {
+   for (i = 0; (i < max) && clk_modules_explicit_en &&
+clk_modules_explicit_en[i]; i++) {
enable_clock_module(clk_modules_explicit_en[i],
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
wait_for_enable);
};
 
/* Put the clock domains in HW_AUTO mode now */
-   for (i = 0; (i < max) && clk_domains[i]; i++) {
+   for (i = 0; (i < max) && clk_domains && clk_domains[i]; i++) {
enable_clock_domain(clk_domains[i],
CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
}
-- 
2.1.4

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[U-Boot] [PATCH] rockchip: spl: RK3399: add COUNTER_FREQUENCY define to rk3399_common.h

2017-03-23 Thread Philipp Tomsich
The BootROM of the RK3399 SoC does not initialise the cntfrq_el0 (which
holds the value 0 (zero) on entry into the SPL. This causes the timebase
for U-Boot not to advance (and will cause a hang where a timeout would
be expected... e.g. if something goes wrong during MMC/SD card startup).

This change defines COUNTER_FREQUENCY, which is used by the AArch64 init
code in arch/arm/cpu/armv8/start.S to set up cntfrq_el0 (if necessary).

Signed-off-by: Philipp Tomsich 
---

 include/configs/rk3399_common.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h
index aeee805..c44f8ad 100644
--- a/include/configs/rk3399_common.h
+++ b/include/configs/rk3399_common.h
@@ -19,6 +19,8 @@
 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
 #define CONFIG_SPL_SERIAL_SUPPORT
 
+#define COUNTER_FREQUENCY   2400
+
 #define CONFIG_SYS_NS16550_MEM32
 
 #define CONFIG_SYS_TEXT_BASE   0x0020
-- 
1.9.1

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[U-Boot] [PATCH 0/3] rockchip: rk3188 fixed early stage and radxarock board

2017-03-23 Thread Heiko Stuebner
Applies on top of current rockchip master branch and needs
Kever's early_init patch for rk3188 and rk3399.

After this one series, there is of course still
rockchip: rk3188: fixups and armclk speedup
series and
rockchip: rk3188: enable remap function
patch open.


changes compared to the original patches:
- made it apply on top of current rockchip master
- arranged in a way to not create build errors
- so adapted the TPL_LIBGENERIC patch to be in front
  of the rock board addition

Heiko Stuebner (3):
  rockchip: rk3188: enable TPL_LIBGENERIC for generic memset
  rockchip: rk3188: Add Radxa Rock board
  rockchip: rk3188: add README.rockchip paragraph describing sd boot

 arch/arm/dts/Makefile |   1 +
 arch/arm/dts/rk3188-radxarock.dts | 382 ++
 arch/arm/mach-rockchip/rk3188/Kconfig |  14 ++
 board/radxa/rock/Kconfig  |  15 ++
 board/radxa/rock/MAINTAINERS  |   6 +
 board/radxa/rock/Makefile |   7 +
 board/radxa/rock/rock.c   |   7 +
 configs/rock_defconfig|  58 ++
 doc/README.rockchip   |  26 +++
 include/configs/rock.h|  30 +++
 10 files changed, 546 insertions(+)
 create mode 100644 arch/arm/dts/rk3188-radxarock.dts
 create mode 100644 board/radxa/rock/Kconfig
 create mode 100644 board/radxa/rock/MAINTAINERS
 create mode 100644 board/radxa/rock/Makefile
 create mode 100644 board/radxa/rock/rock.c
 create mode 100644 configs/rock_defconfig
 create mode 100644 include/configs/rock.h

-- 
2.11.0

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[U-Boot] [PATCH 1/3] rockchip: rk3188: enable TPL_LIBGENERIC for generic memset

2017-03-23 Thread Heiko Stuebner
Commit c67c8c604b6c ("board_init.c: Always use memset()") dropped the naive
memset alternative from board_init_f_init_reserve.
So activate CONFIG_TPL_LIBGENERIC for that common memset implementation.
We cannot use the ARCH-specific memset, as that would incur 200bytes of
additional TPL size, space we do not have.

Signed-off-by: Heiko Stuebner 
---
 arch/arm/mach-rockchip/rk3188/Kconfig | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-rockchip/rk3188/Kconfig 
b/arch/arm/mach-rockchip/rk3188/Kconfig
index f8e1d0316b..b70d45cd62 100644
--- a/arch/arm/mach-rockchip/rk3188/Kconfig
+++ b/arch/arm/mach-rockchip/rk3188/Kconfig
@@ -18,6 +18,9 @@ config SPL_SERIAL_SUPPORT
 config TPL_LIBCOMMON_SUPPORT
default y
 
+config TPL_LIBGENERIC_SUPPORT
+   default y
+
 config TPL_SERIAL_SUPPORT
default y
 
-- 
2.11.0

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[U-Boot] [PATCH 2/3] rockchip: rk3188: Add Radxa Rock board

2017-03-23 Thread Heiko Stuebner
The Rock is a RK3188 based single board computer by Radxa.
Currently it still relies on the proprietary DDR init and
cannot use the generic SPL, but at least is able to boot
a linux kernel and system up to a regular login prompt.

Signed-off-by: Heiko Stuebner 
Reviewed-by: Simon Glass 
Tested-by: Kever Yang 
---
 arch/arm/dts/Makefile |   1 +
 arch/arm/dts/rk3188-radxarock.dts | 382 ++
 arch/arm/mach-rockchip/rk3188/Kconfig |  11 +
 board/radxa/rock/Kconfig  |  15 ++
 board/radxa/rock/MAINTAINERS  |   6 +
 board/radxa/rock/Makefile |   7 +
 board/radxa/rock/rock.c   |   7 +
 configs/rock_defconfig|  58 ++
 include/configs/rock.h|  30 +++
 9 files changed, 517 insertions(+)
 create mode 100644 arch/arm/dts/rk3188-radxarock.dts
 create mode 100644 board/radxa/rock/Kconfig
 create mode 100644 board/radxa/rock/MAINTAINERS
 create mode 100644 board/radxa/rock/Makefile
 create mode 100644 board/radxa/rock/rock.c
 create mode 100644 configs/rock_defconfig
 create mode 100644 include/configs/rock.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index d00651c74c..8c726c3d10 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -29,6 +29,7 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
 dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3036-sdk.dtb \
+   rk3188-radxarock.dtb \
rk3288-firefly.dtb \
rk3288-veyron-jerry.dtb \
rk3288-veyron-mickey.dtb \
diff --git a/arch/arm/dts/rk3188-radxarock.dts 
b/arch/arm/dts/rk3188-radxarock.dts
new file mode 100644
index 00..5f5b5e9a1f
--- /dev/null
+++ b/arch/arm/dts/rk3188-radxarock.dts
@@ -0,0 +1,382 @@
+/*
+ * Copyright (c) 2013 Heiko Stuebner 
+ *
+ * SPDX-License-Identifier: GPL-2.0+ or X11
+ */
+
+/dts-v1/;
+#include 
+#include "rk3188.dtsi"
+
+/ {
+   model = "Radxa Rock";
+   compatible = "radxa,rock", "rockchip,rk3188";
+
+   chosen {
+/* stdout-path = &uart2; */
+   stdout-path = "serial2:115200n8";
+   };
+
+   config {
+   u-boot,dm-pre-reloc;
+   u-boot,boot-led = "rock:red:power";
+   };
+
+   memory {
+   device_type = "memory";
+   reg = <0x6000 0x8000>;
+   };
+
+   gpio-keys {
+   compatible = "gpio-keys";
+   autorepeat;
+
+   power {
+   gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
+   linux,code = ;
+   label = "GPIO Key Power";
+   linux,input-type = <1>;
+   wakeup-source;
+   debounce-interval = <100>;
+   };
+   };
+
+   gpio-leds {
+   compatible = "gpio-leds";
+
+   green {
+   label = "rock:green:user1";
+   gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
+   default-state = "off";
+   };
+
+   blue {
+   label = "rock:blue:user2";
+   gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
+   default-state = "off";
+   };
+
+   sleep {
+   label = "rock:red:power";
+   gpios = <&gpio0 15 0>;
+   default-state = "off";
+   };
+   };
+
+   sound {
+   compatible = "simple-audio-card";
+   simple-audio-card,name = "SPDIF";
+
+   simple-audio-card,dai-link@1 {  /* S/PDIF - S/PDIF */
+   cpu { sound-dai = <&spdif>; };
+   codec { sound-dai = <&spdif_out>; };
+   };
+   };
+
+   spdif_out: spdif-out {
+   compatible = "linux,spdif-dit";
+   #sound-dai-cells = <0>;
+   };
+
+   ir_recv: gpio-ir-receiver {
+   compatible = "gpio-ir-receiver";
+   gpios = <&gpio0 10 1>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&ir_recv_pin>;
+   };
+
+   vcc_otg: usb-otg-regulator {
+   compatible = "regulator-fixed";
+   enable-active-high;
+   gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&otg_vbus_drv>;
+   regulator-name = "otg-vbus";
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   regulator-always-on;
+   regulator-boot-on;
+   };
+
+   vcc_sd0: sdmmc-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "sdmmc-supply";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   gpio = <&gpio3 1 GPIO_ACTIVE_LOW>;
+   

[U-Boot] [PATCH 3/3] rockchip: rk3188: add README.rockchip paragraph describing sd boot

2017-03-23 Thread Heiko Stuebner
Building sd images for rk3188 requires more steps due to the needed split
into TPL and SPL as loaders. Describe how to build an image for it in a
separate paragraph in the READER.rockchip file.

Signed-off-by: Heiko Stuebner 
---
 doc/README.rockchip | 26 ++
 1 file changed, 26 insertions(+)

diff --git a/doc/README.rockchip b/doc/README.rockchip
index 186a1a007e..cb81efd4bf 100644
--- a/doc/README.rockchip
+++ b/doc/README.rockchip
@@ -147,6 +147,32 @@ For evb_rk3036 board:
 Note: rk3036 SDMMC and debug uart use the same iomux, so if you boot from SD, 
the
   debug uart must be disabled
 
+
+Booting from an SD card on RK3188
+=
+
+For rk3188 boards the general storage onto the card stays the same as
+described above, but the image creation needs a bit more care.
+
+The bootrom of rk3188 expects to find a small 1kb loader which returns
+control to the bootrom, after which it will load the real loader, which
+can then be up to 29kb in size and does the regular ddr init.
+
+Additionally the rk3188 requires everything the bootrom loads to be
+rc4-encrypted. Except for the very first stage the bootrom always reads
+and decodes 2kb pages, so files should be sized accordingly.
+
+# copy tpl, pad to 1020 bytes and append spl
+cat tpl/u-boot-tpl.bin > tplspl.bin
+truncate -s 1020 tplspl.bin
+cat spl/u-boot-spl.bin >> tplspl.bin
+tools/mkimage -n rk3188 -T rksd -d tplspl.bin out
+
+# truncate, encode and append u-boot.bin
+truncate -s %2048 u-boot.bin
+cat u-boot.bin | split -b 512 --filter='openssl rc4 -K 
7C4E0304550509072D2C7B38170D1711' >> out
+
+
 Using fastboot on rk3288
 
 - Write GPT partition layout to mmc device which fastboot want to use it to
-- 
2.11.0

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[U-Boot] [PATCH] rockchip: Add support for MiQi rk3288 board

2017-03-23 Thread Jernej Skrabec
MiQi is rk3288 based development board with 1 or 2 GB SDRAM, 16 GB eMMC,
micro SD card interface, 4 USB 2.0 ports, HDMI, gigabit Ethernet and
expansion ports.

Signed-off-by: Jernej Skrabec 
---

 arch/arm/dts/Makefile   |   1 +
 arch/arm/dts/rk3288-miqi.dts|  46 
 arch/arm/dts/rk3288-miqi.dtsi   | 459 
 arch/arm/mach-rockchip/rk3288/Kconfig   |  11 +
 board/mqmaker/miqi_rk3288/Kconfig   |  15 ++
 board/mqmaker/miqi_rk3288/MAINTAINERS   |   6 +
 board/mqmaker/miqi_rk3288/Makefile  |   7 +
 board/mqmaker/miqi_rk3288/miqi-rk3288.c |  15 ++
 configs/miqi-rk3288_defconfig   |  73 +
 doc/README.rockchip |   5 +-
 include/configs/miqi_rk3288.h   |  22 ++
 11 files changed, 658 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/dts/rk3288-miqi.dts
 create mode 100644 arch/arm/dts/rk3288-miqi.dtsi
 create mode 100644 board/mqmaker/miqi_rk3288/Kconfig
 create mode 100644 board/mqmaker/miqi_rk3288/MAINTAINERS
 create mode 100644 board/mqmaker/miqi_rk3288/Makefile
 create mode 100644 board/mqmaker/miqi_rk3288/miqi-rk3288.c
 create mode 100644 configs/miqi-rk3288_defconfig
 create mode 100644 include/configs/miqi_rk3288.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index afeb43ff66..60a9aeb698 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -38,6 +38,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-fennec.dtb \
rk3288-tinker.dtb \
rk3288-popmetal.dtb \
+   rk3288-miqi.dtb \
rk3328-evb.dtb \
rk3399-evb.dtb
 dtb-$(CONFIG_ARCH_MESON) += \
diff --git a/arch/arm/dts/rk3288-miqi.dts b/arch/arm/dts/rk3288-miqi.dts
new file mode 100644
index 00..7b92caf024
--- /dev/null
+++ b/arch/arm/dts/rk3288-miqi.dts
@@ -0,0 +1,46 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/dts-v1/;
+#include "rk3288-miqi.dtsi"
+
+/ {
+   model = "mqmaker MiQi";
+   compatible = "mqmaker,miqi", "rockchip,rk3288";
+
+   chosen {
+   stdout-path = "serial2:115200n8";
+   };
+};
+
+&dmc {
+   rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
+   0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
+   0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
+   0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
+   0x5 0x0>;
+   rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
+   0xa60 0x40 0x10 0x0>;
+   rockchip,sdram-params = <0x30B25564 0x627 3 66600 3 9 1>;
+};
+
+
+&pinctrl {
+   u-boot,dm-pre-reloc;
+};
+
+&uart2 {
+   u-boot,dm-pre-reloc;
+   reg-shift = <2>;
+};
+
+&sdmmc {
+   u-boot,dm-pre-reloc;
+};
+
+&emmc {
+   u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/rk3288-miqi.dtsi b/arch/arm/dts/rk3288-miqi.dtsi
new file mode 100644
index 00..12e584f242
--- /dev/null
+++ b/arch/arm/dts/rk3288-miqi.dtsi
@@ -0,0 +1,459 @@
+/*
+ * Copyright (c) 2016 Heiko Stuebner 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALING

Re: [U-Boot] [PATCH 16/17] aspeed: Add AST2500/AST2400 compatible NIC Driver

2017-03-23 Thread Maxim Sloyko
On Wed, Mar 22, 2017 at 6:06 AM, Simon Glass  wrote:

> Hi Maxim,
>
> On 21 March 2017 at 17:44, Maxim Sloyko  wrote:
> > Hi Joe,
> >
> > Please see responses inline, simply ACK'ed comments will be addressed
> > in the next version.
> >
> > On Tue, Mar 21, 2017 at 12:32 PM, Joe Hershberger
> >  wrote:
> >> On Thu, Mar 16, 2017 at 4:36 PM, Maxim Sloyko 
> wrote:
> >>> The device that Aspeed uses is basically Faraday FTGMAC100, but with
> >>> some differences here and there. Since I don't have access to a
> properly
> >>> implemented FTGMAC100 though, I can't really test it and so I don't
> >>> feel comfortable claiming compatibility, even though I reused a lot of
> >>> FTGMAC100 driver code.
> >>
> >> I think it would be better to attempt to integrate this driver with
> >> the FTGMAC driver and ask others on the list who have that HW to test
> >> your changes to ensure no regressions. I prefer we have fewer drivers
> >> to maintain.
> >
> > One concern: this driver also performs its clock configuration, which
> > I believe is very specific to the SoC, so to have that compatibility
> > clock configuration needs to be externalized somehow. I don't know
> > what is the best way to do it.
>
> Generally the clock is defined by a DT property in the node, so this
> should work out OK.
>

Well, this device on this SoC needs two different clocks configured, one
for all devices and one device specific. The device speed is also hardware
strapped, so it reads the unrelated register to figure out which rate to
enable. Not to mention, it's still unclear how it's going to be done in
Linux, so somewhere else in this review Tom actually suggested to go non-DT
way with this.

Anyway, I'm going to drop this driver from this series and work this out
separately, just to keep things moving, because it looks like it raises the
largest number of concerns.


>
> Regards,
> Simon
>



-- 
*M*axim *S*loyko
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