Re: [U-Boot] Config for karo tx28

2017-01-30 Thread Wim Vinckier
On 28 January 2017 at 16:02, Fabio Estevam  wrote:

> On Fri, Jan 27, 2017 at 12:28 PM, Wim Vinckier 
> wrote:
> > Hi,
> >
> > I'm wondering if someone has a configuration laying around for karo tx28.
> > I've been using the karo version for a while but wanted to switch to the
> > latest u-boot version.
> > Or does there exist a way to convert an old manual configuration to a
> > modern .config one?
>
> Yes, you would need to port the old U-Boot to the mainline style. Then
> you can submit the patch in the list, so that it gets reviewed and if
> it looks good it will be applied.
>

Thanks for the answer but is there an easy way to do it?  I've been trying
but I currently get no console on my new version.  I'm hoping there is some
kind of magic program which could convert my old header file to a .config
file for the latest version.

wim.
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Re: [U-Boot] [PATCH v4 2/9] arm: imx6ul: Add Engicam Is.IoT MX6UL Starter Kit initial support

2017-01-30 Thread Jagan Teki
On Sat, Jan 28, 2017 at 1:39 PM, Michael Nazzareno Trimarchi
 wrote:
> Hi
>
>
>
> On 28 Jan 2017 1:25 p.m., "Stefano Babic"  wrote:
>
> Hi Jagan, Tom,
>
> On 27/01/2017 16:55, Jagan Teki wrote:
>> n Fri, Jan 27, 2017 at 1:38 PM, Stefano Babic  wrote:
>>> Hi Jagan,
>>>
>>> On 27/01/2017 09:54, Jagan Teki wrote:
 From: Jagan Teki 

 Boot from MMC:
 -
 U-Boot SPL 2017.01-rc2-gba3c151-dirty (Jan 02 2017 - 16:59:33)
 Trying to boot from MMC1

 U-Boot 2017.01-rc2-gba3c151-dirty (Jan 02 2017 - 16:59:33 +0100)

 CPU:   Freescale i.MX6UL rev1.1 528 MHz (running at 396 MHz)
 CPU:   Industrial temperature grade (-40C to 105C) at 33C
 Reset cause: POR
 Model: Engicam Is.IoT MX6UL Starterkit
 DRAM:  512 MiB
 MMC:   FSL_SDHC: 0
 *** Warning - bad CRC, using default environment

 In:serial
 Out:   serial
 Err:   serial
 Net:   CPU Net Initialization Failed
 No ethernet found.
 Hit any key to stop autoboot:  0
 isiotmx6ul>

 Cc: Stefano Babic 
 Cc: Matteo Lisi 
 Cc: Michael Trimarchi 
 Signed-off-by: Jagan Teki 
 ---
  arch/arm/cpu/armv7/mx6/Kconfig|  11 ++
  arch/arm/dts/Makefile |   3 +-
  arch/arm/dts/imx6ul-isiot-mmc.dts |  50 +++
  arch/arm/dts/imx6ul-isiot.dtsi|  92 +
  board/engicam/isiotmx6ul/Kconfig  |  12 ++
  board/engicam/isiotmx6ul/MAINTAINERS  |   6 +
  board/engicam/isiotmx6ul/Makefile |   6 +
  board/engicam/isiotmx6ul/README   |  28 
  board/engicam/isiotmx6ul/isiotmx6ul.c | 247
> ++
  configs/imx6ul_isiot_mmc_defconfig|  36 +
  include/configs/imx6ul_isiot.h| 142 +++
  11 files changed, 632 insertions(+), 1 deletion(-)
  create mode 100644 arch/arm/dts/imx6ul-isiot-mmc.dts
  create mode 100644 arch/arm/dts/imx6ul-isiot.dtsi
  create mode 100644 board/engicam/isiotmx6ul/Kconfig
  create mode 100644 board/engicam/isiotmx6ul/MAINTAINERS
  create mode 100644 board/engicam/isiotmx6ul/Makefile
  create mode 100644 board/engicam/isiotmx6ul/README
  create mode 100644 board/engicam/isiotmx6ul/isiotmx6ul.c
  create mode 100644 configs/imx6ul_isiot_mmc_defconfig
  create mode 100644 include/configs/imx6ul_isiot.h

 diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/
> Kconfig
 index c646966..72780d7 100644
 --- a/arch/arm/cpu/armv7/mx6/Kconfig
 +++ b/arch/arm/cpu/armv7/mx6/Kconfig
 @@ -205,6 +205,16 @@ config TARGET_MX6UL_GEAM
   select DM_THERMAL
   select SUPPORT_SPL

 +config TARGET_MX6UL_ISIOT
 + bool "Support Engicam Is.IoT MX6UL"
 + select MX6UL
 + select OF_CONTROL
 + select DM
 + select DM_GPIO
 + select DM_MMC
 + select DM_THERMAL
 + select SUPPORT_SPL
 +
  config TARGET_MX6ULL_14X14_EVK
   bool "Support mx6ull_14x14_evk"
   select MX6ULL
 @@ -313,6 +323,7 @@ source "board/embest/mx6boards/Kconfig"
  source "board/engicam/geam6ul/Kconfig"
  source "board/engicam/icorem6/Kconfig"
  source "board/engicam/icorem6_rqs/Kconfig"
 +source "board/engicam/isiotmx6ul/Kconfig"
  source "board/freescale/mx6qarm2/Kconfig"
  source "board/freescale/mx6qsabreauto/Kconfig"
  source "board/freescale/mx6sabresd/Kconfig"
 diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
 index 6a7924e..e83308c 100644
 --- a/arch/arm/dts/Makefile
 +++ b/arch/arm/dts/Makefile
 @@ -313,7 +313,8 @@ dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \
   imx6dl-icore-rqs.dtb \
   imx6q-icore.dtb \
   imx6q-icore-rqs.dtb \
 - imx6ul-geam-kit.dtb
 + imx6ul-geam-kit.dtb \
 + imx6ul-isiot-mmc.dtb

  dtb-$(CONFIG_MX7) += imx7-colibri.dtb

 diff --git a/arch/arm/dts/imx6ul-isiot-mmc.dts
> b/arch/arm/dts/imx6ul-isiot-mmc.dts
 new file mode 100644
 index 000..bb5086a
 --- /dev/null
 +++ b/arch/arm/dts/imx6ul-isiot-mmc.dts
 @@ -0,0 +1,50 @@
 +/*
 + * Copyright (C) 2016 Amarula Solutions B.V.
 + * Copyright (C) 2016 Engicam S.r.l.
 + *
 + * This file is dual-licensed: you can use it either under the terms
 + * of the GPL or the X11 license, at your option. Note that this dual
 + * licensing only applies to this file, and not this project as a
 + * whole.
 + *
>>>
>>>
>>> I have seen that a lot of files slipped into mainline, and I have myself
>>> not paid enough attention befeore (see your imx6ul-geam-kit.dts for
>>> example).
>>>
>>> But we moved some years ago to SPDX-License-Identifier. Other DTS files
>>> are using this as well without copying the whole license. Could you do
>>> this here, too ? It would be also nice if you plan to fix this for all
>>> Engicam's boards, thanks !
>

Re: [U-Boot] [PATCH] LS1021ATWR: Modify u-boot size for sd secureboot

2017-01-30 Thread Sumit Garg
> -Original Message-
> From: york sun
> Sent: Friday, January 27, 2017 10:55 PM
> To: Vini Pillai ; Sumit Garg 
> Cc: u-boot@lists.denx.de; Ruchika Gupta ;
> Prabhakar Kushwaha 
> Subject: Re: [PATCH] LS1021ATWR: Modify u-boot size for sd secureboot
> 
> "Secure boot" is a two-word phrase, not one word.
> 
> On 01/20/2017 01:35 AM, Vinitha Pillai-B57223 wrote:
> > From: Vinitha Pillai 
> >
> > Raw uboot image is used in place of FIT image in secure boot.
> > The maximum allocated size of raw u-boot bin is 1MB in memory map.
> > Hence , CONFIG_SYS_MONITOR_LEN has been modified to 1 MB.
> > The bootscript  (BS_ADDR) and its header (BS_HDR_ADDR) offset on MMC
> have also been modified to accommodate the increase in uboot size.
> 
> Please wrap back at or before 70 characters. Avoid putting extra white space 
> in
> the message.
> 
> >
> > Signed-off-by: Vinitha Pillai-B57223 
> 
> Sumit,
> 
> This change seems harmless. However I don't have the images setup for
> testing. Please review this patch as the secure boot maintainer.
> 
> York

Reviewed-by: Sumit Garg 

Vinitha,

Please incorporate York comments.

Sumit
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Re: [U-Boot] [PATCH v4 2/9] arm: imx6ul: Add Engicam Is.IoT MX6UL Starter Kit initial support

2017-01-30 Thread Stefano Babic
Hi Jagan,

On 30/01/2017 10:41, Jagan Teki wrote:

>> You are the board maintainer, and it is your decision. Anyway, clocks
>> are not disable in u-boot, and they can remain on in Linux, because they
>> are set just if needed. Some kernels had disabled in the past for some
>> platform (I know OMAP3) all not required clocks, but this was in the era
>> before DT. Kernel just supposes that nothing is set.
>>
>>
>> I agree with Stefano. Clocks part should clean up. We have done in the past
>> for OMAP architecture
> 
> I would like to go-ahead with these now, since many of i.MX(even other
> engicam) boards does the same.

Just because I (or someone else) did not note this isuse in the past, it
does not mean that this is a good reason to go on doing wrongly.

Fix this, and you will have time later to send patches for the other boards.

Best regards,
Stefano

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[U-Boot] [UBOOT v2 03/15] mmc: sdhci: Add SD3.0 support

2017-01-30 Thread Siva Durga Prasad Paladugu
Add support for all UHS modes of SD3.0.
This patch defines the routines to switch
volatge, setting uhs modes and execute tuning
as these are needed for SD3.0 support

Signed-off-by: Siva Durga Prasad Paladugu 
---
Changes from v1:
- Split the patch with only sdhci changes
  as per comment
---
 drivers/mmc/sdhci.c | 157 +++-
 include/sdhci.h |   8 +++
 2 files changed, 163 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 884b6a6..bba2c30 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -13,6 +13,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
 void *aligned_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
@@ -155,7 +156,8 @@ static int sdhci_send_command(struct mmc *mmc, struct 
mmc_cmd *cmd,
 
/* We shouldn't wait for data inihibit for stop commands, even
   though they might use busy signaling */
-   if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
+   if ((cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) ||
+   (cmd->cmdidx ==  MMC_CMD_SEND_TUNING_BLOCK))
mask &= ~SDHCI_DATA_INHIBIT;
 
while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
@@ -175,6 +177,11 @@ static int sdhci_send_command(struct mmc *mmc, struct 
mmc_cmd *cmd,
}
 
mask = SDHCI_INT_RESPONSE;
+
+   /* only buffer read ready interrupt whil tuning */
+   if (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
+   mask = SDHCI_INT_DATA_AVAIL;
+
if (!(cmd->resp_type & MMC_RSP_PRESENT))
flags = SDHCI_CMD_RESP_NONE;
else if (cmd->resp_type & MMC_RSP_136)
@@ -190,7 +197,7 @@ static int sdhci_send_command(struct mmc *mmc, struct 
mmc_cmd *cmd,
flags |= SDHCI_CMD_CRC;
if (cmd->resp_type & MMC_RSP_OPCODE)
flags |= SDHCI_CMD_INDEX;
-   if (data)
+   if (data || (cmd->cmdidx ==  MMC_CMD_SEND_TUNING_BLOCK))
flags |= SDHCI_CMD_DATA;
 
/* Set Transfer mode regarding to data flag */
@@ -291,6 +298,80 @@ static int sdhci_send_command(struct mmc *mmc, struct 
mmc_cmd *cmd,
else
return -ECOMM;
 }
+#ifdef CONFIG_DM_MMC_OPS
+static int sdhci_execute_tuning(struct udevice *dev, u8 opcode)
+{
+   struct mmc *mmc = mmc_get_mmc_dev(dev);
+#else
+static int sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
+{
+#endif
+   struct mmc_cmd cmd;
+   struct mmc_data data;
+   u32 ctrl;
+   u8 tuning_loop_counter = 40;
+   struct sdhci_host *host = mmc->priv;
+
+   debug("%s\n", __func__);
+
+   ctrl = sdhci_readw(host, SDHCI_HOST_CTRL2);
+   ctrl |= SDHCI_CTRL_EXEC_TUNING;
+   sdhci_writew(host, ctrl, SDHCI_HOST_CTRL2);
+
+   sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
+   sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
+
+   do {
+   cmd.cmdidx = opcode;
+   cmd.resp_type = MMC_RSP_R1;
+   cmd.cmdarg = 0;
+
+   data.blocksize = 64;
+   data.blocks = 1;
+   data.flags = MMC_DATA_READ;
+
+   if (tuning_loop_counter == 0)
+   break;
+
+   tuning_loop_counter--;
+
+   if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200 &&
+   mmc->bus_width == 8) {
+   data.blocksize = 128;
+   }
+
+   sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
+   data.blocksize),
+SDHCI_BLOCK_SIZE);
+   sdhci_writew(host, data.blocks, SDHCI_BLOCK_COUNT);
+   sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
+
+   sdhci_send_command(dev, &cmd, &data);
+   ctrl = sdhci_readw(host, SDHCI_HOST_CTRL2);
+
+   if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
+   udelay(1);
+
+   } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
+
+   if (tuning_loop_counter < 0) {
+   ctrl &= ~SDHCI_CTRL_TUNED_CLK;
+   sdhci_writel(host, ctrl, SDHCI_HOST_CTRL2);
+   }
+
+   if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
+   debug("%s:Tuning failed\n", __func__);
+   return -1;
+   }
+
+   /* Enable only interrupts served by the SD controller */
+   sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
+SDHCI_INT_ENABLE);
+   /* Mask all sdhci interrupt sources */
+   sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
+
+   return 0;
+}
 
 static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
 {
@@ -384,6 +465,72 @@ static int sdhci_set_clock(struct mmc *mmc, unsigned int 
clock)
return 0;
 }
 
+#ifdef CONFIG_DM_MMC_OPS
+static int sdhci_set_voltage(struct udevice *dev)
+{
+   struct mmc *mmc = mmc_get_mmc_dev(dev);
+#el

[U-Boot] [UBOOT v2 02/15] mmc: Add support for SD3.0

2017-01-30 Thread Siva Durga Prasad Paladugu
The SD3.0 needs voltage switching to 1.8V
based on host and cards capabilities and also
needs to switch to one of the uhs modes based
on cards capability. This supports frequencies
till 200MHz. This patch define hooks to perform
the same at sdhci driver level.

Signed-off-by: Siva Durga Prasad Paladugu 
---
Changes from v1:
- Split the patch with only mmc changes
  as per comment
---
 drivers/mmc/mmc-uclass.c |  52 ++
 drivers/mmc/mmc.c| 138 ---
 include/mmc.h|  55 ++-
 3 files changed, 238 insertions(+), 7 deletions(-)

diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c
index 2fe5d61..3ca3e49 100644
--- a/drivers/mmc/mmc-uclass.c
+++ b/drivers/mmc/mmc-uclass.c
@@ -77,6 +77,58 @@ int mmc_getcd(struct mmc *mmc)
 {
return dm_mmc_get_cd(mmc->dev);
 }
+
+int dm_mmc_set_voltage(struct udevice *dev)
+{
+   struct dm_mmc_ops *ops = mmc_get_ops(dev);
+
+   if (!ops->set_voltage)
+   return -ENOSYS;
+
+   return ops->set_voltage(dev);
+}
+
+int mmc_set_voltage(struct mmc *mmc)
+{
+   return dm_mmc_set_voltage(mmc->dev);
+}
+
+int dm_mmc_set_uhs(struct udevice *dev)
+{
+   struct dm_mmc_ops *ops = mmc_get_ops(dev);
+
+   if (!ops->set_uhs)
+   return -ENOSYS;
+
+   return ops->set_uhs(dev);
+}
+
+int mmc_switch_uhs(struct mmc *mmc)
+{
+   return dm_mmc_set_uhs(mmc->dev);
+}
+
+int dm_mmc_execute_tuning(struct udevice *dev)
+{
+   struct mmc *mmc = mmc_get_mmc_dev(dev);
+   struct dm_mmc_ops *ops = mmc_get_ops(dev);
+   u8 opcode;
+
+   if (!ops->execute_tuning)
+   return -ENOSYS;
+
+   if (IS_SD(mmc))
+   opcode = MMC_CMD_SEND_TUNING_BLOCK;
+   else
+   opcode = MMC_CMD_SEND_TUNING_BLOCK_HS200;
+
+   return ops->execute_tuning(dev, opcode);
+}
+
+int mmc_execute_tuning(struct mmc *mmc)
+{
+   return dm_mmc_execute_tuning(mmc->dev);
+}
 #endif
 
 struct mmc *mmc_get_mmc_dev(struct udevice *dev)
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 3648950..0f0bfc8 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -339,6 +339,47 @@ static int mmc_go_idle(struct mmc *mmc)
return 0;
 }
 
+#ifndef CONFIG_DM_MMC_OPS
+static int mmc_set_voltage(struct mmc *mmc)
+{
+   int err = 0;
+
+   if (mmc->cfg->ops->set_voltage) {
+   err = mmc->cfg->ops->set_voltage(mmc);
+   if (err)
+   return err;
+   }
+
+   return err;
+}
+#endif
+
+static int mmc_switch_voltage(struct mmc *mmc)
+{
+   struct mmc_cmd cmd;
+   int err = 0;
+
+   cmd.cmdidx = SD_CMD_SWITCH_UHS18V;
+   cmd.cmdarg = 0;
+   cmd.resp_type = MMC_RSP_NONE;
+
+   err = mmc_send_cmd(mmc, &cmd, NULL);
+   if (err)
+   return err;
+
+   err = mmc_set_voltage(mmc);
+
+   return err;
+}
+
+static int mmc_host_uhs(struct mmc *mmc)
+{
+   return mmc->cfg->host_caps &
+   (MMC_MODE_UHS_SDR12 | MMC_MODE_UHS_SDR25 |
+MMC_MODE_UHS_SDR50 | MMC_MODE_UHS_SDR104 |
+MMC_MODE_UHS_DDR50);
+}
+
 static int sd_send_op_cond(struct mmc *mmc)
 {
int timeout = 1000;
@@ -371,6 +412,9 @@ static int sd_send_op_cond(struct mmc *mmc)
if (mmc->version == SD_VERSION_2)
cmd.cmdarg |= OCR_HCS;
 
+   if (mmc_host_uhs(mmc))
+   cmd.cmdarg |= SD_OCR_S18R;
+
err = mmc_send_cmd(mmc, &cmd, NULL);
 
if (err)
@@ -401,6 +445,13 @@ static int sd_send_op_cond(struct mmc *mmc)
 
mmc->ocr = cmd.response[0];
 
+   if (mmc->ocr & SD_OCR_S18R) {
+   err = mmc_switch_voltage(mmc);
+   if (err)
+   return err;
+   mmc->is_uhs = 1;
+   }
+
mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
mmc->rca = 0;
 
@@ -886,6 +937,7 @@ static int sd_change_freq(struct mmc *mmc)
ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
struct mmc_data data;
int timeout;
+   u8 mode;
 
mmc->card_caps = 0;
 
@@ -963,6 +1015,40 @@ retry_scr:
break;
}
 
+   mode = MMC_TIMING_HS;
+
+   if (mmc->is_uhs && mmc->version >= SD_VERSION_3) {
+   if (!(mmc_host_uhs(mmc)))
+   return 0;
+
+   if (__be32_to_cpu(switch_status[3]) &
+   SD_UHS_SPEED_SDR104) {
+   mode = MMC_TIMING_UHS_SDR104;
+   mmc->card_caps |= MMC_MODE_UHS_SDR104;
+   mmc->tran_speed = 20800;
+   } else if (__be32_to_cpu(switch_status[3]) &
+  SD_UHS_SPEED_SDR50) {
+   mode = MMC_TIMING_UHS_SDR50;
+   mmc->card_caps |= MMC_MODE_UHS_SDR50;
+   mmc->tran_speed = 1;
+   

[U-Boot] [UBOOT v2 05/15] mmc: sdhci: Add support for platform specific delay

2017-01-30 Thread Siva Durga Prasad Paladugu
Add support for any platform/board specific delays
requirement while setting clocks. Some boards needs
to program tapdelay for setting certain high frequencies
and this patch adds hook for supporting the same.

Signed-off-by: Siva Durga Prasad Paladugu 
---
Changes from v1:
- None
---
 drivers/mmc/sdhci.c | 3 +++
 include/sdhci.h | 1 +
 2 files changed, 4 insertions(+)

diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index a24cc15..bbb6302 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -405,6 +405,9 @@ static int sdhci_set_clock(struct mmc *mmc, unsigned int 
clock)
if (clock == 0)
return 0;
 
+   if (mmc->is_uhs && host->ops->set_delay)
+   host->ops->set_delay(host, mmc->uhsmode);
+
if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
/*
 * Check if the Host Controller supports Programmable Clock
diff --git a/include/sdhci.h b/include/sdhci.h
index dbe3836..a0449d9 100644
--- a/include/sdhci.h
+++ b/include/sdhci.h
@@ -251,6 +251,7 @@ struct sdhci_ops {
void(*set_ios_post)(struct sdhci_host *host);
void(*set_clock)(struct sdhci_host *host, u32 div);
int (*platform_execute_tuning)(struct mmc *host, u8 opcode);
+   void(*set_delay)(struct sdhci_host *host, u8 uhsmode);
 };
 
 struct sdhci_host {
-- 
2.7.4

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[U-Boot] [UBOOT v2 10/15] mmc: sdhci: Add quirk for 1.8v switching not supported

2017-01-30 Thread Siva Durga Prasad Paladugu
Add quirk if voltage switching to 1.8v is broken, in this
case no UHS modes were supported

Signed-off-by: Siva Durga Prasad Paladugu 
---
Changes from v1:
- None
---
 drivers/mmc/sdhci.c | 3 ++-
 include/sdhci.h | 1 +
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index bbb6302..c5538ab 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -753,7 +753,8 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct 
sdhci_host *host,
SDHCI_CLOCK_MUL_SHIFT;
}
 
-   if (!(cfg->voltages & MMC_VDD_165_195))
+   if (!(cfg->voltages & MMC_VDD_165_195) ||
+   (host->quirks & SDHCI_QUIRK_NO_1_8_V))
caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
SDHCI_SUPPORT_DDR50);
 
diff --git a/include/sdhci.h b/include/sdhci.h
index 2317eac..37b23ad 100644
--- a/include/sdhci.h
+++ b/include/sdhci.h
@@ -228,6 +228,7 @@
 #define SDHCI_QUIRK_BROKEN_VOLTAGE (1 << 4)
 #define SDHCI_QUIRK_WAIT_SEND_CMD  (1 << 6)
 #define SDHCI_QUIRK_USE_WIDE8  (1 << 8)
+#define SDHCI_QUIRK_NO_1_8_V   (1 << 9)
 
 /* to make gcc happy */
 struct sdhci_host;
-- 
2.7.4

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[U-Boot] [UBOOT v2 06/15] mmc: sdhci: Make sdhci_ops of host as modifiable

2017-01-30 Thread Siva Durga Prasad Paladugu
Make sdhci_ops of host modifiable as ops may contain
platform specific funtion pointers which may need
to be defined for some platforms(example: platform specific
tuning and delays)

Signed-off-by: Siva Durga Prasad Paladugu 
---
Changes from v1:
- None
---
 include/sdhci.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/sdhci.h b/include/sdhci.h
index a0449d9..2317eac 100644
--- a/include/sdhci.h
+++ b/include/sdhci.h
@@ -264,7 +264,7 @@ struct sdhci_host {
unsigned int clk_mul;   /* Clock Multiplier value */
unsigned int clock;
struct mmc *mmc;
-   const struct sdhci_ops *ops;
+   struct sdhci_ops *ops;
int index;
 
int bus_width;
-- 
2.7.4

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[U-Boot] [UBOOT v2 08/15] mmc: sdhci: zynq: Define private structure arasan_sdhci_priv

2017-01-30 Thread Siva Durga Prasad Paladugu
Deine private structure arasan_sdhci_priv instead of sdhci_host
as private. This allows us in adding more private data  as required
for usage in driver.

Signed-off-by: Siva Durga Prasad Paladugu 
---
Changes from v1:
- None
---
 drivers/mmc/zynq_sdhci.c | 19 +++
 1 file changed, 15 insertions(+), 4 deletions(-)

diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index 69efa38..f98089e 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -22,13 +22,20 @@ struct arasan_sdhci_plat {
struct mmc mmc;
 };
 
+struct arasan_sdhci_priv {
+   struct sdhci_host *host;
+};
+
 static int arasan_sdhci_probe(struct udevice *dev)
 {
struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
-   struct sdhci_host *host = dev_get_priv(dev);
+   struct arasan_sdhci_priv *priv = dev_get_priv(dev);
+   struct sdhci_host *host;
int ret;
 
+   host = priv->host;
+
host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
   SDHCI_QUIRK_BROKEN_R1B;
 
@@ -52,10 +59,14 @@ static int arasan_sdhci_probe(struct udevice *dev)
 
 static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
 {
-   struct sdhci_host *host = dev_get_priv(dev);
+   struct arasan_sdhci_priv *priv = dev_get_priv(dev);
+
+   priv->host = calloc(1, sizeof(struct sdhci_host));
+   if (priv->host == NULL)
+   return -1;
 
-   host->name = dev->name;
-   host->ioaddr = (void *)dev_get_addr(dev);
+   priv->host->name = dev->name;
+   priv->host->ioaddr = (void *)dev_get_addr(dev);
 
return 0;
 }
-- 
2.7.4

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[U-Boot] [UBOOT v2 12/15] mmc: sdhci: Add support for eMMC HS200 mode

2017-01-30 Thread Siva Durga Prasad Paladugu
Add support for eMMC HS200 mode by reading
card type from ext_csd and then by switching to
HS200 timing mode.

Signed-off-by: Siva Durga Prasad Paladugu 
---
Changes from v1:
- Split the patch with only mmc changes
---
 drivers/mmc/mmc.c | 24 ++--
 include/mmc.h |  7 +++
 2 files changed, 25 insertions(+), 6 deletions(-)

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 0f0bfc8..02c0408 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -619,9 +619,16 @@ static int mmc_change_freq(struct mmc *mmc)
if (err)
return err;
 
-   cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf;
+   cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0x3f;
 
-   err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1);
+   if (cardtype & EXT_CSD_CARD_TYPE_HS200)
+   err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
+EXT_CSD_HS_TIMING,
+EXT_CSD_HS_TIMING_HS200);
+   else
+   err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
+EXT_CSD_HS_TIMING,
+EXT_CSD_HS_TIMING_HIGH_SPEED);
 
if (err)
return err;
@@ -636,8 +643,10 @@ static int mmc_change_freq(struct mmc *mmc)
if (!ext_csd[EXT_CSD_HS_TIMING])
return 0;
 
-   /* High Speed is set, there are two types: 52MHz and 26MHz */
-   if (cardtype & EXT_CSD_CARD_TYPE_52) {
+   /* High Speed is set, there are three types: 200MHZ, 52MHz and 26MHz */
+   if (cardtype & EXT_CSD_CARD_TYPE_HS200) {
+   mmc->card_caps |= MMC_MODE_HS200;
+   } else if (cardtype & EXT_CSD_CARD_TYPE_52) {
if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
mmc->card_caps |= MMC_MODE_DDR_52MHz;
mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
@@ -1659,7 +1668,9 @@ static int mmc_startup(struct mmc *mmc)
if (err)
return err;
 
-   if (mmc->card_caps & MMC_MODE_HS) {
+   if (mmc->card_caps & MMC_MODE_HS200) {
+   mmc->tran_speed = 2;
+   } else if (mmc->card_caps & MMC_MODE_HS) {
if (mmc->card_caps & MMC_MODE_HS_52MHz)
mmc->tran_speed = 5200;
else
@@ -1670,7 +1681,8 @@ static int mmc_startup(struct mmc *mmc)
mmc_set_clock(mmc, mmc->tran_speed);
 
if ((mmc->card_caps & (MMC_MODE_UHS_SDR50 |
-  MMC_MODE_UHS_SDR104)) &&
+  MMC_MODE_UHS_SDR104 |
+  MMC_MODE_HS200)) &&
(mmc->cfg->host_caps & MMC_MODE_NEEDS_TUNING)) {
err = mmc_execute_tuning(mmc);
if (err)
diff --git a/include/mmc.h b/include/mmc.h
index 56395ee..90e1dcc 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -223,6 +223,13 @@
 #define EXT_CSD_CARD_TYPE_DDR_1_2V (1 << 3)
 #define EXT_CSD_CARD_TYPE_DDR_52   (EXT_CSD_CARD_TYPE_DDR_1_8V \
| EXT_CSD_CARD_TYPE_DDR_1_2V)
+#define EXT_CSD_CARD_TYPE_HS200_1_8V   (1 << 4)
+#define EXT_CSD_CARD_TYPE_HS200_1_2V   (1 << 5)
+#define EXT_CSD_CARD_TYPE_HS200(EXT_CSD_CARD_TYPE_HS200_1_8V \
+   | EXT_CSD_CARD_TYPE_HS200_1_2V)
+
+#define EXT_CSD_HS_TIMING_HIGH_SPEED   1
+#define EXT_CSD_HS_TIMING_HS2002
 
 #define EXT_CSD_BUS_WIDTH_10   /* Card is in 1 bit mode */
 #define EXT_CSD_BUS_WIDTH_41   /* Card is in 4 bit mode */
-- 
2.7.4

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[U-Boot] [UBOOT v2 11/15] mmc: zynq_sdhci: Update quirk if 1.8v switching not supported

2017-01-30 Thread Siva Durga Prasad Paladugu
Update quirk if 1.8 voltage switching is not supported
on boards by reading the property "no-1-8-v" from device
tree.

Signed-off-by: Siva Durga Prasad Paladugu 
---
Changes from v1:
- None
---
 drivers/mmc/zynq_sdhci.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index 7c42a78..4875a4e 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -33,6 +33,7 @@ struct arasan_sdhci_priv {
struct sdhci_host *host;
u8 deviceid;
u8 bank;
+   u8 no_1p8;
 };
 
 #if defined(CONFIG_ARCH_ZYNQMP)
@@ -175,8 +176,12 @@ static int arasan_sdhci_probe(struct udevice *dev)
 
host->max_clk = CONFIG_ZYNQ_SDHCI_MAX_FREQ;
 
+   if (priv->no_1p8)
+   host->quirks |= SDHCI_QUIRK_NO_1_8_V;
+
ret = sdhci_setup_cfg(&plat->cfg, host, 0,
  CONFIG_ZYNQ_SDHCI_MIN_FREQ);
+
host->mmc = &plat->mmc;
if (ret)
return ret;
@@ -207,6 +212,10 @@ static int arasan_sdhci_ofdata_to_platdata(struct udevice 
*dev)
"xlnx,device_id", -1);
priv->bank = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
"xlnx,mio_bank", -1);
+   if (fdt_get_property(gd->fdt_blob, dev->of_offset, "no-1-8-v", NULL))
+   priv->no_1p8 = 1;
+   else
+   priv->no_1p8 = 0;
 
return 0;
 }
-- 
2.7.4

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[U-Boot] [UBOOT v2 07/15] zynqmp: Define routines for mmio write and read

2017-01-30 Thread Siva Durga Prasad Paladugu
Define routines of mmio write and read functionalities
for zynqmp platform.

Signed-off-by: Siva Durga Prasad Paladugu 
---
Changes from v1:
- None
---
 arch/arm/cpu/armv8/zynqmp/cpu.c  | 51 
 arch/arm/include/asm/arch-zynqmp/sys_proto.h |  3 ++
 2 files changed, 54 insertions(+)

diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c
index b0f1295..54afa9e 100644
--- a/arch/arm/cpu/armv8/zynqmp/cpu.c
+++ b/arch/arm/cpu/armv8/zynqmp/cpu.c
@@ -104,3 +104,54 @@ unsigned int zynqmp_get_silicon_version(void)
 
return ZYNQMP_CSU_VERSION_SILICON;
 }
+
+#define PAYLOAD_ARG_CNT5
+#define ZYNQMP_MMIO_READ   0xC214
+#define ZYNQMP_MMIO_WRITE  0xC213
+
+static int invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3,
+   u32 *ret_payload)
+{
+   /*
+* Added SIP service call Function Identifier
+* Make sure to stay in x0 register
+*/
+   struct pt_regs regs;
+
+   regs.regs[0] = pm_api_id;
+   regs.regs[1] = ((u64)arg1 << 32) | arg0;
+   regs.regs[2] = ((u64)arg3 << 32) | arg2;
+
+   smc_call(®s);
+
+   if (ret_payload != NULL) {
+   ret_payload[0] = (u32)regs.regs[0];
+   ret_payload[1] = upper_32_bits(regs.regs[0]);
+   ret_payload[2] = (u32)regs.regs[1];
+   ret_payload[3] = upper_32_bits(regs.regs[1]);
+   ret_payload[4] = (u32)regs.regs[2];
+   }
+
+   return regs.regs[0];
+}
+
+int zynqmp_mmio_write(const u32 address,
+ const u32 mask,
+ const u32 value)
+{
+   return invoke_smc(ZYNQMP_MMIO_WRITE, address, mask, value, 0, NULL);
+}
+
+int zynqmp_mmio_read(const u32 address, u32 *value)
+{
+   u32 ret_payload[PAYLOAD_ARG_CNT];
+   u32 ret;
+
+   if (!value)
+   return -EINVAL;
+
+   ret = invoke_smc(ZYNQMP_MMIO_READ, address, 0, 0, 0, ret_payload);
+   *value = ret_payload[1];
+
+   return ret;
+}
diff --git a/arch/arm/include/asm/arch-zynqmp/sys_proto.h 
b/arch/arm/include/asm/arch-zynqmp/sys_proto.h
index 8c54fce..446e89c 100644
--- a/arch/arm/include/asm/arch-zynqmp/sys_proto.h
+++ b/arch/arm/include/asm/arch-zynqmp/sys_proto.h
@@ -23,4 +23,7 @@ void psu_init(void);
 
 void handoff_setup(void);
 
+int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);
+int zynqmp_mmio_read(const u32 address, u32 *value);
+
 #endif /* _ASM_ARCH_SYS_PROTO_H */
-- 
2.7.4

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[U-Boot] [UBOOT v2 13/15] mmc: sdhci: Update execute tuning and set clock for HS200

2017-01-30 Thread Siva Durga Prasad Paladugu
Update execute tuning and set clock to support for
HS200 mode.

Signed-off-by: Siva Durga Prasad Paladugu 
---
Changes from v1:
- Split the patch with only sdhci related changes
---
 drivers/mmc/sdhci.c | 18 +-
 include/mmc.h   |  1 +
 2 files changed, 14 insertions(+), 5 deletions(-)

diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index c5538ab..e8d76ba 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -157,7 +157,8 @@ static int sdhci_send_command(struct mmc *mmc, struct 
mmc_cmd *cmd,
/* We shouldn't wait for data inihibit for stop commands, even
   though they might use busy signaling */
if ((cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) ||
-   (cmd->cmdidx ==  MMC_CMD_SEND_TUNING_BLOCK))
+   (cmd->cmdidx ==  MMC_CMD_SEND_TUNING_BLOCK) ||
+   (cmd->cmdidx ==  MMC_CMD_SEND_TUNING_BLOCK_HS200))
mask &= ~SDHCI_DATA_INHIBIT;
 
while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
@@ -179,7 +180,8 @@ static int sdhci_send_command(struct mmc *mmc, struct 
mmc_cmd *cmd,
mask = SDHCI_INT_RESPONSE;
 
/* only buffer read ready interrupt whil tuning */
-   if (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
+   if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
+   (cmd->cmdidx ==  MMC_CMD_SEND_TUNING_BLOCK_HS200))
mask = SDHCI_INT_DATA_AVAIL;
 
if (!(cmd->resp_type & MMC_RSP_PRESENT))
@@ -197,7 +199,8 @@ static int sdhci_send_command(struct mmc *mmc, struct 
mmc_cmd *cmd,
flags |= SDHCI_CMD_CRC;
if (cmd->resp_type & MMC_RSP_OPCODE)
flags |= SDHCI_CMD_INDEX;
-   if (data || (cmd->cmdidx ==  MMC_CMD_SEND_TUNING_BLOCK))
+   if (data || (cmd->cmdidx ==  MMC_CMD_SEND_TUNING_BLOCK) ||
+   (cmd->cmdidx ==  MMC_CMD_SEND_TUNING_BLOCK_HS200))
flags |= SDHCI_CMD_DATA;
 
/* Set Transfer mode regarding to data flag */
@@ -405,8 +408,13 @@ static int sdhci_set_clock(struct mmc *mmc, unsigned int 
clock)
if (clock == 0)
return 0;
 
-   if (mmc->is_uhs && host->ops->set_delay)
-   host->ops->set_delay(host, mmc->uhsmode);
+   if (((mmc->card_caps & MMC_MODE_HS200) || mmc->is_uhs) &&
+   host->ops->set_delay) {
+   if (mmc->is_uhs)
+   host->ops->set_delay(host, mmc->uhsmode);
+   else
+   host->ops->set_delay(host, MMC_TIMING_HS200);
+   }
 
if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
/*
diff --git a/include/mmc.h b/include/mmc.h
index 90e1dcc..e0b5510 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -300,6 +300,7 @@
 #define MMC_TIMING_UHS_SDR50   2
 #define MMC_TIMING_UHS_SDR104  3
 #define MMC_TIMING_UHS_DDR50   4
+#define MMC_TIMING_HS200   5
 #define MMC_TIMING_HS  1
 
 /* Driver model support */
-- 
2.7.4

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[U-Boot] [PATCH 1/7] mmc: move CONFIG_GENERIC_MMC to Kconfig

2017-01-30 Thread Masahiro Yamada
Now, CONFIG_GENERIC_MMC seems equivalent to CONFIG_MMC.

Let's create an entry for "config GENERIC_MMC" with "default MMC",
then convert all macro defines in headers to Kconfig.  Almost all
of the defines will go away.

I see only two exceptions:
  configs/blanche_defconfig
  configs/sandbox_noblk_defconfig

They define CONFIG_GENERIC_MMC, but not CONFIG_MMC.  Something
might be wrong with these two boards, so should be checked later.

Anyway, this is the output of the moveconfig tool.

This commit was created as follows:

[1] create a config entry in drivers/mmc/Kconfig

[2] tools/moveconfig.py -r HEAD GENERIC_MMC

[3] manual clean-up of garbage comments in doc/README.* and
include/configs/*.h

Signed-off-by: Masahiro Yamada 
Reviewed-by: Tom Rini 
---

Changes in v2:
  - Rebase on aac477e

 README| 3 ---
 configs/blanche_defconfig | 3 ++-
 configs/sandbox_noblk_defconfig   | 1 +
 doc/README.atmel_mci  | 2 --
 doc/README.socfpga| 3 ---
 drivers/mmc/Kconfig   | 4 
 include/configs/BSC9132QDS.h  | 1 -
 include/configs/MPC8308RDB.h  | 2 --
 include/configs/MPC837XEMDS.h | 1 -
 include/configs/MPC837XERDB.h | 1 -
 include/configs/MPC8536DS.h   | 1 -
 include/configs/MPC8569MDS.h  | 1 -
 include/configs/P1010RDB.h| 1 -
 include/configs/P1022DS.h | 1 -
 include/configs/P2041RDB.h| 1 -
 include/configs/T102xQDS.h| 1 -
 include/configs/T102xRDB.h| 1 -
 include/configs/T1040QDS.h| 1 -
 include/configs/T104xRDB.h| 1 -
 include/configs/T208xQDS.h| 1 -
 include/configs/T208xRDB.h| 1 -
 include/configs/T4240QDS.h| 1 -
 include/configs/T4240RDB.h| 1 -
 include/configs/UCP1020.h | 1 -
 include/configs/adp-ag101p.h  | 1 -
 include/configs/advantech_dms-ba16.h  | 1 -
 include/configs/alt.h | 2 --
 include/configs/am3517_crane.h| 1 -
 include/configs/am3517_evm.h  | 3 ---
 include/configs/apalis_imx6.h | 1 -
 include/configs/apalis_t30.h  | 3 ---
 include/configs/apf27.h   | 1 -
 include/configs/at91sam9260ek.h   | 1 -
 include/configs/at91sam9263ek.h   | 1 -
 include/configs/at91sam9m10g45ek.h| 1 -
 include/configs/at91sam9n12ek.h   | 1 -
 include/configs/at91sam9rlek.h| 1 -
 include/configs/at91sam9x5ek.h| 1 -
 include/configs/atngw100.h| 1 -
 include/configs/atngw100mkii.h| 1 -
 include/configs/atstk1002.h   | 1 -
 include/configs/axs10x.h  | 5 -
 include/configs/bayleybay.h   | 2 --
 include/configs/bcm23550_w1d.h| 2 --
 include/configs/bcm28155_ap.h | 2 --
 include/configs/beaver.h  | 3 ---
 include/configs/bf518f-ezbrd.h| 1 -
 include/configs/bf527-ad7160-eval.h   | 1 -
 include/configs/bf537-stamp.h | 3 ---
 include/configs/bf548-ezkit.h | 1 -
 include/configs/bf609-ezkit.h | 1 -
 include/configs/blanche.h | 2 --
 include/configs/brppt1.h  | 1 -
 include/configs/brxre1.h  | 1 -
 include/configs/cardhu.h  | 3 ---
 include/configs/cei-tk1-som.h | 3 ---
 include/configs/clearfog.h| 1 -
 include/configs/cm-bf537e.h   | 1 -
 include/configs/cm-bf537u.h   | 1 -
 include/configs/cm_t35.h  | 2 --
 include/configs/cm_t3517.h| 2 --
 include/configs/colibri_imx6.h| 1 -
 include/configs/colibri_t20.h | 3 ---
 include/configs/colibri_t30.h | 3 ---
 include/configs/colibri_vf.h  | 2 --
 include/configs/conga-qeval20-qa3-e3845.h | 2 --
 include/configs/controlcenterd.h  | 2 --
 include/configs/corenet_ds.h  | 1 -
 include/configs/crownbay.h| 2 --
 include/configs/cyrus.h   | 1 -
 include/configs/da850evm.h| 5 -
 include/configs/dalmore.h | 3 ---
 include/configs/db-88f6820-gp.h   | 1 -
 include/configs/dfi-bt700.h   | 2 --
 include/configs/dragonboard410c.h | 3 ---
 include/configs/e2220-1170.h  | 3 ---
 include/configs/ethernut5.h   | 1 -
 include/configs/exynos-common.h   | 1 -
 include/configs/galileo.h | 3 ---
 include/configs/ge_bx50v3.h   | 1 -
 include/configs/gose.h| 1 -
 include/configs/harmony.h | 3 ---
 include/configs/hikey.h   | 1 -
 include/configs/hrcon.h   | 2 --
 include/configs/i

[U-Boot] [PATCH 5/7] mmc: msm: rename CONFIG_MSM_SDHCI to CONFIG_MMC_SDHCI_MSM

2017-01-30 Thread Masahiro Yamada
Make the naming scheme consistent; all SDHCI-base drivers prefixed
with CONFIG_MMC_SDHCI_.

Signed-off-by: Masahiro Yamada 
---

Changes in v2: None

 configs/dragonboard410c_defconfig |  2 +-
 drivers/mmc/Kconfig   | 20 ++--
 drivers/mmc/Makefile  |  2 +-
 3 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/configs/dragonboard410c_defconfig 
b/configs/dragonboard410c_defconfig
index bf1a755..8f206e2 100644
--- a/configs/dragonboard410c_defconfig
+++ b/configs/dragonboard410c_defconfig
@@ -21,7 +21,7 @@ CONFIG_PM8916_GPIO=y
 CONFIG_LED=y
 CONFIG_LED_GPIO=y
 CONFIG_DM_MMC=y
-CONFIG_MSM_SDHCI=y
+CONFIG_MMC_SDHCI_MSM=y
 CONFIG_MMC_SDHCI=y
 CONFIG_DM_PMIC=y
 CONFIG_PMIC_PM8916=y
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 6f51354..c9a4ca9 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -51,16 +51,6 @@ config SPL_MMC_TINY
  operations too, which can remove the need for malloc support in SPL
  and thus further reduce footprint.
 
-config MSM_SDHCI
-   bool "Qualcomm SDHCI controller"
-   depends on DM_MMC && BLK && DM_MMC_OPS
-   depends on MMC_SDHCI
-   help
- Enables support for SDHCI 2.0 controller present on some Qualcomm
-  Snapdragon devices. This device is compatible with eMMC v4.5 and
-  SD 3.0 specifications. Both SD and eMMC devices are supported.
- Card-detect gpios are not supported.
-
 config ATMEL_SDHCI
bool "Atmel SDHCI controller support"
depends on DM_MMC && BLK && DM_MMC_OPS && ARCH_AT91
@@ -243,6 +233,16 @@ config MMC_SDHCI_KONA
 
  If you have a controller with this interface, say Y here.
 
+config MMC_SDHCI_MSM
+   bool "Qualcomm SDHCI controller"
+   depends on BLK && DM_MMC_OPS
+   depends on MMC_SDHCI
+   help
+ Enables support for SDHCI 2.0 controller present on some Qualcomm
+  Snapdragon devices. This device is compatible with eMMC v4.5 and
+  SD 3.0 specifications. Both SD and eMMC devices are supported.
+ Card-detect gpios are not supported.
+
 config MMC_SDHCI_MV
bool "SDHCI support on Marvell platform"
depends on ARCH_MVEBU
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 379b08c..7693644 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -51,13 +51,13 @@ else
 obj-$(CONFIG_GENERIC_MMC) += mmc_write.o
 endif
 obj-$(CONFIG_PIC32_SDHCI) += pic32_sdhci.o
-obj-$(CONFIG_MSM_SDHCI) += msm_sdhci.o
 
 # SDHCI
 obj-$(CONFIG_MMC_SDHCI)+= sdhci.o
 obj-$(CONFIG_MMC_SDHCI_BCM2835)+= bcm2835_sdhci.o
 obj-$(CONFIG_MMC_SDHCI_CADENCE)+= sdhci-cadence.o
 obj-$(CONFIG_MMC_SDHCI_KONA)   += kona_sdhci.o
+obj-$(CONFIG_MMC_SDHCI_MSM)+= msm_sdhci.o
 obj-$(CONFIG_MMC_SDHCI_MV) += mv_sdhci.o
 obj-$(CONFIG_MMC_SDHCI_ROCKCHIP)   += rockchip_sdhci.o
 obj-$(CONFIG_MMC_SDHCI_S5P)+= s5p_sdhci.o
-- 
2.7.4

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[U-Boot] [PATCH 6/7] mmc: pic32: rename CONFIG_PIC32_SDHCI to CONFIG_MMC_SDHCI_PIC32

2017-01-30 Thread Masahiro Yamada
Make the naming scheme consistent; all SDHCI-base drivers prefixed
with CONFIG_MMC_SDHCI_.

Signed-off-by: Masahiro Yamada 
---

Changes in v2: None

 configs/pic32mzdask_defconfig |  2 +-
 drivers/mmc/Kconfig   | 14 +++---
 drivers/mmc/Makefile  |  2 +-
 3 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/configs/pic32mzdask_defconfig b/configs/pic32mzdask_defconfig
index 90a0d32..85c0d2a 100644
--- a/configs/pic32mzdask_defconfig
+++ b/configs/pic32mzdask_defconfig
@@ -29,7 +29,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_CLK=y
 CONFIG_DM_GPIO=y
 CONFIG_DM_MMC=y
-CONFIG_PIC32_SDHCI=y
+CONFIG_MMC_SDHCI_PIC32=y
 CONFIG_MMC_SDHCI=y
 CONFIG_DM_ETH=y
 CONFIG_PIC32_ETH=y
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index c9a4ca9..520e7ea 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -148,13 +148,6 @@ config SH_SDHI
help
  Support for the on-chip SDHI host controller on SuperH/Renesas ARM 
SoCs platform
 
-config PIC32_SDHCI
-   bool "Microchip PIC32 on-chip SDHCI support"
-   depends on DM_MMC && MACH_PIC32
-   depends on MMC_SDHCI
-   help
- Support for Microchip PIC32 SDHCI controller.
-
 config MMC_UNIPHIER
bool "UniPhier SD/MMC Host Controller support"
depends on ARCH_UNIPHIER
@@ -255,6 +248,13 @@ config MMC_SDHCI_MV
 
  If unsure, say N.
 
+config MMC_SDHCI_PIC32
+   bool "Microchip PIC32 on-chip SDHCI support"
+   depends on DM_MMC && MACH_PIC32
+   depends on MMC_SDHCI
+   help
+ Support for Microchip PIC32 SDHCI controller.
+
 config MMC_SDHCI_ROCKCHIP
bool "Arasan SDHCI controller for Rockchip support"
depends on ARCH_ROCKCHIP
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 7693644..e63f439 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -50,7 +50,6 @@ obj-$(CONFIG_SPL_SAVEENV) += mmc_write.o
 else
 obj-$(CONFIG_GENERIC_MMC) += mmc_write.o
 endif
-obj-$(CONFIG_PIC32_SDHCI) += pic32_sdhci.o
 
 # SDHCI
 obj-$(CONFIG_MMC_SDHCI)+= sdhci.o
@@ -59,6 +58,7 @@ obj-$(CONFIG_MMC_SDHCI_CADENCE)   += 
sdhci-cadence.o
 obj-$(CONFIG_MMC_SDHCI_KONA)   += kona_sdhci.o
 obj-$(CONFIG_MMC_SDHCI_MSM)+= msm_sdhci.o
 obj-$(CONFIG_MMC_SDHCI_MV) += mv_sdhci.o
+obj-$(CONFIG_MMC_SDHCI_PIC32)  += pic32_sdhci.o
 obj-$(CONFIG_MMC_SDHCI_ROCKCHIP)   += rockchip_sdhci.o
 obj-$(CONFIG_MMC_SDHCI_S5P)+= s5p_sdhci.o
 obj-$(CONFIG_MMC_SDHCI_SPEAR)  += spear_sdhci.o
-- 
2.7.4

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[U-Boot] [PATCH 3/7] mmc: zynq: rename CONFIG_ZYNQ_SDHCI to CONFIG_MMC_SDHCI_ZYNQ

2017-01-30 Thread Masahiro Yamada
Make the naming scheme consistent; all SDHCI-base drivers prefixed
with CONFIG_MMC_SDHCI_.

While we are here, add "depends on ARCH_ZYNQ || ARCH_ZYNQMP".

Signed-off-by: Masahiro Yamada 
---

Changes in v2: None

 arch/arm/mach-zynq/Kconfig   |  2 +-
 configs/topic_miami_defconfig|  2 +-
 configs/topic_miamiplus_defconfig|  2 +-
 configs/xilinx_zynqmp_ep_defconfig   |  2 +-
 configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig |  2 +-
 configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig |  2 +-
 configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig |  2 +-
 configs/xilinx_zynqmp_zcu102_defconfig   |  2 +-
 configs/xilinx_zynqmp_zcu102_revB_defconfig  |  2 +-
 configs/zynq_microzed_defconfig  |  2 +-
 configs/zynq_picozed_defconfig   |  2 +-
 configs/zynq_zc702_defconfig |  2 +-
 configs/zynq_zc706_defconfig |  2 +-
 configs/zynq_zc770_xm010_defconfig   |  2 +-
 configs/zynq_zed_defconfig   |  2 +-
 configs/zynq_zybo_defconfig  |  2 +-
 drivers/mmc/Kconfig  | 15 ---
 drivers/mmc/Makefile |  2 +-
 include/configs/xilinx_zynqmp.h  | 10 +-
 include/configs/zynq-common.h|  8 
 20 files changed, 34 insertions(+), 33 deletions(-)

diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
index c465918..2529c9f 100644
--- a/arch/arm/mach-zynq/Kconfig
+++ b/arch/arm/mach-zynq/Kconfig
@@ -13,7 +13,7 @@ config SPL_LIBGENERIC_SUPPORT
default y
 
 config SPL_MMC_SUPPORT
-   default y if ZYNQ_SDHCI
+   default y if MMC_SDHCI_ZYNQ
 
 config SPL_SERIAL_SUPPORT
default y
diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig
index 3239d99..a822ee1 100644
--- a/configs/topic_miami_defconfig
+++ b/configs/topic_miami_defconfig
@@ -26,7 +26,7 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_EMBED=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_ZYNQ_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_MMC_SDHCI=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
diff --git a/configs/topic_miamiplus_defconfig 
b/configs/topic_miamiplus_defconfig
index 906220c..9b4e82d 100644
--- a/configs/topic_miamiplus_defconfig
+++ b/configs/topic_miamiplus_defconfig
@@ -26,7 +26,7 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_EMBED=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_ZYNQ_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_MMC_SDHCI=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
diff --git a/configs/xilinx_zynqmp_ep_defconfig 
b/configs/xilinx_zynqmp_ep_defconfig
index 1d12440..49c0786 100644
--- a/configs/xilinx_zynqmp_ep_defconfig
+++ b/configs/xilinx_zynqmp_ep_defconfig
@@ -53,7 +53,7 @@ CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_CADENCE=y
 CONFIG_DM_MMC=y
-CONFIG_ZYNQ_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_MMC_SDHCI=y
 CONFIG_NAND_ARASAN=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig 
b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
index 4d90fc3..a3585d0 100644
--- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
@@ -43,7 +43,7 @@ CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_CADENCE=y
 CONFIG_DM_MMC=y
-CONFIG_ZYNQ_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_MMC_SDHCI=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig 
b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
index 817d066..a4c73f8 100644
--- a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
@@ -35,7 +35,7 @@ CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_CADENCE=y
 CONFIG_DM_MMC=y
-CONFIG_ZYNQ_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_MMC_SDHCI=y
 CONFIG_DM_ETH=y
 CONFIG_ZYNQ_GEM=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig 
b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
index 9d15846..f981b21 100644
--- a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
@@ -35,7 +35,7 @@ CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_CADENCE=y
 CONFIG_DM_MMC=y
-CONFIG_ZYNQ_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_MMC_SDHCI=y
 CONFIG_DM_ETH=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_zcu102_defconfig 
b/configs/xilinx_zynqmp_zcu102_defconfig
index f6bbf83..7b65fe0 100644
--- a/configs/xilinx_zynqmp_zcu102_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_defconfig
@@ -43,7 +43,7 @@ CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_ZYNQMPPL=y
 CONFIG_DM_GPIO=y
 CONFIG_DM_MMC=y
-CONFIG_ZYNQ_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_MMC_SDHCI=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig 
b/configs/xilinx_zynqmp_zcu102_revB_defconfig
index 43ad2d9..4bed589 100644
--- a/configs/xilinx_zynqmp_zcu102_r

[U-Boot] [PATCH 7/7] mmc: atmel: rename CONFIG_ATMEL_SDHCI to CONFIG_MMC_SDHCI_ATMEL

2017-01-30 Thread Masahiro Yamada
Make the naming scheme consistent; all SDHCI-base drivers prefixed
with CONFIG_MMC_SDHCI_.

While we are here, add "depends on ARCH_AT91".

Signed-off-by: Masahiro Yamada 
---

Changes in v2: None

 configs/sama5d2_xplained_mmc_defconfig  |  2 +-
 configs/sama5d2_xplained_spiflash_defconfig |  2 +-
 drivers/mmc/Kconfig | 23 ---
 drivers/mmc/Makefile|  2 +-
 4 files changed, 15 insertions(+), 14 deletions(-)

diff --git a/configs/sama5d2_xplained_mmc_defconfig 
b/configs/sama5d2_xplained_mmc_defconfig
index a6daef4..000acee 100644
--- a/configs/sama5d2_xplained_mmc_defconfig
+++ b/configs/sama5d2_xplained_mmc_defconfig
@@ -43,7 +43,7 @@ CONFIG_ATMEL_PIO4=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_AT91=y
 CONFIG_DM_MMC=y
-CONFIG_ATMEL_SDHCI=y
+CONFIG_MMC_SDHCI_ATMEL=y
 CONFIG_MMC_SDHCI=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/sama5d2_xplained_spiflash_defconfig 
b/configs/sama5d2_xplained_spiflash_defconfig
index 41ab772..0838e41 100644
--- a/configs/sama5d2_xplained_spiflash_defconfig
+++ b/configs/sama5d2_xplained_spiflash_defconfig
@@ -42,7 +42,7 @@ CONFIG_ATMEL_PIO4=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_AT91=y
 CONFIG_DM_MMC=y
-CONFIG_ATMEL_SDHCI=y
+CONFIG_MMC_SDHCI_ATMEL=y
 CONFIG_MMC_SDHCI=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 520e7ea..0c07781 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -51,17 +51,6 @@ config SPL_MMC_TINY
  operations too, which can remove the need for malloc support in SPL
  and thus further reduce footprint.
 
-config ATMEL_SDHCI
-   bool "Atmel SDHCI controller support"
-   depends on DM_MMC && BLK && DM_MMC_OPS && ARCH_AT91
-   depends on MMC_SDHCI
-   help
- This enables support for the Atmel SDHCI controller, which supports
- the embedded MultiMedia Card (e.MMC) Specification V4.51, the SD
- Memory Card Specification V3.0, and the SDIO V3.0 specification.
- It is compliant with the SD Host Controller Standard V3.0
- specification.
-
 config MMC_DAVINCI
bool "TI DAVINCI Multimedia Card Interface support"
depends on ARCH_DAVINCI
@@ -191,6 +180,18 @@ config MMC_SDHCI_SDMA
  This enables support for the SDMA (Single Operation DMA) defined
  in the SD Host Controller Standard Specification Version 1.00 .
 
+config MMC_SDHCI_ATMEL
+   bool "Atmel SDHCI controller support"
+   depends on ARCH_AT91
+   depends on DM_MMC && BLK && DM_MMC_OPS && ARCH_AT91
+   depends on MMC_SDHCI
+   help
+ This enables support for the Atmel SDHCI controller, which supports
+ the embedded MultiMedia Card (e.MMC) Specification V4.51, the SD
+ Memory Card Specification V3.0, and the SDIO V3.0 specification.
+ It is compliant with the SD Host Controller Standard V3.0
+ specification.
+
 config MMC_SDHCI_BCM2835
tristate "SDHCI support for the BCM2835 SD/MMC Controller"
depends on ARCH_BCM283X
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index e63f439..e78bd0d 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -14,7 +14,6 @@ obj-$(CONFIG_GENERIC_MMC) += mmc_legacy.o
 endif
 
 obj-$(CONFIG_ARM_PL180_MMCI) += arm_pl180_mmci.o
-obj-$(CONFIG_ATMEL_SDHCI) += atmel_sdhci.o
 obj-$(CONFIG_BFIN_SDH) += bfin_sdh.o
 obj-$(CONFIG_MMC_DAVINCI)  += davinci_mmc.o
 
@@ -53,6 +52,7 @@ endif
 
 # SDHCI
 obj-$(CONFIG_MMC_SDHCI)+= sdhci.o
+obj-$(CONFIG_MMC_SDHCI_ATMEL)  += atmel_sdhci.o
 obj-$(CONFIG_MMC_SDHCI_BCM2835)+= bcm2835_sdhci.o
 obj-$(CONFIG_MMC_SDHCI_CADENCE)+= sdhci-cadence.o
 obj-$(CONFIG_MMC_SDHCI_KONA)   += kona_sdhci.o
-- 
2.7.4

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[U-Boot] [PATCH 2/7] mmc: sandbox: rename CONFIG, fix dependency, and use it in Makefile

2017-01-30 Thread Masahiro Yamada
[1] Rename CONFIG_SANDBOX_MMC to CONFIG_MMC_SANDBOX for consistency
I want all MMC driver options prefixed with CONFIG_MMC_.

[2] Fix dependency
Add necessary depends on to avoid compile error.
Instead "depends on MMC" is unneeded because this config entry
resides inside of "if MMC".

[3] Currently, this config symbol is not referenced at all.
Use it to enable/disable the driver in Makefile.

Signed-off-by: Masahiro Yamada 
---

Changes in v2: None

 configs/sandbox_defconfig | 2 +-
 configs/sandbox_spl_defconfig | 2 +-
 drivers/mmc/Kconfig   | 5 +++--
 drivers/mmc/Makefile  | 6 +-
 4 files changed, 6 insertions(+), 9 deletions(-)

diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 877aa94..01f6f5d 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -94,7 +94,7 @@ CONFIG_CROS_EC_SPI=y
 CONFIG_PWRSEQ=y
 CONFIG_SPL_PWRSEQ=y
 CONFIG_I2C_EEPROM=y
-CONFIG_SANDBOX_MMC=y
+CONFIG_MMC_SANDBOX=y
 CONFIG_SPI_FLASH_SANDBOX=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig
index 0569647..896b15d 100644
--- a/configs/sandbox_spl_defconfig
+++ b/configs/sandbox_spl_defconfig
@@ -104,7 +104,7 @@ CONFIG_CROS_EC_SANDBOX=y
 CONFIG_CROS_EC_SPI=y
 CONFIG_PWRSEQ=y
 CONFIG_SPL_PWRSEQ=y
-CONFIG_SANDBOX_MMC=y
+CONFIG_MMC_SANDBOX=y
 CONFIG_SPI_FLASH_SANDBOX=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index df4913b..97d245e 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -187,9 +187,10 @@ config MMC_UNIPHIER
help
  This selects support for the SD/MMC Host Controller on UniPhier SoCs.
 
-config SANDBOX_MMC
+config MMC_SANDBOX
bool "Sandbox MMC support"
-   depends on MMC && SANDBOX
+   depends on SANDBOX
+   depends on BLK && DM_MMC_OPS && OF_CONTROL
help
  This select a dummy sandbox MMC driver. At present this does nothing
  other than allow sandbox to be build with MMC support. This
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 6af7f79..2747deb 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -40,11 +40,7 @@ obj-$(CONFIG_X86) += pci_mmc.o
 obj-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o
 obj-$(CONFIG_SUPPORT_EMMC_RPMB) += rpmb.o
 obj-$(CONFIG_S3C_SDI) += s3c_sdi.o
-ifdef CONFIG_BLK
-ifdef CONFIG_GENERIC_MMC
-obj-$(CONFIG_SANDBOX) += sandbox_mmc.o
-endif
-endif
+obj-$(CONFIG_MMC_SANDBOX)  += sandbox_mmc.o
 obj-$(CONFIG_SH_MMCIF) += sh_mmcif.o
 obj-$(CONFIG_SH_SDHI) += sh_sdhi.o
 obj-$(CONFIG_ZYNQ_SDHCI) += zynq_sdhci.o
-- 
2.7.4

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[U-Boot] [PATCH 4/7] mmc: rockchip: rename CONFIG_ROCKCHIP_SDHCI to CONFIG_MMC_SDHCI_ROCKCHIP

2017-01-30 Thread Masahiro Yamada
Make the naming scheme consistent; all SDHCI-base drivers prefixed
with CONFIG_MMC_SDHCI_.

While we are here, add "depends on ARCH_ROCKCHIP".

Signed-off-by: Masahiro Yamada 
---

Changes in v2: None

 configs/evb-rk3399_defconfig |  2 +-
 drivers/mmc/Kconfig  | 15 ---
 drivers/mmc/Makefile |  2 +-
 3 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
index ca292cf..47064f9 100644
--- a/configs/evb-rk3399_defconfig
+++ b/configs/evb-rk3399_defconfig
@@ -18,7 +18,7 @@ CONFIG_CLK=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
-CONFIG_ROCKCHIP_SDHCI=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
 CONFIG_MMC_SDHCI=y
 CONFIG_PINCTRL=y
 CONFIG_ROCKCHIP_RK3399_PINCTRL=y
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 1d15cdd..6f51354 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -165,13 +165,6 @@ config PIC32_SDHCI
help
  Support for Microchip PIC32 SDHCI controller.
 
-config ROCKCHIP_SDHCI
-   bool "Arasan SDHCI controller for Rockchip support"
-   depends on DM_MMC && BLK && DM_MMC_OPS
-   depends on MMC_SDHCI
-   help
- Support for Arasan SDHCI host controller on Rockchip ARM SoCs platform
-
 config MMC_UNIPHIER
bool "UniPhier SD/MMC Host Controller support"
depends on ARCH_UNIPHIER
@@ -262,6 +255,14 @@ config MMC_SDHCI_MV
 
  If unsure, say N.
 
+config MMC_SDHCI_ROCKCHIP
+   bool "Arasan SDHCI controller for Rockchip support"
+   depends on ARCH_ROCKCHIP
+   depends on DM_MMC && BLK && DM_MMC_OPS
+   depends on MMC_SDHCI
+   help
+ Support for Arasan SDHCI host controller on Rockchip ARM SoCs platform
+
 config MMC_SDHCI_S5P
bool "SDHCI support on Samsung S5P SoC"
depends on MMC_SDHCI
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 5a497f5..379b08c 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -43,7 +43,6 @@ obj-$(CONFIG_S3C_SDI) += s3c_sdi.o
 obj-$(CONFIG_MMC_SANDBOX)  += sandbox_mmc.o
 obj-$(CONFIG_SH_MMCIF) += sh_mmcif.o
 obj-$(CONFIG_SH_SDHI) += sh_sdhi.o
-obj-$(CONFIG_ROCKCHIP_SDHCI) += rockchip_sdhci.o
 
 ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o
@@ -60,6 +59,7 @@ obj-$(CONFIG_MMC_SDHCI_BCM2835)   += 
bcm2835_sdhci.o
 obj-$(CONFIG_MMC_SDHCI_CADENCE)+= sdhci-cadence.o
 obj-$(CONFIG_MMC_SDHCI_KONA)   += kona_sdhci.o
 obj-$(CONFIG_MMC_SDHCI_MV) += mv_sdhci.o
+obj-$(CONFIG_MMC_SDHCI_ROCKCHIP)   += rockchip_sdhci.o
 obj-$(CONFIG_MMC_SDHCI_S5P)+= s5p_sdhci.o
 obj-$(CONFIG_MMC_SDHCI_SPEAR)  += spear_sdhci.o
 obj-$(CONFIG_MMC_SDHCI_TEGRA)  += tegra_mmc.o
-- 
2.7.4

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[U-Boot] [UBOOT v2 15/15] mmc: Change frequency while accessing to boot partition

2017-01-30 Thread Siva Durga Prasad Paladugu
Boot partition is not supported in HS200 mode, hence change
clock to high speed while accessing boot partition and
revert back when partition is switching to other than boot
partition

Signed-off-by: Siva Durga Prasad Paladugu 
---
Changes from v1:
- Added this in series as per review comment
---
 drivers/mmc/mmc.c | 58 +++
 include/mmc.h |  2 ++
 2 files changed, 60 insertions(+)

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 02c0408..be6003f 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -621,6 +621,9 @@ static int mmc_change_freq(struct mmc *mmc)
 
cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0x3f;
 
+   if (mmc->forcehs)
+   cardtype &= ~EXT_CSD_CARD_TYPE_HS200;
+
if (cardtype & EXT_CSD_CARD_TYPE_HS200)
err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
 EXT_CSD_HS_TIMING,
@@ -685,10 +688,65 @@ static int mmc_set_capacity(struct mmc *mmc, int part_num)
return 0;
 }
 
+static int mmc_boot_part_access_chk(struct mmc *mmc, unsigned int part_num)
+{
+   int ret;
+
+   if (((part_num & PART_ACCESS_MASK) == PART_ACCESS_BOOT0) &&
+   (mmc->card_caps == MMC_MODE_HS200)) {
+   mmc->forcehs = 1;
+   ret = mmc_change_freq(mmc);
+   if (ret)
+   return ret;
+
+   mmc->card_caps &= mmc->cfg->host_caps;
+   if (mmc->card_caps & MMC_MODE_HS) {
+   if (mmc->card_caps & MMC_MODE_HS_52MHz)
+   mmc->tran_speed = 5200;
+   else
+   mmc->tran_speed = 2600;
+   }
+   mmc_set_clock(mmc, mmc->tran_speed);
+   }
+
+   if (((part_num & PART_ACCESS_MASK) != PART_ACCESS_BOOT0) &&
+   mmc->forcehs) {
+   mmc->forcehs = 0;
+   ret = mmc_change_freq(mmc);
+   if (ret)
+   return ret;
+
+   mmc->card_caps &= mmc->cfg->host_caps;
+   if (mmc->card_caps & MMC_MODE_HS200) {
+   mmc->tran_speed = 2;
+   } else if (mmc->card_caps & MMC_MODE_HS) {
+   if (mmc->card_caps & MMC_MODE_HS_52MHz)
+   mmc->tran_speed = 5200;
+   else
+   mmc->tran_speed = 2600;
+   }
+
+   mmc_set_clock(mmc, mmc->tran_speed);
+
+   if ((mmc->card_caps &  MMC_MODE_HS200) &&
+   (mmc->cfg->host_caps & MMC_MODE_NEEDS_TUNING)) {
+   ret = mmc_execute_tuning(mmc);
+   if (ret)
+   return ret;
+   }
+   }
+
+   return 0;
+}
+
 int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
 {
int ret;
 
+   ret = mmc_boot_part_access_chk(mmc, part_num);
+   if (ret)
+   return ret;
+
ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
 (mmc->part_config & ~PART_ACCESS_MASK)
 | (part_num & PART_ACCESS_MASK));
diff --git a/include/mmc.h b/include/mmc.h
index e0b5510..6f9a41c 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -282,6 +282,7 @@
 
 #define MMCPART_NOAVAILABLE(0xff)
 #define PART_ACCESS_MASK   (0x7)
+#define PART_ACCESS_BOOT0  (0x2)
 #define PART_SUPPORT   (0x1)
 #define ENHNCD_SUPPORT (0x2)
 #define PART_ENH_ATTRIB(0x1f)
@@ -522,6 +523,7 @@ struct mmc {
 #endif
u8 is_uhs;
u8 uhsmode;
+   u8 forcehs;
 };
 
 struct mmc_hwpart_conf {
-- 
2.7.4

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[U-Boot] [UBOOT v2 04/15] mmc: sdhci: Add support for platform/board specific tuning

2017-01-30 Thread Siva Durga Prasad Paladugu
Add support to execute platform/board specific tuning needed
for SDR104 and SDR50 UHS modes.This patch adds hook routine
to support specific tuning requirements.

Signed-off-by: Siva Durga Prasad Paladugu 
---
Changes from v1:
- None
---
 drivers/mmc/sdhci.c | 8 
 include/sdhci.h | 1 +
 2 files changed, 9 insertions(+)

diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index bba2c30..a24cc15 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -309,11 +309,19 @@ static int sdhci_execute_tuning(struct mmc *mmc, u8 
opcode)
struct mmc_cmd cmd;
struct mmc_data data;
u32 ctrl;
+   int err;
u8 tuning_loop_counter = 40;
struct sdhci_host *host = mmc->priv;
 
debug("%s\n", __func__);
 
+   if (host->ops->platform_execute_tuning) {
+   err = host->ops->platform_execute_tuning(mmc, opcode);
+   if (err)
+   return err;
+   return 0;
+   }
+
ctrl = sdhci_readw(host, SDHCI_HOST_CTRL2);
ctrl |= SDHCI_CTRL_EXEC_TUNING;
sdhci_writew(host, ctrl, SDHCI_HOST_CTRL2);
diff --git a/include/sdhci.h b/include/sdhci.h
index fc0708c..dbe3836 100644
--- a/include/sdhci.h
+++ b/include/sdhci.h
@@ -250,6 +250,7 @@ struct sdhci_ops {
void(*set_control_reg)(struct sdhci_host *host);
void(*set_ios_post)(struct sdhci_host *host);
void(*set_clock)(struct sdhci_host *host, u32 div);
+   int (*platform_execute_tuning)(struct mmc *host, u8 opcode);
 };
 
 struct sdhci_host {
-- 
2.7.4

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[U-Boot] [UBOOT v2 09/15] mmc: sdhci: zynqmp: Add support of SD3.0

2017-01-30 Thread Siva Durga Prasad Paladugu
Add SD3.0 support for ZynqMP, this support needs a
platform specific tuning and tap delays for UHS
modes of SD3.0 and this patch takes care of it.

Signed-off-by: Siva Durga Prasad Paladugu 
---
Changes from v1:
- None
---
 board/xilinx/zynqmp/Makefile |   1 +
 board/xilinx/zynqmp/tap_delays.c | 249 +++
 drivers/mmc/zynq_sdhci.c | 142 +-
 include/zynqmp_tap_delay.h   |  20 
 4 files changed, 411 insertions(+), 1 deletion(-)
 create mode 100644 board/xilinx/zynqmp/tap_delays.c
 create mode 100644 include/zynqmp_tap_delay.h

diff --git a/board/xilinx/zynqmp/Makefile b/board/xilinx/zynqmp/Makefile
index 9d69d65..2bf0375 100644
--- a/board/xilinx/zynqmp/Makefile
+++ b/board/xilinx/zynqmp/Makefile
@@ -20,6 +20,7 @@ $(warning Put custom psu_init_gpl.c/h to 
board/xilinx/zynqmp/custom_hw_platform/
 endif
 endif
 
+obj-$(CONFIG_ZYNQ_SDHCI) += tap_delays.o
 obj-$(CONFIG_SPL_BUILD) += $(init-objs)
 
 # Suppress "warning: function declaration isn't a prototype"
diff --git a/board/xilinx/zynqmp/tap_delays.c b/board/xilinx/zynqmp/tap_delays.c
new file mode 100644
index 000..d57587e
--- /dev/null
+++ b/board/xilinx/zynqmp/tap_delays.c
@@ -0,0 +1,249 @@
+/*
+ * Xilinx ZynqMP SoC Tap Delay Programming
+ *
+ * Copyright (C) 2016 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+#include 
+
+#define SD_DLL_CTRL0xFF180358
+#define SD_ITAP_DLY0xFF180314
+#define SD_OTAP_DLY0xFF180318
+#define SD0_DLL_RST_MASK   0x0004
+#define SD0_DLL_RST0x0004
+#define SD1_DLL_RST_MASK   0x0004
+#define SD1_DLL_RST0x0004
+#define SD0_ITAPCHGWIN_MASK0x0200
+#define SD0_ITAPCHGWIN 0x0200
+#define SD1_ITAPCHGWIN_MASK0x0200
+#define SD1_ITAPCHGWIN 0x0200
+#define SD0_ITAPDLYENA_MASK0x0100
+#define SD0_ITAPDLYENA 0x0100
+#define SD1_ITAPDLYENA_MASK0x0100
+#define SD1_ITAPDLYENA 0x0100
+#define SD0_ITAPDLYSEL_MASK0x00FF
+#define SD0_ITAPDLYSEL_HSD 0x0015
+#define SD0_ITAPDLYSEL_SD_DDR500x003D
+#define SD0_ITAPDLYSEL_MMC_DDR50   0x0012
+
+#define SD1_ITAPDLYSEL_MASK0x00FF
+#define SD1_ITAPDLYSEL_HSD 0x0015
+#define SD1_ITAPDLYSEL_SD_DDR500x003D
+#define SD1_ITAPDLYSEL_MMC_DDR50   0x0012
+
+#define SD0_OTAPDLYENA_MASK0x0040
+#define SD0_OTAPDLYENA 0x0040
+#define SD1_OTAPDLYENA_MASK0x0040
+#define SD1_OTAPDLYENA 0x0040
+#define SD0_OTAPDLYSEL_MASK0x003F
+#define SD0_OTAPDLYSEL_MMC_HSD 0x0006
+#define SD0_OTAPDLYSEL_SD_HSD  0x0005
+#define SD0_OTAPDLYSEL_SDR50   0x0003
+#define SD0_OTAPDLYSEL_SDR104_B0   0x0003
+#define SD0_OTAPDLYSEL_SDR104_B2   0x0002
+#define SD0_OTAPDLYSEL_SD_DDR500x0004
+#define SD0_OTAPDLYSEL_MMC_DDR50   0x0006
+
+#define SD1_OTAPDLYSEL_MASK0x003F
+#define SD1_OTAPDLYSEL_MMC_HSD 0x0006
+#define SD1_OTAPDLYSEL_SD_HSD  0x0005
+#define SD1_OTAPDLYSEL_SDR50   0x0003
+#define SD1_OTAPDLYSEL_SDR104_B0   0x0003
+#define SD1_OTAPDLYSEL_SDR104_B2   0x0002
+#define SD1_OTAPDLYSEL_SD_DDR500x0004
+#define SD1_OTAPDLYSEL_MMC_DDR50   0x0006
+
+#define MMC_BANK2  0x2
+
+#define MMC_TIMING_UHS_SDR25   1
+#define MMC_TIMING_UHS_SDR50   2
+#define MMC_TIMING_UHS_SDR104  3
+#define MMC_TIMING_UHS_DDR50   4
+#define MMC_TIMING_MMC_HS200   5
+#define MMC_TIMING_SD_HS   6
+#define MMC_TIMING_MMC_DDR52   7
+#define MMC_TIMING_MMC_HS  8
+
+void zynqmp_dll_reset(u8 deviceid)
+{
+   /* Issue DLL Reset */
+   if (deviceid == 0)
+   zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK,
+ SD0_DLL_RST);
+   else
+   zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK,
+ SD1_DLL_RST);
+
+   mdelay(1);
+
+   /* Release DLL Reset */
+   if (deviceid == 0)
+   zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, 0x0);
+   else
+   zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, 0x0);
+}
+
+static void arasan_zynqmp_tap_sdr104(u8 deviceid, u8 timing, u8 bank)
+{
+   if (deviceid == 0) {
+   /* Program OTAP */
+   zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYENA_MASK,
+ SD0_OTAPDLYENA);
+   if (bank == MMC_BANK2)
+   zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
+  

[U-Boot] [UBOOT v2 01/15] mmc: sdhci: Update host capabilities about host controller

2017-01-30 Thread Siva Durga Prasad Paladugu
Update host capabilities for driver with host controller
information related to UHS modes incase of SD and HS200
mode incase of eMMC.

Signed-off-by: Siva Durga Prasad Paladugu 
---
Changes from v1:
- None
---
 drivers/mmc/sdhci.c | 28 +++-
 include/mmc.h   |  7 +++
 include/sdhci.h |  5 +
 3 files changed, 39 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 93cefd8..884b6a6 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -517,7 +517,8 @@ static const struct mmc_ops sdhci_ops = {
 int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
u32 f_max, u32 f_min)
 {
-   u32 caps, caps_1;
+   u32 caps;
+   u32 caps_1 = 0;
 
caps = sdhci_readl(host, SDHCI_CAPABILITIES);
 
@@ -588,6 +589,31 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct 
sdhci_host *host,
SDHCI_CLOCK_MUL_SHIFT;
}
 
+   if (!(cfg->voltages & MMC_VDD_165_195))
+   caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
+   SDHCI_SUPPORT_DDR50);
+
+   if (caps_1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
+ SDHCI_SUPPORT_DDR50))
+   cfg->host_caps |= MMC_MODE_UHS_SDR12 | MMC_MODE_UHS_SDR25;
+
+   if (caps_1 & SDHCI_SUPPORT_SDR104) {
+   cfg->host_caps |= MMC_MODE_UHS_SDR104 | MMC_MODE_UHS_SDR50;
+   /*
+* SD3.0: SDR104 is supported so (for eMMC) the caps2
+* field can be promoted to support HS200.
+*/
+   cfg->host_caps |= MMC_MODE_HS200;
+   } else if (caps_1 & SDHCI_SUPPORT_SDR50) {
+   cfg->host_caps |= MMC_MODE_UHS_SDR50;
+   }
+
+   if (caps_1 & SDHCI_SUPPORT_DDR50)
+   cfg->host_caps |= MMC_MODE_UHS_DDR50;
+
+   if (caps_1 & SDHCI_USE_SDR50_TUNING)
+   cfg->host_caps |= MMC_MODE_NEEDS_TUNING;
+
if (host->host_caps)
cfg->host_caps |= host->host_caps;
 
diff --git a/include/mmc.h b/include/mmc.h
index fad12d6..5c94eae 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -58,6 +58,13 @@
 #define MMC_MODE_8BIT  (1 << 3)
 #define MMC_MODE_SPI   (1 << 4)
 #define MMC_MODE_DDR_52MHz (1 << 5)
+#define MMC_MODE_UHS_SDR12 (1 << 6)
+#define MMC_MODE_UHS_SDR25 (1 << 7)
+#define MMC_MODE_UHS_SDR50 (1 << 8)
+#define MMC_MODE_UHS_SDR104(1 << 9)
+#define MMC_MODE_UHS_DDR50 (1 << 10)
+#define MMC_MODE_NEEDS_TUNING  (1 << 11)
+#define MMC_MODE_HS200 (1 << 12)
 
 #define SD_DATA_4BIT   0x0004
 
diff --git a/include/sdhci.h b/include/sdhci.h
index 6a43271..685bcf2 100644
--- a/include/sdhci.h
+++ b/include/sdhci.h
@@ -167,6 +167,11 @@
 #define  SDHCI_CAN_64BIT   BIT(28)
 
 #define SDHCI_CAPABILITIES_1   0x44
+#define  SDHCI_SUPPORT_SDR50   0x0001
+#define  SDHCI_SUPPORT_SDR104  0x0002
+#define  SDHCI_SUPPORT_DDR50   0x0004
+#define  SDHCI_USE_SDR50_TUNING0x2000
+#define  SDHCI_SUPPORT_HS400   0x8000 /* Non-standard */
 #define  SDHCI_CLOCK_MUL_MASK  0x00FF
 #define  SDHCI_CLOCK_MUL_SHIFT 16
 
-- 
2.7.4

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[U-Boot] [PATCH 1/5][v6] arch: powerpc: Move CONFIG_FSL_IFC to Kconfig

2017-01-30 Thread Prabhakar Kushwaha
Enable IFC from Kconfig.

Signed-off-by: Prabhakar Kushwaha 
---
Changes for v5: Added first time
Changes for v6: Sending as it is

 arch/powerpc/cpu/mpc85xx/Kconfig | 17 +
 include/configs/B4860QDS.h   |  1 -
 include/configs/BSC9131RDB.h |  1 -
 include/configs/BSC9132QDS.h |  1 -
 include/configs/C29XPCIE.h   |  1 -
 include/configs/P1010RDB.h   |  1 -
 include/configs/T102xQDS.h   |  1 -
 include/configs/T102xRDB.h   |  1 -
 include/configs/T1040QDS.h   |  1 -
 include/configs/T104xRDB.h   |  1 -
 include/configs/T208xQDS.h   |  1 -
 include/configs/T208xRDB.h   |  1 -
 include/configs/T4240RDB.h   |  1 -
 include/configs/t4qds.h  |  1 -
 14 files changed, 17 insertions(+), 13 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 704f65b..c67b6b0 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -349,6 +349,7 @@ config ARCH_B4420
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select SYS_PPC64
+   select FSL_IFC
 
 config ARCH_B4860
bool
@@ -372,6 +373,7 @@ config ARCH_B4860
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select SYS_PPC64
+   select FSL_IFC
 
 config ARCH_BSC9131
bool
@@ -384,6 +386,7 @@ config ARCH_BSC9131
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
+   select FSL_IFC
 
 config ARCH_BSC9132
bool
@@ -400,6 +403,7 @@ config ARCH_BSC9132
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select SYS_PPC_E500_USE_DEBUG_TLB
+   select FSL_IFC
 
 config ARCH_C29X
bool
@@ -412,6 +416,7 @@ config ARCH_C29X
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_6
select SYS_PPC_E500_USE_DEBUG_TLB
+   select FSL_IFC
 
 config ARCH_MPC8536
bool
@@ -527,6 +532,7 @@ config ARCH_P1010
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select SYS_PPC_E500_USE_DEBUG_TLB
+   select FSL_IFC
 
 config ARCH_P1011
bool
@@ -769,6 +775,7 @@ config ARCH_T1023
select SYS_FSL_QORIQ_CHASSIS2
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_5
+   select FSL_IFC
 
 config ARCH_T1024
bool
@@ -785,6 +792,7 @@ config ARCH_T1024
select SYS_FSL_QORIQ_CHASSIS2
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_5
+   select FSL_IFC
 
 config ARCH_T1040
bool
@@ -802,6 +810,7 @@ config ARCH_T1040
select SYS_FSL_QORIQ_CHASSIS2
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_5
+   select FSL_IFC
 
 config ARCH_T1042
bool
@@ -819,6 +828,7 @@ config ARCH_T1042
select SYS_FSL_QORIQ_CHASSIS2
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_5
+   select FSL_IFC
 
 config ARCH_T2080
bool
@@ -838,6 +848,7 @@ config ARCH_T2080
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select SYS_PPC64
+   select FSL_IFC
 
 config ARCH_T2081
bool
@@ -857,6 +868,7 @@ config ARCH_T2081
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select SYS_PPC64
+   select FSL_IFC
 
 config ARCH_T4160
bool
@@ -877,6 +889,7 @@ config ARCH_T4160
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select SYS_PPC64
+   select FSL_IFC
 
 config ARCH_T4240
bool
@@ -898,6 +911,7 @@ config ARCH_T4240
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select SYS_PPC64
+   select FSL_IFC
 
 config BOOKE
bool
@@ -1224,6 +1238,9 @@ config SYS_PPC64
 config SYS_PPC_E500_USE_DEBUG_TLB
bool
 
+config FSL_IFC
+   bool
+
 config SYS_PPC_E500_DEBUG_TLB
int "Temporary TLB entry for external debugger"
depends on SYS_PPC_E500_USE_DEBUG_TLB
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index 3ad9f80..4267d81 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -63,7 +63,6 @@
 
 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_FSL_IFC /* Enable IFC Support */
 #define CONFIG_FSL_CAAM/* Enable SEC/CAAM */
 #define CONFIG_PCIE1   /* PCIE controller 1 */
 #define CONFIG_FSL_PCI_INIT/* Use common FSL init code */
diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h
index a6f73f2..1fe22b6 100644
--- a/include/configs/BSC9131RDB.h
+++ b/include/configs/BSC9131RDB.h
@@ -46,7 +46,6 @@
 #endif
 
 /* High Level Configuration Options */
-#define CONFIG_FSL_IFC /* Enable IFC Support */
 #define CONFIG_FSL_CAAM/* Enable SEC/CAAM */
 
 #define CONFIG_TSEC_ENET
diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h

[U-Boot] [PATCH 2/5][v6] arch: powerpc: update the IFC IP input clock

2017-01-30 Thread Prabhakar Kushwaha
IFC IP clock is always a constant divisor of platform clock
pre-defined per SoC. Clock control register (CCR) used in
current implementation governs IFC IP output clock.

Update sys_info->freq_localbus to represent IFC input clock with
value constant divisor of platform clock.

Signed-off-by: Prabhakar Kushwaha 
---
Changes for v2: Split the patch in 2 patch set
Changes for v3: Rebased on top of u-boot commit
Changes for v4: fix compilation error
Changes for v5: Adding FSL_IFC as dependency
Changes for v6: Updated subject description 

 README   |  3 +++
 arch/powerpc/cpu/mpc85xx/Kconfig | 16 
 arch/powerpc/cpu/mpc85xx/speed.c | 10 ++
 3 files changed, 21 insertions(+), 8 deletions(-)

diff --git a/README b/README
index a95348a..9fda381 100644
--- a/README
+++ b/README
@@ -504,6 +504,9 @@ The following options need to be configured:
CONFIG_SYS_FSL_IFC_LE
Defines the IFC controller register space as Little Endian
 
+   CONFIG_SYS_FSL_IFC_CLK_DIV
+   Defines divider of platform clock(clock input to IFC 
controller).
+
CONFIG_SYS_FSL_PBL_PBI
It enables addition of RCW (Power on reset configuration) in 
built image.
Please refer doc/README.pblimage for more details
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index c67b6b0..8c6503d 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -1265,6 +1265,22 @@ config SYS_PPC_E500_DEBUG_TLB
 symbol should be set to the TLB1 entry to be used for this
 purpose. If unsure, do not change.
 
+config SYS_FSL_IFC_CLK_DIV
+   int "Divider of platform clock"
+   depends on FSL_IFC
+   default 2 ifARCH_B4420  || \
+   ARCH_B4860  || \
+   ARCH_T1024  || \
+   ARCH_T1023  || \
+   ARCH_T1040  || \
+   ARCH_T1042  || \
+   ARCH_T4160  || \
+   ARCH_T4240
+   default 1
+   help
+   Defines divider of platform clock(clock input to
+   IFC controller).
+
 source "board/freescale/b4860qds/Kconfig"
 source "board/freescale/bsc9131rdb/Kconfig"
 source "board/freescale/bsc9132qds/Kconfig"
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index fcf5d92..adba092 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -27,10 +27,6 @@ DECLARE_GLOBAL_DATA_PTR;
 void get_sys_info(sys_info_t *sys_info)
 {
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-#ifdef CONFIG_FSL_IFC
-   struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
-   u32 ccr;
-#endif
 #ifdef CONFIG_FSL_CORENET
volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
unsigned int cpu;
@@ -640,10 +636,8 @@ void get_sys_info(sys_info_t *sys_info)
 #endif
 
 #if defined(CONFIG_FSL_IFC)
-   ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
-   ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
-
-   sys_info->freq_localbus = sys_info->freq_systembus / ccr;
+   sys_info->freq_localbus = sys_info->freq_systembus /
+   CONFIG_SYS_FSL_IFC_CLK_DIV;
 #endif
 }
 
-- 
2.7.4


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[U-Boot] [PATCH 3/5][v6] arch: arm: update the IFC IP input clock

2017-01-30 Thread Prabhakar Kushwaha
IFC IP clock is always a constant divisor of platform clock
pre-defined per SoC. Clock control register (CCR) used in
current implementation governs IFC IP output clock.

Update sys_info->freq_localbus to represent IFC input clock with
value constant divisor of platform clock.

Signed-off-by: Prabhakar Kushwaha 
---
Changes for v2: Split the patch in 2 patch set
Changes for v3: Rebased on top of u-boot commit
Changes for v4: Sending as it is
Changes for v5: Sending as it is
Changes for v6: Subject updated

 arch/arm/cpu/armv7/ls102xa/clock.c  |  9 +
 arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 10 ++
 arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 10 ++
 3 files changed, 5 insertions(+), 24 deletions(-)

diff --git a/arch/arm/cpu/armv7/ls102xa/clock.c 
b/arch/arm/cpu/armv7/ls102xa/clock.c
index 7a337e1..b7d61ad 100644
--- a/arch/arm/cpu/armv7/ls102xa/clock.c
+++ b/arch/arm/cpu/armv7/ls102xa/clock.c
@@ -19,10 +19,6 @@ DECLARE_GLOBAL_DATA_PTR;
 void get_sys_info(struct sys_info *sys_info)
 {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
-#ifdef CONFIG_FSL_IFC
-   struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
-   u32 ccr;
-#endif
struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_LS1_CLK_ADDR);
unsigned int cpu;
const u8 core_cplx_pll[6] = {
@@ -74,10 +70,7 @@ void get_sys_info(struct sys_info *sys_info)
}
 
 #if defined(CONFIG_FSL_IFC)
-   ccr = in_be32(&ifc_regs.gregs->ifc_ccr);
-   ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
-
-   sys_info->freq_localbus = sys_info->freq_systembus / ccr;
+   sys_info->freq_localbus = sys_info->freq_systembus;
 #endif
 }
 
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
index 3da7037..2d7775e 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
@@ -22,10 +22,6 @@ DECLARE_GLOBAL_DATA_PTR;
 void get_sys_info(struct sys_info *sys_info)
 {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
-#ifdef CONFIG_FSL_IFC
-   struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
-   u32 ccr;
-#endif
 #if (defined(CONFIG_FSL_ESDHC) &&\
defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)) ||\
defined(CONFIG_SYS_DPAA_FMAN)
@@ -156,10 +152,8 @@ void get_sys_info(struct sys_info *sys_info)
 #endif
 
 #if defined(CONFIG_FSL_IFC)
-   ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
-   ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
-
-   sys_info->freq_localbus = sys_info->freq_systembus / ccr;
+   sys_info->freq_localbus = sys_info->freq_systembus /
+   CONFIG_SYS_FSL_IFC_CLK_DIV;
 #endif
 }
 
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
index f8fefc7..ab46431 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
@@ -26,10 +26,6 @@ DECLARE_GLOBAL_DATA_PTR;
 void get_sys_info(struct sys_info *sys_info)
 {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
-#ifdef CONFIG_FSL_IFC
-   struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
-   u32 ccr;
-#endif
struct ccsr_clk_cluster_group __iomem *clk_grp[2] = {
(void *)(CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR),
(void *)(CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR)
@@ -128,10 +124,8 @@ void get_sys_info(struct sys_info *sys_info)
}
 
 #if defined(CONFIG_FSL_IFC)
-   ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
-   ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
-
-   sys_info->freq_localbus = sys_info->freq_systembus / ccr;
+   sys_info->freq_localbus = sys_info->freq_systembus /
+   CONFIG_SYS_FSL_IFC_CLK_DIV;
 #endif
 }
 
-- 
2.7.4


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[U-Boot] [PATCH 4/5][v6] arch: powerpc: Move CONFIG_FSL_ELBC to Kconfig

2017-01-30 Thread Prabhakar Kushwaha
Enable ELBC from Kconfig.

Signed-off-by: Prabhakar Kushwaha 
---
Changes for v5: Added first time in the patch set
Changes for v6: Sending as it is

 arch/powerpc/cpu/mpc85xx/Kconfig| 26 ++
 include/configs/MPC8313ERDB.h   |  1 -
 include/configs/MPC8315ERDB.h   |  1 -
 include/configs/MPC837XEMDS.h   |  1 -
 include/configs/MPC837XERDB.h   |  1 -
 include/configs/MPC8536DS.h |  1 -
 include/configs/MPC8569MDS.h|  2 --
 include/configs/MPC8572DS.h |  1 -
 include/configs/P1022DS.h   |  1 -
 include/configs/P1023RDB.h  |  1 -
 include/configs/P2041RDB.h  |  1 -
 include/configs/UCP1020.h   |  1 -
 include/configs/controlcenterd.h|  1 -
 include/configs/corenet_ds.h|  1 -
 include/configs/cyrus.h |  1 -
 include/configs/ids8313.h   |  2 --
 include/configs/km/kmp204x-common.h |  1 -
 include/configs/p1_p2_rdb_pc.h  |  1 -
 include/configs/p1_twr.h|  1 -
 include/configs/ve8313.h|  1 -
 include/configs/xpedite537x.h   |  1 -
 include/configs/xpedite550x.h   |  1 -
 22 files changed, 26 insertions(+), 23 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 8c6503d..765d328 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -429,11 +429,13 @@ config ARCH_MPC8536
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
+   select FSL_ELBC
 
 config ARCH_MPC8540
bool
select FSL_LAW
select SYS_FSL_HAS_DDR1
+   select FSL_ELBC
 
 config ARCH_MPC8541
bool
@@ -442,6 +444,7 @@ config ARCH_MPC8541
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
+   select FSL_ELBC
 
 config ARCH_MPC8544
bool
@@ -452,6 +455,7 @@ config ARCH_MPC8544
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
+   select FSL_ELBC
 
 config ARCH_MPC8548
bool
@@ -467,6 +471,7 @@ config ARCH_MPC8548
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
+   select FSL_ELBC
 
 config ARCH_MPC8555
bool
@@ -475,11 +480,13 @@ config ARCH_MPC8555
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
+   select FSL_ELBC
 
 config ARCH_MPC8560
bool
select FSL_LAW
select SYS_FSL_HAS_DDR1
+   select FSL_ELBC
 
 config ARCH_MPC8568
bool
@@ -488,6 +495,7 @@ config ARCH_MPC8568
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
+   select FSL_ELBC
 
 config ARCH_MPC8569
bool
@@ -498,6 +506,7 @@ config ARCH_MPC8569
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
+   select FSL_ELBC
 
 config ARCH_MPC8572
bool
@@ -512,6 +521,7 @@ config ARCH_MPC8572
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
+   select FSL_ELBC
 
 config ARCH_P1010
bool
@@ -546,6 +556,7 @@ config ARCH_P1011
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
+   select FSL_ELBC
 
 config ARCH_P1020
bool
@@ -559,6 +570,7 @@ config ARCH_P1020
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
+   select FSL_ELBC
 
 config ARCH_P1021
bool
@@ -572,6 +584,7 @@ config ARCH_P1021
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
+   select FSL_ELBC
 
 config ARCH_P1022
bool
@@ -587,6 +600,7 @@ config ARCH_P1022
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
+   select FSL_ELBC
 
 config ARCH_P1023
bool
@@ -598,6 +612,7 @@ config ARCH_P1023
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
+   select FSL_ELBC
 
 config ARCH_P1024
bool
@@ -611,6 +626,7 @@ config ARCH_P1024
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
+   select FSL_ELBC
 
 config ARCH_P1025
bool
@@ -624,6 +640,7 @@ config ARCH_P1025
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
+   select FSL_ELBC
 
 config ARCH_P2020
bool
@@ -638,6 +655,7 @@ config ARCH_P2020
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
+   select FSL_ELBC
 
 config ARCH_P2041
bool
@@ -659,6 +677,7 @@ config ARCH_P2041
select SYS_FSL_QORIQ_CHASSIS1
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPA

[U-Boot] [UBOOT v2 00/15] Add support for SD3.0 and eMMC HS200

2017-01-30 Thread Siva Durga Prasad Paladugu
This patch series adds support SD3.0 and eMMC HS200
modes for ZynqMP. This series also contains changes
in mmc and sdhci framework to support SD3.0 and HS200.

Siva Durga Prasad Paladugu (15):
  mmc: sdhci: Update host capabilities about host controller
  mmc: Add support for SD3.0
  mmc: sdhci: Add SD3.0 support
  mmc: sdhci: Add support for platform/board specific tuning
  mmc: sdhci: Add support for platform specific delay
  mmc: sdhci: Make sdhci_ops of host as modifiable
  zynqmp: Define routines for mmio write and read
  mmc: sdhci: zynq: Define private structure arasan_sdhci_priv
  mmc: sdhci: zynqmp: Add support of SD3.0
  mmc: sdhci: Add quirk for 1.8v switching not supported
  mmc: zynq_sdhci: Update quirk if 1.8v switching not supported
  mmc: sdhci: Add support for eMMC HS200 mode
  mmc: sdhci: Update execute tuning and set clock for HS200
  mmc: sdhci: zynqmp: Set tapdelays for eMMC HS200 mode
  mmc: Change frequency while accessing to boot partition

 arch/arm/cpu/armv8/zynqmp/cpu.c  |  51 ++
 arch/arm/include/asm/arch-zynqmp/sys_proto.h |   3 +
 board/xilinx/zynqmp/Makefile |   1 +
 board/xilinx/zynqmp/tap_delays.c | 250 +++
 drivers/mmc/mmc-uclass.c |  52 ++
 drivers/mmc/mmc.c| 218 +--
 drivers/mmc/sdhci.c  | 205 +-
 drivers/mmc/zynq_sdhci.c | 170 +-
 include/mmc.h|  74 +++-
 include/sdhci.h  |  18 +-
 include/zynqmp_tap_delay.h   |  20 +++
 11 files changed, 1040 insertions(+), 22 deletions(-)
 create mode 100644 board/xilinx/zynqmp/tap_delays.c
 create mode 100644 include/zynqmp_tap_delay.h

-- 
2.7.4

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[U-Boot] [UBOOT v2 14/15] mmc: sdhci: zynqmp: Set tapdelays for eMMC HS200 mode

2017-01-30 Thread Siva Durga Prasad Paladugu
Sets the tapdelays for eMMC HS200 mode support for
ZynqMP as tapdelays needs to be programmed for it to
work

Signed-off-by: Siva Durga Prasad Paladugu 
---
Changes from v1:
- None
---
 board/xilinx/zynqmp/tap_delays.c | 1 +
 drivers/mmc/zynq_sdhci.c | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/board/xilinx/zynqmp/tap_delays.c b/board/xilinx/zynqmp/tap_delays.c
index d57587e..aa0825a 100644
--- a/board/xilinx/zynqmp/tap_delays.c
+++ b/board/xilinx/zynqmp/tap_delays.c
@@ -235,6 +235,7 @@ void arasan_zynqmp_set_tapdelay(u8 deviceid, u8 timing, u8 
bank)
arasan_zynqmp_tap_sdr50(deviceid, timing, bank);
break;
case MMC_TIMING_UHS_SDR104:
+   case MMC_TIMING_MMC_HS200:
arasan_zynqmp_tap_sdr104(deviceid, timing, bank);
break;
case MMC_TIMING_UHS_DDR50:
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index 4875a4e..8fa5df8 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -151,7 +151,7 @@ static void arasan_sdhci_set_tapdelay(struct sdhci_host 
*host, u8 uhsmode)
debug("%s, %d:%d, mode:%d\n", __func__, priv->deviceid, priv->bank,
  uhsmode);
if ((uhsmode >= MMC_TIMING_UHS_SDR25) &&
-   (uhsmode <= MMC_TIMING_UHS_DDR50))
+   (uhsmode <= MMC_TIMING_HS200))
arasan_zynqmp_set_tapdelay(priv->deviceid, uhsmode,
   priv->bank);
 }
-- 
2.7.4

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[U-Boot] [PATCH] armv8:fsl-layerscape: Avoid RCWSR28 register hard-coding

2017-01-30 Thread Ashish Kumar
From: Prabhakar Kushwaha 

SerDes information is not necessary to be present in RCWSR29 register.
It may vary from SoC to SoC.

So Avoid RCWSR28 register hard-coding.

Signed-off-by: Prabhakar Kushwaha 
---
 .../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c|   28 +++
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |9 ++
 2 files changed, 25 insertions(+), 12 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
index 601651a..af2684e 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
@@ -53,20 +53,22 @@ int is_serdes_configured(enum srds_prtcl device)
 int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
 {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
-   u32 cfg = gur_in32(&gur->rcwsr[28]);
+   u32 cfg = 0;
int i;
 
switch (sd) {
 #ifdef CONFIG_SYS_FSL_SRDS_1
case FSL_SRDS_1:
-   cfg &= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
-   cfg >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
+   cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]);
+   cfg &= FSL_CHASSIS3_SRDS1_PRTCL_MASK;
+   cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
break;
 #endif
 #ifdef CONFIG_SYS_FSL_SRDS_2
case FSL_SRDS_2:
-   cfg &= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
-   cfg >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
+   cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]);
+   cfg &= FSL_CHASSIS3_SRDS2_PRTCL_MASK;
+   cfg >>= FSL_CHASSIS3_SRDS2_PRTCL_SHIFT;
break;
 #endif
default:
@@ -85,8 +87,8 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
return -ENODEV;
 }
 
-void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
-   u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
+void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,
+u32 sd_prctl_shift, u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
 {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 cfg;
@@ -97,7 +99,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 
sd_prctl_shift,
 
memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT);
 
-   cfg = gur_in32(&gur->rcwsr[28]) & sd_prctl_mask;
+   cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask;
cfg >>= sd_prctl_shift;
printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
 
@@ -154,15 +156,17 @@ void fsl_serdes_init(void)
 #ifdef CONFIG_SYS_FSL_SRDS_1
serdes_init(FSL_SRDS_1,
CONFIG_SYS_FSL_LSCH3_SERDES_ADDR,
-   FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK,
-   FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT,
+   FSL_CHASSIS3_SRDS1_REGSR,
+   FSL_CHASSIS3_SRDS1_PRTCL_MASK,
+   FSL_CHASSIS3_SRDS1_PRTCL_SHIFT,
serdes1_prtcl_map);
 #endif
 #ifdef CONFIG_SYS_FSL_SRDS_2
serdes_init(FSL_SRDS_2,
CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x1,
-   FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK,
-   FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT,
+   FSL_CHASSIS3_SRDS2_REGSR,
+   FSL_CHASSIS3_SRDS2_PRTCL_MASK,
+   FSL_CHASSIS3_SRDS2_PRTCL_SHIFT,
serdes2_prtcl_map);
 #endif
 }
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 43ae686..5ea9130 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -232,10 +232,19 @@ struct ccsr_gur {
 #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK   0x3f
 #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT 18
 #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK  0x3f
+
+#if defined(CONFIG_LS2080A)
 #defineFSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK   0x00FF
 #defineFSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT  16
 #defineFSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK   0xFF00
 #defineFSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT  24
+#define FSL_CHASSIS3_SRDS1_PRTCL_MASK  FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK
+#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT
+#define FSL_CHASSIS3_SRDS2_PRTCL_MASK  FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK
+#define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT
+#define FSL_CHASSIS3_SRDS1_REGSR   29
+#define FSL_CHASSIS3_SRDS2_REGSR   29
+#endif
 #define RCW_SB_EN_REG_INDEX9
 #define RCW_SB_EN_MASK 0x0400
 
-- 
1.7.6.GIT

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[U-Boot] [PATCH 1/2][v4] board: freescale: ls1012a: Enable secure DDR on LS1012A platforms

2017-01-30 Thread Prabhakar Kushwaha
PPA binary needs to be relocated on secure DDR, hence marking out
a portion of DDR as secure if CONFIG_SYS_MEM_RESERVE_SECURE flag
is set

Signed-off-by: Hou Zhiqiang 
Signed-off-by: Abhimanyu Saini 
Signed-off-by: Prabhakar Kushwaha 
---
Changes for v2: Sending as it is
Changes for v3: Rebased top of the tree
Changes for v4: incorporated York's comments

 arch/arm/include/asm/arch-fsl-layerscape/config.h |  3 +++
 board/freescale/ls1012afrdm/ls1012afrdm.c | 29 +++
 board/freescale/ls1012aqds/ls1012aqds.c   | 29 +++
 board/freescale/ls1012ardb/ls1012ardb.c   | 29 +++
 include/configs/ls1012a_common.h  |  1 +
 5 files changed, 91 insertions(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h 
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 8c426af..83f5501 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -192,6 +192,9 @@
 #define GICD_BASE  0x01401000
 #define GICC_BASE  0x01402000
 
+#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED  CONFIG_SYS_DDR_BLOCK1_SIZE
+
 #elif defined(CONFIG_ARCH_LS1046A)
 #define CONFIG_SYS_FMAN_V3
 #define CONFIG_SYS_NUM_FMAN1
diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c 
b/board/freescale/ls1012afrdm/ls1012afrdm.c
index b03bdb8..c2432c3 100644
--- a/board/freescale/ls1012afrdm/ls1012afrdm.c
+++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
@@ -85,3 +85,32 @@ int ft_board_setup(void *blob, bd_t *bd)
 
return 0;
 }
+
+void dram_init_banksize(void)
+{
+   /*
+* gd->arch.secure_ram tracks the location of secure memory.
+* It was set as if the memory starts from 0.
+* The address needs to add the offset of its bank.
+*/
+   gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+   if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
+   gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
+   gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
+   gd->bd->bi_dram[1].size = gd->ram_size -
+   CONFIG_SYS_DDR_BLOCK1_SIZE;
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+   gd->arch.secure_ram = gd->bd->bi_dram[1].start +
+   gd->arch.secure_ram -
+   CONFIG_SYS_DDR_BLOCK1_SIZE;
+   gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+#endif
+   } else {
+   gd->bd->bi_dram[0].size = gd->ram_size;
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+   gd->arch.secure_ram = gd->bd->bi_dram[0].start +
+   gd->arch.secure_ram;
+   gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+#endif
+   }
+}
diff --git a/board/freescale/ls1012aqds/ls1012aqds.c 
b/board/freescale/ls1012aqds/ls1012aqds.c
index 88fb4ce..bdd9529 100644
--- a/board/freescale/ls1012aqds/ls1012aqds.c
+++ b/board/freescale/ls1012aqds/ls1012aqds.c
@@ -159,3 +159,32 @@ int ft_board_setup(void *blob, bd_t *bd)
return 0;
 }
 #endif
+
+void dram_init_banksize(void)
+{
+   /*
+* gd->arch.secure_ram tracks the location of secure memory.
+* It was set as if the memory starts from 0.
+* The address needs to add the offset of its bank.
+*/
+   gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+   if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
+   gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
+   gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
+   gd->bd->bi_dram[1].size = gd->ram_size -
+   CONFIG_SYS_DDR_BLOCK1_SIZE;
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+   gd->arch.secure_ram = gd->bd->bi_dram[1].start +
+   gd->arch.secure_ram -
+   CONFIG_SYS_DDR_BLOCK1_SIZE;
+   gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+#endif
+   } else {
+   gd->bd->bi_dram[0].size = gd->ram_size;
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+   gd->arch.secure_ram = gd->bd->bi_dram[0].start +
+   gd->arch.secure_ram;
+   gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+#endif
+   }
+}
diff --git a/board/freescale/ls1012ardb/ls1012ardb.c 
b/board/freescale/ls1012ardb/ls1012ardb.c
index 65fa94c..2dece02 100644
--- a/board/freescale/ls1012ardb/ls1012ardb.c
+++ b/board/freescale/ls1012ardb/ls1012ardb.c
@@ -159,3 +159,32 @@ int ft_board_setup(void *blob, bd_t *bd)
 
return 0;
 }
+
+void dram_init_banksize(void)
+{
+   /*
+* gd->secure_ram tracks the location of secure memory.
+* It was set as if the memory starts from 0.
+* The address needs to add the offset of its bank.
+*/
+   gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+   if (gd->ram_siz

Re: [U-Boot] [PATCH 2/2][v3] armv8: ls1012a: Add support of PPA

2017-01-30 Thread Prabhakar Kushwaha

> -Original Message-
> From: york sun
> Sent: Saturday, January 28, 2017 2:10 AM
> To: Prabhakar Kushwaha ; u-
> b...@lists.denx.de
> Cc: Z.Q. Hou ; Abhimanyu Saini
> 
> Subject: Re: [PATCH 2/2][v3] armv8: ls1012a: Add support of PPA
> 
> On 01/26/2017 08:09 PM, Prabhakar Kushwaha wrote:
> > The PPA implements PSCI which requires for power managment.
> >
> > Added support of PPA for LS1012AQDS, LS1012ARDB and LS1012AFRDM.
> >
> > Signed-off-by: Hou Zhiqiang 
> > Signed-off-by: Abhimanyu Saini 
> > Signed-off-by: Prabhakar Kushwaha 
> > ---
> > Changes for v2: Enabled FSL_LS_PPA
> > Changes for v3: Rebased and updated as per latest PPA code
> >
> >  board/freescale/ls1012afrdm/ls1012afrdm.c | 6 ++
> >  board/freescale/ls1012aqds/ls1012aqds.c   | 7 +++
> >  board/freescale/ls1012ardb/ls1012ardb.c   | 6 ++
> >  configs/ls1012afrdm_qspi_defconfig| 1 +
> >  configs/ls1012aqds_qspi_defconfig | 1 +
> >  configs/ls1012ardb_qspi_defconfig | 1 +
> >  6 files changed, 22 insertions(+)
> >
> > diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c
> b/board/freescale/ls1012afrdm/ls1012afrdm.c
> > index c2432c3..789cae2 100644
> > --- a/board/freescale/ls1012afrdm/ls1012afrdm.c
> > +++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
> > @@ -9,6 +9,9 @@
> >  #include 
> >  #include 
> >  #include 
> > +#ifdef CONFIG_FSL_LS_PPA
> > +#include 
> > +#endif
> 
> Do you really need #ifdef here?
> 

Yes, if CONFIG_FSL_LS_PPA is undefined then  ppa_init() should not be called. 
As ppa_init declaration is present in ppa.h. So need to remove inclusion of 
ppa.h also. 

--prabhakar

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[U-Boot] [PATCH] arm: fsl-layerscape: Move QSGMII wriop_init to SoC file

2017-01-30 Thread Ashish Kumar
From: Prabhakar Kushwaha 

MAC number used per QSGMII is not fixed. It may wary from SoC to SoC.

So move QSGMII wriop_init_dpmac() to SoC file.

Signed-off-by: Prabhakar Kushwaha 
---
 .../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c|   27 +
 .../include/asm/arch-fsl-layerscape/fsl_serdes.h   |8 ++--
 drivers/net/ldpaa_eth/ls2080a.c|   30 
 include/fsl-mc/ldpaa_wriop.h   |1 +
 4 files changed, 43 insertions(+), 23 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
index 7faa86c..601651a 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
@@ -23,6 +23,13 @@ int xfi_dpmac[XFI8 + 1];
 int sgmii_dpmac[SGMII16 + 1];
 #endif
 
+void __wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
+{
+   return;
+}
+void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
+   __attribute__((weak, alias("__wriop_init_dpmac_qsgmii")));
+
 int is_serdes_configured(enum srds_prtcl device)
 {
int ret = 0;
@@ -106,28 +113,10 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, 
u32 sd_prctl_shift,
 #ifdef CONFIG_FSL_MC_ENET
switch (lane_prtcl) {
case QSGMII_A:
-   wriop_init_dpmac(sd, 5, (int)lane_prtcl);
-   wriop_init_dpmac(sd, 6, (int)lane_prtcl);
-   wriop_init_dpmac(sd, 7, (int)lane_prtcl);
-   wriop_init_dpmac(sd, 8, (int)lane_prtcl);
-   break;
case QSGMII_B:
-   wriop_init_dpmac(sd, 1, (int)lane_prtcl);
-   wriop_init_dpmac(sd, 2, (int)lane_prtcl);
-   wriop_init_dpmac(sd, 3, (int)lane_prtcl);
-   wriop_init_dpmac(sd, 4, (int)lane_prtcl);
-   break;
case QSGMII_C:
-   wriop_init_dpmac(sd, 13, (int)lane_prtcl);
-   wriop_init_dpmac(sd, 14, (int)lane_prtcl);
-   wriop_init_dpmac(sd, 15, (int)lane_prtcl);
-   wriop_init_dpmac(sd, 16, (int)lane_prtcl);
-   break;
case QSGMII_D:
-   wriop_init_dpmac(sd, 9, (int)lane_prtcl);
-   wriop_init_dpmac(sd, 10, (int)lane_prtcl);
-   wriop_init_dpmac(sd, 11, (int)lane_prtcl);
-   wriop_init_dpmac(sd, 12, (int)lane_prtcl);
+   wriop_init_dpmac_qsgmii(sd, (int)lane_prtcl);
break;
default:
if (lane_prtcl >= XFI1 && lane_prtcl <= XFI8)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h 
b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
index d9d948e..70181c5 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
@@ -48,10 +48,10 @@ enum srds_prtcl {
SGMII14,
SGMII15,
SGMII16,
-   QSGMII_A, /* A indicates MACs 1-4 */
-   QSGMII_B, /* B indicates MACs 5-8 */
-   QSGMII_C, /* C indicates MACs 9-12 */
-   QSGMII_D, /* D indicates MACs 12-16 */
+   QSGMII_A,
+   QSGMII_B,
+   QSGMII_C,
+   QSGMII_D,
SERDES_PRCTL_COUNT
 };
 
diff --git a/drivers/net/ldpaa_eth/ls2080a.c b/drivers/net/ldpaa_eth/ls2080a.c
index 93ed4f1..673e428 100644
--- a/drivers/net/ldpaa_eth/ls2080a.c
+++ b/drivers/net/ldpaa_eth/ls2080a.c
@@ -79,3 +79,33 @@ phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int 
lane_prtcl)
 
return PHY_INTERFACE_MODE_NONE;
 }
+
+void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
+{
+   switch (lane_prtcl) {
+   case QSGMII_A:
+   wriop_init_dpmac(sd, 5, (int)lane_prtcl);
+   wriop_init_dpmac(sd, 6, (int)lane_prtcl);
+   wriop_init_dpmac(sd, 7, (int)lane_prtcl);
+   wriop_init_dpmac(sd, 8, (int)lane_prtcl);
+   break;
+   case QSGMII_B:
+   wriop_init_dpmac(sd, 1, (int)lane_prtcl);
+   wriop_init_dpmac(sd, 2, (int)lane_prtcl);
+   wriop_init_dpmac(sd, 3, (int)lane_prtcl);
+   wriop_init_dpmac(sd, 4, (int)lane_prtcl);
+   break;
+   case QSGMII_C:
+   wriop_init_dpmac(sd, 13, (int)lane_prtcl);
+   wriop_init_dpmac(sd, 14, (int)lane_prtcl);
+   wriop_init_dpmac(sd, 15, (int)lane_prtcl);
+   wriop_init_dpmac(sd, 16, (int)lane_prtcl);
+   break;
+   case QSGMII_D:
+   wriop_init_dpmac(sd, 9, (int)lane_prtcl);
+

[U-Boot] [PATCH 2/2][v4] armv8: ls1012a: Add support of PPA

2017-01-30 Thread Prabhakar Kushwaha
The PPA implements PSCI which requires for power managment.

Added support of PPA for LS1012AQDS, LS1012ARDB and LS1012AFRDM.

Signed-off-by: Hou Zhiqiang 
Signed-off-by: Abhimanyu Saini 
Signed-off-by: Prabhakar Kushwaha 
---
Changes for v2: Enabled FSL_LS_PPA
Changes for v3: Rebased and updated as per latest PPA code
Changes for v4: Sending as it is

 board/freescale/ls1012afrdm/ls1012afrdm.c | 6 ++
 board/freescale/ls1012aqds/ls1012aqds.c   | 7 +++
 board/freescale/ls1012ardb/ls1012ardb.c   | 6 ++
 configs/ls1012afrdm_qspi_defconfig| 1 +
 configs/ls1012aqds_qspi_defconfig | 1 +
 configs/ls1012ardb_qspi_defconfig | 1 +
 6 files changed, 22 insertions(+)

diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c 
b/board/freescale/ls1012afrdm/ls1012afrdm.c
index c2432c3..789cae2 100644
--- a/board/freescale/ls1012afrdm/ls1012afrdm.c
+++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
@@ -9,6 +9,9 @@
 #include 
 #include 
 #include 
+#ifdef CONFIG_FSL_LS_PPA
+#include 
+#endif
 #include 
 #include 
 #include 
@@ -74,6 +77,9 @@ int board_init(void)
gd->env_addr = (ulong)&default_environment[0];
 #endif
 
+#ifdef CONFIG_FSL_LS_PPA
+   ppa_init();
+#endif
return 0;
 }
 
diff --git a/board/freescale/ls1012aqds/ls1012aqds.c 
b/board/freescale/ls1012aqds/ls1012aqds.c
index bdd9529..4281790 100644
--- a/board/freescale/ls1012aqds/ls1012aqds.c
+++ b/board/freescale/ls1012aqds/ls1012aqds.c
@@ -10,6 +10,9 @@
 #include 
 #include 
 #include 
+#ifdef CONFIG_FSL_LS_PPA
+#include 
+#endif
 #include 
 #include 
 #include 
@@ -113,6 +116,10 @@ int board_init(void)
 #ifdef CONFIG_ENV_IS_NOWHERE
gd->env_addr = (ulong)&default_environment[0];
 #endif
+
+#ifdef CONFIG_FSL_LS_PPA
+   ppa_init();
+#endif
return 0;
 }
 
diff --git a/board/freescale/ls1012ardb/ls1012ardb.c 
b/board/freescale/ls1012ardb/ls1012ardb.c
index 2dece02..e3a8a76 100644
--- a/board/freescale/ls1012ardb/ls1012ardb.c
+++ b/board/freescale/ls1012ardb/ls1012ardb.c
@@ -9,6 +9,9 @@
 #include 
 #include 
 #include 
+#ifdef CONFIG_FSL_LS_PPA
+#include 
+#endif
 #include 
 #include 
 #include 
@@ -110,6 +113,9 @@ int board_init(void)
gd->env_addr = (ulong)&default_environment[0];
 #endif
 
+#ifdef CONFIG_FSL_LS_PPA
+   ppa_init();
+#endif
return 0;
 }
 
diff --git a/configs/ls1012afrdm_qspi_defconfig 
b/configs/ls1012afrdm_qspi_defconfig
index 8932650..8b42962 100644
--- a/configs/ls1012afrdm_qspi_defconfig
+++ b/configs/ls1012afrdm_qspi_defconfig
@@ -6,6 +6,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm"
 # CONFIG_SYS_MALLOC_F is not set
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_FSL_LS_PPA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
diff --git a/configs/ls1012aqds_qspi_defconfig 
b/configs/ls1012aqds_qspi_defconfig
index 0bb40d0..d400276 100644
--- a/configs/ls1012aqds_qspi_defconfig
+++ b/configs/ls1012aqds_qspi_defconfig
@@ -5,6 +5,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds"
 # CONFIG_SYS_MALLOC_F is not set
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_FSL_LS_PPA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
diff --git a/configs/ls1012ardb_qspi_defconfig 
b/configs/ls1012ardb_qspi_defconfig
index 6fed6c7..06c4243 100644
--- a/configs/ls1012ardb_qspi_defconfig
+++ b/configs/ls1012ardb_qspi_defconfig
@@ -5,6 +5,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
 # CONFIG_SYS_MALLOC_F is not set
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_FSL_LS_PPA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
-- 
2.7.4


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[U-Boot] [PATCH 5/5][v6] arch: powerpc: update the eLBC IP input clock

2017-01-30 Thread Prabhakar Kushwaha
eLBC IP clock is always a constant divisor of platform clock
pre-defined per SoC. Clock ratio register (LCRR) used in
current implementation governs eLBC IP output cloc.

Update sys_info->freq_localbus to represent eLBC input clock with
value constant divisor of platform clock.

Signed-off-by: Prabhakar Kushwaha 
---
Changes for v5: Added first time in patch
Changes for v6: Updated subject description

 README   |  3 +++
 arch/powerpc/cpu/mpc85xx/Kconfig | 14 ++
 arch/powerpc/cpu/mpc85xx/speed.c | 28 ++--
 arch/powerpc/cpu/mpc86xx/speed.c | 14 +-
 4 files changed, 20 insertions(+), 39 deletions(-)

diff --git a/README b/README
index 9fda381..b27e757 100644
--- a/README
+++ b/README
@@ -507,6 +507,9 @@ The following options need to be configured:
CONFIG_SYS_FSL_IFC_CLK_DIV
Defines divider of platform clock(clock input to IFC 
controller).
 
+   CONFIG_SYS_FSL_LBC_CLK_DIV
+   Defines divider of platform clock(clock input to eLBC 
controller).
+
CONFIG_SYS_FSL_PBL_PBI
It enables addition of RCW (Power on reset configuration) in 
built image.
Please refer doc/README.pblimage for more details
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 765d328..7442495 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -1307,6 +1307,20 @@ config SYS_FSL_IFC_CLK_DIV
Defines divider of platform clock(clock input to
IFC controller).
 
+config SYS_FSL_LBC_CLK_DIV
+   int "Divider of platform clock"
+   depends on FSL_ELBC
+   default 2 ifARCH_P2041  || \
+   ARCH_P3041  || \
+   ARCH_P4080  || \
+   ARCH_P5020  || \
+   ARCH_P5040
+   default 1
+
+   help
+   Defines divider of platform clock(clock input to
+   eLBC controller).
+
 source "board/freescale/b4860qds/Kconfig"
 source "board/freescale/bsc9131rdb/Kconfig"
 source "board/freescale/bsc9132qds/Kconfig"
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index adba092..cb8281e 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -607,32 +607,8 @@ void get_sys_info(sys_info_t *sys_info)
 #endif /* CONFIG_FSL_CORENET */
 
 #if defined(CONFIG_FSL_LBC)
-   uint lcrr_div;
-#if defined(CONFIG_SYS_LBC_LCRR)
-   /* We will program LCRR to this value later */
-   lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
-#else
-   lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV;
-#endif
-   if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
-#if defined(CONFIG_FSL_CORENET)
-   /* If this is corenet based SoC, bit-representation
-* for four times the clock divider values.
-*/
-   lcrr_div *= 4;
-#elif !defined(CONFIG_ARCH_MPC8540) && !defined(CONFIG_ARCH_MPC8541) && \
-   !defined(CONFIG_ARCH_MPC8555) && !defined(CONFIG_ARCH_MPC8560)
-   /*
-* Yes, the entire PQ38 family use the same
-* bit-representation for twice the clock divider values.
-*/
-   lcrr_div *= 2;
-#endif
-   sys_info->freq_localbus = sys_info->freq_systembus / lcrr_div;
-   } else {
-   /* In case anyone cares what the unknown value is */
-   sys_info->freq_localbus = lcrr_div;
-   }
+   sys_info->freq_localbus = sys_info->freq_systembus /
+   CONFIG_SYS_FSL_LBC_CLK_DIV;
 #endif
 
 #if defined(CONFIG_FSL_IFC)
diff --git a/arch/powerpc/cpu/mpc86xx/speed.c b/arch/powerpc/cpu/mpc86xx/speed.c
index 05f23db..b9e2100 100644
--- a/arch/powerpc/cpu/mpc86xx/speed.c
+++ b/arch/powerpc/cpu/mpc86xx/speed.c
@@ -78,19 +78,7 @@ void get_sys_info(sys_info_t *sys_info)
break;
}
 
-#if defined(CONFIG_SYS_LBC_LCRR)
-   /* We will program LCRR to this value later */
-   lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
-#else
-   lcrr_div = in_be32(&immap->im_lbc.lcrr) & LCRR_CLKDIV;
-#endif
-   if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
-   sys_info->freq_localbus = sys_info->freq_systembus
-   / (lcrr_div * 2);
-   } else {
-   /* In case anyone cares what the unknown value is */
-   sys_info->freq_localbus = lcrr_div;
-   }
+   sys_info->freq_localbus = sys_info->freq_systembus;
 }
 
 
-- 
2.7.4


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Re: [U-Boot] Falcon boot breaks on DRA7 because of commit b9c8ccab "env_mmc.c: Allow environment to be used within SPL"

2017-01-30 Thread Jean-Jacques Hiblot



On 27/01/2017 00:36, Tom Rini wrote:

On Wed, Jan 25, 2017 at 11:21:32AM +0100, Jean-Jacques Hiblot wrote:


On 24/01/2017 20:11, Tom Rini wrote:

On Tue, Jan 24, 2017 at 06:04:47PM +0100, Jean-Jacques Hiblot wrote:

On 24/01/2017 16:46, Tom Rini wrote:

I had noticed that it's quite old indeed. I didn't mean that it's a
regression. I'm just puzzled by the commit. what is its purpose ?
why is SPL not using  CONFIG_SYS_MMC_ENV_DEV ?

Because in SPL we do not have both MMC devices initialized.

That is not always the case. Actually in spl_mmc.c the code requires
us to register more than one MMC device to work properly when
multiple MMC boot devices can be used (see
spl_mmc_get_device_index())
I did the test of registering only MMC2 when booting from eMMC, the
SPL fails because it can't find device 1:
Trying to boot from MMC2_2
MMC Device 1 not found
spl: could not find mmc device. error: -19


We register
the one we booted from and thus it is device 0 to U-Boot in this case.
I suspect the rest of the issues stem from this quirk, or something
having broken around this quirk.  Thanks!

Right.  So I suspect the problem is that some level of the env_mmc.c
code needs to be adapted again for the change in how SPL now works with
the possibility of multiple devices.  It's possible that the change you
found is the right fix, please investigate a bit more and confirm
things before submitting a proper patch, thanks!

I did more tests and it turns out that there I find no real benefit
of registering only the controller for the boot device.
The initialization of the MMC/SD/eMMC is done only prior accessing
it, not when it's registered. So in terms of boot time the impact of
registering many controllers is not significant.
By registering the same controllers in SPL and in u-boot, we would
get the same mapping for the MMC devices in SPL and u-boot. It would
remove a source of confusion and of #ifdef CONFIG_SPL_BUILD

The catch is that many boards register only one MMC controller in
the SPL, depending on what the boot source is (ex: board_mmc_init()
in board/freescale/mx6slevk/mx6slevk.c)
To reduce the risk of regression, we could deal with those boards in
2 steps:
1) Don't change the code of the board except to override the weak
function mmc_get_env_dev() and make it return 0. This is not likely
to introduce a regression
2) One by one, change the code of the boards to register all the
controllers in SPL as done in u-boot. Also we need to adapt
spl_boot_device() to return the right boot device. There has been a
partial attempt at this ""ARM: mx6: add MMC2 boot device detection
support in SPL" but had to be reverted probably because it was not
coherent with the registration of the controllers.

Due to the issue you mention in #2, we probably need to do #1 and with
care and testing, as there's enough places that assume SPL is a single
MMC device that it'll be problematic to do them one at a time.
I made a survey of the code in 2017.01 to identify the platforms that 
may be impacted by the change in env_mmc.c


Here is the method:
1)  *  find the platforms that override mmc_get_env_dev(). Those may not 
rely on CONFIG_SYS_MMC_ENV_DEV to get the MMC device where the env is 
stored.

* find the platforms that define CONFIG_SYS_MMC_ENV_DEV as not 0
2) Find the paltforms that use CONFIG_SPL_ENV_SUPPORT
3) Cross the info from 1 and 2 to get the platforms that may be impacted 
by the change



1) Platforms that my use a device that is not dev 0 for en storage:

$ git grep -w mmc_get_env_dev
arch/arm/cpu/armv7/mx6/soc.c:int mmc_get_env_dev(void)
arch/arm/cpu/armv7/mx7/soc.c:int mmc_get_env_dev(void)
arch/arm/mach-uniphier/boot-mode/boot-mode.c:int mmc_get_env_dev(void)
board/freescale/mx7dsabresd/mx7dsabresd.c:  u32 dev_no = 
mmc_get_env_dev();

common/env_mmc.c:__weak int mmc_get_env_dev(void)
common/env_mmc.c:   int dev = mmc_get_env_dev();
common/env_mmc.c:   int dev = mmc_get_env_dev();
common/env_mmc.c:   int dev = mmc_get_env_dev();
common/env_mmc.c:   int dev = mmc_get_env_dev();
common/env_mmc.c:   int dev = mmc_get_env_dev();
include/mmc.h:int mmc_get_env_dev(void);


$ git grep -e 'ne\sCONFIG_SYS_MMC_ENV_DEV\s*[1-9a-zA-Z\(\)]' include/
include/configs/am335x_evm.h:#define CONFIG_SYS_MMC_ENV_DEV 1
include/configs/am335x_shc.h:#define CONFIG_SYS_MMC_ENV_DEV 1
include/configs/am335x_sl50.h:#define CONFIG_SYS_MMC_ENV_DEV1
include/configs/bav335x.h:#define CONFIG_SYS_MMC_ENV_DEV1
include/configs/cm_t54.h:#define CONFIG_SYS_MMC_ENV_DEV 1   
/* SLOT2: eMMC(1) */
include/configs/dra7xx_evm.h:#define CONFIG_SYS_MMC_ENV_DEV 
1   /* SLOT2: eMMC(1) */

include/configs/el6x_common.h:#define CONFIG_SYS_MMC_ENV_DEV1
include/configs/embestmx6boards.h:#define 
CONFIG_SYS_MMC_ENV_DEV2   /* SDHC4 */

include/configs/evb_rk3288.h:#define CONFIG_SYS_MMC_ENV_DEV 1
include/configs/evb_rk3399.h:#define CONF

[U-Boot] [PATCH v1] cmd: gpt: backup boot code before writing MBR

2017-01-30 Thread Andy Shevchenko
From: Vincent Tinelli 

On some cases the first 440 bytes of MBR are used to keep an additional
information for ROM boot loader. 'gpt write' command doesn't preserve
that area and makes boot code gone.

Preserve boot code area when run 'gpt write' command.

Signed-off-by: Vincent Tinelli 
Signed-off-by: Brennan Ashton 
Signed-off-by: Andy Shevchenko 
---
 disk/part_efi.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/disk/part_efi.c b/disk/part_efi.c
index 19243380da..fcb267b42a 100644
--- a/disk/part_efi.c
+++ b/disk/part_efi.c
@@ -324,6 +324,13 @@ static int set_protective_mbr(struct blk_desc *dev_desc)
printf("%s: calloc failed!\n", __func__);
return -1;
}
+
+   /* Read MBR to backup boot code if it exists */
+   if (blk_dread(dev_desc, 0, 1, p_mbr) != 1) {
+   error("** Can't read from device %d **\n", dev_desc->devnum);
+   return -1;
+   }
+
/* Append signature */
p_mbr->signature = MSDOS_MBR_SIGNATURE;
p_mbr->partition_record[0].sys_ind = EFI_PMBR_OSTYPE_EFI_GPT;
-- 
2.11.0

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[U-Boot] HAB and fuse reading

2017-01-30 Thread Vincent
Hi !
I'm wondering why the is_hab_enabled function (see
arch/arm/imx-common/hab.c) is reading the fuses rather than the OCOTP
shadow registers ?
During my attempts at secure boot I realized two things:
- by default, if secure boot is not enabled, the HAB rom will block any
authenticate code
- if the secure boot fuse is not burnt, but the shadow register is written
by software before calling the HAB entry point, authenticate works fine.

Since the ROM seems to read the shadow register rather than the fuse, why
is u-boot doing differently ?

Best regards,
Vincent
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Re: [U-Boot] [PATCH 2/3] armv8: fsl-lsch3: Update VID support

2017-01-30 Thread Priyanka Jain


> -Original Message-
> From: york sun
> Sent: Friday, January 27, 2017 11:13 PM
> To: Priyanka Jain ; u-boot@lists.denx.de
> Cc: Arpit Goel 
> Subject: Re: [PATCH 2/3] armv8: fsl-lsch3: Update VID support
> 
> On 01/18/2017 09:43 PM, Priyanka Jain wrote:
> > VID support in NXP layerscape Chassis-3 (lsch3) compilant SoCs like
> > LS2088A, LS2080A differs from existing logic.
> > -VDD voltage array is different
> > -Registers are different
> > -VDD calculation logic is different
> >
> > Add new function adjust_vdd() for LSCH3 compliant SoCs
> >
> > Signed-off-by: Priyanka Jain 
> > Signed-off-by: Arpit Goel 
> > ---
> >  .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |4 +-
> >  board/freescale/common/vid.c   |  174 
> > ++--
> >  2 files changed, 164 insertions(+), 14 deletions(-)
> >
> > diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> > b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> > index 38a6d03..fc4d33b 100644
> > --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> > +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> > @@ -187,9 +187,9 @@ struct ccsr_gur {
> > u32 gpporcr3;
> > u32 gpporcr4;
> > u8  res_030[0x60-0x30];
> > -#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 25
> > +#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 2
> >  #define FSL_CHASSIS3_DCFG_FUSESR_VID_MASK  0x1F
> > -#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT  20
> > +#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT  7
> >  #define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK   0x1F
> 
> 
> Priyanka,
> 
> You changed the fuse register offset and fuse position in this and previous 
> patch
> of this set. What's going on? I presume you have verified it on LS2080ARDB.
> How did it work before? Do we have two fuse status registers?
> 
> York

York,

These code changes are valid for both LS2080A and LS2088A.
VID was not working before on LS2080A also.

Priyanka
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Re: [U-Boot] [PATCH v2] SPL: add support to boot from a partition type

2017-01-30 Thread Alexander Graf

On 01/29/2017 04:13 AM, Dalon Westergreen wrote:

From: Dalon Westergreen 

the socfpga bootrom supports mmc booting from either a raw image
starting at 0x0, or from a partition of type 0xa2.  This patch
adds support for locating the boot image in the first type 0xa2
partition found.

Signed-off-by: Dalon Westergreen 
---
  common/spl/Kconfig   | 17 +
  common/spl/spl_mmc.c | 13 +
  disk/part_dos.c  |  1 +
  include/part.h   |  1 +
  4 files changed, 32 insertions(+)

diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index b1aa148..a0430ec 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -97,6 +97,23 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
  Address on the MMC to load U-Boot from, when the MMC is being used
  in raw mode. Units: MMC sectors (1 sector = 512 bytes).
  
+config SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE

+   bool "MMC raw mode: by partition type"
+   depends on SPL


This also depends on CONFIG_DOS_PARTITION, right? IIRC Tom just merged a 
patch set that moved it to kconfig, so you can depend on it here now.



+   default y if ARCH_SOCFPGA
+   help
+ Use partition type for specifying U-Boot partition on MMC/SD in
+ raw mode. U-Boot will be loaded from the first partition of this
+ type to be found.
+
+config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
+   hex "Partition Type on the MMC to load U-Boot from"
+   depends on SPL && SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
+   default 0xa2 if ARCH_SOCFPGA


What's the default for others platforms? In fact, why would any other 
platform care?


IMHO the best thing to do for now is to instead of "default y" to set it 
as "depends on ARCH_SOCFPGA". That way we don't accidentally add support 
for booting 0x00 type partitions to other systems ;).


Alternatively if you think it's nicer to allow non-Altera 
implementations to boot from partition with a simple kconfig switch, 
just always default to 0xa2 ragardless of arch.



+   help
+ Partition Type on the MMC to load U-Boot from, when the MMC is being
+ used in raw mode.
+
  config TPL
bool
depends on SPL && SUPPORT_TPL
diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index 0cd355c..cce9584 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -157,6 +157,19 @@ static int mmc_load_image_raw_partition(struct 
spl_image_info *spl_image,
disk_partition_t info;
int err;
  
+#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE

+   if ( partition == -1 ) {
+   /* Only support MBR so DOS_ENTRY_NUMBERS */
+   for (partition = 1; partition <= DOS_ENTRY_NUMBERS; 
partition++) {
+   err = part_get_info(mmc_get_blk_desc(mmc), partition, 
&info);
+   if(err)
+   continue;
+   if(info.sys_ind == 
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE)
+   break;
+   }
+   }
+#endif
+
err = part_get_info(mmc_get_blk_desc(mmc), partition, &info);
if (err) {
  #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
diff --git a/disk/part_dos.c b/disk/part_dos.c
index ed78334..f485f11 100644
--- a/disk/part_dos.c
+++ b/disk/part_dos.c
@@ -217,6 +217,7 @@ static int part_get_info_extended(struct blk_desc *dev_desc,
  #ifdef CONFIG_PARTITION_UUIDS
sprintf(info->uuid, "%08x-%02x", disksig, part_num);
  #endif
+   info->sys_ind = pt->sys_ind;
return 0;
}
  
diff --git a/include/part.h b/include/part.h

index 0979005..a58b687 100644
--- a/include/part.h
+++ b/include/part.h
@@ -59,6 +59,7 @@ typedef struct disk_partition {
  #ifdef CONFIG_PARTITION_TYPE_GUID
chartype_guid[37];  /* type GUID as string, if exists   */
  #endif
+   uchar   sys_ind;/* partition type   */


Shouldn't that also be #ifdef'ed to CONFIG_DOS_PARTITION? At least the 
field semantic would be obvious then.



Alex

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Re: [U-Boot] [PATCH] drivers: net: fsl-mc: Fixup MAC addresses in DPC

2017-01-30 Thread Prabhakar Kushwaha
Hi York,


> -Original Message-
> From: york sun
> Sent: Saturday, January 28, 2017 2:15 AM
> To: Prabhakar Kushwaha ; Bogdan Purcareata
> ; u-boot@lists.denx.de
> Subject: Re: [PATCH] drivers: net: fsl-mc: Fixup MAC addresses in DPC
> 
> On 01/26/2017 05:05 AM, Prabhakar Kushwaha wrote:
> >
> >> -Original Message-
> >> From: Bogdan Purcareata [mailto:bogdan.purcare...@nxp.com]
> >> Sent: Thursday, January 11, 2017 9:35 AM
> >> To: u-boot@lists.denx.de
> >> Cc: Bogdan Purcareata 
> >> Subject: [PATCH] drivers: net: fsl-mc: Fixup MAC addresses in DPC
> >>
> >> Fixup port_mac_address property in MC DPC with values from the u-boot
> >> environment. Since u-boot already reads the environment MAC addresses
> >> when probing the PHYs, use these values.
> >>
> >> The u-boot environment MAC addresses take precedence over any eventual
> >> ones defined in the DPC, except for the case where they are randomly
> >> assigned (no u-boot env value declared for port).
> >>
> >> The patch assumes the "/board_info/ports/" node is present in the DPC.
> >>
> >> Signed-off-by: Bogdan Purcareata 
> >
> > Reviewed-by: Prabhakar Kushwaha 
> >
> 
> Prabhakar,
> 
> I don't know how you replied with your comment. But your email client
> changed the message ID so patchwork couldn't match it.
> 

Oh..  
Looks like I did some mistake... 

Will it be possible to provide original message/mail which was sent on the 
mailing list so that I can provide "review-by" again

--prabhakar

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Re: [U-Boot] [PATCH v8 1/7] arm: socfpga: add env settings to common header

2017-01-30 Thread Alexander Graf

On 01/29/2017 12:05 AM, Dalon Westergreen wrote:

From: Dalon Westergreen 

Move repeated environment settings for socfpga boards
to a common header.

The default values for the boot partition and the
OS filesystem partition have changed and as
as result the default uboot environment for socfpga
boards needs updating.

Move to using  CONFIG_DEFAULT_DEVICE_TREE for setting the
default linux devicetree used during linux boot.

Signed-off-by: Dalon Westergreen 
---
  include/configs/socfpga_common.h | 35 +--
  1 file changed, 33 insertions(+), 2 deletions(-)

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 6285266..744aee9 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -312,10 +312,14 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
  /* SPL SDMMC boot support */
  #ifdef CONFIG_SPL_MMC_SUPPORT
  #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
-#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 2
  #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME   "u-boot-dtb.img"
+#ifdef CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
+#else
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 2
+#endif
  #else
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 3
  #endif
  #endif
  
@@ -336,5 +340,32 @@ unsigned int cm_get_qspi_controller_clk_hz(void);

   * Stack setup
   */
  #define CONFIG_SPL_STACK  CONFIG_SYS_INIT_SP_ADDR
+   
+/* Extra Environment */
+#ifndef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+   "verify=n\0" \
+   "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+   "bootimage=" CONFIG_BOOTFILE "\0" \
+   "fdt_addr=100\0" \
+   "fdtimage=" CONFIG_DEFAULT_FDT_FILE "\0" \
+   "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
+   "bootm ${loadaddr} - ${fdt_addr}\0" \
+   "mmcroot=/dev/mmcblk0p2\0" \
+   "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
+   " root=${mmcroot} rw rootwait;" \
+   "bootz ${loadaddr} - ${fdt_addr}\0" \
+   "mmcload=mmc rescan;" \
+   "load mmc 0:1 ${loadaddr} ${bootimage};" \
+   "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
+   "qspiload=sf probe && mtdparts default && run ubiload\0" \
+   "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
+   " ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\
+   "bootz ${loadaddr} - ${fdt_addr}\0" \
+   "ubiload=ubi part UBI && ubifsmount ubi0 && " \
+   "ubifsload ${loadaddr} /boot/${bootimage} && " \
+   "ubifsload ${fdt_addr} /boot/${fdtimage}\0"


What is the default bootcmd with this environment? Also, keep in mind 
that it's 2017. Is there any good reason not to default to distro boot?



Alex

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Re: [U-Boot] [PATCH v8 2/7] arm: socfpga: update de0 nano default environment

2017-01-30 Thread Alexander Graf

On 01/29/2017 12:05 AM, Dalon Westergreen wrote:

From: Dalon Westergreen 

Remove the default environment as it is now in a common
header.

Add the CONFIG_DEFAULT_DEVICE_TREE to the board's defconfig
to set the linux devicetree name.

Signed-off-by: Dalon Westergreen 
Acked-by: Marek Vasut 
---
  configs/socfpga_de0_nano_soc_defconfig |  3 +--
  include/configs/socfpga_common.h   |  2 +-
  include/configs/socfpga_de0_nano_soc.h | 19 +--
  3 files changed, 3 insertions(+), 21 deletions(-)

diff --git a/configs/socfpga_de0_nano_soc_defconfig 
b/configs/socfpga_de0_nano_soc_defconfig
index af41e1e..4837809 100644
--- a/configs/socfpga_de0_nano_soc_defconfig
+++ b/configs/socfpga_de0_nano_soc_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
  CONFIG_TARGET_SOCFPGA_TERASIC_DE0_NANO=y
  CONFIG_SPL_STACK_R_ADDR=0x0080
  CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de0_nano_soc"
+CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_de0_sockit.dtb"
  CONFIG_FIT=y
  CONFIG_SYS_CONSOLE_IS_IN_ENV=y
  CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
@@ -20,7 +21,6 @@ CONFIG_CMD_ASKENV=y
  CONFIG_CMD_GREPENV=y
  # CONFIG_CMD_FLASH is not set
  CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y


This change is not mentioned in teh change log?


  CONFIG_CMD_SPI=y
  CONFIG_CMD_I2C=y
  CONFIG_CMD_USB=y
@@ -35,7 +35,6 @@ CONFIG_CMD_EXT4=y
  CONFIG_CMD_EXT4_WRITE=y
  CONFIG_CMD_FAT=y
  CONFIG_CMD_FS_GENERIC=y
-CONFIG_CMD_UBI=y


Neither is this.


  CONFIG_SPL_DM=y
  CONFIG_DFU_MMC=y
  CONFIG_DM_GPIO=y
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 744aee9..ed6d8ea 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -319,7 +319,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
  #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION2
  #endif
  #else
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 3
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1
  #endif
  #endif
  
diff --git a/include/configs/socfpga_de0_nano_soc.h b/include/configs/socfpga_de0_nano_soc.h

index 6b9546e..97216ea 100644
--- a/include/configs/socfpga_de0_nano_soc.h
+++ b/include/configs/socfpga_de0_nano_soc.h
@@ -18,7 +18,7 @@
  #define PHYS_SDRAM_1_SIZE 0x4000  /* 1GiB */
  
  /* Booting Linux */

-#define CONFIG_BOOTFILE"fitImage"
+#define CONFIG_BOOTFILE"zImage"
  #define CONFIG_BOOTARGS   "console=ttyS0," 
__stringify(CONFIG_BAUDRATE)
  #define CONFIG_BOOTCOMMAND"run mmcload; run mmcboot"


... oh, I see. So the default boot command is defined per-target rather 
than generically.


Loading a predefined file name (usually also + initrd file) + dtb file 
from mmc sounds like something that would be generically useful to 
boards that want to support legacy boot paths. Take a look at the 
SCAN_DEV_FOR_EFI define in include/config_distro_bootcmd.h. Something 
along those lines to replace mmcload/mmcboot should work for you, right?


That way your boot script would search for legacy boot options as well 
as fancy awesome state-of-the-art extlinux/efi ones.



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Re: [U-Boot] [PATCH v8 5/7] arm: socfpga: Update DE1 environment

2017-01-30 Thread Alexander Graf

On 01/29/2017 12:05 AM, Dalon Westergreen wrote:

From: Dalon Westergreen 

Remove the default environment as it is now in a common
header.

Add the CONFIG_DEFAULT_DEVICE_TREE to the board's defconfig
to set the linux devicetree name.

Signed-off-by: Dalon Westergreen 
Acked-by: Marek Vasut 
Acked-by: Dinh Nguyen 
---
  configs/socfpga_de1_soc_defconfig |  1 +
  include/configs/socfpga_de1_soc.h | 19 +--
  2 files changed, 2 insertions(+), 18 deletions(-)

diff --git a/configs/socfpga_de1_soc_defconfig 
b/configs/socfpga_de1_soc_defconfig
index 032deef..d78e8a1 100644
--- a/configs/socfpga_de1_soc_defconfig
+++ b/configs/socfpga_de1_soc_defconfig
@@ -6,6 +6,7 @@ CONFIG_TARGET_SOCFPGA_TERASIC_DE1_SOC=y
  CONFIG_SPL_STACK_R_ADDR=0x0080
  CONFIG_SPL_YMODEM_SUPPORT=y
  CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de1_soc"
+CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_de1_soc.dtb"
  CONFIG_FIT=y
  CONFIG_SYS_CONSOLE_IS_IN_ENV=y
  CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
diff --git a/include/configs/socfpga_de1_soc.h 
b/include/configs/socfpga_de1_soc.h
index deec647..3142bd1 100644
--- a/include/configs/socfpga_de1_soc.h
+++ b/include/configs/socfpga_de1_soc.h
@@ -18,7 +18,7 @@
  #define PHYS_SDRAM_1_SIZE 0x4000  /* 1GiB */
  
  /* Booting Linux */

-#define CONFIG_BOOTFILE"fitImage"
+#define CONFIG_BOOTFILE"zImage"


ok, here you're confusing me. I thought the point of having the crude, 
hacky mmcload/mmcboot in bootcmd was because you want to be legacy 
compatible. If you're changing the bootfile name, that point is moot.


So at this point, why not just switch to distro boot and extlinux.conf / 
efi altogether?



Alex

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Re: [U-Boot] [PATCH v8 1/7] arm: socfpga: add env settings to common header

2017-01-30 Thread Dalon Westergreen
On Mon, 2017-01-30 at 15:55 +0100, Alexander Graf wrote:
> On 01/29/2017 12:05 AM, Dalon Westergreen wrote:
> > 
> > From: Dalon Westergreen 
> > 
> > Move repeated environment settings for socfpga boards
> > to a common header.
> > 
> > The default values for the boot partition and the
> > OS filesystem partition have changed and as
> > as result the default uboot environment for socfpga
> > boards needs updating.
> > 
> > Move to using  CONFIG_DEFAULT_DEVICE_TREE for setting the
> > default linux devicetree used during linux boot.
> > 
> > Signed-off-by: Dalon Westergreen 
> > ---
> >   include/configs/socfpga_common.h | 35 +--
> >   1 file changed, 33 insertions(+), 2 deletions(-)
> > 
> > diff --git a/include/configs/socfpga_common.h
> > b/include/configs/socfpga_common.h
> > index 6285266..744aee9 100644
> > --- a/include/configs/socfpga_common.h
> > +++ b/include/configs/socfpga_common.h
> > @@ -312,10 +312,14 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
> >   /* SPL SDMMC boot support */
> >   #ifdef CONFIG_SPL_MMC_SUPPORT
> >   #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
> > -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 2
> >   #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME   "u-boot-dtb.img"
> > +#ifdef CONFIG_SPL_FAT_SUPPORT
> > +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
> > +#else
> > +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 2
> > +#endif
> >   #else
> > -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1
> > +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 3
> >   #endif
> >   #endif
> >   
> > @@ -336,5 +340,32 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
> >    * Stack setup
> >    */
> >   #define CONFIG_SPL_STACK  CONFIG_SYS_INIT_SP_ADDR
> > +   
> > +/* Extra Environment */
> > +#ifndef CONFIG_EXTRA_ENV_SETTINGS
> > +#define CONFIG_EXTRA_ENV_SETTINGS \
> > +   "verify=n\0" \
> > +   "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
> > +   "bootimage=" CONFIG_BOOTFILE "\0" \
> > +   "fdt_addr=100\0" \
> > +   "fdtimage=" CONFIG_DEFAULT_FDT_FILE "\0" \
> > +   "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
> > +   "bootm ${loadaddr} - ${fdt_addr}\0" \
> > +   "mmcroot=/dev/mmcblk0p2\0" \
> > +   "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
> > +   " root=${mmcroot} rw rootwait;" \
> > +   "bootz ${loadaddr} - ${fdt_addr}\0" \
> > +   "mmcload=mmc rescan;" \
> > +   "load mmc 0:1 ${loadaddr} ${bootimage};" \
> > +   "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
> > +   "qspiload=sf probe && mtdparts default && run ubiload\0" \
> > +   "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
> > +   " ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\
> > +   "bootz ${loadaddr} - ${fdt_addr}\0" \
> > +   "ubiload=ubi part UBI && ubifsmount ubi0 && " \
> > +   "ubifsload ${loadaddr} /boot/${bootimage} && " \
> > +   "ubifsload ${fdt_addr} /boot/${fdtimage}\0"
> 
> What is the default bootcmd with this environment? Also, keep in mind 
> that it's 2017. Is there any good reason not to default to distro boot?
> 
> 
> Alex
> 
The default is board dependent, but in general is mmcboot. there is no
good reason to not use distro boot.  Frank Kunz submitted something
to that end for one of these boards the other day.  once the 
environment common, we will move to distro boot.
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Re: [U-Boot] [PATCH v8 1/7] arm: socfpga: add env settings to common header

2017-01-30 Thread Alexander Graf

On 01/30/2017 04:11 PM, Dalon Westergreen wrote:

On Mon, 2017-01-30 at 15:55 +0100, Alexander Graf wrote:

On 01/29/2017 12:05 AM, Dalon Westergreen wrote:

From: Dalon Westergreen 

Move repeated environment settings for socfpga boards
to a common header.

The default values for the boot partition and the
OS filesystem partition have changed and as
as result the default uboot environment for socfpga
boards needs updating.

Move to using  CONFIG_DEFAULT_DEVICE_TREE for setting the
default linux devicetree used during linux boot.

Signed-off-by: Dalon Westergreen 
---
   include/configs/socfpga_common.h | 35 +--
   1 file changed, 33 insertions(+), 2 deletions(-)

diff --git a/include/configs/socfpga_common.h
b/include/configs/socfpga_common.h
index 6285266..744aee9 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -312,10 +312,14 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
   /* SPL SDMMC boot support */
   #ifdef CONFIG_SPL_MMC_SUPPORT
   #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
-#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 2
   #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME  "u-boot-dtb.img"
+#ifdef CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
+#else
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 2
+#endif
   #else
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 3
   #endif
   #endif
   
@@ -336,5 +340,32 @@ unsigned int cm_get_qspi_controller_clk_hz(void);

* Stack setup
*/
   #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
+   
+/* Extra Environment */
+#ifndef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+   "verify=n\0" \
+   "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+   "bootimage=" CONFIG_BOOTFILE "\0" \
+   "fdt_addr=100\0" \
+   "fdtimage=" CONFIG_DEFAULT_FDT_FILE "\0" \
+   "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
+   "bootm ${loadaddr} - ${fdt_addr}\0" \
+   "mmcroot=/dev/mmcblk0p2\0" \
+   "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
+   " root=${mmcroot} rw rootwait;" \
+   "bootz ${loadaddr} - ${fdt_addr}\0" \
+   "mmcload=mmc rescan;" \
+   "load mmc 0:1 ${loadaddr} ${bootimage};" \
+   "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
+   "qspiload=sf probe && mtdparts default && run ubiload\0" \
+   "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
+   " ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\
+   "bootz ${loadaddr} - ${fdt_addr}\0" \
+   "ubiload=ubi part UBI && ubifsmount ubi0 && " \
+   "ubifsload ${loadaddr} /boot/${bootimage} && " \
+   "ubifsload ${fdt_addr} /boot/${fdtimage}\0"

What is the default bootcmd with this environment? Also, keep in mind
that it's 2017. Is there any good reason not to default to distro boot?


Alex


The default is board dependent, but in general is mmcboot. there is no
good reason to not use distro boot.  Frank Kunz submitted something
to that end for one of these boards the other day.  once the
environment common, we will move to distro boot.



Ok, that sounds like a reasonable plan to me :)


Alex


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[U-Boot] [u-boot PATCH v2 0/8] am57xx-idk LCD and am571x-idk 6 port ethernet pinmux

2017-01-30 Thread Roger Quadros
Hi,

This series contains

- Support am571x-idk LCD vs 6 port ethernet pinmux configuration.
- AM57xx-idk LCD detection support.
- K2G: pick up PRUSS ethernet MAC addresses from board EEPROM.

Changelog:
v2:
- avoid using __maybe_unused.
- moved EEPROM address configuration to Kconfig.
- LCD detection patch no longer update device tree.

cheers,
-roger

Lokesh Vutla (1):
  ti: common: board_detect: Rename EEPROM scratch start macro

Nishanth Menon (1):
  board: ti: am57xx-idk: Auto detect LCD Panel

Roger Quadros (6):
  ARM: OMAP5+: GPIO: Add GPIO_TO_PIN() macro
  ti: common: board_detect: commodify ethaddr environment setting code
  board: ti: am571x-idk: Support 6 port Ethernet or 4 port Ethernet with
LCD
  board: ti: am571x-idk: Update pinmux for ICSS2 Ethernet
  ARM: Use Kconfig for board EEPROM's I2C bus and chip address
  ARM: k2g: setup PRU ethernet MAC addresses

 arch/arm/Kconfig   |  10 ++
 arch/arm/include/asm/arch-omap5/gpio.h |   4 +
 arch/arm/include/asm/omap_common.h |   8 +-
 board/ti/am57xx/board.c| 102 
 board/ti/am57xx/mux_data.h | 166 -
 board/ti/common/board_detect.c |  57 +++
 board/ti/common/board_detect.h |  14 ++-
 board/ti/ks2_evm/board_k2g.c   |  19 
 configs/am57xx_evm_defconfig   |   2 +
 configs/am57xx_evm_nodt_defconfig  |   2 +
 configs/am57xx_hs_evm_defconfig|   2 +
 configs/dra7xx_evm_defconfig   |   2 +
 configs/dra7xx_hs_evm_defconfig|   2 +
 configs/k2g_evm_defconfig  |   2 +
 include/configs/am57xx_evm.h   |   4 -
 include/configs/dra7xx_evm.h   |   4 -
 16 files changed, 322 insertions(+), 78 deletions(-)

-- 
2.7.4

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[U-Boot] [u-boot PATCH v2 2/8] ti: common: board_detect: commodify ethaddr environment setting code

2017-01-30 Thread Roger Quadros
Keystone and OMAP platforms will need this to set ethernet
MAC addresses from board EEPROM.

Signed-off-by: Roger Quadros 
---
 board/ti/common/board_detect.c | 57 ++
 board/ti/common/board_detect.h | 12 +
 2 files changed, 69 insertions(+)

diff --git a/board/ti/common/board_detect.c b/board/ti/common/board_detect.c
index a5dba94..23388d0 100644
--- a/board/ti/common/board_detect.c
+++ b/board/ti/common/board_detect.c
@@ -314,3 +314,60 @@ void __maybe_unused set_board_info_env(char *name)
else
setenv("board_serial", unknown);
 }
+
+static u64 mac_to_u64(u8 mac[6])
+{
+   int i;
+   u64 addr = 0;
+
+   for (i = 0; i < 6; i++) {
+   addr <<= 8;
+   addr |= mac[i];
+   }
+
+   return addr;
+}
+
+static void u64_to_mac(u64 addr, u8 mac[6])
+{
+   mac[5] = addr;
+   mac[4] = addr >> 8;
+   mac[3] = addr >> 16;
+   mac[2] = addr >> 24;
+   mac[1] = addr >> 32;
+   mac[0] = addr >> 40;
+}
+
+void board_ti_set_ethaddr(int index)
+{
+   uint8_t mac_addr[6];
+   int i;
+   u64 mac1, mac2;
+   u8 mac_addr1[6], mac_addr2[6];
+   int num_macs;
+   /*
+* Export any Ethernet MAC addresses from EEPROM.
+* The 2 MAC addresses in EEPROM define the address range.
+*/
+   board_ti_get_eth_mac_addr(0, mac_addr1);
+   board_ti_get_eth_mac_addr(1, mac_addr2);
+
+   if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
+   mac1 = mac_to_u64(mac_addr1);
+   mac2 = mac_to_u64(mac_addr2);
+
+   /* must contain an address range */
+   num_macs = mac2 - mac1 + 1;
+   /* <= 50 to protect against user programming error */
+   if (num_macs > 0 && num_macs <= 50) {
+   for (i = 0; i < num_macs; i++) {
+   u64_to_mac(mac1 + i, mac_addr);
+   if (is_valid_ethaddr(mac_addr)) {
+   eth_setenv_enetaddr_by_index("eth",
+i + index,
+mac_addr);
+   }
+   }
+   }
+   }
+}
diff --git a/board/ti/common/board_detect.h b/board/ti/common/board_detect.h
index 343fcb4..4bcb64f 100644
--- a/board/ti/common/board_detect.h
+++ b/board/ti/common/board_detect.h
@@ -193,4 +193,16 @@ u64 board_ti_get_emif2_size(void);
  */
 void set_board_info_env(char *name);
 
+/**
+ * board_ti_set_ethaddr- Sets the ethaddr environment from EEPROM
+ * @index: The first ethaddr environment variable to set
+ *
+ * EEPROM should be already read before calling this function.
+ * The EEPROM contains 2 MAC addresses which define the MAC address
+ * range (i.e. first and last MAC address).
+ * This function sets the ethaddr environment variable for all
+ * the available MAC addresses starting from ethaddr.
+ */
+void board_ti_set_ethaddr(int index);
+
 #endif /* __BOARD_DETECT_H */
-- 
2.7.4

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[U-Boot] [u-boot PATCH v2 1/8] ARM: OMAP5+: GPIO: Add GPIO_TO_PIN() macro

2017-01-30 Thread Roger Quadros
GPIO_TO_PIN(bank, bank_gpio) returns the GPIO index
from the GPIO bank number and bank's GPIO offset number.

Signed-off-by: Roger Quadros 
Reviewed-by: Tom Rini 
---
 arch/arm/include/asm/arch-omap5/gpio.h | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/include/asm/arch-omap5/gpio.h 
b/arch/arm/include/asm/arch-omap5/gpio.h
index 9dd03c9..48e8ca5 100644
--- a/arch/arm/include/asm/arch-omap5/gpio.h
+++ b/arch/arm/include/asm/arch-omap5/gpio.h
@@ -34,4 +34,8 @@
 #define OMAP54XX_GPIO7_BASE0x48051000
 #define OMAP54XX_GPIO8_BASE0x48053000
 
+
+/* Get the GPIO index from the given bank number and bank gpio */
+#define GPIO_TO_PIN(bank, bank_gpio)   (32 * (bank - 1) + (bank_gpio))
+
 #endif /* _GPIO_OMAP5_H */
-- 
2.7.4

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[U-Boot] [u-boot PATCH v2 3/8] board: ti: am571x-idk: Support 6 port Ethernet or 4 port Ethernet with LCD

2017-01-30 Thread Roger Quadros
The board can support either ICSS1 Ethernet ports or LCD
based on J51 jumper. Factory default is ICSS1 Ethernet ports
(i.e. Jumper not populated).

Use the GPIO to detect the jumper setting and configure the
pinmux accordingly. Also select the right DT blob based on
the chosen configuration.

J51 absent -> ICSS1 Ethernet, no LCD on VOUT -> am571x-idk.dtb
J51 present -> LCD on VOUT, no ICSS1 Ethernet -> am571x-idk-lcd-osd.dtb

At present we only support the assume it is the Legacy LCD.
LCD detection mechanism needs to be added later to differentiate
between legacy vs new LCD.

For ICSS1 Ethernet pins use the following convention to set the pinmux
as PMT data is not yet finalized.

- If pin is output, set as PIN_OUTPUT
- If pin is input and external pull resistor present set as PIN_INPUT
- If pin is input and external pull resistor absent, set pull to same
as that of the external PHY's internall pull.
- Do not use SLEW_CONTROLon any pin.

Cc: Nishanth Menon 
Signed-off-by: Roger Quadros 
Reviewed-by: Tom Rini 
---
 board/ti/am57xx/board.c|  40 +
 board/ti/am57xx/mux_data.h | 104 ++---
 2 files changed, 109 insertions(+), 35 deletions(-)

diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index 5f2d4df..81ad86c 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -50,6 +50,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define GPIO_ETH_LCD   GPIO_TO_PIN(2, 22)
 /* GPIO 7_11 */
 #define GPIO_DDR_VTT_EN 203
 
@@ -449,6 +450,21 @@ void hw_data_init(void)
*ctrl = &dra7xx_ctrl;
 }
 
+bool am571x_idk_needs_lcd(void)
+{
+   bool needs_lcd;
+
+   gpio_request(GPIO_ETH_LCD, "nLCD_Detect");
+   if (gpio_get_value(GPIO_ETH_LCD))
+   needs_lcd = false;
+   else
+   needs_lcd = true;
+
+   gpio_free(GPIO_ETH_LCD);
+
+   return needs_lcd;
+}
+
 int board_init(void)
 {
gpmc_init();
@@ -459,6 +475,8 @@ int board_init(void)
 
 int board_late_init(void)
 {
+   char *idk_lcd;
+
setup_board_eeprom_env();
u8 val;
 
@@ -487,6 +505,17 @@ int board_late_init(void)
palmas_i2c_write_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
val);
 
+   /* TBD: Add LCD panel detection once information is available */
+   if (am571x_idk_needs_lcd())
+   idk_lcd = "osd101t2045"; /* Default to legacy LCD */
+   else
+   idk_lcd = "no";
+   setenv("idk_lcd", idk_lcd);
+
+#if !defined(CONFIG_SPL_BUILD)
+   board_ti_set_ethaddr(2);
+#endif
+
return 0;
 }
 
@@ -549,6 +578,17 @@ void recalibrate_iodelay(void)
do_set_mux32((*ctrl)->control_padconf_core_base, pconf, 
pconf_sz);
}
 
+   if (board_is_am571x_idk()) {
+   if (am571x_idk_needs_lcd()) {
+   pconf = core_padconf_array_vout_am571x_idk;
+   pconf_sz = 
ARRAY_SIZE(core_padconf_array_vout_am571x_idk);
+   } else {
+   pconf = core_padconf_array_icss1eth_am571x_idk;
+   pconf_sz = 
ARRAY_SIZE(core_padconf_array_icss1eth_am571x_idk);
+   }
+   do_set_mux32((*ctrl)->control_padconf_core_base, pconf, 
pconf_sz);
+   }
+
/* Setup IOdelay configuration */
ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz);
 err:
diff --git a/board/ti/am57xx/mux_data.h b/board/ti/am57xx/mux_data.h
index 2f5243e..ff0e517 100644
--- a/board/ti/am57xx/mux_data.h
+++ b/board/ti/am57xx/mux_data.h
@@ -549,13 +549,6 @@ const struct pad_conf_entry 
core_padconf_array_essential_am571x_idk[] = {
{VIN2A_D0, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d0.pr1_uart0_rxd */
{VIN2A_D1, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d1.pr1_uart0_txd */
{VIN2A_D2, (M10 | PIN_INPUT_PULLDOWN)}, /* vin2a_d2.eCAP1_in_PWM1_out */
-   {VIN2A_D3, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d3.pr1_mi1_col */
-   {VIN2A_D4, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d4.pr1_mii1_txd1 */
-   {VIN2A_D5, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d5.pr1_mii1_txd0 */
-   {VIN2A_D6, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d6.pr1_mii_mt1_clk */
-   {VIN2A_D7, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d7.pr1_mii1_txen */
-   {VIN2A_D8, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d8.pr1_mii1_txd3 */
-   {VIN2A_D9, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d9.pr1_mii1_txd2 */
{VIN2A_D10, (M11 | PIN_INPUT_PULLDOWN)},/* 
vin2a_d10.pr1_mdio_mdclk */
{VIN2A_D11, (M11 | PIN_INPUT_PULLUP)},  /* vin2a_d11.pr1_mdio_data */
{VIN2A_D12, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},   /* 
vin2a_d12.rgmii1_txc */
@@ -570,35 +563,7 @@ const struct pad_conf_entry 
core_padconf_array_essential_am571x_idk[] = {
{VIN2A_D21, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* 
vin2a_d21.rgmii1_rxd2 */
{VIN2A_D22, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* 
vin2a_d22.rgmii1_rxd1 */
   

[U-Boot] [u-boot PATCH v2 4/8] board: ti: am571x-idk: Update pinmux for ICSS2 Ethernet

2017-01-30 Thread Roger Quadros
Use the same convention that was used for ICSS1 Ethernet
- If pin is output, set as PIN_OUTPUT
- If pin is input and external pull resistor present set as PIN_INPUT
- If pin is input and external pull resistor absent, set pull to same
as that of the external PHY's internall pull.

Signed-off-by: Roger Quadros 
Reviewed-by: Tom Rini 
---
 board/ti/am57xx/mux_data.h | 62 +++---
 1 file changed, 31 insertions(+), 31 deletions(-)

diff --git a/board/ti/am57xx/mux_data.h b/board/ti/am57xx/mux_data.h
index ff0e517..5485212 100644
--- a/board/ti/am57xx/mux_data.h
+++ b/board/ti/am57xx/mux_data.h
@@ -586,46 +586,46 @@ const struct pad_conf_entry 
core_padconf_array_essential_am571x_idk[] = {
{GPIO6_14, (M14 | PIN_INPUT_PULLUP)},   /* gpio6_14.gpio6_14 */
{GPIO6_15, (M14 | PIN_INPUT_PULLUP)},   /* gpio6_15.gpio6_15 */
{GPIO6_16, (M14 | PIN_INPUT_PULLDOWN)}, /* gpio6_16.gpio6_16 */
-   {XREF_CLK0, (M11 | PIN_INPUT_PULLDOWN)},/* 
xref_clk0.pr2_mii1_col */
-   {XREF_CLK1, (M11 | PIN_INPUT_PULLDOWN)},/* 
xref_clk1.pr2_mii1_crs */
+   {XREF_CLK0, (M11 | PIN_INPUT)}, /* xref_clk0.pr2_mii1_col */
+   {XREF_CLK1, (M11 | PIN_INPUT_PULLUP)},  /* xref_clk1.pr2_mii1_crs */
{XREF_CLK2, (M14 | PIN_INPUT_PULLDOWN)},/* xref_clk2.gpio6_19 */
{XREF_CLK3, (M15 | PIN_INPUT_PULLDOWN)},/* xref_clk3.Driveroff 
*/
{MCASP1_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* 
mcasp1_aclkx.pr2_mdio_mdclk */
{MCASP1_FSX, (M11 | PIN_INPUT_SLEW)},   /* mcasp1_fsx.pr2_mdio_data */
{MCASP1_ACLKR, (M14 | PIN_INPUT_PULLUP)},   /* mcasp1_aclkr.gpio5_0 
*/
{MCASP1_FSR, (M14 | PIN_INPUT_PULLUP)}, /* mcasp1_fsr.gpio5_1 */
-   {MCASP1_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)},  /* 
mcasp1_axr0.pr2_mii0_rxer */
-   {MCASP1_AXR1, (M11 | PIN_INPUT_SLEW)},  /* mcasp1_axr1.pr2_mii_mt0_clk 
*/
+   {MCASP1_AXR0, (M11 | PIN_INPUT_PULLUP)},/* 
mcasp1_axr0.pr2_mii0_rxer */
+   {MCASP1_AXR1, (M11 | PIN_INPUT_PULLDOWN)},  /* 
mcasp1_axr1.pr2_mii_mt0_clk */
{MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)},  /* mcasp1_axr2.gpio5_4 
*/
{MCASP1_AXR3, (M14 | PIN_INPUT_PULLUP)},/* mcasp1_axr3.gpio5_5 
*/
{MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)},  /* mcasp1_axr4.gpio5_6 
*/
{MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)},  /* mcasp1_axr5.gpio5_7 
*/
{MCASP1_AXR6, (M14 | PIN_INPUT_PULLUP)},/* mcasp1_axr6.gpio5_8 
*/
{MCASP1_AXR7, (M14 | PIN_INPUT_PULLUP)},/* mcasp1_axr7.gpio5_9 
*/
-   {MCASP1_AXR8, (M11 | PIN_INPUT_SLEW)},  /* mcasp1_axr8.pr2_mii0_txen */
-   {MCASP1_AXR9, (M11 | PIN_INPUT_SLEW)},  /* mcasp1_axr9.pr2_mii0_txd3 */
-   {MCASP1_AXR10, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr10.pr2_mii0_txd2 */
-   {MCASP1_AXR11, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr11.pr2_mii0_txd1 */
-   {MCASP1_AXR12, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr12.pr2_mii0_txd0 */
-   {MCASP1_AXR13, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr13.pr2_mii_mr0_clk 
*/
-   {MCASP1_AXR14, (M11 | PIN_INPUT_PULLDOWN | SLEWCONTROL)},   /* 
mcasp1_axr14.pr2_mii0_rxdv */
-   {MCASP1_AXR15, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr15.pr2_mii0_rxd3 */
-   {MCASP2_ACLKX, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_aclkx.pr2_mii0_rxd2 */
-   {MCASP2_FSX, (M11 | PIN_INPUT_SLEW)},   /* mcasp2_fsx.pr2_mii0_rxd1 */
+   {MCASP1_AXR8, (M11 | PIN_OUTPUT)},  /* mcasp1_axr8.pr2_mii0_txen */
+   {MCASP1_AXR9, (M11 | PIN_OUTPUT)},  /* mcasp1_axr9.pr2_mii0_txd3 */
+   {MCASP1_AXR10, (M11 | PIN_OUTPUT)}, /* mcasp1_axr10.pr2_mii0_txd2 */
+   {MCASP1_AXR11, (M11 | PIN_OUTPUT)}, /* mcasp1_axr11.pr2_mii0_txd1 */
+   {MCASP1_AXR12, (M11 | PIN_OUTPUT)}, /* mcasp1_axr12.pr2_mii0_txd0 */
+   {MCASP1_AXR13, (M11 | PIN_INPUT_PULLDOWN)}, /* 
mcasp1_axr13.pr2_mii_mr0_clk */
+   {MCASP1_AXR14, (M11 | PIN_INPUT_PULLDOWN)}, /* 
mcasp1_axr14.pr2_mii0_rxdv */
+   {MCASP1_AXR15, (M11 | PIN_INPUT)},  /* mcasp1_axr15.pr2_mii0_rxd3 */
+   {MCASP2_ACLKX, (M11 | PIN_INPUT)},  /* mcasp2_aclkx.pr2_mii0_rxd2 */
+   {MCASP2_FSX, (M11 | PIN_INPUT)},/* mcasp2_fsx.pr2_mii0_rxd1 */
{MCASP2_ACLKR, (M15 | PIN_INPUT_PULLDOWN)}, /* 
mcasp2_aclkr.Driveroff */
{MCASP2_FSR, (M15 | PIN_INPUT_PULLDOWN)},   /* mcasp2_fsr.Driveroff 
*/
{MCASP2_AXR0, (M15 | PIN_INPUT_PULLDOWN)},  /* 
mcasp2_axr0.Driveroff */
{MCASP2_AXR1, (M15 | PIN_INPUT_PULLDOWN)},  /* 
mcasp2_axr1.Driveroff */
-   {MCASP2_AXR2, (M11 | PIN_INPUT_SLEW)},  /* mcasp2_axr2.pr2_mii0_rxd0 */
-   {MCASP2_AXR3, (M11 | PIN_INPUT_PULLDOWN | SLEWCONTROL)},/* 
mcasp2_axr3.pr2_mii0_rxlink */
+   {MCASP2_AXR2, (M11 | PIN_INPUT)},   /* mcasp2_axr2.pr2_mii0_rxd0 */
+   {MCASP2_AXR3, (M11 | PIN_INPUT)},   /* mcasp2_axr3.pr2_mii0_rxlink 
*/
{MCASP2_AXR4, (M14 | PIN_

[U-Boot] [u-boot PATCH v2 6/8] ARM: Use Kconfig for board EEPROM's I2C bus and chip address

2017-01-30 Thread Roger Quadros
In stead of defining the board EEPROM address in the board headers
let's define them in the board config files and make them
configurable by Kconfig.

Signed-off-by: Roger Quadros 
---
 arch/arm/Kconfig  | 10 ++
 configs/am57xx_evm_defconfig  |  2 ++
 configs/am57xx_evm_nodt_defconfig |  2 ++
 configs/am57xx_hs_evm_defconfig   |  2 ++
 configs/dra7xx_evm_defconfig  |  2 ++
 configs/dra7xx_hs_evm_defconfig   |  2 ++
 include/configs/am57xx_evm.h  |  4 
 include/configs/dra7xx_evm.h  |  4 
 8 files changed, 20 insertions(+), 8 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c04adfb..19886ad 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1009,6 +1009,16 @@ config TARGET_THUNDERX_88XX
 
 endchoice
 
+config EEPROM_BUS_ADDRESS
+int "Board EEPROM's I2C bus address"
+range 0 8
+default 0
+
+config EEPROM_CHIP_ADDRESS
+hex "Board EEPROM's I2C chip address"
+range 0 0xff
+default 0x50
+
 source "arch/arm/mach-at91/Kconfig"
 
 source "arch/arm/mach-bcm283x/Kconfig"
diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index 656d991..3b3e74a 100644
--- a/configs/am57xx_evm_defconfig
+++ b/configs/am57xx_evm_defconfig
@@ -2,6 +2,8 @@ CONFIG_ARM=y
 CONFIG_OMAP54XX=y
 # CONFIG_SPL_NAND_SUPPORT is not set
 CONFIG_TARGET_AM57XX_EVM=y
+CONFIG_EEPROM_BUS_ADDRESS=0
+CONFIG_EEPROM_CHIP_ADDRESS=0x50
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_ARMV7_LPAE=y
diff --git a/configs/am57xx_evm_nodt_defconfig 
b/configs/am57xx_evm_nodt_defconfig
index b3b95f9..8d722e7 100644
--- a/configs/am57xx_evm_nodt_defconfig
+++ b/configs/am57xx_evm_nodt_defconfig
@@ -2,6 +2,8 @@ CONFIG_ARM=y
 CONFIG_OMAP54XX=y
 # CONFIG_SPL_NAND_SUPPORT is not set
 CONFIG_TARGET_AM57XX_EVM=y
+CONFIG_EEPROM_BUS_ADDRESS=0
+CONFIG_EEPROM_CHIP_ADDRESS=0x50
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig
index d920d68..36c8004 100644
--- a/configs/am57xx_hs_evm_defconfig
+++ b/configs/am57xx_hs_evm_defconfig
@@ -3,6 +3,8 @@ CONFIG_OMAP54XX=y
 CONFIG_TI_SECURE_DEVICE=y
 # CONFIG_SPL_NAND_SUPPORT is not set
 CONFIG_TARGET_AM57XX_EVM=y
+CONFIG_EEPROM_BUS_ADDRESS=0
+CONFIG_EEPROM_CHIP_ADDRESS=0x50
 CONFIG_TI_SECURE_EMIF_REGION_START=0xbe00
 CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x0200
 CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c0
diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index 1836021..3108c58 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -2,6 +2,8 @@ CONFIG_ARM=y
 CONFIG_OMAP54XX=y
 # CONFIG_SPL_NAND_SUPPORT is not set
 CONFIG_TARGET_DRA7XX_EVM=y
+CONFIG_EEPROM_BUS_ADDRESS=0
+CONFIG_EEPROM_CHIP_ADDRESS=0x50
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_ARMV7_LPAE=y
diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig
index 1d107e4..7f5ce49 100644
--- a/configs/dra7xx_hs_evm_defconfig
+++ b/configs/dra7xx_hs_evm_defconfig
@@ -4,6 +4,8 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TI_SECURE_DEVICE=y
 # CONFIG_SPL_NAND_SUPPORT is not set
 CONFIG_TARGET_DRA7XX_EVM=y
+CONFIG_EEPROM_BUS_ADDRESS=0
+CONFIG_EEPROM_CHIP_ADDRESS=0x50
 CONFIG_TI_SECURE_EMIF_REGION_START=0xbe00
 CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x0200
 CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c0
diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h
index 840502c..d9e1119 100644
--- a/include/configs/am57xx_evm.h
+++ b/include/configs/am57xx_evm.h
@@ -105,10 +105,6 @@
 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
 
-/* EEPROM */
-#define CONFIG_EEPROM_CHIP_ADDRESS 0x50
-#define CONFIG_EEPROM_BUS_ADDRESS 0
-
 /*
  * Default to using SPI for environment, etc.
  * 0x00 - 0x04 : QSPI.SPL (256KiB)
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index da458a4..46beb8b 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -264,8 +264,4 @@
 #endif
 #endif  /* NOR support */
 
-/* EEPROM */
-#define CONFIG_EEPROM_CHIP_ADDRESS 0x50
-#define CONFIG_EEPROM_BUS_ADDRESS 0
-
 #endif /* __CONFIG_DRA7XX_EVM_H */
-- 
2.7.4

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[U-Boot] [u-boot PATCH v2 8/8] ti: common: board_detect: Rename EEPROM scratch start macro

2017-01-30 Thread Roger Quadros
From: Lokesh Vutla 

Non OMAP platforms i.e. Keystone will also need to use the board
EEPROM helpers so let's make the macro platform independent.

Signed-off-by: Roger Quadros 
Signed-off-by: Lokesh Vutla 
---
 arch/arm/include/asm/omap_common.h | 8 +---
 board/ti/common/board_detect.h | 2 +-
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/arch/arm/include/asm/omap_common.h 
b/arch/arm/include/asm/omap_common.h
index 2034a5e..c1a70b1 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -767,9 +767,11 @@ static inline u8 is_dra72x(void)
 #define OMAP_SRAM_SCRATCH_VCORES_PTR(SRAM_SCRATCH_SPACE_ADDR + 0x1C)
 #define OMAP_SRAM_SCRATCH_SYS_CTRL (SRAM_SCRATCH_SPACE_ADDR + 0x20)
 #define OMAP_SRAM_SCRATCH_BOOT_PARAMS  (SRAM_SCRATCH_SPACE_ADDR + 0x24)
-#define OMAP_SRAM_SCRATCH_BOARD_EEPROM_START (SRAM_SCRATCH_SPACE_ADDR + 0x28)
-#define OMAP_SRAM_SCRATCH_BOARD_EEPROM_END (SRAM_SCRATCH_SPACE_ADDR + 0x200)
-#define OMAP_SRAM_SCRATCH_SPACE_END(OMAP_SRAM_SCRATCH_BOARD_EEPROM_END)
+#ifndef TI_SRAM_SCRATCH_BOARD_EEPROM_START
+#define TI_SRAM_SCRATCH_BOARD_EEPROM_START (SRAM_SCRATCH_SPACE_ADDR + 0x28)
+#define TI_SRAM_SCRATCH_BOARD_EEPROM_END (SRAM_SCRATCH_SPACE_ADDR + 0x200)
+#endif
+#define OMAP_SRAM_SCRATCH_SPACE_END(TI_SRAM_SCRATCH_BOARD_EEPROM_END)
 
 /* Boot parameters */
 #define DEVICE_DATA_OFFSET 0x18
diff --git a/board/ti/common/board_detect.h b/board/ti/common/board_detect.h
index 4bcb64f..88b0a59 100644
--- a/board/ti/common/board_detect.h
+++ b/board/ti/common/board_detect.h
@@ -98,7 +98,7 @@ struct ti_common_eeprom {
 };
 
 #define TI_EEPROM_DATA ((struct ti_common_eeprom *)\
-   OMAP_SRAM_SCRATCH_BOARD_EEPROM_START)
+   TI_SRAM_SCRATCH_BOARD_EEPROM_START)
 
 /**
  * ti_i2c_eeprom_am_get() - Consolidated eeprom data collection for AM* TI EVMs
-- 
2.7.4

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[U-Boot] [u-boot PATCH v2 7/8] ARM: k2g: setup PRU ethernet MAC addresses

2017-01-30 Thread Roger Quadros
PRU ethernet MAC address range is present in the
board EEPROM. Parse it and setup eth?addr
environment variables.

Signed-off-by: Roger Quadros 
---
 board/ti/ks2_evm/board_k2g.c | 19 +++
 configs/k2g_evm_defconfig|  2 ++
 2 files changed, 21 insertions(+)

diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c
index 40edbaa..a738dd2 100644
--- a/board/ti/ks2_evm/board_k2g.c
+++ b/board/ti/ks2_evm/board_k2g.c
@@ -12,6 +12,7 @@
 #include 
 #include 
 #include "mux-k2g.h"
+#include "../common/board_detect.h"
 
 #define SYS_CLK2400
 
@@ -149,6 +150,24 @@ int board_early_init_f(void)
 }
 #endif
 
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_TI_I2C_BOARD_DETECT)
+   int rc;
+
+   rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
+   CONFIG_EEPROM_CHIP_ADDRESS);
+   if (rc)
+   printf("ti_i2c_eeprom_init failed %d\n", rc);
+
+   board_ti_set_ethaddr(1);
+#endif
+
+   return 0;
+}
+#endif
+
 #ifdef CONFIG_SPL_BUILD
 void spl_init_keystone_plls(void)
 {
diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig
index 5251105..372e20b 100644
--- a/configs/k2g_evm_defconfig
+++ b/configs/k2g_evm_defconfig
@@ -3,6 +3,8 @@ CONFIG_ARCH_KEYSTONE=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_TARGET_K2G_EVM=y
+CONFIG_EEPROM_BUS_ADDRESS=0
+CONFIG_EEPROM_CHIP_ADDRESS=0x50
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_POWER_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
-- 
2.7.4

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Re: [U-Boot] [PATCH v8 5/7] arm: socfpga: Update DE1 environment

2017-01-30 Thread Westergreen, Dalon
On Mon, 2017-01-30 at 16:07 +0100, Alexander Graf wrote:
> On 01/29/2017 12:05 AM, Dalon Westergreen wrote:
> > 
> > From: Dalon Westergreen 
> > 
> > Remove the default environment as it is now in a common
> > header.
> > 
> > Add the CONFIG_DEFAULT_DEVICE_TREE to the board's defconfig
> > to set the linux devicetree name.
> > 
> > Signed-off-by: Dalon Westergreen 
> > Acked-by: Marek Vasut 
> > Acked-by: Dinh Nguyen 
> > ---
> >   configs/socfpga_de1_soc_defconfig |  1 +
> >   include/configs/socfpga_de1_soc.h | 19 +--
> >   2 files changed, 2 insertions(+), 18 deletions(-)
> > 
> > diff --git a/configs/socfpga_de1_soc_defconfig
> > b/configs/socfpga_de1_soc_defconfig
> > index 032deef..d78e8a1 100644
> > --- a/configs/socfpga_de1_soc_defconfig
> > +++ b/configs/socfpga_de1_soc_defconfig
> > @@ -6,6 +6,7 @@ CONFIG_TARGET_SOCFPGA_TERASIC_DE1_SOC=y
> >   CONFIG_SPL_STACK_R_ADDR=0x0080
> >   CONFIG_SPL_YMODEM_SUPPORT=y
> >   CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de1_soc"
> > +CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_de1_soc.dtb"
> >   CONFIG_FIT=y
> >   CONFIG_SYS_CONSOLE_IS_IN_ENV=y
> >   CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
> > diff --git a/include/configs/socfpga_de1_soc.h
> > b/include/configs/socfpga_de1_soc.h
> > index deec647..3142bd1 100644
> > --- a/include/configs/socfpga_de1_soc.h
> > +++ b/include/configs/socfpga_de1_soc.h
> > @@ -18,7 +18,7 @@
> >   #define PHYS_SDRAM_1_SIZE 0x4000  /* 1GiB */
> >   
> >   /* Booting Linux */
> > -#define CONFIG_BOOTFILE"fitImage"
> > +#define CONFIG_BOOTFILE"zImage"
> 
> ok, here you're confusing me. I thought the point of having the crude, 
> hacky mmcload/mmcboot in bootcmd was because you want to be legacy 
> compatible. If you're changing the bootfile name, that point is moot.
> 
> So at this point, why not just switch to distro boot and extlinux.conf / 
> efi altogether?
> 
Bootfile was never used in the environment, neither have any of the
kits by default been using fitimages. When the environment was moved
to a common one i setting the bootfile def to match what was actually
used.  moving to distro boot is in the works and i will look at
SCAN_DEV_FOR_EFI for legacy support.

thanks,
dalon
> 
> Alex
> 
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[U-Boot] [u-boot PATCH v2 5/8] board: ti: am57xx-idk: Auto detect LCD Panel

2017-01-30 Thread Roger Quadros
From: Nishanth Menon 

AM571x IDK and AM572x IDK have optional LCD Kits that can be purchased.
These can be one of OSD101T2045 or the newer OSD101T2587. The LCD panel
itself has no registers that can be used to identify the panel, however,
the touchscreen controllers on the panels are different.

Hence to ease user experience, we can use the touch screen controller's
ID information to detect what kind of panel we use and select the
appropriate kernel dtb for the platform configuration.

NOTE: AM572x IDK default configuration is for LCD Connectivity, however
the AM571x IDK has a jumper (J51) that needs to be mounted for the IDK
to operate with LCD (Vs two PRUSS ethernet port option).

Touchscreen ID information is documented in:
http://www.osddisplays.com/TI/OSD101T2587-53TS_A.1.pdf

Acked-by: Lokesh Vutla 
Signed-off-by: Nishanth Menon 
Signed-off-by: Lokesh Vutla 
Signed-off-by: Roger Quadros 
Reviewed-by: Tom Rini 
---
 board/ti/am57xx/board.c | 78 -
 1 file changed, 70 insertions(+), 8 deletions(-)

diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index 81ad86c..9ec0448 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -54,6 +54,19 @@ DECLARE_GLOBAL_DATA_PTR;
 /* GPIO 7_11 */
 #define GPIO_DDR_VTT_EN 203
 
+/* Touch screen controller to identify the LCD */
+#define OSD_TS_FT_BUS_ADDRESS  0
+#define OSD_TS_FT_CHIP_ADDRESS 0x38
+#define OSD_TS_FT_REG_ID   0xA3
+/*
+ * Touchscreen IDs for various OSD panels
+ * Ref: http://www.osddisplays.com/TI/OSD101T2587-53TS_A.1.pdf
+ */
+/* Used on newer osd101t2587 Panels */
+#define OSD_TS_FT_ID_5x46  0x54
+/* Used on older osd101t2045 Panels */
+#define OSD_TS_FT_ID_5606  0x08
+
 #define SYSINFO_BOARD_NAME_MAX_LEN 45
 
 #define TPS65903X_PRIMARY_SECONDARY_PAD2   0xFB
@@ -473,10 +486,64 @@ int board_init(void)
return 0;
 }
 
-int board_late_init(void)
+void am57x_idk_lcd_detect(void)
 {
-   char *idk_lcd;
+   int r = -ENODEV;
+   char *idk_lcd = "no";
+   uint8_t buf = 0;
+
+   /* Only valid for IDKs */
+   if (board_is_x15() || board_is_am572x_evm())
+   return;
+
+   /* Only AM571x IDK has gpio control detect.. so check that */
+   if (board_is_am571x_idk() && !am571x_idk_needs_lcd())
+   goto out;
+
+   r = i2c_set_bus_num(OSD_TS_FT_BUS_ADDRESS);
+   if (r) {
+   printf("%s: Failed to set bus address to %d: %d\n",
+  __func__, OSD_TS_FT_BUS_ADDRESS, r);
+   goto out;
+   }
+   r = i2c_probe(OSD_TS_FT_CHIP_ADDRESS);
+   if (r) {
+   /* AM572x IDK has no explicit settings for optional LCD kit */
+   if (board_is_am571x_idk()) {
+   printf("%s: Touch screen detect failed: %d!\n",
+  __func__, r);
+   }
+   goto out;
+   }
+
+   /* Read FT ID */
+   r = i2c_read(OSD_TS_FT_CHIP_ADDRESS, OSD_TS_FT_REG_ID, 1, &buf, 1);
+   if (r) {
+   printf("%s: Touch screen ID read %d:0x%02x[0x%02x] failed:%d\n",
+  __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
+  OSD_TS_FT_REG_ID, r);
+   goto out;
+   }
+
+   switch (buf) {
+   case OSD_TS_FT_ID_5606:
+   idk_lcd = "osd101t2045";
+   break;
+   case OSD_TS_FT_ID_5x46:
+   idk_lcd = "osd101t2587";
+   break;
+   default:
+   printf("%s: Unidentifed Touch screen ID 0x%02x\n",
+  __func__, buf);
+   /* we will let default be "no lcd" */
+   }
+out:
+   setenv("idk_lcd", idk_lcd);
+   return;
+}
 
+int board_late_init(void)
+{
setup_board_eeprom_env();
u8 val;
 
@@ -505,12 +572,7 @@ int board_late_init(void)
palmas_i2c_write_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
val);
 
-   /* TBD: Add LCD panel detection once information is available */
-   if (am571x_idk_needs_lcd())
-   idk_lcd = "osd101t2045"; /* Default to legacy LCD */
-   else
-   idk_lcd = "no";
-   setenv("idk_lcd", idk_lcd);
+   am57x_idk_lcd_detect();
 
 #if !defined(CONFIG_SPL_BUILD)
board_ti_set_ethaddr(2);
-- 
2.7.4

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Re: [U-Boot] [PATCH] arm: dts: imx53-cx9020: fix packetloss on fec_mxc

2017-01-30 Thread Stefano Babic
On 23/01/2017 18:45, Tom Rini wrote:
> On Mon, Jan 23, 2017 at 05:20:25PM +, linux-kernel-dev wrote:
>>> From: Tom Rini [mailto:tr...@konsulko.com]
>>> Sent: Montag, 23. Januar 2017 16:31
>>>
>>> On Mon, Jan 23, 2017 at 03:11:27PM +0100, linux-kernel-...@beckhoff.com
>>> wrote:
>>>
 From: Patrick Bruenn 

 The pinmuxing for i.MX53 FEC ethernet copied from
 /arch/arm/boot/dts/imx53-qsb-common.dtsi (at least until v4.9)
 was bad. It is different from the manual pinmuxing in
 /board/freescale/mx53loco/mx53loco.c which was used in
 cx9020 implementation previously before mainlining into u-boot.
 It seems the bug in imx53-qsb kernel device tree is hidden for so long,
 because it was never used, by the kernel driver.

 Signed-off-by: Patrick Bruenn 
>>>
>>> So in other words, the dts file is correct in current mainline kernel?
>>> Or still pending?  Thanks!
>> Sorry, no it is still pending. I just reported it to the kernel maintainers:
>> https://mail-archive.com/linux-kernel@vger.kernel.org/msg1316717.html
> 
> Ah, OK.  I think we want get this in the release, but it can wait for
> -rc3 or so, unless it gets ack'ed by the kernel folks sooner.  Please
> keep us apprised, thanks!
>

I saw patch was integrated in kernel - I merge this as well in u-boot-imx.

Regards,
Stefano


-- 
=
DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
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Re: [U-Boot] [PATCH] drivers: net: fsl-mc: Fixup MAC addresses in DPC

2017-01-30 Thread york sun
On 01/30/2017 03:09 AM, Prabhakar Kushwaha wrote:
> Hi York,
>
>
>> -Original Message-
>> From: york sun
>> Sent: Saturday, January 28, 2017 2:15 AM
>> To: Prabhakar Kushwaha ; Bogdan Purcareata
>> ; u-boot@lists.denx.de
>> Subject: Re: [PATCH] drivers: net: fsl-mc: Fixup MAC addresses in DPC
>>
>> On 01/26/2017 05:05 AM, Prabhakar Kushwaha wrote:
>>>
 -Original Message-
 From: Bogdan Purcareata [mailto:bogdan.purcare...@nxp.com]
 Sent: Thursday, January 11, 2017 9:35 AM
 To: u-boot@lists.denx.de
 Cc: Bogdan Purcareata 
 Subject: [PATCH] drivers: net: fsl-mc: Fixup MAC addresses in DPC

 Fixup port_mac_address property in MC DPC with values from the u-boot
 environment. Since u-boot already reads the environment MAC addresses
 when probing the PHYs, use these values.

 The u-boot environment MAC addresses take precedence over any eventual
 ones defined in the DPC, except for the case where they are randomly
 assigned (no u-boot env value declared for port).

 The patch assumes the "/board_info/ports/" node is present in the DPC.

 Signed-off-by: Bogdan Purcareata 
>>>
>>> Reviewed-by: Prabhakar Kushwaha 
>>>
>>
>> Prabhakar,
>>
>> I don't know how you replied with your comment. But your email client
>> changed the message ID so patchwork couldn't match it.
>>
>
> Oh..
> Looks like I did some mistake...
>
> Will it be possible to provide original message/mail which was sent on the 
> mailing list so that I can provide "review-by" again
>
> --prabhakar
>

I will manually add your review signature when merging this one. Just 
curious how it was messed up.

York

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Re: [U-Boot] [PATCH] LS1021ATWR: Modify u-boot size for sd secure boot

2017-01-30 Thread york sun
On 01/29/2017 11:24 PM, Vinitha Pillai-B57223 wrote:
> From: Vinitha Pillai 
>
> Raw uboot image is used in place of FIT image in secure boot.
> The maximum allocated size of raw u-boot bin is 1MB in memory map.
> Hence , CONFIG_SYS_MONITOR_LEN has been modified to 1 MB.
> The bootscript  (BS_ADDR) and its header (BS_HDR_ADDR) offset on
> MMC have also been modified to accommodate the increase in uboot size.
>
> Signed-off-by: Vinitha Pillai-B57223 
> Reviewed-by: Sumit Garg 
> Reviewed-by: Ruchika Gupta 
> Reviewed-by: Prabhakar Kushwaha 
> ---

For future patches, please add change log under this --- line to explain 
what has changed since last version.

York

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Re: [U-Boot] [PATCH] LS1021ATWR: Modify u-boot size for sd secure boot

2017-01-30 Thread york sun
On 01/29/2017 11:24 PM, Vinitha Pillai-B57223 wrote:
> From: Vinitha Pillai 
>
> Raw uboot image is used in place of FIT image in secure boot.
> The maximum allocated size of raw u-boot bin is 1MB in memory map.
> Hence , CONFIG_SYS_MONITOR_LEN has been modified to 1 MB.
> The bootscript  (BS_ADDR) and its header (BS_HDR_ADDR) offset on
> MMC have also been modified to accommodate the increase in uboot size.
>
> Signed-off-by: Vinitha Pillai-B57223 
> Reviewed-by: Sumit Garg 
> Reviewed-by: Ruchika Gupta 
> Reviewed-by: Prabhakar Kushwaha 
> ---

This patch wasn't received by the mailing list. Please resend with this 
tag in the subject [RESEND PATCH v2].

York
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Re: [U-Boot] [PATCH v2 1/8] armv8: Add workaround for USB erratum A-009008

2017-01-30 Thread york sun
On 01/30/2017 05:42 AM, Suresh Gupta wrote:
> From: Suresh Gupta 
>
> USB High Speed (HS) EYE Height Adjustment
> USB HS speed eye diagram fails with the default value at
> many corners, particularly at a high temperature
>
> Optimal eye at TXVREFTUNE value to 1001 is observed, change
> set the same vale.
>
> Signed-off-by: Sriram Dash 
> Signed-off-by: Rajesh Bhagat 
> Signed-off-by: Suresh Gupta 
> ---
> Changes in v2: None
>
>  arch/arm/cpu/armv8/fsl-layerscape/Kconfig  |  6 ++
>  arch/arm/cpu/armv8/fsl-layerscape/soc.c| 25 
> ++
>  .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  6 ++
>  .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  1 +
>  4 files changed, 38 insertions(+)
>
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
> b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> index de0b580..666a3d1 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> @@ -18,6 +18,7 @@ config ARCH_LS1043A
>   select SYS_FSL_ERRATUM_A009942
>   select SYS_FSL_ERRATUM_A010315
>   select SYS_FSL_ERRATUM_A010539
> + select SYS_FSL_ERRATUM_A009008
>   select SYS_FSL_HAS_DDR3
>   select SYS_FSL_HAS_DDR4
>
> @@ -33,6 +34,7 @@ config ARCH_LS1046A
>   select SYS_FSL_ERRATUM_A009942
>   select SYS_FSL_ERRATUM_A010165
>   select SYS_FSL_ERRATUM_A010539
> + select SYS_FSL_ERRATUM_A009008
>   select SYS_FSL_HAS_DDR4
>   select SYS_FSL_SRDS_2
>
> @@ -58,6 +60,7 @@ config ARCH_LS2080A
>   select SYS_FSL_ERRATUM_A009803
>   select SYS_FSL_ERRATUM_A009942
>   select SYS_FSL_ERRATUM_A010165
> + select SYS_FSL_ERRATUM_A009008
>
>  config FSL_LSCH2
>   bool
> @@ -102,6 +105,9 @@ config SYS_FSL_ERRATUM_A010315
>  config SYS_FSL_ERRATUM_A010539
>   bool "Workaround for PIN MUX erratum A010539"
>
> +config SYS_FSL_ERRATUM_A009008
> + bool "Workaround for USB PHY erratum A009008"
> +
>  config MAX_CPUS
>   int "Maximum number of CPUs permitted for Layerscape"
>   default 4 if ARCH_LS1043A
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
> b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> index 2f54625..951ccba 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> @@ -52,6 +52,29 @@ bool soc_has_aiop(void)
>   return false;
>  }
>
> +static void erratum_a009008(void)
> +{
> +#ifdef CONFIG_SYS_FSL_ERRATUM_A009008
> +#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1046A)

Should this be CONFIG_FSL_LSCH2? If it has to be SoC name, use 
CONFIG_ARCH_LS1043A. Same comment goes to other patches in this set.

York

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Re: [U-Boot] [PATCH 4/5][v5] arch: powerpc: Move CONFIG_FSL_ELBC to Kconfig

2017-01-30 Thread york sun
On 01/24/2017 02:35 AM, Prabhakar Kushwaha wrote:
> Enable ELBC from Kconfig.
>
> Signed-off-by: Prabhakar Kushwaha 
> ---
>  arch/powerpc/cpu/mpc85xx/Kconfig| 26 ++
>  include/configs/MPC8313ERDB.h   |  1 -
>  include/configs/MPC8315ERDB.h   |  1 -
>  include/configs/MPC837XEMDS.h   |  1 -
>  include/configs/MPC837XERDB.h   |  1 -
>  include/configs/MPC8536DS.h |  1 -
>  include/configs/MPC8569MDS.h|  2 --
>  include/configs/MPC8572DS.h |  1 -
>  include/configs/P1022DS.h   |  1 -
>  include/configs/P1023RDB.h  |  1 -
>  include/configs/P2041RDB.h  |  1 -
>  include/configs/UCP1020.h   |  1 -
>  include/configs/controlcenterd.h|  1 -
>  include/configs/corenet_ds.h|  1 -
>  include/configs/cyrus.h |  1 -
>  include/configs/ids8313.h   |  2 --
>  include/configs/km/kmp204x-common.h |  1 -
>  include/configs/p1_p2_rdb_pc.h  |  1 -
>  include/configs/p1_twr.h|  1 -
>  include/configs/ve8313.h|  1 -
>  include/configs/xpedite537x.h   |  1 -
>  include/configs/xpedite550x.h   |  1 -
>  22 files changed, 26 insertions(+), 23 deletions(-)
>

Prabhakar,

Please test your changes on more platforms. I got a lot of compiling 
errors such as

+(MPC8540ADS) ../board/freescale/mpc8540ads/mpc8540ads.c: In function 
'lbc_sdram_init':
+(MPC8540ADS) ../board/freescale/mpc8540ads/mpc8540ads.c:126:5: error: 
'fsl_lbc_t' has no member named 'lsrt'
+(MPC8540ADS) ../board/freescale/mpc8540ads/mpc8540ads.c:133:5: error: 
'fsl_lbc_t' has no member named 'lsdmr'
+(MPC8540ADS) ../board/freescale/mpc8540ads/mpc8540ads.c:139:5: error: 
'fsl_lbc_t' has no member named 'lsdmr'
+(MPC8540ADS) ../board/freescale/mpc8540ads/mpc8540ads.c:145:5: error: 
'fsl_lbc_t' has no member named 'lsdmr'
+(MPC8540ADS) ../board/freescale/mpc8540ads/mpc8540ads.c:151:5: error: 
'fsl_lbc_t' has no member named 'lsdmr'
+(MPC8540ADS) ../board/freescale/mpc8540ads/mpc8540ads.c:157:5: error: 
'fsl_lbc_t' has no member named 'lsdmr'

It happens on MPC8313ERDB_NAND_66 MPC8540ADS MPC837XEMDS_HOST ve8313 
sbc8548_PCI_33_PCIE MPC8548CDS MPC8315ERDB MPC8541CDS MPC8555CDS_legacy 
MPC8548CDS_legacy MPC8541CDS_legacy sbc8548_PCI_33 MPC837XEMDS 
MPC8568MDS MPC8313ERDB_NAND_33 sbc8548_PCI_66 MPC8555CDS 
MPC8548CDS_36BIT sbc8548_PCI_66_PCIE MPC8313ERDB_33 sbc8548 MPC8560ADS 
MPC8313ERDB_66.

I noticed you sent out v6 patch "as is". So this probably happens to the 
new version as well.

York

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Re: [U-Boot] [PATCH 5/5][v5] arch: powerpc: update the eLBC IP input clock

2017-01-30 Thread york sun
On 01/24/2017 02:35 AM, Prabhakar Kushwaha wrote:
> eLBC IP clock is always a constant divisor of platform clock
> pre-defined per SoC. Clock ratio register (LCRR) used in
> current implementation governs eLBC IP output clock.
>
> So update eLBC IP clock to be defined as per predefined clock
> divisor of platform clock.
>
> Signed-off-by: Prabhakar Kushwaha 
> ---
>  README   |  3 +++
>  arch/powerpc/cpu/mpc85xx/Kconfig | 14 ++
>  arch/powerpc/cpu/mpc85xx/speed.c | 28 ++--
>  arch/powerpc/cpu/mpc86xx/speed.c | 14 +-
>  4 files changed, 20 insertions(+), 39 deletions(-)
>

Prabhakar,

This patch has compiling error for 86xx. Please check.

York

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Re: [U-Boot] [PATCH] arm: fsl-layerscape: Move QSGMII wriop_init to SoC file

2017-01-30 Thread york sun
On 01/30/2017 02:19 AM, Ashish Kumar wrote:
> From: Prabhakar Kushwaha 
>
> MAC number used per QSGMII is not fixed. It may wary from SoC to SoC.
>
> So move QSGMII wriop_init_dpmac() to SoC file.
>
> Signed-off-by: Prabhakar Kushwaha 
> ---
>  .../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c|   27 +
>  .../include/asm/arch-fsl-layerscape/fsl_serdes.h   |8 ++--
>  drivers/net/ldpaa_eth/ls2080a.c|   30 
> 
>  include/fsl-mc/ldpaa_wriop.h   |1 +
>  4 files changed, 43 insertions(+), 23 deletions(-)
>
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c 
> b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
> index 7faa86c..601651a 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
> @@ -23,6 +23,13 @@ int xfi_dpmac[XFI8 + 1];
>  int sgmii_dpmac[SGMII16 + 1];
>  #endif
>
> +void __wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
> +{
> + return;
> +}
> +void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
> + __attribute__((weak, alias("__wriop_init_dpmac_qsgmii")));
> +

This could be simplified as

__weak void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl) {}

York

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Re: [U-Boot] [PATCH] armv8:fsl-layerscape: Avoid RCWSR28 register hard-coding

2017-01-30 Thread york sun
On 01/30/2017 02:56 AM, Ashish Kumar wrote:
> From: Prabhakar Kushwaha 
>
> SerDes information is not necessary to be present in RCWSR29 register.
> It may vary from SoC to SoC.
>
> So Avoid RCWSR28 register hard-coding.
>
> Signed-off-by: Prabhakar Kushwaha 

Ashish,

Please add your signature next time. Even it was created by Prabhakar, 
you should sign it if you send it out.

> ---
>  .../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c|   28 +++
>  .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |9 ++
>  2 files changed, 25 insertions(+), 12 deletions(-)
>
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c 
> b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
> index 601651a..af2684e 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
> @@ -53,20 +53,22 @@ int is_serdes_configured(enum srds_prtcl device)
>  int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
>  {
>   struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
> - u32 cfg = gur_in32(&gur->rcwsr[28]);
> + u32 cfg = 0;
>   int i;
>
>   switch (sd) {
>  #ifdef CONFIG_SYS_FSL_SRDS_1
>   case FSL_SRDS_1:
> - cfg &= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
> - cfg >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
> + cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]);
> + cfg &= FSL_CHASSIS3_SRDS1_PRTCL_MASK;
> + cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
>   break;
>  #endif
>  #ifdef CONFIG_SYS_FSL_SRDS_2
>   case FSL_SRDS_2:
> - cfg &= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
> - cfg >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
> + cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]);
> + cfg &= FSL_CHASSIS3_SRDS2_PRTCL_MASK;
> + cfg >>= FSL_CHASSIS3_SRDS2_PRTCL_SHIFT;
>   break;
>  #endif
>   default:
> @@ -85,8 +87,8 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
>   return -ENODEV;
>  }
>
> -void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
> - u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
> +void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,
> +  u32 sd_prctl_shift, u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
>  {
>   struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
>   u32 cfg;
> @@ -97,7 +99,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, 
> u32 sd_prctl_shift,
>
>   memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT);
>
> - cfg = gur_in32(&gur->rcwsr[28]) & sd_prctl_mask;
> + cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask;
>   cfg >>= sd_prctl_shift;
>   printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
>
> @@ -154,15 +156,17 @@ void fsl_serdes_init(void)
>  #ifdef CONFIG_SYS_FSL_SRDS_1
>   serdes_init(FSL_SRDS_1,
>   CONFIG_SYS_FSL_LSCH3_SERDES_ADDR,
> - FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK,
> - FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT,
> + FSL_CHASSIS3_SRDS1_REGSR,
> + FSL_CHASSIS3_SRDS1_PRTCL_MASK,
> + FSL_CHASSIS3_SRDS1_PRTCL_SHIFT,
>   serdes1_prtcl_map);
>  #endif
>  #ifdef CONFIG_SYS_FSL_SRDS_2
>   serdes_init(FSL_SRDS_2,
>   CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x1,
> - FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK,
> - FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT,
> + FSL_CHASSIS3_SRDS2_REGSR,
> + FSL_CHASSIS3_SRDS2_PRTCL_MASK,
> + FSL_CHASSIS3_SRDS2_PRTCL_SHIFT,
>   serdes2_prtcl_map);
>  #endif
>  }
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
> b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> index 43ae686..5ea9130 100644
> --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> @@ -232,10 +232,19 @@ struct ccsr_gur {
>  #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK 0x3f
>  #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT   18
>  #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK0x3f
> +
> +#if defined(CONFIG_LS2080A)

We are switching to Kconfig macros. Use CONFIG_ARCH_LS2080A instead.

York
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Re: [U-Boot] [PATCH 1/3] fsl-lsch3: rename ls2080a_stream_id.h to stream_id_lsch3.h

2017-01-30 Thread york sun
On 01/30/2017 02:45 AM, Bharat Bhushan wrote:
> The stream ID allocation for Chasis3.0 devices,
> LS1088, LS2088 and LS2080, can be shared.
>
> This patch renames this accordingly.
>
> Signed-off-by: Bharat Bhushan 
> ---
>  .../asm/arch-fsl-layerscape/ls2080a_stream_id.h| 77 
> --
>  .../asm/arch-fsl-layerscape/stream_id_lsch3.h  | 77 
> ++
>  include/configs/ls2080a_common.h   |  2 +-
>  3 files changed, 78 insertions(+), 78 deletions(-)
>  delete mode 100644 
> arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h
>  create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
>

Bharat,

When you create patches, please use tools/patman/patman. It 
automatically does many things for you. If you have to create it 
manually, make sure you use -M -C flag for "git format-patch". This 
patch should show changes as

  .../asm/arch-fsl-layerscape/{ls2080a_stream_id.h => stream_id_lsch3.h} 
  | 0
  include/configs/ls2080a_common.h 
  | 2 +-
  2 files changed, 1 insertion(+), 1 deletion(-)
  rename arch/arm/include/asm/arch-fsl-layerscape/{ls2080a_stream_id.h 
=> stream_id_lsch3.h} (100%)

It would be lot easier to review.

York
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Re: [U-Boot] [PATCH 5/5][v5] arch: powerpc: update the eLBC IP input clock

2017-01-30 Thread york sun
On 01/30/2017 08:43 AM, york@nxp.com wrote:
> On 01/24/2017 02:35 AM, Prabhakar Kushwaha wrote:
>> eLBC IP clock is always a constant divisor of platform clock
>> pre-defined per SoC. Clock ratio register (LCRR) used in
>> current implementation governs eLBC IP output clock.
>>
>> So update eLBC IP clock to be defined as per predefined clock
>> divisor of platform clock.
>>
>> Signed-off-by: Prabhakar Kushwaha 
>> ---
>>  README   |  3 +++
>>  arch/powerpc/cpu/mpc85xx/Kconfig | 14 ++
>>  arch/powerpc/cpu/mpc85xx/speed.c | 28 ++--
>>  arch/powerpc/cpu/mpc86xx/speed.c | 14 +-
>>  4 files changed, 20 insertions(+), 39 deletions(-)
>>
>
> Prabhakar,
>
> This patch has compiling error for 86xx. Please check.
>
>

Correction, it has compiling warning, not error.

York

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Re: [U-Boot] Falcon boot breaks on DRA7 because of commit b9c8ccab "env_mmc.c: Allow environment to be used within SPL"

2017-01-30 Thread Tom Rini
On Mon, Jan 30, 2017 at 01:44:04PM +0100, Jean-Jacques Hiblot wrote:
> 
> 
> On 27/01/2017 00:36, Tom Rini wrote:
> >On Wed, Jan 25, 2017 at 11:21:32AM +0100, Jean-Jacques Hiblot wrote:
> >>
> >>On 24/01/2017 20:11, Tom Rini wrote:
> >>>On Tue, Jan 24, 2017 at 06:04:47PM +0100, Jean-Jacques Hiblot wrote:
> On 24/01/2017 16:46, Tom Rini wrote:
> >>I had noticed that it's quite old indeed. I didn't mean that it's a
> >>regression. I'm just puzzled by the commit. what is its purpose ?
> >>why is SPL not using  CONFIG_SYS_MMC_ENV_DEV ?
> >Because in SPL we do not have both MMC devices initialized.
> That is not always the case. Actually in spl_mmc.c the code requires
> us to register more than one MMC device to work properly when
> multiple MMC boot devices can be used (see
> spl_mmc_get_device_index())
> I did the test of registering only MMC2 when booting from eMMC, the
> SPL fails because it can't find device 1:
> Trying to boot from MMC2_2
> MMC Device 1 not found
> spl: could not find mmc device. error: -19
> 
> >We register
> >the one we booted from and thus it is device 0 to U-Boot in this case.
> >I suspect the rest of the issues stem from this quirk, or something
> >having broken around this quirk.  Thanks!
> >>>Right.  So I suspect the problem is that some level of the env_mmc.c
> >>>code needs to be adapted again for the change in how SPL now works with
> >>>the possibility of multiple devices.  It's possible that the change you
> >>>found is the right fix, please investigate a bit more and confirm
> >>>things before submitting a proper patch, thanks!
> >>I did more tests and it turns out that there I find no real benefit
> >>of registering only the controller for the boot device.
> >>The initialization of the MMC/SD/eMMC is done only prior accessing
> >>it, not when it's registered. So in terms of boot time the impact of
> >>registering many controllers is not significant.
> >>By registering the same controllers in SPL and in u-boot, we would
> >>get the same mapping for the MMC devices in SPL and u-boot. It would
> >>remove a source of confusion and of #ifdef CONFIG_SPL_BUILD
> >>
> >>The catch is that many boards register only one MMC controller in
> >>the SPL, depending on what the boot source is (ex: board_mmc_init()
> >>in board/freescale/mx6slevk/mx6slevk.c)
> >>To reduce the risk of regression, we could deal with those boards in
> >>2 steps:
> >>1) Don't change the code of the board except to override the weak
> >>function mmc_get_env_dev() and make it return 0. This is not likely
> >>to introduce a regression
> >>2) One by one, change the code of the boards to register all the
> >>controllers in SPL as done in u-boot. Also we need to adapt
> >>spl_boot_device() to return the right boot device. There has been a
> >>partial attempt at this ""ARM: mx6: add MMC2 boot device detection
> >>support in SPL" but had to be reverted probably because it was not
> >>coherent with the registration of the controllers.
> >Due to the issue you mention in #2, we probably need to do #1 and with
> >care and testing, as there's enough places that assume SPL is a single
> >MMC device that it'll be problematic to do them one at a time.
> I made a survey of the code in 2017.01 to identify the platforms
> that may be impacted by the change in env_mmc.c
> 
> Here is the method:
> 1)  *  find the platforms that override mmc_get_env_dev(). Those may
> not rely on CONFIG_SYS_MMC_ENV_DEV to get the MMC device where the
> env is stored.
> * find the platforms that define CONFIG_SYS_MMC_ENV_DEV as not 0
> 2) Find the paltforms that use CONFIG_SPL_ENV_SUPPORT
> 3) Cross the info from 1 and 2 to get the platforms that may be
> impacted by the change
> 
> 
> 1) Platforms that my use a device that is not dev 0 for en storage:
> 
> $ git grep -w mmc_get_env_dev
> arch/arm/cpu/armv7/mx6/soc.c:int mmc_get_env_dev(void)
> arch/arm/cpu/armv7/mx7/soc.c:int mmc_get_env_dev(void)
> arch/arm/mach-uniphier/boot-mode/boot-mode.c:int mmc_get_env_dev(void)
> board/freescale/mx7dsabresd/mx7dsabresd.c:  u32 dev_no =
> mmc_get_env_dev();
> common/env_mmc.c:__weak int mmc_get_env_dev(void)
> common/env_mmc.c:   int dev = mmc_get_env_dev();
> common/env_mmc.c:   int dev = mmc_get_env_dev();
> common/env_mmc.c:   int dev = mmc_get_env_dev();
> common/env_mmc.c:   int dev = mmc_get_env_dev();
> common/env_mmc.c:   int dev = mmc_get_env_dev();
> include/mmc.h:int mmc_get_env_dev(void);
> 
> 
> $ git grep -e 'ne\sCONFIG_SYS_MMC_ENV_DEV\s*[1-9a-zA-Z\(\)]' include/
> include/configs/am335x_evm.h:#define CONFIG_SYS_MMC_ENV_DEV 1
> include/configs/am335x_shc.h:#define CONFIG_SYS_MMC_ENV_DEV 1
> include/configs/am335x_sl50.h:#define CONFIG_SYS_MMC_ENV_DEV1
> include/configs/bav335x.h:#define CONFIG_SYS_MMC_ENV_DEV1
> include/configs/cm_t54.h:#define CONFIG_SYS_MMC_ENV_DEV 1
> /* SLOT2: eMMC(1) */
> 

Re: [U-Boot] [PATCH] net: macb: add .remove callback

2017-01-30 Thread Joe Hershberger
On Tue, Jan 24, 2017 at 11:06 PM, Wenyou Yang  wrote:
> To avoid the failure of mdio_register(), add the .remove callback
> to unregister the mii_dev when remove the ethernet device.
>
> Signed-off-by: Wenyou Yang 

Acked-by: Joe Hershberger 
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[U-Boot] [ANN] U-Boot v2017.03-rc1 released

2017-01-30 Thread Tom Rini
Hey all,

It's release day and v2017.03-rc1 is out and the merge window is closed.
I've updated git and the tarballs are also up now.

I plan on doing -rc2 on the 13th of February.  I think my own queue is
looking rather reasonable at this point, but that may be in part due to
moving a few bigger series into 'Deferred' as I had asked for some
changes and they never happened.

Thanks all!

-- 
Tom


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[U-Boot] [RFC] cmd: fdt: memory fixup

2017-01-30 Thread Ladislav Michl
To get Falcon mode working with zImage is currently non trivial as zImages
do not fit into U-Boot's image concept too well. Fortunately at least for
ARM boards it seems getting memory node right is quite sufficient.
What about changing 'fdt memory' command to update memory node according to
detected memory layout when called without parameters?

ladis

diff --git a/cmd/fdt.c b/cmd/fdt.c
index 95dd673b95..e08296d51c 100644
--- a/cmd/fdt.c
+++ b/cmd/fdt.c
@@ -517,11 +517,23 @@ static int do_fdt(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
 * memory command
 */
} else if (strncmp(argv[1], "me", 2) == 0) {
-   uint64_t addr, size;
int err;
-   addr = simple_strtoull(argv[2], NULL, 16);
-   size = simple_strtoull(argv[3], NULL, 16);
-   err = fdt_fixup_memory(working_fdt, addr, size);
+   if (argc < 4) {
+   int i;
+   uint64_t start[CONFIG_NR_DRAM_BANKS];
+   uint64_t size[CONFIG_NR_DRAM_BANKS];
+   bd_t *bd = gd->bd;
+   for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+   start[i] = bd->bi_dram[i].start;
+   size[i] = bd->bi_dram[i].size;
+   }
+   err = fdt_fixup_memory_banks(working_fdt, start, size,
+   CONFIG_NR_DRAM_BANKS);
+   } else {
+   uint64_t addr = simple_strtoull(argv[2], NULL, 16);
+   uint64_t size = simple_strtoull(argv[3], NULL, 16);
+   err = fdt_fixup_memory(working_fdt, addr, size);
+   }
if (err < 0)
return err;
 
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Re: [U-Boot] [PATCH 1/2] power: pmic: add the max8997 controller for DM

2017-01-30 Thread Jaehoon Chung
Hi Simon

On 01/26/2017 11:23 PM, Simon Glass wrote:
> Hi Jaehoon,
> 
> On 18 January 2017 at 23:13, Jaehoon Chung  wrote:
>> Add the max8997 controller for Driver model.
>> Exynos4210 is using max8997 pmic controller.
>> (pmic_max8997.c should be deprecated.)
>>
>> Signed-off-by: Jaehoon Chung 
>> ---
>>  drivers/power/pmic/Kconfig   |  7 +
>>  drivers/power/pmic/Makefile  |  1 +
>>  drivers/power/pmic/max8997.c | 61 
>> 
>>  3 files changed, 69 insertions(+)
>>  create mode 100644 drivers/power/pmic/max8997.c
> 
> Reviewed-by: Simon Glass 
> 
> But please see comments below.
> 
>>
>> diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
>> index 5e244c8..19494fa 100644
>> --- a/drivers/power/pmic/Kconfig
>> +++ b/drivers/power/pmic/Kconfig
>> @@ -54,6 +54,13 @@ config DM_PMIC_MAX77686
>> This config enables implementation of driver-model pmic uclass 
>> features
>> for PMIC MAX77686. The driver implements read/write operations.
>>
>> +config DM_PMIC_MAX8997
> 
> config PMIC_MAX8997
> 
> Since I don't think you have a non-DM option here.

Will fix.

> 
> 
>> +   bool "Enable Driver Model for PMIC MAX8997"
>> +   depends on DM_PMIC
>> +   ---help---
>> +   This config enables implementation of driver-model pmic uclass 
>> features
>> +   for PMIC MAX8997. The driver implements read/write operations.
> 
> Can you mention a few details about the device? Number of LDOs, etc.?

Ok.

> 
>> +
>>  config DM_PMIC_MAX8998
>> bool "Enable Driver Model for PMIC MAX8998"
>> depends on DM_PMIC
>> diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
>> index b4ac7d2..43f5557 100644
>> --- a/drivers/power/pmic/Makefile
>> +++ b/drivers/power/pmic/Makefile
>> @@ -7,6 +7,7 @@
>>
>>  obj-$(CONFIG_DM_PMIC) += pmic-uclass.o
>>  obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o
>> +obj-$(CONFIG_DM_PMIC_MAX8997) += max8997.o
>>  obj-$(CONFIG_DM_PMIC_MAX8998) += max8998.o
>>  obj-$(CONFIG_DM_PMIC_PFUZE100) += pfuze100.o
>>  obj-$(CONFIG_PMIC_S2MPS11) += s2mps11.o
>> diff --git a/drivers/power/pmic/max8997.c b/drivers/power/pmic/max8997.c
>> new file mode 100644
>> index 000..f749d7d
>> --- /dev/null
>> +++ b/drivers/power/pmic/max8997.c
>> @@ -0,0 +1,61 @@
>> +/*
>> + *  Copyright (C) 2016 Samsung Electronics
>> + *  Jaehoon Chung 
>> + *
>> + * SPDX-License-Identifier:GPL-2.0+
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
> 
> nit: Should go above i2.h

Will fix.

Best Regards,
Jaehoon Chung

> 
> [...]
> 
> Regards,
> Simon
> 
> 
> 

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Re: [U-Boot] [PATCH] phy: comphy_a3700: Change SD/MMC compatible DT node to match the updates

2017-01-30 Thread Jaehoon Chung
Hi Stefan,

On 01/25/2017 04:51 PM, Stefan Roese wrote:
> Now that the SD/SDIO/MMC DT properties are updated in the Marvell
> A3700 and A7/8k DT files, we need to match the checks for compatible
> node in the PHY driver as well.

This patch was delegated to me. But i think right that it might be delegated to 
you.
I will change to you. If there is a problem, let me know, plz.

Best Regards,
Jaehoon Chung

> 
> Signed-off-by: Stefan Roese 
> Cc: Kostya Porotchkin 
> Cc: Nadav Haklai 
> ---
>  drivers/phy/marvell/comphy_a3700.c | 7 +++
>  1 file changed, 3 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/phy/marvell/comphy_a3700.c 
> b/drivers/phy/marvell/comphy_a3700.c
> index faa62f90ae..5afd23c052 100644
> --- a/drivers/phy/marvell/comphy_a3700.c
> +++ b/drivers/phy/marvell/comphy_a3700.c
> @@ -884,11 +884,10 @@ void comphy_dedicated_phys_init(void)
>   }
>  
>   node = fdt_node_offset_by_compatible(blob, -1,
> -  "marvell,armada-3700-sdio");
> +  "marvell,armada-8k-sdhci");
>   if (node <= 0) {
> - debug("No SDIO node in DT, looking for MMC one\n");
> - node = fdt_node_offset_by_compatible(blob, -1,
> -  "marvell,xenon-sdhci");
> + node = fdt_node_offset_by_compatible(
> + blob, -1, "marvell,armada-3700-sdhci");
>   }
>  
>   if (node > 0) {
> 

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Re: [U-Boot] [PATCH v3 3/3] odroid-c2: enable new Meson GX MMC driver in board defconfig

2017-01-30 Thread Jaehoon Chung
Hi Heiner,

On 01/28/2017 05:56 AM, Heiner Kallweit wrote:
> Enable new Meson GX MMC driver in Odroid C2 defconfig.

Conflicts this patch on latest u-boot.

Best Regards,
Jaehoon Chung

> 
> Signed-off-by: Heiner Kallweit 
> ---
> v2:
> - move GXBB_PINMUX definition from patch 3 to this one
> v3:
> - remove pinmux configuration in board init and use
>   pinctrl driver instead
> ---
>  configs/odroid-c2_defconfig | 5 -
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/configs/odroid-c2_defconfig b/configs/odroid-c2_defconfig
> index 119ab07..824dd6c 100644
> --- a/configs/odroid-c2_defconfig
> +++ b/configs/odroid-c2_defconfig
> @@ -3,7 +3,9 @@ CONFIG_ARCH_MESON=y
>  CONFIG_MESON_GXBB=y
>  CONFIG_TARGET_ODROID_C2=y
>  CONFIG_IDENT_STRING=" odroid-c2"
> -# CONFIG_MMC is not set
> +CONFIG_MMC=y
> +CONFIG_DM_MMC=y
> +CONFIG_MMC_MESON_GX=y
>  CONFIG_DEFAULT_DEVICE_TREE="meson-gxbb-odroidc2"
>  # CONFIG_DISPLAY_CPUINFO is not set
>  # CONFIG_DISPLAY_BOARDINFO is not set
> @@ -14,6 +16,7 @@ CONFIG_HUSH_PARSER=y
>  # CONFIG_CMD_LOADS is not set
>  # CONFIG_CMD_FPGA is not set
>  # CONFIG_CMD_SETEXPR is not set
> +CONFIG_CMD_MMC=y
>  CONFIG_OF_CONTROL=y
>  CONFIG_NET_RANDOM_ETHADDR=y
>  CONFIG_DM_ETH=y
> 

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[U-Boot] [PATCH] ARM: dts: k2*: Rename the k2* files to keystone-k2* files

2017-01-30 Thread Lokesh Vutla
As reported in [1], rename the k2* dts files to keystone-* files
this will force consistency throughout.

Script for the same (and hand modified for Makefile and config
files):
for i in arch/arm/dts/k2*
do
b=`basename $i`;
git mv $i arch/arm/dts/keystone-$b;
sed -i -e "s/$b/keystone-$b/g" arch/arm/dts/*[si]
done

This is similar to linux kernel commit 5edafc29829bc ("ARM: dts: k2*: Rename
the k2* files to keystone-k2* files")

[1] http://marc.info/?l=linux-arm-kernel&m=145637407804754&w=2

Signed-off-by: Lokesh Vutla 
---
 arch/arm/dts/Makefile| 8 
 arch/arm/dts/{k2e-clocks.dtsi => keystone-k2e-clocks.dtsi}   | 0
 arch/arm/dts/{k2e-evm.dts => keystone-k2e-evm.dts}   | 2 +-
 arch/arm/dts/{k2e-netcp.dtsi => keystone-k2e-netcp.dtsi} | 0
 arch/arm/dts/{k2e.dtsi => keystone-k2e.dtsi} | 4 ++--
 arch/arm/dts/{k2g-evm.dts => keystone-k2g-evm.dts}   | 6 +++---
 arch/arm/dts/{k2g-netcp.dtsi => keystone-k2g-netcp.dtsi} | 2 +-
 arch/arm/dts/{k2g.dtsi => keystone-k2g.dtsi} | 6 +++---
 arch/arm/dts/{k2hk-clocks.dtsi => keystone-k2hk-clocks.dtsi} | 0
 arch/arm/dts/{k2hk-evm.dts => keystone-k2hk-evm.dts} | 2 +-
 arch/arm/dts/{k2hk-netcp.dtsi => keystone-k2hk-netcp.dtsi}   | 0
 arch/arm/dts/{k2hk.dtsi => keystone-k2hk.dtsi}   | 4 ++--
 arch/arm/dts/{k2l-clocks.dtsi => keystone-k2l-clocks.dtsi}   | 0
 arch/arm/dts/{k2l-evm.dts => keystone-k2l-evm.dts}   | 2 +-
 arch/arm/dts/{k2l-netcp.dtsi => keystone-k2l-netcp.dtsi} | 0
 arch/arm/dts/{k2l.dtsi => keystone-k2l.dtsi} | 4 ++--
 configs/k2e_evm_defconfig| 2 +-
 configs/k2g_evm_defconfig| 2 +-
 configs/k2hk_evm_defconfig   | 2 +-
 configs/k2l_evm_defconfig| 2 +-
 20 files changed, 24 insertions(+), 24 deletions(-)
 rename arch/arm/dts/{k2e-clocks.dtsi => keystone-k2e-clocks.dtsi} (100%)
 rename arch/arm/dts/{k2e-evm.dts => keystone-k2e-evm.dts} (98%)
 rename arch/arm/dts/{k2e-netcp.dtsi => keystone-k2e-netcp.dtsi} (100%)
 rename arch/arm/dts/{k2e.dtsi => keystone-k2e.dtsi} (97%)
 rename arch/arm/dts/{k2g-evm.dts => keystone-k2g-evm.dts} (95%)
 rename arch/arm/dts/{k2g-netcp.dtsi => keystone-k2g-netcp.dtsi} (98%)
 rename arch/arm/dts/{k2g.dtsi => keystone-k2g.dtsi} (97%)
 rename arch/arm/dts/{k2hk-clocks.dtsi => keystone-k2hk-clocks.dtsi} (100%)
 rename arch/arm/dts/{k2hk-evm.dts => keystone-k2hk-evm.dts} (99%)
 rename arch/arm/dts/{k2hk-netcp.dtsi => keystone-k2hk-netcp.dtsi} (100%)
 rename arch/arm/dts/{k2hk.dtsi => keystone-k2hk.dtsi} (96%)
 rename arch/arm/dts/{k2l-clocks.dtsi => keystone-k2l-clocks.dtsi} (100%)
 rename arch/arm/dts/{k2l-evm.dts => keystone-k2l-evm.dts} (98%)
 rename arch/arm/dts/{k2l-netcp.dtsi => keystone-k2l-netcp.dtsi} (100%)
 rename arch/arm/dts/{k2l.dtsi => keystone-k2l.dtsi} (96%)

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 796b24d76e..e19b8c01fb 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -319,10 +319,10 @@ dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \
 
 dtb-$(CONFIG_MX7) += imx7-colibri.dtb
 
-dtb-$(CONFIG_SOC_KEYSTONE) += k2hk-evm.dtb \
-   k2l-evm.dtb \
-   k2e-evm.dtb \
-   k2g-evm.dtb
+dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \
+   keystone-k2l-evm.dtb \
+   keystone-k2e-evm.dtb \
+   keystone-k2g-evm.dtb
 
 dtb-$(CONFIG_TARGET_SAMA5D2_XPLAINED) += \
at91-sama5d2_xplained.dtb
diff --git a/arch/arm/dts/k2e-clocks.dtsi 
b/arch/arm/dts/keystone-k2e-clocks.dtsi
similarity index 100%
rename from arch/arm/dts/k2e-clocks.dtsi
rename to arch/arm/dts/keystone-k2e-clocks.dtsi
diff --git a/arch/arm/dts/k2e-evm.dts b/arch/arm/dts/keystone-k2e-evm.dts
similarity index 98%
rename from arch/arm/dts/k2e-evm.dts
rename to arch/arm/dts/keystone-k2e-evm.dts
index e2c3fb4910..3be8b53252 100644
--- a/arch/arm/dts/k2e-evm.dts
+++ b/arch/arm/dts/keystone-k2e-evm.dts
@@ -10,7 +10,7 @@
 /dts-v1/;
 
 #include "keystone.dtsi"
-#include "k2e.dtsi"
+#include "keystone-k2e.dtsi"
 
 / {
compatible =  "ti,k2e-evm","ti,keystone";
diff --git a/arch/arm/dts/k2e-netcp.dtsi b/arch/arm/dts/keystone-k2e-netcp.dtsi
similarity index 100%
rename from arch/arm/dts/k2e-netcp.dtsi
rename to arch/arm/dts/keystone-k2e-netcp.dtsi
diff --git a/arch/arm/dts/k2e.dtsi b/arch/arm/dts/keystone-k2e.dtsi
similarity index 97%
rename from arch/arm/dts/k2e.dtsi
rename to arch/arm/dts/keystone-k2e.dtsi
index 675fb8e492..b5d906184c 100644
--- a/arch/arm/dts/k2e.dtsi
+++ b/arch/arm/dts/keystone-k2e.dtsi
@@ -41,7 +41,7 @@
};
 
soc {
-   /include/ "k2e-clocks.dtsi"
+   /include/ "keystone-k2e-clocks.dtsi"
 
usb: usb@268 {
interrupts = ;
@@ -142,6 +142,6 @@
clock-names = "fck";
  

Re: [U-Boot] [u-boot PATCH v2 2/8] ti: common: board_detect: commodify ethaddr environment setting code

2017-01-30 Thread Lokesh Vutla


On Monday 30 January 2017 08:45 PM, Roger Quadros wrote:
> Keystone and OMAP platforms will need this to set ethernet
> MAC addresses from board EEPROM.
> 
> Signed-off-by: Roger Quadros 

Reviewed-by: Lokesh Vutla 

Thanks and regards,
Lokesh
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Re: [U-Boot] [u-boot PATCH v2 1/8] ARM: OMAP5+: GPIO: Add GPIO_TO_PIN() macro

2017-01-30 Thread Lokesh Vutla


On Monday 30 January 2017 08:45 PM, Quadros, Roger wrote:
> GPIO_TO_PIN(bank, bank_gpio) returns the GPIO index
> from the GPIO bank number and bank's GPIO offset number.
> 
> Signed-off-by: Roger Quadros 
> Reviewed-by: Tom Rini 

Reviewed-by: Lokesh Vutla 

Thanks and regards,
Lokesh

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Re: [U-Boot] [u-boot PATCH v2 3/8] board: ti: am571x-idk: Support 6 port Ethernet or 4 port Ethernet with LCD

2017-01-30 Thread Lokesh Vutla


On Monday 30 January 2017 08:45 PM, Roger Quadros wrote:
> The board can support either ICSS1 Ethernet ports or LCD
> based on J51 jumper. Factory default is ICSS1 Ethernet ports
> (i.e. Jumper not populated).
> 
> Use the GPIO to detect the jumper setting and configure the
> pinmux accordingly. Also select the right DT blob based on
> the chosen configuration.
> 
> J51 absent -> ICSS1 Ethernet, no LCD on VOUT -> am571x-idk.dtb
> J51 present -> LCD on VOUT, no ICSS1 Ethernet -> am571x-idk-lcd-osd.dtb
> 
> At present we only support the assume it is the Legacy LCD.
> LCD detection mechanism needs to be added later to differentiate
> between legacy vs new LCD.
> 
> For ICSS1 Ethernet pins use the following convention to set the pinmux
> as PMT data is not yet finalized.
> 
> - If pin is output, set as PIN_OUTPUT
> - If pin is input and external pull resistor present set as PIN_INPUT
> - If pin is input and external pull resistor absent, set pull to same
> as that of the external PHY's internall pull.
> - Do not use SLEW_CONTROLon any pin.
> 
> Cc: Nishanth Menon 
> Signed-off-by: Roger Quadros 
> Reviewed-by: Tom Rini 

Reviewed-by: Lokesh Vutla 

Thanks and regards,
Lokesh
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Re: [U-Boot] [u-boot PATCH v2 4/8] board: ti: am571x-idk: Update pinmux for ICSS2 Ethernet

2017-01-30 Thread Lokesh Vutla


On Monday 30 January 2017 08:45 PM, Roger Quadros wrote:
> Use the same convention that was used for ICSS1 Ethernet
> - If pin is output, set as PIN_OUTPUT
> - If pin is input and external pull resistor present set as PIN_INPUT
> - If pin is input and external pull resistor absent, set pull to same
> as that of the external PHY's internall pull.
> 
> Signed-off-by: Roger Quadros 
> Reviewed-by: Tom Rini 

Reviewed-by: Lokesh Vutla 

Thanks and regards,
Lokesh
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Re: [U-Boot] [u-boot PATCH v2 6/8] ARM: Use Kconfig for board EEPROM's I2C bus and chip address

2017-01-30 Thread Lokesh Vutla


On Monday 30 January 2017 08:45 PM, Roger Quadros wrote:
> In stead of defining the board EEPROM address in the board headers
> let's define them in the board config files and make them
> configurable by Kconfig.
> 
> Signed-off-by: Roger Quadros 
> ---
>  arch/arm/Kconfig  | 10 ++
>  configs/am57xx_evm_defconfig  |  2 ++
>  configs/am57xx_evm_nodt_defconfig |  2 ++
>  configs/am57xx_hs_evm_defconfig   |  2 ++
>  configs/dra7xx_evm_defconfig  |  2 ++
>  configs/dra7xx_hs_evm_defconfig   |  2 ++
>  include/configs/am57xx_evm.h  |  4 
>  include/configs/dra7xx_evm.h  |  4 
>  8 files changed, 20 insertions(+), 8 deletions(-)
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index c04adfb..19886ad 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1009,6 +1009,16 @@ config TARGET_THUNDERX_88XX
>  
>  endchoice
>  
> +config EEPROM_BUS_ADDRESS
> +int "Board EEPROM's I2C bus address"
> +range 0 8
> +default 0
> +
> +config EEPROM_CHIP_ADDRESS
> +hex "Board EEPROM's I2C chip address"
> +range 0 0xff
> +default 0x50
> +

IMO, these should be placed in board/ti/common/Kconfig. Also need not
specify the value explicitly in defconfig if default value is used.

Thanks and regards,
Lokesh

>  source "arch/arm/mach-at91/Kconfig"
>  
>  source "arch/arm/mach-bcm283x/Kconfig"
> diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
> index 656d991..3b3e74a 100644
> --- a/configs/am57xx_evm_defconfig
> +++ b/configs/am57xx_evm_defconfig
> @@ -2,6 +2,8 @@ CONFIG_ARM=y
>  CONFIG_OMAP54XX=y
>  # CONFIG_SPL_NAND_SUPPORT is not set
>  CONFIG_TARGET_AM57XX_EVM=y
> +CONFIG_EEPROM_BUS_ADDRESS=0
> +CONFIG_EEPROM_CHIP_ADDRESS=0x50
>  CONFIG_SPL_SPI_FLASH_SUPPORT=y
>  CONFIG_SPL_SPI_SUPPORT=y
>  CONFIG_ARMV7_LPAE=y
> diff --git a/configs/am57xx_evm_nodt_defconfig 
> b/configs/am57xx_evm_nodt_defconfig
> index b3b95f9..8d722e7 100644
> --- a/configs/am57xx_evm_nodt_defconfig
> +++ b/configs/am57xx_evm_nodt_defconfig
> @@ -2,6 +2,8 @@ CONFIG_ARM=y
>  CONFIG_OMAP54XX=y
>  # CONFIG_SPL_NAND_SUPPORT is not set
>  CONFIG_TARGET_AM57XX_EVM=y
> +CONFIG_EEPROM_BUS_ADDRESS=0
> +CONFIG_EEPROM_CHIP_ADDRESS=0x50
>  CONFIG_SPL_SPI_FLASH_SUPPORT=y
>  CONFIG_SPL_SPI_SUPPORT=y
>  CONFIG_SYS_CONSOLE_INFO_QUIET=y
> diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig
> index d920d68..36c8004 100644
> --- a/configs/am57xx_hs_evm_defconfig
> +++ b/configs/am57xx_hs_evm_defconfig
> @@ -3,6 +3,8 @@ CONFIG_OMAP54XX=y
>  CONFIG_TI_SECURE_DEVICE=y
>  # CONFIG_SPL_NAND_SUPPORT is not set
>  CONFIG_TARGET_AM57XX_EVM=y
> +CONFIG_EEPROM_BUS_ADDRESS=0
> +CONFIG_EEPROM_CHIP_ADDRESS=0x50
>  CONFIG_TI_SECURE_EMIF_REGION_START=0xbe00
>  CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x0200
>  CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c0
> diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
> index 1836021..3108c58 100644
> --- a/configs/dra7xx_evm_defconfig
> +++ b/configs/dra7xx_evm_defconfig
> @@ -2,6 +2,8 @@ CONFIG_ARM=y
>  CONFIG_OMAP54XX=y
>  # CONFIG_SPL_NAND_SUPPORT is not set
>  CONFIG_TARGET_DRA7XX_EVM=y
> +CONFIG_EEPROM_BUS_ADDRESS=0
> +CONFIG_EEPROM_CHIP_ADDRESS=0x50
>  CONFIG_SPL_SPI_FLASH_SUPPORT=y
>  CONFIG_SPL_SPI_SUPPORT=y
>  CONFIG_ARMV7_LPAE=y
> diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig
> index 1d107e4..7f5ce49 100644
> --- a/configs/dra7xx_hs_evm_defconfig
> +++ b/configs/dra7xx_hs_evm_defconfig
> @@ -4,6 +4,8 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
>  CONFIG_TI_SECURE_DEVICE=y
>  # CONFIG_SPL_NAND_SUPPORT is not set
>  CONFIG_TARGET_DRA7XX_EVM=y
> +CONFIG_EEPROM_BUS_ADDRESS=0
> +CONFIG_EEPROM_CHIP_ADDRESS=0x50
>  CONFIG_TI_SECURE_EMIF_REGION_START=0xbe00
>  CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x0200
>  CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c0
> diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h
> index 840502c..d9e1119 100644
> --- a/include/configs/am57xx_evm.h
> +++ b/include/configs/am57xx_evm.h
> @@ -105,10 +105,6 @@
>  #define CONFIG_SYS_SCSI_MAX_DEVICE   (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
>   CONFIG_SYS_SCSI_MAX_LUN)
>  
> -/* EEPROM */
> -#define CONFIG_EEPROM_CHIP_ADDRESS 0x50
> -#define CONFIG_EEPROM_BUS_ADDRESS 0
> -
>  /*
>   * Default to using SPI for environment, etc.
>   * 0x00 - 0x04 : QSPI.SPL (256KiB)
> diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
> index da458a4..46beb8b 100644
> --- a/include/configs/dra7xx_evm.h
> +++ b/include/configs/dra7xx_evm.h
> @@ -264,8 +264,4 @@
>  #endif
>  #endif  /* NOR support */
>  
> -/* EEPROM */
> -#define CONFIG_EEPROM_CHIP_ADDRESS 0x50
> -#define CONFIG_EEPROM_BUS_ADDRESS 0
> -
>  #endif /* __CONFIG_DRA7XX_EVM_H */
> 
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Re: [U-Boot] [u-boot PATCH v2 7/8] ARM: k2g: setup PRU ethernet MAC addresses

2017-01-30 Thread Lokesh Vutla


On Monday 30 January 2017 08:45 PM, Roger Quadros wrote:
> PRU ethernet MAC address range is present in the
> board EEPROM. Parse it and setup eth?addr
> environment variables.
> 
> Signed-off-by: Roger Quadros 
> ---
>  board/ti/ks2_evm/board_k2g.c | 19 +++
>  configs/k2g_evm_defconfig|  2 ++
>  2 files changed, 21 insertions(+)
> 
> diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c
> index 40edbaa..a738dd2 100644
> --- a/board/ti/ks2_evm/board_k2g.c
> +++ b/board/ti/ks2_evm/board_k2g.c
> @@ -12,6 +12,7 @@
>  #include 
>  #include 
>  #include "mux-k2g.h"
> +#include "../common/board_detect.h"
>  
>  #define SYS_CLK  2400
>  
> @@ -149,6 +150,24 @@ int board_early_init_f(void)
>  }
>  #endif
>  
> +#ifdef CONFIG_BOARD_LATE_INIT
> +int board_late_init(void)
> +{
> +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_TI_I2C_BOARD_DETECT)
> + int rc;
> +
> + rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
> + CONFIG_EEPROM_CHIP_ADDRESS);
> + if (rc)
> + printf("ti_i2c_eeprom_init failed %d\n", rc);
> +
> + board_ti_set_ethaddr(1);
> +#endif
> +
> + return 0;
> +}
> +#endif
> +
>  #ifdef CONFIG_SPL_BUILD
>  void spl_init_keystone_plls(void)
>  {
> diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig
> index 5251105..372e20b 100644
> --- a/configs/k2g_evm_defconfig
> +++ b/configs/k2g_evm_defconfig
> @@ -3,6 +3,8 @@ CONFIG_ARCH_KEYSTONE=y
>  CONFIG_SPL_LIBCOMMON_SUPPORT=y
>  CONFIG_SPL_LIBGENERIC_SUPPORT=y
>  CONFIG_TARGET_K2G_EVM=y
> +CONFIG_EEPROM_BUS_ADDRESS=0
> +CONFIG_EEPROM_CHIP_ADDRESS=0x50

This can be dropped as these are the default values. Rest looks good to me.

Reviewed-by: Lokesh Vutla 

Thanks and regards,
Lokesh
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Re: [U-Boot] [PATCH 15/16] i2c: uniphier(-f): remove unneeded #include

2017-01-30 Thread Heiko Schocher

Hello Masahiro,

Am 27.01.2017 um 22:53 schrieb Masahiro Yamada:

This include is unnecessary for low-level drivers.

Signed-off-by: Masahiro Yamada 
---

  drivers/i2c/i2c-uniphier-f.c | 1 -
  drivers/i2c/i2c-uniphier.c   | 1 -
  2 files changed, 2 deletions(-)


Reviewed-by: Heiko Schocher 

bye,
Heiko


diff --git a/drivers/i2c/i2c-uniphier-f.c b/drivers/i2c/i2c-uniphier-f.c
index 8bfa916..e212c13 100644
--- a/drivers/i2c/i2c-uniphier-f.c
+++ b/drivers/i2c/i2c-uniphier-f.c
@@ -12,7 +12,6 @@
  #include 
  #include 
  #include 
-#include 
  #include 
  #include 

diff --git a/drivers/i2c/i2c-uniphier.c b/drivers/i2c/i2c-uniphier.c
index f391f11..73575e9 100644
--- a/drivers/i2c/i2c-uniphier.c
+++ b/drivers/i2c/i2c-uniphier.c
@@ -12,7 +12,6 @@
  #include 
  #include 
  #include 
-#include 
  #include 
  #include 




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Re: [U-Boot] [PATCH 16/16] i2c: uniphier-f: use readl_poll_timeout() to poll registers

2017-01-30 Thread Heiko Schocher

Hello Masahiro,

Am 27.01.2017 um 22:53 schrieb Masahiro Yamada:

The readl_poll_timeout() is a useful helper to poll registers
and error out if the condition is not met.

Signed-off-by: Masahiro Yamada 
---

  drivers/i2c/i2c-uniphier-f.c | 34 ++
  1 file changed, 10 insertions(+), 24 deletions(-)


Reviewed-by: Heiko Schocher 

bye,
Heiko


diff --git a/drivers/i2c/i2c-uniphier-f.c b/drivers/i2c/i2c-uniphier-f.c
index e212c13..9f0df59 100644
--- a/drivers/i2c/i2c-uniphier-f.c
+++ b/drivers/i2c/i2c-uniphier-f.c
@@ -9,6 +9,7 @@
  #include 
  #include 
  #include 
+#include 
  #include 
  #include 
  #include 
@@ -69,26 +70,14 @@ struct uniphier_fi2c_dev {
unsigned long timeout;  /* time out (us) */
  };

-static int poll_status(u32 __iomem *reg, u32 flag)
-{
-   int wait = 100; /* 1 sec is long enough */
-
-   while (readl(reg) & flag) {
-   if (wait-- < 0)
-   return -EREMOTEIO;
-   udelay(1);
-   }
-
-   return 0;
-}
-
  static int reset_bus(struct uniphier_fi2c_regs __iomem *regs)
  {
+   u32 val;
int ret;

/* bus forcible reset */
writel(I2C_RST_RST, ®s->rst);
-   ret = poll_status(®s->rst, I2C_RST_RST);
+   ret = readl_poll_timeout(®s->rst, val, !(val & I2C_RST_RST), 1);
if (ret < 0)
debug("error: fail to reset I2C controller\n");

@@ -97,9 +86,10 @@ static int reset_bus(struct uniphier_fi2c_regs __iomem *regs)

  static int check_device_busy(struct uniphier_fi2c_regs __iomem *regs)
  {
+   u32 val;
int ret;

-   ret = poll_status(®s->sr, I2C_SR_DB);
+   ret = readl_poll_timeout(®s->sr, val, !(val & I2C_SR_DB), 100);
if (ret < 0) {
debug("error: device busy too long. reset...\n");
ret = reset_bus(regs);
@@ -138,15 +128,11 @@ static int wait_for_irq(struct uniphier_fi2c_dev *dev, 
u32 flags,
bool *stop)
  {
u32 irq;
-   unsigned long wait = dev->timeout;
-   int ret = -EREMOTEIO;
-
-   do {
-   udelay(1);
-   irq = readl(&dev->regs->intr);
-   } while (!(irq & flags) && wait--);
+   int ret;

-   if (wait < 0) {
+   ret = readl_poll_timeout(&dev->regs->intr, irq, irq & flags,
+dev->timeout);
+   if (ret < 0) {
debug("error: time out\n");
return ret;
}
@@ -172,7 +158,7 @@ static int issue_stop(struct uniphier_fi2c_dev *dev, int 
old_ret)
debug("stop condition\n");
writel(I2C_CR_MST | I2C_CR_STO, &dev->regs->cr);

-   ret = poll_status(&dev->regs->sr, I2C_SR_DB);
+   ret = check_device_busy(dev->regs);
if (ret < 0)
debug("error: device busy after operation\n");




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Re: [U-Boot] [PATCH] phy: comphy_a3700: Change SD/MMC compatible DT node to match the updates

2017-01-30 Thread Stefan Roese

Hi Jaehoon,

On 31.01.2017 04:43, Jaehoon Chung wrote:

On 01/25/2017 04:51 PM, Stefan Roese wrote:

Now that the SD/SDIO/MMC DT properties are updated in the Marvell
A3700 and A7/8k DT files, we need to match the checks for compatible
node in the PHY driver as well.


This patch was delegated to me. But i think right that it might be delegated to 
you.
I will change to you.


Thats just fine.


If there is a problem, let me know, plz.


No problem.

Thanks,
Stefan
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Re: [U-Boot] [PATCH] phy: comphy_a3700: Change SD/MMC compatible DT node to match the updates

2017-01-30 Thread Jaehoon Chung
Hi Stefan,

On 01/31/2017 02:44 PM, Stefan Roese wrote:
> Hi Jaehoon,
> 
> On 31.01.2017 04:43, Jaehoon Chung wrote:
>> On 01/25/2017 04:51 PM, Stefan Roese wrote:
>>> Now that the SD/SDIO/MMC DT properties are updated in the Marvell
>>> A3700 and A7/8k DT files, we need to match the checks for compatible
>>> node in the PHY driver as well.
>>
>> This patch was delegated to me. But i think right that it might be delegated 
>> to you.
>> I will change to you.
> 
> Thats just fine.
> 
>> If there is a problem, let me know, plz.
> 
> No problem.

Thanks! Anyway, I have checked this patch, it looks good to me.

Reviewed-by: Jaehoon Chung 

Best Regards,
Jaehoon Chung

> 
> Thanks,
> Stefan
> 
> 
> 

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[U-Boot] [PATCH v2 1/8] armv8: Add workaround for USB erratum A-009008

2017-01-30 Thread Suresh Gupta
From: Suresh Gupta 

USB High Speed (HS) EYE Height Adjustment
USB HS speed eye diagram fails with the default value at
many corners, particularly at a high temperature

Optimal eye at TXVREFTUNE value to 1001 is observed, change
set the same vale.

Signed-off-by: Sriram Dash 
Signed-off-by: Rajesh Bhagat 
Signed-off-by: Suresh Gupta 
---
Changes in v2: None

 arch/arm/cpu/armv8/fsl-layerscape/Kconfig  |  6 ++
 arch/arm/cpu/armv8/fsl-layerscape/soc.c| 25 ++
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  6 ++
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  1 +
 4 files changed, 38 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index de0b580..666a3d1 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -18,6 +18,7 @@ config ARCH_LS1043A
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_ERRATUM_A010539
+   select SYS_FSL_ERRATUM_A009008
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_DDR4
 
@@ -33,6 +34,7 @@ config ARCH_LS1046A
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010165
select SYS_FSL_ERRATUM_A010539
+   select SYS_FSL_ERRATUM_A009008
select SYS_FSL_HAS_DDR4
select SYS_FSL_SRDS_2
 
@@ -58,6 +60,7 @@ config ARCH_LS2080A
select SYS_FSL_ERRATUM_A009803
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010165
+   select SYS_FSL_ERRATUM_A009008
 
 config FSL_LSCH2
bool
@@ -102,6 +105,9 @@ config SYS_FSL_ERRATUM_A010315
 config SYS_FSL_ERRATUM_A010539
bool "Workaround for PIN MUX erratum A010539"
 
+config SYS_FSL_ERRATUM_A009008
+   bool "Workaround for USB PHY erratum A009008"
+
 config MAX_CPUS
int "Maximum number of CPUs permitted for Layerscape"
default 4 if ARCH_LS1043A
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 2f54625..951ccba 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -52,6 +52,29 @@ bool soc_has_aiop(void)
return false;
 }
 
+static void erratum_a009008(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009008
+#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1046A)
+   u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+   u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB1 / 4);
+   val &= ~(0xF << 6);
+   scfg_out32(scfg + SCFG_USB3PRM1CR_USB1 / 4, val|(USB_TXVREFTUNE << 6));
+   val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB2 / 4);
+   val &= ~(0xF << 6);
+   scfg_out32(scfg + SCFG_USB3PRM1CR_USB2 / 4, val|(USB_TXVREFTUNE << 6));
+   val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB3 / 4);
+   val &= ~(0xF << 6);
+   scfg_out32(scfg + SCFG_USB3PRM1CR_USB3 / 4, val|(USB_TXVREFTUNE << 6));
+#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+   u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+   u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR / 4);
+   val &= ~(0xF << 6);
+   scfg_out32(scfg + SCFG_USB3PRM1CR / 4, val|(USB_TXVREFTUNE << 6));
+#endif
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
+}
+
 #if defined(CONFIG_FSL_LSCH3)
 /*
  * This erratum requires setting a value to eddrtqcr1 to
@@ -194,6 +217,7 @@ void fsl_lsch3_early_init_f(void)
erratum_a009203();
erratum_a008514();
erratum_a008336();
+   erratum_a009008();
 #ifdef CONFIG_CHAIN_OF_TRUST
/* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
@@ -370,6 +394,7 @@ void fsl_lsch2_early_init_f(void)
erratum_a009929();
erratum_a009660();
erratum_a010539();
+   erratum_a009008();
 }
 #endif
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index b3cfd89..fe37bc1 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -336,6 +336,12 @@ struct ccsr_gur {
 #define SCFG_USBPWRFAULT_USB2_SHIFT2
 #define SCFG_USBPWRFAULT_USB1_SHIFT0
 
+#define SCFG_BASE  0x0157
+#define SCFG_USB3PRM1CR_USB1   0x070
+#define SCFG_USB3PRM1CR_USB2   0x07C
+#define SCFG_USB3PRM1CR_USB3   0x088
+#define USB_TXVREFTUNE 0x9
+
 #define SCFG_SNPCNFGCR_SECRDSNP0x8000
 #define SCFG_SNPCNFGCR_SECWRSNP0x4000
 #define SCFG_SNPCNFGCR_SATARDSNP   0x0080
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index e18dcbd..9aad471 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -137,6 +137,7 @@
 #define SCFG_BASE  0x01fc

[U-Boot] [PATCH] LS1021ATWR: Modify u-boot size for sd secure boot

2017-01-30 Thread Vinitha Pillai-B57223
From: Vinitha Pillai 

Raw uboot image is used in place of FIT image in secure boot.
The maximum allocated size of raw u-boot bin is 1MB in memory map.
Hence , CONFIG_SYS_MONITOR_LEN has been modified to 1 MB.
The bootscript  (BS_ADDR) and its header (BS_HDR_ADDR) offset on 
MMC have also been modified to accommodate the increase in uboot size.

Signed-off-by: Vinitha Pillai-B57223 
Reviewed-by: Sumit Garg 
Reviewed-by: Ruchika Gupta 
Reviewed-by: Prabhakar Kushwaha 
---
 arch/arm/include/asm/fsl_secure_boot.h | 4 ++--
 include/configs/ls1021atwr.h   | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/include/asm/fsl_secure_boot.h 
b/arch/arm/include/asm/fsl_secure_boot.h
index 4525287..0ef7315 100644
--- a/arch/arm/include/asm/fsl_secure_boot.h
+++ b/arch/arm/include/asm/fsl_secure_boot.h
@@ -99,8 +99,8 @@
 /* For SD boot address and size are assigned in terms of sector
  * offset and no. of sectors respectively.
  */
-#define CONFIG_BS_HDR_ADDR_DEVICE  0x0800
-#define CONFIG_BS_ADDR_DEVICE  0x0840
+#define CONFIG_BS_HDR_ADDR_DEVICE  0x0900
+#define CONFIG_BS_ADDR_DEVICE  0x0940
 #define CONFIG_BS_HDR_SIZE 0x0010
 #define CONFIG_BS_SIZE 0x0008
 #else
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index b48cd00..178239f 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -134,9 +134,9 @@
  * size increases then increase this size in case of secure boot as
  * it uses raw u-boot image instead of fit image.
  */
-#define CONFIG_SYS_MONITOR_LEN (0x8 + CONFIG_U_BOOT_HDR_SIZE)
+#define CONFIG_SYS_MONITOR_LEN (0x10 + CONFIG_U_BOOT_HDR_SIZE)
 #else
-#define CONFIG_SYS_MONITOR_LEN 0x8
+#define CONFIG_SYS_MONITOR_LEN 0x10
 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
 #endif
 
-- 
1.9.1

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[U-Boot] [PATCH 1/3] fsl-lsch3: rename ls2080a_stream_id.h to stream_id_lsch3.h

2017-01-30 Thread Bharat Bhushan
The stream ID allocation for Chasis3.0 devices,
LS1088, LS2088 and LS2080, can be shared.

This patch renames this accordingly.

Signed-off-by: Bharat Bhushan 
---
 .../asm/arch-fsl-layerscape/ls2080a_stream_id.h| 77 --
 .../asm/arch-fsl-layerscape/stream_id_lsch3.h  | 77 ++
 include/configs/ls2080a_common.h   |  2 +-
 3 files changed, 78 insertions(+), 78 deletions(-)
 delete mode 100644 arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h
 create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h 
b/arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h
deleted file mode 100644
index ee28323..000
--- a/arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:GPL-2.0+
- *
- */
-#ifndef __FSL_STREAM_ID_H
-#define __FSL_STREAM_ID_H
-
-/*
- * Stream IDs on ls2080a devices are not hardwired and are
- * programmed by sw.  There are a limited number of stream IDs
- * available, and the partitioning of them is scenario dependent.
- * This header defines the partitioning between legacy, PCI,
- * and DPAA2 devices.
- *
- * This partitioning can be customized in this file depending
- * on the specific hardware config:
- *
- *  -non-PCI legacy, platform devices (USB, SD/MMC, SATA, DMA)
- * -all legacy devices get a unique stream ID assigned and programmed in
- *  their AMQR registers by u-boot
- *
- *  -PCIe
- * -there is a range of stream IDs set aside for PCI in this
- *  file.  U-boot will scan the PCI bus and for each device discovered:
- * -allocate a streamID
- * -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID'
- * -set a msi-map entry in the PEXn controller node in the
- *  device tree (see Documentation/devicetree/bindings/pci/pci-msi.txt
- *  for more info on the msi-map definition)
- *
- *  -DPAA2
- * -u-boot will allocate a range of stream IDs to be used by the Management
- *  Complex for containers and will set these values in the MC DPC image.
- * -the MC is responsible for allocating and setting up 'isolation context
- *  IDs (ICIDs) based on the allocated stream IDs for all DPAA2 devices.
- *
- * On ls2080a SoCs stream IDs are programmed in AMQ registers (32-bits) for
- * each of the different bus masters.  The relationship between
- * the AMQ registers and stream IDs is defined in the table below:
- *  AMQ bitstreamID bit
- *  ---
- *   PL[18] 9// privilege bit
- *  BMT[17] 8// bypass translation
- *   VA[16] 7// reserved
- * [15] -// unused
- * ICID[14:7]   -// unused
- * ICID[6:0]6-0  // isolation context id
- * 
- *
- */
-
-#define AMQ_PL_MASK(0x1 << 18)   /* priviledge bit */
-#define AMQ_BMT_MASK   (0x1 << 17)   /* bypass bit */
-
-#define FSL_INVALID_STREAM_ID  0
-
-#define FSL_BYPASS_AMQ (AMQ_PL_MASK | AMQ_BMT_MASK)
-
-/* legacy devices */
-#define FSL_USB1_STREAM_ID 1
-#define FSL_USB2_STREAM_ID 2
-#define FSL_SDMMC_STREAM_ID3
-#define FSL_SATA1_STREAM_ID4
-#define FSL_SATA2_STREAM_ID5
-#define FSL_DMA_STREAM_ID  6
-
-/* PCI - programmed in PEXn_LUT */
-#define FSL_PEX_STREAM_ID_START7
-#define FSL_PEX_STREAM_ID_END  22
-
-/* DPAA2 - set in MC DPC and alloced by MC */
-#define FSL_DPAA2_STREAM_ID_START  23
-#define FSL_DPAA2_STREAM_ID_END63
-
-#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
new file mode 100644
index 000..ee28323
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ */
+#ifndef __FSL_STREAM_ID_H
+#define __FSL_STREAM_ID_H
+
+/*
+ * Stream IDs on ls2080a devices are not hardwired and are
+ * programmed by sw.  There are a limited number of stream IDs
+ * available, and the partitioning of them is scenario dependent.
+ * This header defines the partitioning between legacy, PCI,
+ * and DPAA2 devices.
+ *
+ * This partitioning can be customized in this file depending
+ * on the specific hardware config:
+ *
+ *  -non-PCI legacy, platform devices (USB, SD/MMC, SATA, DMA)
+ * -all legacy devices get a unique stream ID assigned and programmed in
+ *  their AMQR registers by u-boot
+ *
+ *  -PCIe
+ * -there is a range of stream IDs set aside for PCI in this
+ *  fil

[U-Boot] [PATCH v2 2/8] armv8: Add workaround for USB erratum A-009798

2017-01-30 Thread Suresh Gupta
From: Suresh Gupta 

The default setting for USB High Speed Squelch Threshold results
in a threshold close to or lower than 100mV. This leads to Receiver
Compliance test failure for a 100mV threshold.

The changes shift the threshold from ~100mV towards ~130mV resulting
in passing of USB High Speed Receiver Sensitivity Compliance test

Signed-off-by: Sriram Dash 
Signed-off-by: Rajesh Bhagat 
Signed-off-by: Suresh Gupta 
---
Changes in v2: None

 arch/arm/cpu/armv8/fsl-layerscape/Kconfig   |  6 ++
 arch/arm/cpu/armv8/fsl-layerscape/soc.c | 21 +
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h   |  1 +
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h   |  1 +
 4 files changed, 29 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 666a3d1..10daaa2 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -19,6 +19,7 @@ config ARCH_LS1043A
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_ERRATUM_A009008
+   select SYS_FSL_ERRATUM_A009798
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_DDR4
 
@@ -35,6 +36,7 @@ config ARCH_LS1046A
select SYS_FSL_ERRATUM_A010165
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_ERRATUM_A009008
+   select SYS_FSL_ERRATUM_A009798
select SYS_FSL_HAS_DDR4
select SYS_FSL_SRDS_2
 
@@ -61,6 +63,7 @@ config ARCH_LS2080A
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010165
select SYS_FSL_ERRATUM_A009008
+   select SYS_FSL_ERRATUM_A009798
 
 config FSL_LSCH2
bool
@@ -108,6 +111,9 @@ config SYS_FSL_ERRATUM_A010539
 config SYS_FSL_ERRATUM_A009008
bool "Workaround for USB PHY erratum A009008"
 
+config SYS_FSL_ERRATUM_A009798
+   bool "Workaround for USB PHY erratum A009798"
+
 config MAX_CPUS
int "Maximum number of CPUs permitted for Layerscape"
default 4 if ARCH_LS1043A
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 951ccba..910f345 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -75,6 +75,25 @@ static void erratum_a009008(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
 }
 
+static void erratum_a009798(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009798
+#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1046A)
+   u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+   u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB1 / 4);
+   scfg_out32(scfg + SCFG_USB3PRM1CR_USB1 / 4 , val & USB_SQRXTUNE);
+   val = gur_in32(scfg + SCFG_USB3PRM1CR_USB2 / 4);
+   scfg_out32(scfg + SCFG_USB3PRM1CR_USB2 / 4 , val & USB_SQRXTUNE);
+   val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB3 / 4);
+   scfg_out32(scfg + SCFG_USB3PRM1CR_USB3 / 4 , val & USB_SQRXTUNE);
+#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+   u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+   u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR / 4);
+   scfg_out32(scfg + SCFG_USB3PRM1CR / 4, val & USB_SQRXTUNE);
+#endif
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
+}
+
 #if defined(CONFIG_FSL_LSCH3)
 /*
  * This erratum requires setting a value to eddrtqcr1 to
@@ -218,6 +237,7 @@ void fsl_lsch3_early_init_f(void)
erratum_a008514();
erratum_a008336();
erratum_a009008();
+   erratum_a009798();
 #ifdef CONFIG_CHAIN_OF_TRUST
/* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
@@ -395,6 +415,7 @@ void fsl_lsch2_early_init_f(void)
erratum_a009660();
erratum_a010539();
erratum_a009008();
+   erratum_a009798();
 }
 #endif
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index fe37bc1..ca4a31fe 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -341,6 +341,7 @@ struct ccsr_gur {
 #define SCFG_USB3PRM1CR_USB2   0x07C
 #define SCFG_USB3PRM1CR_USB3   0x088
 #define USB_TXVREFTUNE 0x9
+#define USB_SQRXTUNE   0xFC7F
 
 #define SCFG_SNPCNFGCR_SECRDSNP0x8000
 #define SCFG_SNPCNFGCR_SECWRSNP0x4000
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 9aad471..d726256 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -138,6 +138,7 @@
 #define SCFG_USB3PRM1CR0x000
 #define SCFG_USB3PRM1CR_INIT   0x27672b2a
 #define USB_TXVREFTUNE 0x9
+#define USB_SQRXTUNE   0xFC7F
 #define SCFG_QSPICLKCTLR   0x10
 
 #defi

[U-Boot] [PATCH 2/3] pcie-layerscape: Define stream-ids for Layerscape Chasis-2

2017-01-30 Thread Bharat Bhushan
Layerscape Chasis-2 have PCIe device, some platform devices and
DPAA1 devices which will use stream-ids for iommu level isolation
as they lies behind SMMU.

This patch defines the stream-ids for Chasis-2 devices.
stream-ids for DPAA1 are reserved for future use.

Signed-off-by: Bharat Bhushan 
---
 .../asm/arch-fsl-layerscape/stream_id_lsch2.h  | 60 ++
 include/configs/ls1043a_common.h   |  1 +
 2 files changed, 61 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h
new file mode 100644
index 000..bdfed83
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright 2017 NXP Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ */
+#ifndef __FSL_STREAM_ID_H
+#define __FSL_STREAM_ID_H
+
+/*
+ * Stream IDs on ls1043a devices are not hardwired and are
+ * programmed by sw.  There are a limited number of stream IDs
+ * available, and the partitioning of them is scenario dependent.
+ * This header defines the partitioning between legacy, PCI,
+ * and DPAA1 devices.
+ *
+ * This partitioning can be customized in this file depending
+ * on the specific hardware config:
+ *
+ *  -non-PCI legacy, platform devices (USB, SDHC, SATA, DMA, QE etc)
+ * -all legacy devices get a unique stream ID assigned and programmed in
+ *  their AMQR registers by u-boot
+ *
+ *  -PCIe
+ * -there is a range of stream IDs set aside for PCI in this
+ *  file.  U-boot will scan the PCI bus and for each device discovered:
+ * -allocate a streamID
+ * -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID'
+ * -set a msi-map entry in the PEXn controller node in the
+ *  device tree (see Documentation/devicetree/bindings/pci/pci-msi.txt
+ *  for more info on the msi-map definition)
+ *
+ *  -DPAA1
+ * - Stream ids for DPAA1 use are reserved for future usecase.
+ *
+ */
+
+
+#define FSL_INVALID_STREAM_ID  0
+
+/* legacy devices */
+#define FSL_USB1_STREAM_ID 1
+#define FSL_USB2_STREAM_ID 2
+#define FSL_USB3_STREAM_ID 3
+#define FSL_SDHC_STREAM_ID 4
+#define FSL_SATA_STREAM_ID 5
+#define FSL_QE_STREAM_ID   6
+#define FSL_QDMA_STREAM_ID 7
+#define FSL_EDMA_STREAM_ID 8
+#define FSL_ETR_STREAM_ID  9
+
+/* PCI - programmed in PEXn_LUT */
+#define FSL_PEX_STREAM_ID_START11
+#define FSL_PEX_STREAM_ID_END  26
+
+/* DPAA1 - Stream-ID that can be programmed in DPAA1 h/w */
+#define FSL_DPAA1_STREAM_ID_START  27
+#define FSL_DPAA1_STREAM_ID_END63
+
+#endif
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index aa2b6f1..eee6fad 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -13,6 +13,7 @@
 #define CONFIG_MP
 #define CONFIG_GICV2
 
+#include 
 #include 
 
 /* Link Definitions */
-- 
1.9.3

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[U-Boot] [PATCH 3/3] pcie-layerscape: Initialize pci-lut for NXP chasis-2 socs

2017-01-30 Thread Bharat Bhushan
Layerscape Chasis-2 also uses same PCIe controller
as used in Chasis-3 and have similar PCI-Lut.

We need to initialize the pcie-lut for Chasis-2 also
as in Chasis-3.

Signed-off-by: Bharat Bhushan 
---
 drivers/pci/pcie_layerscape_fixup.c | 4 
 1 file changed, 4 deletions(-)

diff --git a/drivers/pci/pcie_layerscape_fixup.c 
b/drivers/pci/pcie_layerscape_fixup.c
index 19ede2f..2f13e1f 100644
--- a/drivers/pci/pcie_layerscape_fixup.c
+++ b/drivers/pci/pcie_layerscape_fixup.c
@@ -15,7 +15,6 @@
 #include 
 #include "pcie_layerscape.h"
 
-#ifdef CONFIG_FSL_LSCH3
 /*
  * Return next available LUT index.
  */
@@ -141,7 +140,6 @@ static void fdt_fixup_pcie(void *blob)
   streamid);
}
 }
-#endif
 
 static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
 {
@@ -175,9 +173,7 @@ void ft_pci_setup(void *blob, bd_t *bd)
list_for_each_entry(pcie, &ls_pcie_list, list)
ft_pcie_ls_setup(blob, pcie);
 
-#ifdef CONFIG_FSL_LSCH3
fdt_fixup_pcie(blob);
-#endif
 }
 
 #else /* !CONFIG_OF_BOARD_SETUP */
-- 
1.9.3

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[U-Boot] [PATCH 0/3] pcie-layerscape: Enable PCI-LUT initialization for NXP-Chasis-2

2017-01-30 Thread Bharat Bhushan
First patch is rename the stream-id defination file to generic
so that this can be leveraged for new SOCs, ls2088, ls1088 etc.

Second add stream-ids allocation for NXP Chasis-2 based SOCs, ls1043, ls1046 
etc.
and Third patch enables PCI-LUT initialization.

Bharat Bhushan (3):
  fsl-lsch3: rename ls2080a_stream_id.h to stream_id_lsch3.h
  pcie-layerscape: Define stream-ids for Layerscape Chasis-2
  pcie-layerscape: Initialize pci-lut for NXP chasis-2 socs

 .../asm/arch-fsl-layerscape/ls2080a_stream_id.h| 77 --
 .../asm/arch-fsl-layerscape/stream_id_lsch2.h  | 60 +
 .../asm/arch-fsl-layerscape/stream_id_lsch3.h  | 77 ++
 drivers/pci/pcie_layerscape_fixup.c|  4 --
 include/configs/ls1043a_common.h   |  1 +
 include/configs/ls2080a_common.h   |  2 +-
 6 files changed, 139 insertions(+), 82 deletions(-)
 delete mode 100644 arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h
 create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h
 create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h

-- 
1.9.3

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[U-Boot] [PATCH v2 8/8] armv7: Add workaround for USB erratum A-009007

2017-01-30 Thread Suresh Gupta
From: Suresh Gupta 

Rx Compliance tests  may fail intermittently at high
jitter frequencies using default register values

Changes identified in test setup makes the Rx compliance test pass

Signed-off-by: Sriram Dash 
Signed-off-by: Rajesh Bhagat 
Signed-off-by: Suresh Gupta 
---
Changes in v2:
Clean up the code after Scott comments, 
Previously in v1, we was defining the pointer as u32,
then casting it to u8, and then passing it to
a 16-bit accessor.

 arch/arm/cpu/armv7/ls102xa/Kconfig|  4 
 arch/arm/cpu/armv7/ls102xa/soc.c  | 12 
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  5 +
 3 files changed, 21 insertions(+)

diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig 
b/arch/arm/cpu/armv7/ls102xa/Kconfig
index a68674f..b7d785e 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -8,6 +8,7 @@ config ARCH_LS1021A
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A008997
+   select SYS_FSL_ERRATUM_A009007
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR_BE if SYS_FSL_DDR
@@ -54,6 +55,9 @@ config SYS_FSL_ERRATUM_A009798
 config SYS_FSL_ERRATUM_A008997
bool "Workaround for USB PHY erratum A008997"
 
+config SYS_FSL_ERRATUM_A009007
+   bool "Workaround for USB PHY erratum A009007"
+
 config SYS_FSL_SRDS_1
bool
 
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 3d6cc5f..edb64d5 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -94,6 +94,17 @@ static void erratum_a008997(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
 }
 
+static void erratum_a009007(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009007
+   void __iomem *usb_phy = (void __iomem *)USB_PHY_BASE;
+   writew(USB_PHY_RX_EQ_VAL_1, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_2, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_3, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_4, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
+}
+
 void s_init(void)
 {
 }
@@ -184,6 +195,7 @@ int arch_soc_init(void)
erratum_a009008();
erratum_a009798();
erratum_a008997();
+   erratum_a009007();
 
return 0;
 }
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h 
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index c0e4372..9c4c926 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -182,10 +182,15 @@ struct ccsr_gur {
 #define USB_PHY_MPLL_OVRD_IN_HI0x0024
 #define USB_PHY_LEVEL_OVRD_IN  0x002a
 #define USB_PHY_TX_OVRD_IN_HI  0x2002
+#define USB_PHY_RX_OVRD_IN_HI  0x200c
 #define USB_PHY_TX_OVRD_DRV_LO_VAL 0x784C
 #define USB_PHY_MPLL_OVRD_IN_HI_VAL0x0080
 #define USB_PHY_LEVEL_OVRD_IN_VAL  0xA9A5
 #define USB_PHY_TX_OVRD_IN_HI_VAL  0x0003
+#define USB_PHY_RX_EQ_VAL_10x
+#define USB_PHY_RX_EQ_VAL_20x8000
+#define USB_PHY_RX_EQ_VAL_30x8004
+#define USB_PHY_RX_EQ_VAL_40x800C
 
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {
-- 
1.9.3

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[U-Boot] [PATCH v2 6/8] armv7: Add workaround for USB erratum A-009798

2017-01-30 Thread Suresh Gupta
From: Suresh Gupta 

The default setting for USB High Speed Squelch Threshold results
in a threshold close to or lower than 100mV. This leads to Receive
Compliance test failure for a 100mV threshold.

The changes shift the threshold from ~100mV towards ~130mV resulting
in passing of USB High Speed Receiver Sensitivity Compliance test

Signed-off-by: Sriram Dash 
Signed-off-by: Rajesh Bhagat 
Signed-off-by: Suresh Gupta 
---
Changes in v2: None

 arch/arm/cpu/armv7/ls102xa/Kconfig|  4 
 arch/arm/cpu/armv7/ls102xa/soc.c  | 10 ++
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  1 +
 3 files changed, 15 insertions(+)

diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig 
b/arch/arm/cpu/armv7/ls102xa/Kconfig
index 40c6782..b7e6e96 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -6,6 +6,7 @@ config ARCH_LS1021A
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_ERRATUM_A009008
+   select SYS_FSL_ERRATUM_A009798
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR_BE if SYS_FSL_DDR
@@ -46,6 +47,9 @@ config SYS_FSL_ERRATUM_A010315
 config SYS_FSL_ERRATUM_A009008
bool "Workaround for USB PHY erratum A009008"
 
+config SYS_FSL_ERRATUM_A009798
+   bool "Workaround for USB PHY erratum A009798"
+
 config SYS_FSL_SRDS_1
bool
 
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index ee27b0c..7ae5b29 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -70,6 +70,15 @@ static void erratum_a009008(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
 }
 
+static void erratum_a009798(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009798
+   u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+   u32 val = in_be32(scfg + SCFG_USB3PRM1CR / 4);
+   out_be32(scfg + SCFG_USB3PRM1CR / 4, val & USB_SQRXTUNE);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
+}
+
 void s_init(void)
 {
 }
@@ -158,6 +167,7 @@ int arch_soc_init(void)
 
/* Erratum */
erratum_a009008();
+   erratum_a009798();
 
return 0;
 }
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h 
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 6ea8c4b..8cafa07 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -176,6 +176,7 @@ struct ccsr_gur {
 #define SCFG_BASE  0x0157
 #define SCFG_USB3PRM1CR0x070
 #define USB_TXVREFTUNE 0x9
+#define USB_SQRXTUNE   0xFC7F
 
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {
-- 
1.9.3

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[U-Boot] [PATCH v2 7/8] armv7: Add workaround for USB erratum A-008997

2017-01-30 Thread Suresh Gupta
From: Suresh Gupta 

Low Frequency Periodic Signaling (LFPS) Peak-to-Peak Differential
Output Voltage Test Compliance fails using default transmitter settings

Change settings required for transmitter signal swings to pass
compliance tests.

Signed-off-by: Sriram Dash 
Signed-off-by: Rajesh Bhagat 
Signed-off-by: Suresh Gupta 
---
Changes in v2:
Clean up the code after Scott comments, 
Previously in v1, we was defining the pointer as u32,
then casting it to u8, and then passing it to
a 16-bit accessor.

 arch/arm/cpu/armv7/ls102xa/Kconfig|  4 
 arch/arm/cpu/armv7/ls102xa/soc.c  | 16 
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  9 +
 3 files changed, 29 insertions(+)

diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig 
b/arch/arm/cpu/armv7/ls102xa/Kconfig
index b7e6e96..a68674f 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -7,6 +7,7 @@ config ARCH_LS1021A
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
+   select SYS_FSL_ERRATUM_A008997
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR_BE if SYS_FSL_DDR
@@ -50,6 +51,9 @@ config SYS_FSL_ERRATUM_A009008
 config SYS_FSL_ERRATUM_A009798
bool "Workaround for USB PHY erratum A009798"
 
+config SYS_FSL_ERRATUM_A008997
+   bool "Workaround for USB PHY erratum A008997"
+
 config SYS_FSL_SRDS_1
bool
 
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 7ae5b29..3d6cc5f 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -79,6 +79,21 @@ static void erratum_a009798(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
 }
 
+static void erratum_a008997(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008997
+   void __iomem *usb_phy = (void __iomem *)USB_PHY_BASE;
+   writew(USB_PHY_TX_OVRD_DRV_LO_VAL,
+  usb_phy + USB_PHY_TX_OVRD_DRV_LO);
+   writew(USB_PHY_MPLL_OVRD_IN_HI_VAL,
+  usb_phy + USB_PHY_MPLL_OVRD_IN_HI);
+   writew(USB_PHY_LEVEL_OVRD_IN_VAL,
+  usb_phy + USB_PHY_LEVEL_OVRD_IN);
+   writew(USB_PHY_TX_OVRD_IN_HI_VAL,
+  usb_phy + USB_PHY_TX_OVRD_IN_HI);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
+}
+
 void s_init(void)
 {
 }
@@ -168,6 +183,7 @@ int arch_soc_init(void)
/* Erratum */
erratum_a009008();
erratum_a009798();
+   erratum_a008997();
 
return 0;
 }
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h 
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 8cafa07..c0e4372 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -177,6 +177,15 @@ struct ccsr_gur {
 #define SCFG_USB3PRM1CR0x070
 #define USB_TXVREFTUNE 0x9
 #define USB_SQRXTUNE   0xFC7F
+#define USB_PHY_BASE   0x0851
+#define USB_PHY_TX_OVRD_DRV_LO 0x2004
+#define USB_PHY_MPLL_OVRD_IN_HI0x0024
+#define USB_PHY_LEVEL_OVRD_IN  0x002a
+#define USB_PHY_TX_OVRD_IN_HI  0x2002
+#define USB_PHY_TX_OVRD_DRV_LO_VAL 0x784C
+#define USB_PHY_MPLL_OVRD_IN_HI_VAL0x0080
+#define USB_PHY_LEVEL_OVRD_IN_VAL  0xA9A5
+#define USB_PHY_TX_OVRD_IN_HI_VAL  0x0003
 
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {
-- 
1.9.3

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[U-Boot] [PATCH v2 2/8] armv8: Add workaround for USB erratum A-009798

2017-01-30 Thread Suresh Gupta
From: Suresh Gupta 

The default setting for USB High Speed Squelch Threshold results
in a threshold close to or lower than 100mV. This leads to Receiver
Compliance test failure for a 100mV threshold.

The changes shift the threshold from ~100mV towards ~130mV resulting
in passing of USB High Speed Receiver Sensitivity Compliance test

Signed-off-by: Sriram Dash 
Signed-off-by: Rajesh Bhagat 
Signed-off-by: Suresh Gupta 
---
Changes in v2: None

 arch/arm/cpu/armv8/fsl-layerscape/Kconfig   |  6 ++
 arch/arm/cpu/armv8/fsl-layerscape/soc.c | 21 +
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h   |  1 +
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h   |  1 +
 4 files changed, 29 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 666a3d1..10daaa2 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -19,6 +19,7 @@ config ARCH_LS1043A
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_ERRATUM_A009008
+   select SYS_FSL_ERRATUM_A009798
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_DDR4
 
@@ -35,6 +36,7 @@ config ARCH_LS1046A
select SYS_FSL_ERRATUM_A010165
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_ERRATUM_A009008
+   select SYS_FSL_ERRATUM_A009798
select SYS_FSL_HAS_DDR4
select SYS_FSL_SRDS_2
 
@@ -61,6 +63,7 @@ config ARCH_LS2080A
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010165
select SYS_FSL_ERRATUM_A009008
+   select SYS_FSL_ERRATUM_A009798
 
 config FSL_LSCH2
bool
@@ -108,6 +111,9 @@ config SYS_FSL_ERRATUM_A010539
 config SYS_FSL_ERRATUM_A009008
bool "Workaround for USB PHY erratum A009008"
 
+config SYS_FSL_ERRATUM_A009798
+   bool "Workaround for USB PHY erratum A009798"
+
 config MAX_CPUS
int "Maximum number of CPUs permitted for Layerscape"
default 4 if ARCH_LS1043A
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 951ccba..910f345 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -75,6 +75,25 @@ static void erratum_a009008(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
 }
 
+static void erratum_a009798(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009798
+#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1046A)
+   u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+   u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB1 / 4);
+   scfg_out32(scfg + SCFG_USB3PRM1CR_USB1 / 4 , val & USB_SQRXTUNE);
+   val = gur_in32(scfg + SCFG_USB3PRM1CR_USB2 / 4);
+   scfg_out32(scfg + SCFG_USB3PRM1CR_USB2 / 4 , val & USB_SQRXTUNE);
+   val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB3 / 4);
+   scfg_out32(scfg + SCFG_USB3PRM1CR_USB3 / 4 , val & USB_SQRXTUNE);
+#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+   u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+   u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR / 4);
+   scfg_out32(scfg + SCFG_USB3PRM1CR / 4, val & USB_SQRXTUNE);
+#endif
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
+}
+
 #if defined(CONFIG_FSL_LSCH3)
 /*
  * This erratum requires setting a value to eddrtqcr1 to
@@ -218,6 +237,7 @@ void fsl_lsch3_early_init_f(void)
erratum_a008514();
erratum_a008336();
erratum_a009008();
+   erratum_a009798();
 #ifdef CONFIG_CHAIN_OF_TRUST
/* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
@@ -395,6 +415,7 @@ void fsl_lsch2_early_init_f(void)
erratum_a009660();
erratum_a010539();
erratum_a009008();
+   erratum_a009798();
 }
 #endif
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index fe37bc1..ca4a31fe 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -341,6 +341,7 @@ struct ccsr_gur {
 #define SCFG_USB3PRM1CR_USB2   0x07C
 #define SCFG_USB3PRM1CR_USB3   0x088
 #define USB_TXVREFTUNE 0x9
+#define USB_SQRXTUNE   0xFC7F
 
 #define SCFG_SNPCNFGCR_SECRDSNP0x8000
 #define SCFG_SNPCNFGCR_SECWRSNP0x4000
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 9aad471..d726256 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -138,6 +138,7 @@
 #define SCFG_USB3PRM1CR0x000
 #define SCFG_USB3PRM1CR_INIT   0x27672b2a
 #define USB_TXVREFTUNE 0x9
+#define USB_SQRXTUNE   0xFC7F
 #define SCFG_QSPICLKCTLR   0x10
 
 #defi

[U-Boot] [PATCH v2 8/8] armv7: Add workaround for USB erratum A-009007

2017-01-30 Thread Suresh Gupta
From: Suresh Gupta 

Rx Compliance tests  may fail intermittently at high
jitter frequencies using default register values

Changes identified in test setup makes the Rx compliance test pass

Signed-off-by: Sriram Dash 
Signed-off-by: Rajesh Bhagat 
Signed-off-by: Suresh Gupta 
---
Changes in v2:
Clean up the code after Scott comments, 
Previously in v1, we was defining the pointer as u32,
then casting it to u8, and then passing it to
a 16-bit accessor.

 arch/arm/cpu/armv7/ls102xa/Kconfig|  4 
 arch/arm/cpu/armv7/ls102xa/soc.c  | 12 
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  5 +
 3 files changed, 21 insertions(+)

diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig 
b/arch/arm/cpu/armv7/ls102xa/Kconfig
index a68674f..b7d785e 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -8,6 +8,7 @@ config ARCH_LS1021A
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A008997
+   select SYS_FSL_ERRATUM_A009007
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR_BE if SYS_FSL_DDR
@@ -54,6 +55,9 @@ config SYS_FSL_ERRATUM_A009798
 config SYS_FSL_ERRATUM_A008997
bool "Workaround for USB PHY erratum A008997"
 
+config SYS_FSL_ERRATUM_A009007
+   bool "Workaround for USB PHY erratum A009007"
+
 config SYS_FSL_SRDS_1
bool
 
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 3d6cc5f..edb64d5 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -94,6 +94,17 @@ static void erratum_a008997(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
 }
 
+static void erratum_a009007(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009007
+   void __iomem *usb_phy = (void __iomem *)USB_PHY_BASE;
+   writew(USB_PHY_RX_EQ_VAL_1, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_2, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_3, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_4, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
+}
+
 void s_init(void)
 {
 }
@@ -184,6 +195,7 @@ int arch_soc_init(void)
erratum_a009008();
erratum_a009798();
erratum_a008997();
+   erratum_a009007();
 
return 0;
 }
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h 
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index c0e4372..9c4c926 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -182,10 +182,15 @@ struct ccsr_gur {
 #define USB_PHY_MPLL_OVRD_IN_HI0x0024
 #define USB_PHY_LEVEL_OVRD_IN  0x002a
 #define USB_PHY_TX_OVRD_IN_HI  0x2002
+#define USB_PHY_RX_OVRD_IN_HI  0x200c
 #define USB_PHY_TX_OVRD_DRV_LO_VAL 0x784C
 #define USB_PHY_MPLL_OVRD_IN_HI_VAL0x0080
 #define USB_PHY_LEVEL_OVRD_IN_VAL  0xA9A5
 #define USB_PHY_TX_OVRD_IN_HI_VAL  0x0003
+#define USB_PHY_RX_EQ_VAL_10x
+#define USB_PHY_RX_EQ_VAL_20x8000
+#define USB_PHY_RX_EQ_VAL_30x8004
+#define USB_PHY_RX_EQ_VAL_40x800C
 
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {
-- 
1.9.3

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[U-Boot] [PATCH v2 0/8] Add workaround for USB PHY errata

2017-01-30 Thread Suresh Gupta
The patch set implement USB PHY errata workaround which are
required for LS series of freescale platforms which have
Synopsis UTMI PHY

Suresh Gupta (8):
  armv8: Add workaround for USB erratum A-009008
  armv8: Add workaround for USB erratum A-009798
  armv8: Add workaround for USB erratum A-008997
  armv8: Add workaround for USB erratum A-009007
  armv7: Add workaround for USB erratum A-009008
  armv7: Add workaround for USB erratum A-009798
  armv7: Add workaround for USB erratum A-008997
  armv7: Add workaround for USB erratum A-009007

 arch/arm/cpu/armv7/ls102xa/Kconfig |  16 +++
 arch/arm/cpu/armv7/ls102xa/soc.c   |  51 +
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig  |  24 +
 arch/arm/cpu/armv8/fsl-layerscape/soc.c| 117 +
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  20 
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  13 +++
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h  |  19 
 7 files changed, 260 insertions(+)

-- 
1.9.3

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