Re: [U-Boot] Coldfire Architecture and SELF

2010-09-28 Thread SANCHEZ VITORICA, GUILLERMO

Hello,

One last thing on this topic. Could I use also CoudeSourcery Lite +
Coldfire toolchain ? 

Kind regards,

Guillermo


-Mensaje original-
De: Ben Warren [mailto:biggerbadder...@gmail.com] 
Enviado el: martes, 28 de septiembre de 2010 4:30
Para: SANCHEZ VITORICA, GUILLERMO
CC: Wolfgang Wegner; u-boot@lists.denx.de
Asunto: Re: [U-Boot] Coldfire Architecture and SELF

Hello,

On Monday, September 27, 2010, SANCHEZ VITORICA, GUILLERMO
 wrote:
>
>
>
>
>
>
>
>
>
>
>
>
>
>
> Hi again,
>
>
>
> So, if I have got it
> straight, with VirtualBox + Ubuntu + ELDK + U-BOOT sources I can start
> developing U-BOOT for the MCF5445EVB?
>
>
Yes, that's how I'd do it if in your situation.

Regards,
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Re: [U-Boot] Coldfire Architecture and SELF

2010-09-28 Thread Wolfgang Wegner
Hi,

On Tue, Sep 28, 2010 at 09:09:56AM +0200, SANCHEZ VITORICA, GUILLERMO wrote:
> 
> Hello,
> 
> One last thing on this topic. Could I use also CoudeSourcery Lite +
> Coldfire toolchain ? 

for U-Boot: yes
For Linux (ELDK/LTIB), it is IMHO better to rely on the toolchain
provided with the ELDK/LTIB package you use.

Regards,
Wolfgang

> 
> -Mensaje original-
> De: Ben Warren [mailto:biggerbadder...@gmail.com] 
> Enviado el: martes, 28 de septiembre de 2010 4:30
> Para: SANCHEZ VITORICA, GUILLERMO
> CC: Wolfgang Wegner; u-boot@lists.denx.de
> Asunto: Re: [U-Boot] Coldfire Architecture and SELF
> 
> Hello,
> 
> On Monday, September 27, 2010, SANCHEZ VITORICA, GUILLERMO
>  wrote:
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> > Hi again,
> >
> >
> >
> > So, if I have got it
> > straight, with VirtualBox + Ubuntu + ELDK + U-BOOT sources I can start
> > developing U-BOOT for the MCF5445EVB?
> >
> >
> Yes, that's how I'd do it if in your situation.
> 
> Regards,
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[U-Boot] Sequoia board and U-boot

2010-09-28 Thread Sergio Navarrez
Dear all:



I’m working with AMCC Sequioa board. Nor and Nand memories was erased, and
I’m trying to program the Nand flash with the last u-boot version via
debugger. I followed the respective steps from your manual and compiled
u-boot with ELDK. But u-boot doesn’t work.



What can I do, to solve this problem?


Thanks,

Sergio Navarrez
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Re: [U-Boot] Sequoia board and U-boot

2010-09-28 Thread Stefan Roese
Hi Sergio,

On Tuesday 28 September 2010 10:10:52 Sergio Navarrez wrote:
> I’m working with AMCC Sequioa board. Nor and Nand memories was erased, and
> I’m trying to program the Nand flash with the last u-boot version via
> debugger. I followed the respective steps from your manual and compiled
> u-boot with ELDK. But u-boot doesn’t work.
> 
> What can I do, to solve this problem?

You can only program NOR flash via the JTAG debugger. At least the 
BDI2000/3000 doesn't support NAND flash programming. So you either need to 
program U-Boot into NOR flash (target sequoia) or use the RAM booting Sequoia 
image (target sequoia_ramboot). And then use U-Boot itself to program the NAND 
booting image (target sequoia_nand) into NAND.

Cheers,
Stefan

--
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HRB 165235 Munich,  Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: off...@denx.de
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[U-Boot] [PATCH] Add support for operating system OSE

2010-09-28 Thread Torkel Lundgren
Add OSE as operating system for mkimage and bootm.

Signed-off-by: Torkel Lundgren 
---
 common/cmd_bootm.c|   39 +++
 common/image.c|1 +
 include/config_defaults.h |1 +
 include/image.h   |1 +
 4 files changed, 42 insertions(+), 0 deletions(-)

diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index 4c6ed48..b2c2e07 100644
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -118,6 +118,9 @@ extern void lynxkdi_boot (image_header_t *);
 #ifdef CONFIG_BOOTM_RTEMS
 static boot_os_fn do_bootm_rtems;
 #endif
+#if defined(CONFIG_BOOTM_OSE)
+static boot_os_fn do_bootm_ose;
+#endif
 #if defined(CONFIG_CMD_ELF)
 static boot_os_fn do_bootm_vxworks;
 static boot_os_fn do_bootm_qnxelf;
@@ -141,6 +144,9 @@ static boot_os_fn *boot_os[] = {
 #ifdef CONFIG_BOOTM_RTEMS
[IH_OS_RTEMS] = do_bootm_rtems,
 #endif
+#if defined(CONFIG_BOOTM_OSE)
+   [IH_OS_OSE] = do_bootm_ose,
+#endif
 #if defined(CONFIG_CMD_ELF)
[IH_OS_VXWORKS] = do_bootm_vxworks,
[IH_OS_QNX] = do_bootm_qnxelf,
@@ -1382,6 +1388,39 @@ static int do_bootm_rtems (int flag, int argc, char * 
const argv[],
 }
 #endif /* CONFIG_BOOTM_RTEMS */
 
+#if defined(CONFIG_BOOTM_OSE)
+static int do_bootm_ose (int flag, int argc, char * const argv[],
+  bootm_headers_t *images)
+{
+   void (*entry_point)(void);
+
+   if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
+   return 1;
+
+#if defined(CONFIG_FIT)
+   if (!images->legacy_hdr_valid) {
+   fit_unsupported_reset ("OSE");
+   return 1;
+   }
+#endif
+
+   entry_point = (void (*)(void))images->ep;
+
+   printf ("## Transferring control to OSE (at address %08lx) ...\n",
+   (ulong)entry_point);
+
+   show_boot_progress (15);
+
+   /*
+* OSE Parameters:
+*   None
+*/
+   (*entry_point)();
+
+   return 1;
+}
+#endif /* CONFIG_BOOTM_OSE */
+
 #if defined(CONFIG_CMD_ELF)
 static int do_bootm_vxworks (int flag, int argc, char * const argv[],
 bootm_headers_t *images)
diff --git a/common/image.c b/common/image.c
index fcb938b..3a2f25e 100644
--- a/common/image.c
+++ b/common/image.c
@@ -103,6 +103,7 @@ static table_entry_t uimage_os[] = {
{   IH_OS_LYNXOS,   "lynxos",   "LynxOS",   },
 #endif
{   IH_OS_NETBSD,   "netbsd",   "NetBSD",   },
+   {   IH_OS_OSE,  "ose",  "Enea OSE", },
{   IH_OS_RTEMS,"rtems","RTEMS",},
{   IH_OS_U_BOOT,   "u-boot",   "U-Boot",   },
 #if defined(CONFIG_CMD_ELF) || defined(USE_HOSTCC)
diff --git a/include/config_defaults.h b/include/config_defaults.h
index 0337163..abdf3be 100644
--- a/include/config_defaults.h
+++ b/include/config_defaults.h
@@ -12,6 +12,7 @@
 /* Support bootm-ing different OSes */
 #define CONFIG_BOOTM_LINUX 1
 #define CONFIG_BOOTM_NETBSD 1
+#define CONFIG_BOOTM_OSE 1
 #define CONFIG_BOOTM_RTEMS 1
 
 #define CONFIG_GZIP 1
diff --git a/include/image.h b/include/image.h
index bcc08d1..18a9f0e 100644
--- a/include/image.h
+++ b/include/image.h
@@ -83,6 +83,7 @@
 #define IH_OS_ARTOS19  /* ARTOS*/
 #define IH_OS_UNITY20  /* Unity OS */
 #define IH_OS_INTEGRITY21  /* INTEGRITY*/
+#define IH_OS_OSE  22  /* OSE  */
 
 /*
  * CPU Architecture Codes (supported by Linux)
-- 
1.6.3.3

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[U-Boot] [RFC] [PATCH 0/4] Add support for Freescale's 85xx and P1/P2xxx eSPI controller

2010-09-28 Thread Can Aydin


Hi All,

This patch series adds support for the eSPI controller found on the 
newer range of Freescale SoCs including the 85xx, P1/P2xx (and I believe 
the P4xx) series.

The reason this is an RFC is that unfortunately the hardware on these 
chips does not permit indefinite SPI transactions on a given chip 
select. A chip select is asserted only when a 'transaction length' has 
been passed to the controller. Once the number of characters specified 
in the transaction length have been transmitted, the controller decides 
that the 'frame' has ended and de-asserts the chip select after a 
defined delay. It is not possible to initiate a second transfer without 
re-initialising the command register, and hence clearing and 
re-asserting a chip select signal.

This patch set addresses the issue by defining a read/write function in 
the spi_flash_internal API. Subsequent patches add the freescale eSPI 
driver and add support for it in the spansion driver and the P1/P2 board 
configuration header.

I'm pretty sure that there are better ways of doing this, especially if 
a driver model with support for driver quirks was implemented for 
instance. Until then however, I assume having some sort of ability to 
use the SPI controller on these boards would be better than not being 
able to do anything at all. If anyone has a better solution please feel 
free to comment.


Regards,

Can

--
  drivers/mtd/spi/spansion.c   |   60 -
  drivers/mtd/spi/spi_flash.c  |   38 +-
  drivers/mtd/spi/spi_flash_internal.h |9 ++
  drivers/spi/Makefile |1 +
  drivers/spi/fsl_espi.c   |  251 
++
  include/configs/P1_P2_RDB.h  |   18 +++
  include/fsl_espi.h   |   50 +++
  7 files changed, 419 insertions(+), 8 deletions(-)
  mode change 100644 => 100755 drivers/mtd/spi/spansion.c
  mode change 100644 => 100755 drivers/mtd/spi/spi_flash.c
  mode change 100644 => 100755 drivers/mtd/spi/spi_flash_internal.h
  create mode 100755 drivers/spi/fsl_espi.c
  create mode 100755 include/fsl_espi.h



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[U-Boot] [RFC] [PATCH 1/4] Support for 'single frame' spi flash commands

2010-09-28 Thread Can Aydin
  Add a single-hit transaction to the spi flash framework.
  Useful for when the hardware makes it impossible to maintain CS
  state between disparate command and data calls by requiring a
  'frame length' (thus pre-determining how many clock cycles the
  CS will stay asserted).
  Such is the case with the Freescale eSPI controller.

Signed-off-by: Can Aydin

---
  drivers/mtd/spi/spi_flash.c  |   38 +++--
  drivers/mtd/spi/spi_flash_internal.h |9 
  2 files changed, 44 insertions(+), 3 deletions(-)
  mode change 100644 =>  100755 drivers/mtd/spi/spi_flash.c
  mode change 100644 =>  100755 drivers/mtd/spi/spi_flash_internal.h

diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
old mode 100644
new mode 100755
index ea875dc..7646fc5
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -70,12 +70,12 @@ int spi_flash_cmd_write(struct spi_slave *spi, const u8 
*cmd, size_t cmd_len,

ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags);
if (ret) {
-   debug("SF: Failed to send read command (%zu bytes): %d\n",
+   debug("SF: Failed to send write command (%zu bytes): %d\n",
cmd_len, ret);
} else if (data_len != 0) {
ret = spi_xfer(spi, data_len * 8, data, NULL, SPI_XFER_END);
if (ret)
-   debug("SF: Failed to read %zu bytes of data: %d\n",
+   debug("SF: Failed to write %zu bytes of data: %d\n",
data_len, ret);
}

@@ -96,6 +96,37 @@ int spi_flash_read_common(struct spi_flash *flash, const u8 
*cmd,
return ret;
  }

+int spi_flash_cmd_rw_frame(struct spi_slave *spi, const u8 *cmd,
+   size_t cmd_len, void *data, size_t data_len)
+{
+   unsigned char *buffer;
+   int ret;
+
+   buffer = (unsigned char *)malloc(cmd_len + data_len);
+   if (!buffer) {
+   debug("SF: Failed to malloc memory.\n");
+   return 1;
+   }
+   if ( cmd_len&&  cmd )
+   memcpy(buffer, cmd, cmd_len);
+   if ( data_len&&  data )
+   memcpy(buffer+cmd_len, data, data_len);
+   ret = spi_xfer(spi, (cmd_len + data_len)*8, buffer, buffer,
+   SPI_XFER_BEGIN|SPI_XFER_END);
+   if (!ret) {
+   if ( cmd&&  cmd_len )
+   memcpy(cmd, buffer,cmd_len);
+   if ( data&&  data_len)
+   memcpy(data, buffer + cmd_len,data_len);
+   } else {
+   debug("SF: Transaction failed (command length: %zu bytes),"
+   " (data length: %zu bytes) : %d\n",
+ cmd_len, data_len, ret);
+   }
+   free(buffer);
+   return ret;
+}
+
  struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int spi_mode)
  {
@@ -117,7 +148,8 @@ struct spi_flash *spi_flash_probe(unsigned int bus, 
unsigned int cs,
}

/* Read the ID codes */
-   ret = spi_flash_cmd(spi, CMD_READ_ID,&idcode, sizeof(idcode));
+   idcode[0] = CMD_READ_ID;
+   ret = spi_flash_cmd_rw_frame(spi,&(idcode[0]), 1, idcode, 
sizeof(idcode));
if (ret)
goto err_read_id;

diff --git a/drivers/mtd/spi/spi_flash_internal.h 
b/drivers/mtd/spi/spi_flash_internal.h
old mode 100644
new mode 100755
index 08546fb..0455dcc
--- a/drivers/mtd/spi/spi_flash_internal.h
+++ b/drivers/mtd/spi/spi_flash_internal.h
@@ -43,6 +43,15 @@ int spi_flash_cmd_write(struct spi_slave *spi, const u8 
*cmd, size_t cmd_len,
  int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
size_t cmd_len, void *data, size_t data_len);

+/*
+ * Similar to spi_flash_read_common() but command and data are combined and
+ * transferred in a single,pre-buffered frame. Useful for when the
+ * hardware makes it impossible to deterministically maintain CS state between
+ * disparate command and data calls.
+ */
+int spi_flash_cmd_rw_frame(struct spi_slave *spi, const u8 *cmd,
+   size_t cmd_len, void *data, size_t data_len);
+
  /* Manufacturer-specific probe functions */
  struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode);
  struct spi_flash *spi_flash_probe_atmel(struct spi_slave *spi, u8 *idcode);
-- 
1.7.0.4

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[U-Boot] [RFC] [PATCH 3/4] FSL eSPI support for the Spansion Flash driver

2010-09-28 Thread Can Aydin


Modify Spansion flash driver to add support for the FSL eSPI controller.
  Due to the nature of the eSPI controller the upper level drivers must
  ensure to use single frame transactions (i.e. that have begin and end
  flags set) and keep the size of each frame below maximum length.

Signed-off-by: Can Aydin
---
  drivers/mtd/spi/spansion.c |   60 ---
  1 files changed, 55 insertions(+), 5 deletions(-)
  mode change 100644 =>  100755 drivers/mtd/spi/spansion.c

diff --git a/drivers/mtd/spi/spansion.c b/drivers/mtd/spi/spansion.c
old mode 100644
new mode 100755
index d6c1a5f..d66f4e0
--- a/drivers/mtd/spi/spansion.c
+++ b/drivers/mtd/spi/spansion.c
@@ -31,6 +31,10 @@

  #include "spi_flash_internal.h"

+#ifdef CONFIG_FSL_ESPI
+#include
+#endif
+
  /* S25FLxx-specific commands */
  #define CMD_S25FLXX_READ  0x03/* Read Data Bytes */
  #define CMD_S25FLXX_FAST_READ 0x0b/* Read Data Bytes at Higher Speed */
@@ -135,7 +139,13 @@ static int spansion_wait_ready(struct spi_flash *flash, 
unsigned long timeout)

timebase = get_timer(0);
do {
+#ifdef CONFIG_FSL_ESPI
+   u8 cmd = CMD_S25FLXX_RDSR;
+   ret = spi_flash_cmd_rw_frame(spi,&(cmd), sizeof(cmd),
+   &status, sizeof(status));
+#else
ret = spi_flash_cmd(spi, CMD_S25FLXX_RDSR,&status, 
sizeof(status));
+#endif
if (ret)
return -1;

@@ -158,22 +168,56 @@ static int spansion_read_fast(struct spi_flash *flash,
struct spansion_spi_flash *spsn = to_spansion_spi_flash(flash);
unsigned long page_addr;
unsigned long page_size;
+   int ret = 0;
u8 cmd[5];

page_size = spsn->params->page_size;
-   page_addr = offset / page_size;
+   
+#ifdef CONFIG_FSL_ESPI
+   /* Break up read into ESPI_MAX_TRANLEN size chunks */
+   while (( len )&&  (!ret))
+   {
+   unsigned int tranlen;
+   if ( len + sizeof(cmd)>= ESPI_MAX_TRANLEN ) {
+   tranlen = ESPI_MAX_TRANLEN - sizeof(cmd);
+   len -= tranlen;
+   } else {
+   tranlen = len;
+   len = 0;
+   }
+   
+   page_addr = offset / page_size;
+   
+   cmd[0] = CMD_READ_ARRAY_FAST;
+   cmd[1] = page_addr>>  8;
+   cmd[2] = page_addr;
+   cmd[3] = offset % page_size;
+   cmd[4] = 0x00;
+   
+   debug ("READ: 0x%x =>  cmd = { 0x%02x 0x%02x%02x%02x%02x } len 
= 0x%x\n",
+   offset, cmd[0], cmd[1], cmd[2], cmd[3], cmd[4], tranlen);
+   
+   ret = spi_flash_cmd_rw_frame(flash->spi, cmd, sizeof(cmd), buf, 
tranlen);
+   offset += tranlen;
+   buf += tranlen;
+   }
+   return ret;
+#else

+   page_addr = offset / page_size;
+   
cmd[0] = CMD_READ_ARRAY_FAST;
cmd[1] = page_addr>>  8;
cmd[2] = page_addr;
cmd[3] = offset % page_size;
cmd[4] = 0x00;
-
+   
debug
("READ: 0x%x =>  cmd = { 0x%02x 0x%02x%02x%02x%02x } len = 
0x%x\n",
 offset, cmd[0], cmd[1], cmd[2], cmd[3], cmd[4], len);

return spi_flash_read_common(flash, cmd, sizeof(cmd), buf, len);
+#endif
  }

  static int spansion_write(struct spi_flash *flash,
@@ -187,6 +231,7 @@ static int spansion_write(struct spi_flash *flash,
size_t actual;
int ret;
u8 cmd[4];
+   u8 cmd_wren = CMD_S25FLXX_WREN;

page_size = spsn->params->page_size;
page_addr = offset / page_size;
@@ -216,9 +261,13 @@ static int spansion_write(struct spi_flash *flash,
debug("SF: Enabling Write failed\n");
break;
}
-
-   ret = spi_flash_cmd_write(flash->spi, cmd, 4,
+#ifdef CONFIG_FSL_ESPI
+   ret = spi_flash_cmd_rw_frame(flash->spi, cmd, sizeof(cmd),
+ buf + actual, chunk_len);
+#else
+   ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd),
  buf + actual, chunk_len);
+#endif
if (ret<  0) {
debug("SF: SPANSION Page Program failed\n");
break;
@@ -258,7 +307,8 @@ int spansion_erase(struct spi_flash *flash, u32 offset, 
size_t len)
sector_size = spsn->params->page_size * spsn->params->pages_per_sector;

if (offset % sector_size || len % sector_size) {
-   debug("SF: Erase offset/length not multiple of sector size\n");
+   debug("SF: Erase offset/length not multiple of sector size 
(0x%x)\n",
+   sector_size);
return -1;
}

-- 
1.7.0.4


   

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[U-Boot] [RFC] [PATCH 2/4] Freescale 85xx/P1/P2 eSPI controller driver

2010-09-28 Thread Can Aydin


Driver for the Freescale eSPI controller found in 85xx, P1/P2 and P4xx SoCs.

Signed-off-by: Can Aydin
---
  drivers/spi/Makefile   |1 +
  drivers/spi/fsl_espi.c |  251 
  include/fsl_espi.h |   50 ++
  3 files changed, 302 insertions(+), 0 deletions(-)
  create mode 100755 drivers/spi/fsl_espi.c
  create mode 100755 include/fsl_espi.h

diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index dfcbb8b..1aaa8e7 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -31,6 +31,7 @@ COBJS-$(CONFIG_ATMEL_SPI) += atmel_spi.o
  COBJS-$(CONFIG_BFIN_SPI) += bfin_spi.o
  COBJS-$(CONFIG_CF_SPI) += cf_spi.o
  COBJS-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
+COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o
  COBJS-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
  COBJS-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o
  COBJS-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c
new file mode 100755
index 000..1a42827
--- /dev/null
+++ b/drivers/spi/fsl_espi.c
@@ -0,0 +1,251 @@
+/*
+ * Freescale eSPI controller driver.
+ *
+ * Copyright 2010 Locata Corporation Pty. Ltd.
+ * Author: Can Aydin   can.ay...@locatacorp.com
+ * Collab: Clayton Gumbrellclayton.gumbr...@locatacorp.com
+ *
+ * Adapted from Freescale ltib code by Mingkai Hu (mingkai...@freescale.com)
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include
+
+#include
+#include
+#include
+#include
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+   unsigned int max_hz, unsigned int mode)
+{
+   volatile ccsr_espi_t *espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR);
+   struct spi_slave *slave;
+   sys_info_t sysinfo;
+   unsigned long spibrg = 0;
+   unsigned char pm = 0;
+   int i;
+
+   if (!spi_cs_is_valid(bus, cs))
+   return NULL;
+
+   slave = malloc(sizeof(struct spi_slave));
+   if (!slave)
+   return NULL;
+
+   slave->bus = bus;
+   slave->cs = cs;
+
+   /* Enable eSPI interface */
+   espi->mode = ESPI_MODE_RXTHR(3) | ESPI_MODE_TXTHR(4) | ESPI_MODE_EN;
+
+   espi->event = 0x;   /* Clear all eSPI events */
+   espi->mask = 0x;/* Mask  all eSPI interrupts */
+
+   /* Init CS mode interface */
+   for (i = 0; i<  ESPI_MAX_CS_NUM; i++)
+   espi->csmode[i] = ESPI_CSMODE_INIT_VAL;
+
+   espi->csmode[cs]&=
+   ~(ESPI_CSMODE_PM(0xF) | ESPI_CSMODE_DIV16
+   | ESPI_CSMODE_CI_INACTIVEHIGH | ESPI_CSMODE_CP_BEGIN_EDGCLK
+   | ESPI_CSMODE_REV_MSB_FIRST
+   | ESPI_CSMODE_LEN(ESPI_MAX_CHARSIZE));
+
+   /* Set eSPI BRG clock source */
+   get_sys_info(&sysinfo);
+   spibrg = sysinfo.freqSystemBus / 2;
+   if ((spibrg / max_hz)>  32) {
+   espi->csmode[cs] |= ESPI_CSMODE_DIV16;
+   pm = spibrg / (max_hz * 16 * 2);
+   if (pm>  16) {
+   pm = 16;
+   debug("Requested speed is too low: %d Hz"
+   " %u Hz is used.\n", max_hz, (uint) (spibrg / 
(32 * 16)));
+   }
+   } else
+   pm = spibrg / (max_hz * 2);
+   if (pm)
+   pm--;
+   espi->csmode[cs] |= ESPI_CSMODE_PM(pm);
+
+   /* Set eSPI mode */
+   if (mode&  SPI_CPHA)
+   espi->csmode[cs] |= ESPI_CSMODE_CP_BEGIN_EDGCLK;
+   if (mode&  SPI_CPOL)
+   espi->csmode[cs] |= ESPI_CSMODE_CI_INACTIVEHIGH;
+
+   /* Character bit order: msb first */
+   espi->csmode[cs] |= ESPI_CSMODE_REV_MSB_FIRST;
+
+   /* Character length in bits, between 0x3~0xf, i.e. 4bits~16bits */
+   espi->csmode[cs] |= ESPI_CSMODE_LEN(ESPI_CHARSIZE);
+
+   return slave;
+}
+
+
+static inline void write_u32_part(u32 * in, u32 * out, u8 size)
+{
+   int i;
+   u8 * ibyte = (u8 *) in;
+   u8 * obyte = (u8 *) out;
+
+   for ( i = 0; i<  size; i++)
+   obyte[i] = ibyte[i];
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
+   void *din, unsigned long flags)
+{
+   volatile ccsr_espi_t *espi = (void *)(CONFIG_SYS_MPC85

[U-Boot] [RFC] [PATCH 4/4] FSL eSPI support on P1/P2 RDB platforms

2010-09-28 Thread Can Aydin


Add FSL eSPI support on P1/P2 RDB platforms

Signed-off-by: Can Aydin
---
  include/configs/P1_P2_RDB.h |   18 ++
  1 files changed, 18 insertions(+), 0 deletions(-)

diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h
index 7e901e1..d830b4a 100644
--- a/include/configs/P1_P2_RDB.h
+++ b/include/configs/P1_P2_RDB.h
@@ -149,6 +149,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
  #define CONFIG_SYS_DDR_ERR_DIS0x
  #define CONFIG_SYS_DDR_SBE0x00FF

+
  /*
   * Memory map
   *
@@ -168,6 +169,23 @@ extern unsigned long get_board_sys_clk(unsigned long 
dummy);
   */

  /*
+ * eSPI - Enhanced SPI
+ */
+#define CONFIG_FSL_ESPI
+#define CONFIG_HARD_SPI
+#define CONFIG_CMD_SPI
+
+/*
+ * Spansion SPI Flash
+ */
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED 1000
+#define CONFIG_SF_DEFAULT_MODE 0
+
+/*
   * Local Bus Definitions
   */
  #define CONFIG_SYS_FLASH_BASE 0xef00  /* start of FLASH 16M */
-- 
1.7.0.4


   

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Re: [U-Boot] [PATCH v5 1/2] APM821xx: Add CPU support

2010-09-28 Thread Stefan Roese
Hi Marri,

On Monday 27 September 2010 21:47:04 tma...@apm.com wrote:
> From: Tirumala Marri 
> 
> APM821XX is a new line of SoCs which are derivatives of
> PPC44X family of processors. This patch adds support of CPU, cache,
> tlb, 32k ocm, bootstraps, PLB and AHB bus.

Hopefully the last (coding style related) comments below.



> +++ b/arch/powerpc/cpu/ppc4xx/cpu.c
> @@ -250,6 +250,20 @@ static char *bootstrap_str[] = {
> 
>  };
>  static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
>  #endif
> 
> +#if defined(CONFIG_APM821XX)
> +#define SDR0_PINSTP_SHIFT   29
> +static char *bootstrap_str[] = {
> +   "RESERVED",
> +   "RESERVED",
> +   "RESERVED",
> +   "NAND (8 bits)",
> +   "NOR  (8 bits)",
> +   "NOR  (8 bits) w/PLL Bypassed",
> +   "I2C (Addr 0x54)",
> +   "I2C (Addr 0x52)",
> +};

Indentation with tabs instead of spaces please.

> +++ b/arch/powerpc/include/asm/apm821xx.h
> @@ -0,0 +1,70 @@
> +/*
> + * Copyright (c) 2010, Applied Micro Circuits Corporation
> + * Author: Tirumala R Marri 
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.   See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef _APM821XX_H_
> +#define _APM821XX_H_
> +
> +#define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */

Insert empty line here.

> +/* Memory mapped registers */
> +#define CONFIG_SYS_PERIPHERAL_BASE  0xEF60

Please use tab instead of spaces for indentation.

> +#define CONFIG_SYS_NS16550_COM1  (CONFIG_SYS_PERIPHERAL_BASE + 0x0200)
> +#define CONFIG_SYS_NS16550_COM2  (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
> +
> +#define GPIO0_BASE   (CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
> +
> +#define SDR0_SRST0_DMC   0x0020
> +#define SDR0_SRST1_AHB   0x0040  /* PLB4XAHB bridge */

Again, empty would look better here.

> +/* AHB config. */
> +#define AHB_TOP 0xA4
> +#define AHB_BOT 0xA5

Tabs vs. spaces again.

> +
> +

Remove one of those empty lines.

> +#define PLLSYS0_FWD_DIV_A_MASK   0x00f0  /* Fwd Div A */
> +#define PLLSYS0_FWD_DIV_B_MASK   0x000f  /* Fwd Div B */
> +#define PLLSYS0_FB_DIV_MASK  0xff00  /* Feedback divisor */
> +#define PLLSYS0_OPB_DIV_MASK 0x0c00  /* OPB Divisor */
> +#define PLLSYS0_EPB_DIV_MASK0x0300  /* EPB divisor */

Tabs vs spaces again. Please fix globally and resubmit. Thanks.

Cheers,
Stefan

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Re: [U-Boot] [RFC] [PATCH 0/4] Add support for Freescale's 85xx and P1/P2xxx eSPI controller

2010-09-28 Thread Reinhard Meyer
Dear Can Aydin,
> The reason this is an RFC is that unfortunately the hardware on these
> chips does not permit indefinite SPI transactions on a given chip
> select. A chip select is asserted only when a 'transaction length' has
> been passed to the controller. Once the number of characters specified
> in the transaction length have been transmitted, the controller decides
> that the 'frame' has ended and de-asserts the chip select after a
> defined delay. It is not possible to initiate a second transfer without
> re-initialising the command register, and hence clearing and
> re-asserting a chip select signal.
>
> This patch set addresses the issue by defining a read/write function in
> the spi_flash_internal API. Subsequent patches add the freescale eSPI
> driver and add support for it in the spansion driver and the P1/P2 board
> configuration header.
>
> I'm pretty sure that there are better ways of doing this, especially if
> a driver model with support for driver quirks was implemented for
> instance. Until then however, I assume having some sort of ability to
> use the SPI controller on these boards would be better than not being
> able to do anything at all. If anyone has a better solution please feel
> free to comment.
Can the Chip Select Pins be used as GPIO? It might be simpler to do that than
adding a speciality to common code.

>mode change 100644 =>  100755 drivers/mtd/spi/spansion.c
>mode change 100644 =>  100755 drivers/mtd/spi/spi_flash.c
>mode change 100644 =>  100755 drivers/mtd/spi/spi_flash_internal.h
>create mode 100755 drivers/spi/fsl_espi.c
>create mode 100755 include/fsl_espi.h
Having edited from W** using Samba?
Make sure the file modes are and stay 644!

Without looking at the functionality I saw several coding style issues in
the patch series:
+   if ( cmd_len&&  cmd )
+   memcpy(buffer, cmd, cmd_len);
should be like "if (cmd_len && cmd)"

Similar space issues seem to happen all over your patches,
examples:

+   for ( i = 0; i<  size; i++)

+   return bus == 0&&  cs<  ESPI_MAX_CS_NUM;

+#define ESPI_COM_CS(x) ((x)<<  30)

You need to fix that globally...

Best Regards,

Reinhard

PS: you might want to wait and see if that patch in common code to
fix a special hardware issue is welcome at all ;)
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Re: [U-Boot] [RFC] [PATCH 0/4] Add support for Freescale's 85xx and P1/P2xxx eSPI controller

2010-09-28 Thread Can Aydin
  Dear Reinhard,

On 28/09/2010 9:02 PM, Reinhard Meyer wrote:
> Dear Can Aydin,
>> The reason this is an RFC is that unfortunately the hardware on these
>> chips does not permit indefinite SPI transactions on a given chip
>> select. A chip select is asserted only when a 'transaction length' has
>> been passed to the controller. Once the number of characters specified
>> in the transaction length have been transmitted, the controller decides
>> that the 'frame' has ended and de-asserts the chip select after a
>> defined delay. It is not possible to initiate a second transfer without
>> re-initialising the command register, and hence clearing and
>> re-asserting a chip select signal.
>>
>> This patch set addresses the issue by defining a read/write function in
>> the spi_flash_internal API. Subsequent patches add the freescale eSPI
>> driver and add support for it in the spansion driver and the P1/P2 board
>> configuration header.
>>
>> I'm pretty sure that there are better ways of doing this, especially if
>> a driver model with support for driver quirks was implemented for
>> instance. Until then however, I assume having some sort of ability to
>> use the SPI controller on these boards would be better than not being
>> able to do anything at all. If anyone has a better solution please feel
>> free to comment.
> Can the Chip Select Pins be used as GPIO? It might be simpler to do 
> that than
> adding a speciality to common code.
True, a GPIO pin could be re-purposed to serve as chip select, but that 
would involve a soldering iron and a steady hand as the P1/P2xxRDB 
boards are reference design boards sold by a lot of third party vendors 
(including Denx if I'm not mistaken) this would detract from the ability 
to just plug u-boot in and run with it.

People could also choose to bitbang the SPI on their custom hardware but 
again I feel that might defeat the purpose and spirit of u-boot. (Then 
again, I'm new so don't quote me on that).
>
>>mode change 100644 =>  100755 drivers/mtd/spi/spansion.c
>>mode change 100644 =>  100755 drivers/mtd/spi/spi_flash.c
>>mode change 100644 =>  100755 drivers/mtd/spi/spi_flash_internal.h
>>create mode 100755 drivers/spi/fsl_espi.c
>>create mode 100755 include/fsl_espi.h
> Having edited from W** using Samba?
> Make sure the file modes are and stay 644!
Dammit, I was hoping to not let on about that. Yes, I am unfortunately 
confined to a certain OS due to certain factors. Will fix those.
>
> Without looking at the functionality I saw several coding style issues in
> the patch series:
> +if ( cmd_len&&  cmd )
> +memcpy(buffer, cmd, cmd_len);
> should be like "if (cmd_len && cmd)"
>
> Similar space issues seem to happen all over your patches,
> examples:
>
> +for ( i = 0; i<  size; i++)
>
> +return bus == 0&&  cs<  ESPI_MAX_CS_NUM;
>
> +#define ESPI_COM_CS(x)((x)<<  30)
>
> You need to fix that globally...
Again I plead newbie. Will fix also.
>
> Best Regards,
>
> Reinhard
>
> PS: you might want to wait and see if that patch in common code to
> fix a special hardware issue is welcome at all ;)
>
Well, even if the common code patch is rejected (and breaking the 
spi_flash abstraction was definitely not the high point of my day), at 
least the cmd_spi module will work with these boards if only the driver 
patch gets in. Even that might help those trying to get their own hw off 
the ground at least somewhat.


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[U-Boot] [PATCH 2/2] bmw: Remove duplicated include of header file

2010-09-28 Thread Thomas Weber
Signed-off-by: Thomas Weber 
---
 board/bmw/bmw.c |1 -
 1 files changed, 0 insertions(+), 1 deletions(-)

diff --git a/board/bmw/bmw.c b/board/bmw/bmw.c
index 4039145..5ba6c09 100644
--- a/board/bmw/bmw.c
+++ b/board/bmw/bmw.c
@@ -22,7 +22,6 @@
  */
 
 #include 
-#include 
 #include 
 #include 
 #include 
-- 
1.7.3

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[U-Boot] [PATCH 1/2] ixp/npe: Remove duplicated comment

2010-09-28 Thread Thomas Weber
Signed-off-by: Thomas Weber 
---
 arch/arm/cpu/ixp/npe/IxNpeDlNpeMgr.c |5 -
 1 files changed, 0 insertions(+), 5 deletions(-)

diff --git a/arch/arm/cpu/ixp/npe/IxNpeDlNpeMgr.c 
b/arch/arm/cpu/ixp/npe/IxNpeDlNpeMgr.c
index f5a4c5f..a9ea8bc 100644
--- a/arch/arm/cpu/ixp/npe/IxNpeDlNpeMgr.c
+++ b/arch/arm/cpu/ixp/npe/IxNpeDlNpeMgr.c
@@ -51,11 +51,6 @@
 /*
  * Put the user defined include files required.
  */
-
-
-/*
- * Put the user defined include files required.
- */
 #include "IxOsal.h"
 #include "IxNpeDl.h"
 #include "IxNpeDlNpeMgr_p.h"
-- 
1.7.3

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Re: [U-Boot] [RFC] [PATCH 0/4] Add support for Freescale's 85xx and P1/P2xxx eSPI controller

2010-09-28 Thread Can Aydin


>> Can the Chip Select Pins be used as GPIO? It might be simpler to do
>> that than
>> adding a speciality to common code.
> True, a GPIO pin could be re-purposed to serve as chip select, but that
> would involve a soldering iron and a steady hand as the P1/P2xxRDB
> boards are reference design boards sold by a lot of third party vendors
> (including Denx if I'm not mistaken) this would detract from the ability
> to just plug u-boot in and run with it.
>
> People could also choose to bitbang the SPI on their custom hardware but
> again I feel that might defeat the purpose and spirit of u-boot. (Then
> again, I'm new so don't quote me on that).
>
Quick followup, I may have misunderstood that question. The SPI pins can 
only be re-purposed as extra data pins for the SDHC. It's not possible 
to use them as GPIO.

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Re: [U-Boot] [PATCH] README: Fix description of version numbering scheme

2010-09-28 Thread Wolfgang Denk
Dear Thomas Weber,

In message <1285653985-11796-1-git-send-email-we...@corscience.de> you wrote:
> The version numbering scheme was changed in Oct, 2008.
> This patch brings the documentation to the actual level.
> The description is taken from: 
> http://www.denx.de/wiki/U-Boot/ReleaseCycle
> 
> Signed-off-by: Thomas Weber 
> ---
>  README |   18 ++
>  1 files changed, 10 insertions(+), 8 deletions(-)

Thanks. Applied (with slightly changed text; I also change dthe web
sit to match again).

Best regards,

Wolfgang Denk

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Tactical? TACTICAL!?!? Hey, buddy, we went from kilotons to  megatons
several  minutes  ago.  We don't need no stinkin' tactical nukes. (By
the way, do you have change for 10 million people?)   - lwall
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Re: [U-Boot] [PATCH] Add support for operating system OSE

2010-09-28 Thread Wolfgang Denk
Dear Torkel Lundgren,

In message <1285664736-21181-1-git-send-email-torkel.lundg...@enea.com> you 
wrote:
> Add OSE as operating system for mkimage and bootm.
> 
> Signed-off-by: Torkel Lundgren 
> ---
>  common/cmd_bootm.c|   39 +++
>  common/image.c|1 +
>  include/config_defaults.h |1 +
>  include/image.h   |1 +
>  4 files changed, 42 insertions(+), 0 deletions(-)

Applied to "next" branch.

Best regards,

Wolfgang Denk

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it usually is :-) - Larry Wall in <1991jul31.174523.9...@netlabs.com>
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Re: [U-Boot] [RFC] [PATCH 0/4] Add support for Freescale's 85xx and P1/P2xxx eSPI controller

2010-09-28 Thread Wolfgang Denk
Dear Can Aydin,

In message <4ca1d63e.3090...@locatacorp.com> you wrote:
> 
> > Can the Chip Select Pins be used as GPIO? It might be simpler to do 
> > that than
> > adding a speciality to common code.
> True, a GPIO pin could be re-purposed to serve as chip select, but that 
> would involve a soldering iron and a steady hand as the P1/P2xxRDB 

That was not the question.

Reinhard asked if the SPI Chip Select Pins could be configured such so
that they can be used in GPIO mode instead of special function mode.
That would make code way simpler.

> People could also choose to bitbang the SPI on their custom hardware but 
> again I feel that might defeat the purpose and spirit of u-boot. (Then 
> again, I'm new so don't quote me on that).

Oops?  Where exactly do you see conflicts with "the purpose and
spirit" of U-Boot?

Best regards,

Wolfgang Denk

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Re: [U-Boot] [PATCH 2/2] bmw: Remove duplicated include of header file

2010-09-28 Thread Wolfgang Denk
Dear Thomas Weber,

In message <1285675413-13865-2-git-send-email-we...@corscience.de> you wrote:
> Signed-off-by: Thomas Weber 
> ---
>  board/bmw/bmw.c |1 -
>  1 files changed, 0 insertions(+), 1 deletions(-)

Applied, thanks.

Best regards,

Wolfgang Denk

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Re: [U-Boot] [PATCH 1/2] ixp/npe: Remove duplicated comment

2010-09-28 Thread Wolfgang Denk
Dear Thomas Weber,

In message <1285675413-13865-1-git-send-email-we...@corscience.de> you wrote:
> Signed-off-by: Thomas Weber 
> ---
>  arch/arm/cpu/ixp/npe/IxNpeDlNpeMgr.c |5 -
>  1 files changed, 0 insertions(+), 5 deletions(-)

Applied, because it's such a trivial patch - otoh, don;t waste efforts
on the npe/ code. It will be trhown out rather sooner than later due
to license conflicts.

Thanks.

Best regards,

Wolfgang Denk

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[U-Boot] [PATCH V3 1/2] [NEXT] arm: change relocation flag from -fPIC to -fPIE

2010-09-28 Thread Albert Aribaud
Replace GOT indirect addressing with more efficient pic-base
relative addressing for initialized data (uninitialized data
still use GOTi indirect addressing).  This also reduces code
size by 0.4% compared to -fPIC.

Signed-off-by: Albert Aribaud 
---
SUMMARY

This patch aims at optimizing relocatable code both in size and
speed. The first patch switches from '-fPIC' to '-fPIE', which makes
initialized data accesses pc-relative rather than GOT-indirect, and
the second adds '-msingle-pic-base' which factors out GOT addressing
by computing it once and for all.

PATCHSET HISTORY

V1  Initial submission
V2  Compute RAM pic base only if actually relocating
Fixed RAM pic base computation and copy loop
V3  Added fix for tx25

 arch/arm/config.mk |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/config.mk b/arch/arm/config.mk
index 6923f6d..138c43a 100644
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -35,7 +35,7 @@ endif
 
 ifndef CONFIG_SYS_ARM_WITHOUT_RELOC
 # needed for relocation
-PLATFORM_RELFLAGS += -fPIC
+PLATFORM_RELFLAGS += -fPIE
 endif
 
 ifdef CONFIG_SYS_ARM_WITHOUT_RELOC
-- 
1.7.0.4

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[U-Boot] [PATCH V3 2/2] [NEXT] arm926ejs: reduce code size with -msingle-pic-base

2010-09-28 Thread Albert Aribaud
Add -msingle-pic-base to the relocation flags, and compute the pic base
in start.S twice and for all -- once before relocation to run board_init_f,
and once after relocation to run board_init_r and the rest of u-boot.
This further reduces code size by 2.5% compared to -fPIE alone.

Signed-off-by: Albert Aribaud 
---
 arch/arm/cpu/arm926ejs/config.mk|5 
 arch/arm/cpu/arm926ejs/start.S  |   40 +-
 arch/arm/cpu/arm926ejs/u-boot.lds   |1 +
 board/karo/tx25/config.mk   |2 +-
 include/configs/tx25.h  |2 +-
 nand_spl/board/karo/tx25/u-boot.lds |1 +
 6 files changed, 43 insertions(+), 8 deletions(-)

diff --git a/arch/arm/cpu/arm926ejs/config.mk b/arch/arm/cpu/arm926ejs/config.mk
index f8ef90f..aa84706 100644
--- a/arch/arm/cpu/arm926ejs/config.mk
+++ b/arch/arm/cpu/arm926ejs/config.mk
@@ -23,6 +23,11 @@
 
 PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
 
+ifndef CONFIG_SYS_ARM_WITHOUT_RELOC
+# needed for optimal relocation
+PLATFORM_RELFLAGS += -msingle-pic-base
+endif
+
 PLATFORM_CPPFLAGS += -march=armv5te
 # =
 #
diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S
index 16ee972..904bd8d 100644
--- a/arch/arm/cpu/arm926ejs/start.S
+++ b/arch/arm/cpu/arm926ejs/start.S
@@ -198,9 +198,23 @@ reset:
bl  cpu_init_crit
 #endif
 
-/* Set stackpointer in internal RAM to call board_init_f */
-call_board_init_f:
+   /*
+* Set stack pointer in internal RAM
+*/
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
+
+   /*
+* Set pic base register to the link-time GOT position.
+* At the moment this is also our run-time position.
+* Set both r10 and r9 because either could be used as pic base
+* depending on whether stack checking is off or on.
+*/
+   ldr r10, _got_base
+   mov r9, r10
+
+   /*
+* Call board_init_f, passing it 0 for bootflag
+*/
ldr r0,=0x
bl  board_init_f
 
@@ -220,7 +234,9 @@ relocate_code:
mov r6, r2  /* save addr of destination */
mov r7, r2  /* save addr of destination */
 
-   /* Set up the stack */
+   /*
+* Set up the stack
+*/
 stack_setup:
mov sp, r4
 
@@ -234,9 +250,9 @@ stack_setup:
 
 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
 copy_loop:
-   ldmia   r0!, {r9-r10}   /* copy from source address [r0]*/
-   stmia   r6!, {r9-r10}   /* copy to   target address [r1]*/
-   cmp r0, r2  /* until source end addreee [r2]*/
+   ldmia   r0!, {r11-r12}  /* copy from source address [r0]*/
+   stmia   r6!, {r11-r12}  /* copy to   target address [r6]*/
+   cmp r0, r2  /* until source end address [r2]*/
ble copy_loop
 
 #ifndef CONFIG_PRELOADER
@@ -259,6 +275,15 @@ fixloop:
cmp r2, r3
bne fixloop
 #endif
+
+   /*
+* Fix pic base register as well
+*/
+   sub r9, r9, r1
+   add r9, r9, r0
+   sub r10, r10, r1
+   add r10, r10, r0
+
 #endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
 
 clear_bss:
@@ -305,6 +330,9 @@ _nand_boot: .word nand_boot
 _board_init_r: .word board_init_r
 #endif
 
+_got_base:
+   .word __got_base
+
 #else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
 /*
  * the actual reset code
diff --git a/arch/arm/cpu/arm926ejs/u-boot.lds 
b/arch/arm/cpu/arm926ejs/u-boot.lds
index 02eb8ca..b6e21f2 100644
--- a/arch/arm/cpu/arm926ejs/u-boot.lds
+++ b/arch/arm/cpu/arm926ejs/u-boot.lds
@@ -53,6 +53,7 @@ SECTIONS
 
__got_start = .;
. = ALIGN(4);
+   __got_base = .;
.got : { *(.got) }
 
__got_end = .;
diff --git a/board/karo/tx25/config.mk b/board/karo/tx25/config.mk
index 51ca1ab..1a32c87 100644
--- a/board/karo/tx25/config.mk
+++ b/board/karo/tx25/config.mk
@@ -1,5 +1,5 @@
 ifdef CONFIG_NAND_SPL
 TEXT_BASE = 0x810c
 else
-TEXT_BASE = 0x81fc
+TEXT_BASE = 0x81fc1000
 endif
diff --git a/include/configs/tx25.h b/include/configs/tx25.h
index c798570..b83c95f 100644
--- a/include/configs/tx25.h
+++ b/include/configs/tx25.h
@@ -41,7 +41,7 @@
 #define CONFIG_SYS_NAND_U_BOOT_OFFS0x800
 #define CONFIG_SYS_NAND_U_BOOT_SIZE0x3
 
-#define CONFIG_SYS_NAND_U_BOOT_DST  (0x81fc)
+#define CONFIG_SYS_NAND_U_BOOT_DST  (0x81fc1000)
 #define CONFIG_SYS_NAND_U_BOOT_STARTCONFIG_SYS_NAND_U_BOOT_DST
 
 #define CONFIG_SYS_NAND_PAGE_SIZE  2048
diff --git a/nand_spl/board/karo/tx25/u-boot.lds 
b/nand_spl/board/karo/tx25/u-boot.lds
index c572557..b60c0df 100644
--- a/nand_spl/board/karo/tx25/u-boot.lds
+++ b/nand_spl/board/karo/tx25/u-boot.lds
@@ -55,6 +55,7 @@ SECTIONS
 
__got_start = .;
. = ALIGN(4);
+   __got_b

Re: [U-Boot] [RFC] [PATCH 0/4] Add support for Freescale's 85xx and P1/P2xxx eSPI controller

2010-09-28 Thread Reinhard Meyer
Dear Wolfgang Denk, Can Aydin,
>> True, a GPIO pin could be re-purposed to serve as chip select, but that 
>> would involve a soldering iron and a steady hand as the P1/P2xxRDB 
> 
> That was not the question.
> 
> Reinhard asked if the SPI Chip Select Pins could be configured such so
> that they can be used in GPIO mode instead of special function mode.
> That would make code way simpler.
Exactly. Just have this pin work as GPIO, while the rest stays special
function. But then, some SoCs can not individually assign pins to special
functions but can only do that in groups. Maybe that's the issue here.

And then: currently an "sf write" is not restricted in the length of data
written. It would be limited due to the malloc needed for the patch.

Reinhard

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Re: [U-Boot] [PATCH V3 1/2] [NEXT] arm: change relocation flag from -fPIC to -fPIE

2010-09-28 Thread Ben Gardiner
On Tue, Sep 28, 2010 at 9:14 AM, Albert Aribaud  wrote:
> Replace GOT indirect addressing with more efficient pic-base
> relative addressing for initialized data (uninitialized data
> still use GOTi indirect addressing).  This also reduces code
> size by 0.4% compared to -fPIC.
>
> Signed-off-by: Albert Aribaud 

Applies cleanly to 3df61957938586c512c17e72d83551d190400981 of u-boot/next.

Tested on da850evm -- u-boot prompt is obtained and bootm of linux
uImage is possible with the fix for bootparam address on the da850evm.

Tested-by: Ben Gardiner 

Best Regards,
Ben Gardiner

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Re: [U-Boot] [PATCH V3 2/2] [NEXT] arm926ejs: reduce code size with -msingle-pic-base

2010-09-28 Thread Ben Gardiner
On Tue, Sep 28, 2010 at 9:14 AM, Albert Aribaud  wrote:
> Add -msingle-pic-base to the relocation flags, and compute the pic base
> in start.S twice and for all -- once before relocation to run board_init_f,
> and once after relocation to run board_init_r and the rest of u-boot.
> This further reduces code size by 2.5% compared to -fPIE alone.
>
> Signed-off-by: Albert Aribaud 

Applies cleanly to 3df61957938586c512c17e72d83551d190400981 of u-boot/next.

Tested on da850evm -- u-boot prompt is obtained and bootm of linux
uImage is possible with the fix for bootparam address on the da850evm.

Tested-by: Ben Gardiner 

Best Regards,
Ben Gardiner

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Re: [U-Boot] [PATCH V3 1/2] [NEXT] arm: change relocation flag from -fPIC to -fPIE

2010-09-28 Thread Heiko Schocher
Hello Albert,

Albert Aribaud wrote:
> Replace GOT indirect addressing with more efficient pic-base
> relative addressing for initialized data (uninitialized data
> still use GOTi indirect addressing).  This also reduces code
> size by 0.4% compared to -fPIC.
> 
> Signed-off-by: Albert Aribaud 

Tested on the tx25 board.

Tested-by: Heiko Schocher 

bye,
Heiko
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Re: [U-Boot] [PATCH V3 2/2] [NEXT] arm926ejs: reduce code size with -msingle-pic-base

2010-09-28 Thread Heiko Schocher
Hello Albert,

Albert Aribaud wrote:
> Add -msingle-pic-base to the relocation flags, and compute the pic base
> in start.S twice and for all -- once before relocation to run board_init_f,
> and once after relocation to run board_init_r and the rest of u-boot.
> This further reduces code size by 2.5% compared to -fPIE alone.
> 
> Signed-off-by: Albert Aribaud 

Tested on the tx25 board.

Tested-by: Heiko Schocher 

bye,
Heiko
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Re: [U-Boot] [PATCH v4 2/2] TI: DaVinci DA850 EVM: support passing maximum allowed cpu clock rate information to kernel

2010-09-28 Thread Ben Gardiner
On Fri, Sep 24, 2010 at 1:10 AM, Nori, Sekhar  wrote:
> Hello All,
>
> On Fri, Aug 27, 2010 at 10:44:58, Nori, Sekhar wrote:
>> The TI DA850/OMAP-L138/AM18x EVM can be populated with devices
>> having different maximum allowed CPU clock rating.
>>
>> The maximum clock the chip can support can only be determined from
>> the label on the package (not software readable).
>>
>> Introduce a method to pass the maximum allowed clock rate information
>> to kernel using ATAG_REVISION. The kernel uses this information to
>> determine the maximum cpu clock rate reachable using cpufreq.
>>
>> Note that U-Boot itself does not set the CPU clock rate. The CPU
>> clock is setup by a primary bootloader ("UBL"). The rate setup by
>> UBL could be different from the maximum clock rate supported by the
>> device.
>
> Any more feedback on this patch? There are couple of kernel patches
> which depend on this, that's why I ask.

FWIW: it's fine with me.

Applies cleanly to 3df61957938586c512c17e72d83551d190400981 of u-boot/next.

Tested on da850evm -- bootm of linux uImage works with the patch
'da850evm: fix linux bootparam address' aplied.

The kernel uImage used did not have support for parsing the
ATAG_REVISION information since that patch has not been posted to the
davinci-linux list.

Tested-by: Ben Gardiner 

Best Regards,
Ben Gardiner

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Re: [U-Boot] [PATCH] ppc44x: config GPIOs for USB on canyonlands board

2010-09-28 Thread Detlev Zundel
Hi Feng,

[general remark - isn't it possible that you quote mails "the regular
way"[1]?  I'm having a hard time to distinguish the new text from the
original text].

> On Fri, Sep 24, 2010 at 10:43 AM, Wolfgang Denk  wrote:
>> Dear Feng Kan,
>>
>> In message  
>> you wrote:
>>>
>>> FKAN: Dear Wolfgang, is the symmetry needed here? If a user
>>> plan to use the usb, he will trigger the function. Otherwise, on
>>> a stop what value would we put it back to.
>>
>> Design rules say:
>>
>>        Shall initialize only such peripherals used by U-Boot itself,
>>        and must deinitialize them after use. Note that especially the
>>        deinitialization is mandatory!
>>
> FKAN: I agree, thanks. However, this conflict with one of your other
> rule "Don't make U-Boot slow". If another software entity wish to use
> the GPIO after, the code would deinit to gpio state and the
> other init would init gpio to the same state. Essentially doubling the
> code doing the same thing.

The time it takes to initialize a GPIO pin is really negligible in
comparision to the gain of robustness and correctness of the code.  When
a driver needs the pin in a certain state, it should initialize this and
_not_ depend on any other piece of software.  This is the well known
rule of modularity[2].

>> Isn't this GPI reset to the initial values part of the
>> deinitialization sequence?
>
> FKAN: In this case, gpio is double muxed in functionality. Do we need
> to remember state if the gpio is tri-muxed?

I don't understand this question.  The de-initialization is meant to
stop functional blocks and put pins into a "conservative state",
i.e. configure GPIOs as inputs so that they don't drive possible shared
lines.  Code using the pins will surely know which mode they need and
put the pins into this mode upon initialization.

Cheers
  Detlev

[1] http://www.netmeister.org/news/learn2quote.html
[2] http://www.catb.org/~esr/writings/taoup/html/ch01s06.html#id2877537

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he will say that on the average he feels fine.
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Re: [U-Boot] [PATCH] usb: fix usb start problem with SMSC USB hub and Toshiba USB stick

2010-09-28 Thread Detlev Zundel
Hi Roland,

[...]

>> See, that's another reason why we still have such problems - once a
>> hardware replacement is found, the problem is no longer pursued.
>
> Oh, have a look on the linux bugtracker or other linux communities.

USB support in Linux is way better than what we have in U-Boot and thats
what I was talking about.

> Anyway, i found one of the problematic USB bridge cables being problematic
> on my new netbook, too (disk not being recognized), so i assume it`s really
> crap and my 2 failing setups are mostly due to bad hardware. I will keep an
> eye on that and report my findings, if appreciated.

Of course this is appreciated!  Many samples in the "experince space"
are important information for developers.  Although we usually only see
the "it doesn't work" samples, some "hey it works!" would also not hurt
;)

Cheers
  Detlev

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Re: [U-Boot] u-boot on dockstar problem - ** Bad partition 1 **

2010-09-28 Thread Detlev Zundel
Hi Roland,

> regarding the status of the dockstar integration:
>
>> Yes, indeed - the feedback only touched some formal points.  Reworking
>> the patches should be easy.
>
> taken from http://forum.doozan.com/read.php?3,881,978#msg-978 :
>
> "Cool. I'm currently hung up on making my patches work with the new ARM
> relocation stuff that's been pulled into the upcoming (2010.09)
> release. I just
> don't know enough about the low-level hardware to know how to adapt it. So
> I'm waiting for the "real" SheevaPlug maintainers to adapt their code,
> then it
> should be trivial to copy."

Yes I read that.  Has anybody pinged the SheevaPlug maintainer about it?

If nothing happens on this front, I believe there are examples of what
the conversion has to do and it should not be _that_ difficult to do
it.  Of course the mailing list is always a good ressource for actual
problems ;)

> regarding broken gmane search:
>
>>> (just wondering, why i did not find that via google and gmane
>>> search on the
>>> u-boot mailing list archive - i searched for dockstar and for
>>> freeagent , but got
>>> no hits!)
>>
>> Actually I have no clue.  The gmane search seems to miss newer articles
>> of this year.  I'll try to contact Lars about this.
>
> Any update on this ? Search on gmane is definitely broken.

No, thanks for reminding - I just sent another ping.

> Btw, i found that marc.info also has u-boot searchable archive at
> http://marc.info/?l=u-boot , so maybe it helps if another link would be
> added on http://www.denx.de/wiki/U-Boot  ?
> Some may find that marc.info is more easy to use/browse anyway, and
> the guys @marc.info offer an remarkable and reliable service.

 That page is a wiki page  :)

Cheers
  Detlev

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Re: [U-Boot] Coldfire Architecture and SELF

2010-09-28 Thread SANCHEZ VITORICA, GUILLERMO
Hello all,

I feel a little bit silly for asking this but, is the Coldfire
Architecture supported by ELDK?

Kind regards,
 
Guillermo Sanchez Vitorica
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Re: [U-Boot] how to u-boot in LPC2468 board using uClinux

2010-09-28 Thread Detlev Zundel
Hi Shashidhar.H.G,

> I'm trying to port uCLinux on to the LPC 2468-16 OEM Board.

You may have noticed that this is the U-Boot mailing list.  If you have
trouble with uCLinux, the linux-arm mailing list is more to the point.

> .HEX file is been generated by following the steps (Section 10) given in the
> document (Getting_started_with_uClinux), and now am trying to flash the same
> .HEX file to the board using Flash Magic tool and am facing some issue,
> please find the attachment for Error Snapshot.

I have no clue what document you are talking about, sorry.

> On target side, all the necessary setting has been done including the jumper
> setting given in LPC2468_OEM_Board_Users_Guide.
>  
> but i din't get the u-boot prompt in the terminal window its gets struck in
> the
> starting display itself. http://old.nabble.com/file/p29815748/Error.jpg.JPG
> Error.jpg.JPG 

This seems like a general problem outside the scope of U-Boot.  Have you
communicated with the board previously at all?  Are the cables correct?

Cheers
  Detlev

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[U-Boot] [PATCH V2 1/7] Expand POST memory test to support arch-depended implementation.

2010-09-28 Thread York Sun
Add weak functions to enable architecture depended preparation, address
advancing, cleaning up and error handling.

Signed-off-by: York Sun 
---
 post/drivers/memory.c |   65 +++-
 1 files changed, 47 insertions(+), 18 deletions(-)

diff --git a/post/drivers/memory.c b/post/drivers/memory.c
index 0062360..203bc36 100644
--- a/post/drivers/memory.c
+++ b/post/drivers/memory.c
@@ -452,31 +452,60 @@ static int memory_post_tests (unsigned long start, 
unsigned long size)
return ret;
 }
 
-int memory_post_test (int flags)
+__attribute__((weak))
+int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
 {
-   int ret = 0;
bd_t *bd = gd->bd;
-   unsigned long memsize = (bd->bi_memsize >= 256 << 20 ?
-256 << 20 : bd->bi_memsize) - (1 << 20);
-
+   *vstart = CONFIG_SYS_SDRAM_BASE;
+   *size = (bd->bi_memsize >= 256 << 20 ?
+   256 << 20 : bd->bi_memsize) - (1 << 20);
/* Limit area to be tested with the board info struct */
-   if (CONFIG_SYS_SDRAM_BASE + memsize > (ulong)bd)
-   memsize = (ulong)bd - CONFIG_SYS_SDRAM_BASE;
+   if ((*vstart) + (*size) > (ulong)bd)
+   *size = (ulong)bd - CONFIG_SYS_SDRAM_BASE;
+   return 0;
+}
 
-   if (flags & POST_SLOWTEST) {
-   ret = memory_post_tests (CONFIG_SYS_SDRAM_BASE, memsize);
-   } else {/* POST_NORMAL */
+__attribute__((weak))
+int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
+{
+   return 1;
+}
 
-   unsigned long i;
+__attribute__((weak))
+int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
+{
+   return 0;
+}
 
-   for (i = 0; i < (memsize >> 20) && ret == 0; i++) {
-   if (ret == 0)
-   ret = memory_post_tests (i << 20, 0x800);
-   if (ret == 0)
-   ret = memory_post_tests ((i << 20) + 0xff800, 
0x800);
-   }
-   }
+__attribute__((weak))
+void arch_memory_failure_handle(void)
+{
+   return;
+}
 
+int memory_post_test(int flags)
+{
+   int ret = 0;
+   phys_addr_t phys_offset = 0;
+   u32 memsize, vstart;
+
+   arch_memory_test_prepare(&vstart, &memsize, &phys_offset);
+   do {
+   if (flags & POST_SLOWTEST) {
+   ret = memory_post_tests(vstart, memsize);
+   } else {/* POST_NORMAL */
+   unsigned long i;
+   for (i = 0; i < (memsize >> 20) && ret == 0; i++) {
+   if (ret == 0)
+   ret = memory_post_tests(i << 20, 0x800);
+   if (ret == 0)
+   ret = memory_post_tests((i << 20) + 
0xff800, 0x800);
+   }
+   }
+   } while (!ret && !arch_memory_test_advance(&vstart, &memsize, 
&phys_offset));
+   arch_memory_test_cleanup(&vstart, &memsize, &phys_offset);
+   if (ret)
+   arch_memory_failure_handle();
return ret;
 }
 
-- 
1.7.0.4


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[U-Boot] [PATCH V2 2/7] Adding more control to physical address mapping

2010-09-28 Thread York Sun
A worker function __setup_ddr_tlbs() is introduced to implement more
control on physical address mapping.

Signed-off-by: York Sun 
---
 arch/powerpc/cpu/mpc85xx/tlb.c |   16 ++--
 1 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c
index f2833a5..019fab7 100644
--- a/arch/powerpc/cpu/mpc85xx/tlb.c
+++ b/arch/powerpc/cpu/mpc85xx/tlb.c
@@ -245,7 +245,8 @@ void init_addr_map(void)
 }
 #endif
 
-unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
+unsigned int
+__setup_ddr_tlbs(phys_addr_t p_addr, unsigned int memsize_in_meg)
 {
int i;
unsigned int tlb_size;
@@ -275,21 +276,24 @@ unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
 
tlb_size = (camsize - 10) / 2;
 
-   set_tlb(1, ram_tlb_address, ram_tlb_address,
+   set_tlb(1, ram_tlb_address, p_addr,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, ram_tlb_index, tlb_size, 1);
 
size -= 1ULL << camsize;
memsize -= 1ULL << camsize;
ram_tlb_address += 1UL << camsize;
+   p_addr += 1UL << camsize;
}
 
if (memsize)
print_size(memsize, " left unmapped\n");
-
-   /*
-* Confirm that the requested amount of memory was mapped.
-*/
return memsize_in_meg;
 }
+
+unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
+{
+   return
+   __setup_ddr_tlbs(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg);
+}
 #endif /* !CONFIG_NAND_SPL */
-- 
1.7.0.4


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[U-Boot] [PATCH V2 4/7] Fix address for POST for 85xx with CPM

2010-09-28 Thread York Sun
The address used for post_word_load and post_word_store is in the dual port
RAM for processors with CPM.

Signed-off-by: York Sun 
---
 arch/powerpc/cpu/mpc85xx/commproc.c |4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/commproc.c 
b/arch/powerpc/cpu/mpc85xx/commproc.c
index f0fd1cb..1671b5e 100644
--- a/arch/powerpc/cpu/mpc85xx/commproc.c
+++ b/arch/powerpc/cpu/mpc85xx/commproc.c
@@ -189,7 +189,7 @@ m8560_cpm_extcbrg(uint brg, uint rate, uint extclk, int 
pinsel)
 void post_word_store (ulong a)
 {
volatile ulong *save_addr =
-   (volatile ulong *)(CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR);
+   (volatile ulong *)(CONFIG_SYS_MPC85xx_CPM_ADDR + 
CPM_POST_WORD_ADDR);
 
*save_addr = a;
 }
@@ -197,7 +197,7 @@ void post_word_store (ulong a)
 ulong post_word_load (void)
 {
volatile ulong *save_addr =
-   (volatile ulong *)(CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR);
+   (volatile ulong *)(CONFIG_SYS_MPC85xx_CPM_ADDR + 
CPM_POST_WORD_ADDR);
 
return *save_addr;
 }
-- 
1.7.0.4


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[U-Boot] [PATCH V2 6/7] Enable POST memory test for corenet_ds

2010-09-28 Thread York Sun
Signed-off-by: York Sun 
---
 include/configs/corenet_ds.h |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index cbe5024..5ce0efd 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -86,6 +86,7 @@
 #define CONFIG_SYS_NUM_ADDR_MAP64  /* number of TLB1 
entries */
 #endif
 
+#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
 #define CONFIG_SYS_MEMTEST_START   0x0020  /* memtest works on */
 #define CONFIG_SYS_MEMTEST_END 0x0040
 #define CONFIG_SYS_ALT_MEMTEST
-- 
1.7.0.4


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[U-Boot] [PATCH V2 5/7] Setup POST word for generic mpc85xx

2010-09-28 Thread York Sun
Using PIC TFRR register for post word load/store for generic MPC85xx.

Signed-off-by: York Sun 
---
 arch/powerpc/cpu/mpc85xx/cpu.c |   17 +
 1 files changed, 17 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index f60fa47..7662cb8 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -286,6 +286,23 @@ void mpc85xx_reginfo(void)
print_lbc_regs();
 }
 
+#ifdef CONFIG_POST
+
+__attribute__((weak))
+void post_word_store(ulong a)
+{
+   void *save_addr = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR + 
offsetof(ccsr_pic_t, tfrr));
+   out_be32(save_addr, a);
+}
+__attribute__((weak))
+ulong post_word_load(void)
+{
+   void *save_addr = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR + 
offsetof(ccsr_pic_t, tfrr));
+   return in_be32(save_addr);
+}
+
+#endif /* CONFIG_POST */
+
 #if CONFIG_POST & CONFIG_SYS_POST_MEMORY
 
 /* Board-specific functions defined in each board's ddr.c */
-- 
1.7.0.4


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[U-Boot] [PATCH V2 7/7] Enable POST memory test for P2020DS

2010-09-28 Thread York Sun
Signed-off-by: York Sun 
---
 include/configs/P2020DS.h |5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h
index 79ce2c0..923072a 100644
--- a/include/configs/P2020DS.h
+++ b/include/configs/P2020DS.h
@@ -73,8 +73,9 @@
 #define CONFIG_SYS_NUM_ADDR_MAP16  /* number of TLB1 
entries */
 #endif
 
-#define CONFIG_SYS_MEMTEST_START   0x  /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x7fff
+#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
+#define CONFIG_SYS_MEMTEST_START   0x0020  /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x0040
 #define CONFIG_PANIC_HANG  /* do not reset board on panic */
 
 /*
-- 
1.7.0.4


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[U-Boot] [PATCH V2 3/7] Add memory test feature for mpc85xx POST.

2010-09-28 Thread York Sun
The memory test is performed after DDR initialization when U-boot stills runs
in flash and cache. Whole memory can be tested. It is mapped 2GB at a time
using a sliding TLB window. After the testing, DDR is remapped with up to 2GB
memory from the lowest address as normal.

If memory test fails, DDR DIMM SPD and DDR controller registers are dumped.

Signed-off-by: York Sun 
---
 arch/powerpc/cpu/mpc85xx/cpu.c |  197 
 doc/README.fsl-ddr |   13 +++
 2 files changed, 210 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 3f80700..f60fa47 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -34,6 +34,9 @@
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -282,3 +285,197 @@ void mpc85xx_reginfo(void)
print_laws();
print_lbc_regs();
 }
+
+#if CONFIG_POST & CONFIG_SYS_POST_MEMORY
+
+/* Board-specific functions defined in each board's ddr.c */
+void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
+   unsigned int ctrl_num);
+void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
+  phys_addr_t *rpn);
+unsigned int __setup_ddr_tlbs(phys_addr_t p_addr, unsigned int memsize_in_meg);
+
+static void dump_spd_ddr_reg(void)
+{
+   int i, j, k, m;
+   u8 *p_8;
+   u32 *p_32;
+   ccsr_ddr_t *ddr[CONFIG_NUM_DDR_CONTROLLERS];
+   generic_spd_eeprom_t
+   spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR];
+
+   for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
+   fsl_ddr_get_spd(spd[i], i);
+
+   puts("SPD data of all dimms (zero vaule is omitted)...\n");
+   puts("Byte (hex)  ");
+   k = 1;
+   for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+   for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++)
+   printf("Dimm%d ", k++);
+   }
+   puts("\n");
+   for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) {
+   m = 0;
+   printf("%3d (0x%02x)  ", k, k);
+   for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+   for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
+   p_8 = (u8 *) &spd[i][j];
+   if (p_8[k]) {
+   printf("0x%02x  ", p_8[k]);
+   m++;
+   } else
+   puts("  ");
+   }
+   }
+   if (m)
+   puts("\n");
+   else
+   puts("\r");
+   }
+
+   for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+   switch (i) {
+   case 0:
+   ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
+   break;
+#ifdef CONFIG_SYS_MPC85xx_DDR2_ADDR
+   case 1:
+   ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR;
+   break;
+#endif
+   default:
+   printf("%s unexpected controller number = %u\n",
+   __func__, i);
+   return;
+   }
+   }
+   printf("DDR registers dump for all controllers "
+   "(zero vaule is omitted)...\n");
+   puts("Offset (hex)   ");
+   for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
+   printf(" Base + 0x%04x", (u32)ddr[i] & 0x);
+   puts("\n");
+   for (k = 0; k < sizeof(ccsr_ddr_t)/4; k++) {
+   m = 0;
+   printf("%6d (0x%04x)", k * 4, k * 4);
+   for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+   p_32 = (u32 *) ddr[i];
+   if (p_32[k]) {
+   printf("0x%08x", p_32[k]);
+   m++;
+   } else
+   puts("  ");
+   }
+   if (m)
+   puts("\n");
+   else
+   puts("\r");
+   }
+   puts("\n");
+}
+
+static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset)
+{
+   u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
+   unsigned long epn;
+   u32 tsize, valid, ptr;
+   phys_addr_t rpn = 0;
+   int ddr_esel;
+
+   ptr = vstart;
+   while (ptr < (vstart + size)) {
+   ddr_esel = find_tlb_idx((void *)ptr, 1);
+   if (ddr_esel != -1) {
+   read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
+   disable_tlb(ddr_esel);
+   }
+   ptr += TSIZE_TO_BYTES(tsize);
+   }
+   /* Setup new tlb to cover the physical address */
+   __setup_ddr_tlbs(p_addr, si

Re: [U-Boot] Coldfire Architecture and SELF

2010-09-28 Thread Wolfgang Denk
Dear "SANCHEZ VITORICA, GUILLERMO",

In message <3694e0885cb1d844aaf54f75dbdc255834d...@mail1.usr.corp.gamesa.es> 
you wrote:
> 
> I feel a little bit silly for asking this but, is the Coldfire
> Architecture supported by ELDK?

No, it is not. We support ARM, Power, and MIPS.

Best regards,

Wolfgang Denk

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They say, well, meybe it _is_ smelly, maybe it _is_ overcrowded, may-
be it _is_ a bit like Hell would be if they shut the  fires  off  and
stabled  a  herd  of  incontinent cows there for a year, but you must
admit that it is full of sheer, vibrant, dynamic _life_.
 - Terry Pratchett, _Moving Pictures_
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Re: [U-Boot] [PATCH V2 1/7] Expand POST memory test to support arch-depended implementation.

2010-09-28 Thread Wolfgang Denk
Dear York Sun,

In message <1285691891-32700-1-git-send-email-york...@freescale.com> you wrote:
> Add weak functions to enable architecture depended preparation, address
> advancing, cleaning up and error handling.
> 
> Signed-off-by: York Sun 

This needs some comments to explain the interfaces you are providing.

> -int memory_post_test (int flags)
> +__attribute__((weak))
> +int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t 
> *phys_offset)

phys_offset is unused here. Drop it?

> - int ret = 0;
>   bd_t *bd = gd->bd;
> - unsigned long memsize = (bd->bi_memsize >= 256 << 20 ?
> -  256 << 20 : bd->bi_memsize) - (1 << 20);
> -
> + *vstart = CONFIG_SYS_SDRAM_BASE;

Blank line after declarations, please.

> + *size = (bd->bi_memsize >= 256 << 20 ?
> + 256 << 20 : bd->bi_memsize) - (1 << 20);
>   /* Limit area to be tested with the board info struct */
> - if (CONFIG_SYS_SDRAM_BASE + memsize > (ulong)bd)
> - memsize = (ulong)bd - CONFIG_SYS_SDRAM_BASE;
> + if ((*vstart) + (*size) > (ulong)bd)
> + *size = (ulong)bd - CONFIG_SYS_SDRAM_BASE;

Should this eventually be

*size = (ulong)bd - *vstart;
??

> +__attribute__((weak))
> +int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t 
> *phys_offset)
> +{
> + return 1;
> +}

Unused arguments?

Don't you get compiler warnings for these?

> +__attribute__((weak))
> +int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t 
> *phys_offset)
> +{
> + return 0;
> +}

Ditto ?

> +int memory_post_test(int flags)
> +{
> + int ret = 0;
> + phys_addr_t phys_offset = 0;
> + u32 memsize, vstart;
> +
> + arch_memory_test_prepare(&vstart, &memsize, &phys_offset);
> + do {

Empty line before the do, please.

> + if (flags & POST_SLOWTEST) {
> + ret = memory_post_tests(vstart, memsize);
> + } else {/* POST_NORMAL */
> + unsigned long i;
> + for (i = 0; i < (memsize >> 20) && ret == 0; i++) {
> + if (ret == 0)
> + ret = memory_post_tests(i << 20, 0x800);
> + if (ret == 0)
> + ret = memory_post_tests((i << 20) + 
> 0xff800, 0x800);

Line too long.

> + }
> + }
> + } while (!ret && !arch_memory_test_advance(&vstart, &memsize, 
> &phys_offset));
> + arch_memory_test_cleanup(&vstart, &memsize, &phys_offset);

Empty line before and after, please.

> + if (ret)
> + arch_memory_failure_handle();
>   return ret;

Empty line before.

Best regards,

Wolfgang Denk

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[U-Boot] [PATCH] ARMV7: OMAP: Use default vendor/product ID for USB gadget

2010-09-28 Thread Steve Sakoman
TI hasn't reserved a USB Product ID for gadgets, so use the default
vendor and product ID to avoid confusion.

Signed-off-by: Steve Sakoman 
---
 include/configs/omap3_beagle.h  |5 -
 include/configs/omap4_panda.h   |5 -
 include/configs/omap4_sdp4430.h |5 -
 3 files changed, 0 insertions(+), 15 deletions(-)

diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index 71553f9..fbe96aa 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -111,11 +111,6 @@
 #define CONFIG_USB_DEVICE  1
 #define CONFIG_USB_TTY 1
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV   1
-/* Change these to suit your needs */
-#define CONFIG_USBD_VENDORID   0x0451
-#define CONFIG_USBD_PRODUCTID  0x5678
-#define CONFIG_USBD_MANUFACTURER   "Texas Instruments"
-#define CONFIG_USBD_PRODUCT_NAME   "Beagle"
 
 /* commands to include */
 #include 
diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h
index a0d27a4..d4a1d1c 100644
--- a/include/configs/omap4_panda.h
+++ b/include/configs/omap4_panda.h
@@ -120,11 +120,6 @@
 #define CONFIG_USB_DEVICE  1
 #define CONFIG_USB_TTY 1
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV   1
-/* Change these to suit your needs */
-#define CONFIG_USBD_VENDORID   0x0451
-#define CONFIG_USBD_PRODUCTID  0x5678
-#define CONFIG_USBD_MANUFACTURER   "Texas Instruments"
-#define CONFIG_USBD_PRODUCT_NAME   "OMAP4 Panda"
 
 /* Flash */
 #define CONFIG_SYS_NO_FLASH1
diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h
index d5439f9..98a86c3 100644
--- a/include/configs/omap4_sdp4430.h
+++ b/include/configs/omap4_sdp4430.h
@@ -121,11 +121,6 @@
 #define CONFIG_USB_DEVICE  1
 #define CONFIG_USB_TTY 1
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV   1
-/* Change these to suit your needs */
-#define CONFIG_USBD_VENDORID   0x0451
-#define CONFIG_USBD_PRODUCTID  0x5678
-#define CONFIG_USBD_MANUFACTURER   "Texas Instruments"
-#define CONFIG_USBD_PRODUCT_NAME   "SDP4430"
 
 /* Flash */
 #define CONFIG_SYS_NO_FLASH1
-- 
1.7.0.4



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Re: [U-Boot] [PATCH V2 2/7] Adding more control to physical address mapping

2010-09-28 Thread Wolfgang Denk
Dear York Sun,

In message <1285691891-32700-2-git-send-email-york...@freescale.com> you wrote:
> A worker function __setup_ddr_tlbs() is introduced to implement more
> control on physical address mapping.

The __ name prefix has a special, reserved meaning. What is your
rationale for using it here?

> +unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
> +{
> + return
> + __setup_ddr_tlbs(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg);

Remove line break.

Best regards,

Wolfgang Denk

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Re: [U-Boot] [PATCH V2 3/7] Add memory test feature for mpc85xx POST.

2010-09-28 Thread Wolfgang Denk
Dear York Sun,

In message <1285691891-32700-3-git-send-email-york...@freescale.com> you wrote:
> The memory test is performed after DDR initialization when U-boot stills runs
> in flash and cache. Whole memory can be tested. It is mapped 2GB at a time
> using a sliding TLB window. After the testing, DDR is remapped with up to 2GB
> memory from the lowest address as normal.
> 
> If memory test fails, DDR DIMM SPD and DDR controller registers are dumped.
> 
> Signed-off-by: York Sun 

Please see previous comments about empty lines etc. to make to code
more readable.

Also, please add some comments to explain what you are actually doing.

> +Memory testing options for mpc85xx
> +==
> +1. Memory test can be done one U-boot prompt comes up using mtest, or

s/one/once/ ?

> +2. Memory test can be done with Power-On-Self-Test function, activated at 
> compile time.
> +
> +   In order to enable the POST memory test, CONFIG_POST needs to be
> +   defined in board configuraiton header file. By default, POST memory test 
> performs
> +   a fast test. A slow test can be enabled by changing the flag at compiling 
> time.
> +   To test memory bigger than 2GB, 36BIT support is needed. Memory is tested 
> within
> +   a 2GB window. TLBs are used to map the virtual 2GB window to physical 
> address
> +   so that all physical memory can be tested.

Lines too long.


Best regards,

Wolfgang Denk

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Re: [U-Boot] [PATCH] ARMV7: OMAP4: Calculate SDRAM size

2010-09-28 Thread Wolfgang Denk
Dear Sandeep,

In message <1285623705.4705.45.ca...@quadra> Steve Sakoman wrote:
> On Mon, 2010-09-27 at 23:37 +0200, Wolfgang Denk wrote:
> > Dear Steve Sakoman,
> > 
> > In message <1285622277.4705.43.ca...@quadra> you wrote:
> > >
> > > The subject patch does indeed set the ram size properly in the OMAP4
> > > specific dram_init() function.  As Wolfgang says above, this is the
> > > proper place.  If there are no other objections we should try to get
> > > this integrated.
> > 
> > It's ok with me. Just waiting for a pull request.
> > 
> > 24 hours to go.
> 
> Thanks Wolfgang.
> 
> Copying Sandeep so he knows he has to work fast :-)

Ping???

Best regards,

Wolfgang Denk

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This was an  amazing  creation  using  small  squares  of  compressed
vegetable  matter on which letters were made by means of small carbon
particles from a stylus, giving an effect similar to the  traditional
word-processor  screen. It seemed amazingly portable and I never once
saw him have to change the batteries.
- Terry Pratchett & Stephen Briggs, _The Discworld Companion_
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Re: [U-Boot] [PATCH] mpc5xxx_fec: add call to reset_phy() after PHY initialization

2010-09-28 Thread Wolfgang Denk
Dear Ben,

ping again...

In message <20100913093325.a8a84152...@gemini.denx.de> I wrote:
> Dear Ben,
> 
> In message <1282208946-18823-1-git-send-email-ya...@emcraft.com> Ilya Yanok 
> wrote:
> > Some boards need their board-specific PHY quirks to be called
> > to PHY to work normally. As mpc5xxx_fec driver uses on demand
> > PHY initialization and can even reinit PHY during normal operation
> > we can't count on reset_phy() call from arch//lib/board.c
> > (it is most likely called _before_ we init the PHY from the
> > driver) so we need to add call to reset_phy() directly in the
> > driver.
> > 
> > Cc: Ben Warren 
> > Signed-off-by: Ilya Yanok 
> > ---
> >  drivers/net/mpc5xxx_fec.c |7 +++
> >  1 files changed, 7 insertions(+), 0 deletions(-)
> 
> Do you have any comments?


Please comment how to go on - this is a real problem that needs to be
fixed one way or another.

Best regards,

Wolfgang Denk

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Re: [U-Boot] [PATCH] ARMV7: OMAP4: Calculate SDRAM size

2010-09-28 Thread Paulraj, Sandeep


> > Thanks Wolfgang.
> >
> > Copying Sandeep so he knows he has to work fast :-)
> 
> Ping???

Its coming in a few minutes
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Re: [U-Boot] [PATCH V2 1/7] Expand POST memory test to support arch-depended implementation.

2010-09-28 Thread York Sun
On Tue, 2010-09-28 at 19:31 +0200, Wolfgang Denk wrote:

> > -int memory_post_test (int flags)
> > +__attribute__((weak))
> > +int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t 
> > *phys_offset)
> 
> phys_offset is unused here. Drop it?
> 

The phys_offset is not used by _this_ weak function but it is used by
another function implemented in the third patch. Is it OK to leave the
unused phys_offset here?

Regards,

York


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[U-Boot] Please Pull u-boot-ti/master

2010-09-28 Thread s-paulraj
The following changes since commit 85d3eba90df54bac27844221e2436550984c4d58:
  Thomas Weber (1):
ixp/npe: Remove duplicated comment

are available in the git repository at:

  git://git.denx.de/u-boot-ti.git master

Aneesh V (1):
  ARMV7: OMAP4: Calculate SDRAM size

Steve Sakoman (2):
  ARMV7: OMAP4: Fix Panda pinmux setting to enable Wifi/BT Module
  ARMV7: OMAP3: Update Beagle xM pinmux with USB hub and DVI gpio setup

 arch/arm/cpu/armv7/omap4/board.c|   30 +-
 arch/arm/include/asm/arch-omap4/omap4.h |   10 ++
 board/ti/beagle/beagle.h|4 
 board/ti/panda/panda.h  |   18 +-
 4 files changed, 52 insertions(+), 10 deletions(-)
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[U-Boot] [PATCH v6 0/2] Add support for new SoC APM821XX

2010-09-28 Thread tmarri
From: Tirumala Marri 

APM821XX is Applied Micro Circuits Corporations naming
convention for new line of SoCs.

V5:
  * Move CONFIG_SYS_PERIPHERAL_BASE  to apm821xx.h
  * MAKEALL change is not needed anymore
  * CONFIG_SYS_NOR_CS is not used anywhere.
  * CONFIG_PHY_RESET_R is not used anywhere
V6:
  * Correcting indentation.

Tirumala Marri (2):
  APM821xx: Add CPU support
  APM821xx: Add bluestone board support

 MAINTAINERS |4 +
 arch/powerpc/cpu/ppc4xx/cpu.c   |   19 
 arch/powerpc/cpu/ppc4xx/cpu_init.c  |5 +-
 arch/powerpc/cpu/ppc4xx/speed.c |   75 +-
 arch/powerpc/cpu/ppc4xx/start.S |   11 ++-
 arch/powerpc/include/asm/apm821xx.h |   72 +
 arch/powerpc/include/asm/ppc4xx-ebc.h   |3 +-
 arch/powerpc/include/asm/ppc4xx-isram.h |   14 ++-
 arch/powerpc/include/asm/ppc4xx-sdram.h |   12 +-
 arch/powerpc/include/asm/ppc4xx-uic.h   |5 +-
 arch/powerpc/include/asm/ppc4xx.h   |4 +
 arch/powerpc/include/asm/processor.h|1 +
 board/amcc/bluestone/Makefile   |   52 +
 board/amcc/bluestone/bluestone.c|  111 +++
 board/amcc/bluestone/config.mk  |   40 +++
 board/amcc/bluestone/init.S |   60 +++
 boards.cfg  |1 +
 include/configs/bluestone.h |  178 +++
 18 files changed, 648 insertions(+), 19 deletions(-)
 create mode 100644 arch/powerpc/include/asm/apm821xx.h
 create mode 100644 board/amcc/bluestone/Makefile
 create mode 100644 board/amcc/bluestone/bluestone.c
 create mode 100644 board/amcc/bluestone/config.mk
 create mode 100644 board/amcc/bluestone/init.S
 create mode 100644 include/configs/bluestone.h

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[U-Boot] [PATCH v6 1/2] APM821xx: Add CPU support

2010-09-28 Thread tmarri
From: Tirumala Marri 

APM821XX is a new line of SoCs which are derivatives of
PPC44X family of processors. This patch adds support of CPU, cache,
tlb, 32k ocm, bootstraps, PLB and AHB bus.

Signed-off-by: Tirumala R Marri 
---
V5:
  * Move CONFIG_SYS_PERIPHERAL_BASE  to apm821xx.h
V6:
  * Correcting indentation.
---
---
 arch/powerpc/cpu/ppc4xx/cpu.c   |   19 
 arch/powerpc/cpu/ppc4xx/cpu_init.c  |5 +-
 arch/powerpc/cpu/ppc4xx/speed.c |   75 ++-
 arch/powerpc/cpu/ppc4xx/start.S |   11 +++--
 arch/powerpc/include/asm/apm821xx.h |   72 +
 arch/powerpc/include/asm/ppc4xx-ebc.h   |3 +-
 arch/powerpc/include/asm/ppc4xx-isram.h |   14 +-
 arch/powerpc/include/asm/ppc4xx-sdram.h |   12 +++---
 arch/powerpc/include/asm/ppc4xx-uic.h   |5 +-
 arch/powerpc/include/asm/ppc4xx.h   |4 ++
 arch/powerpc/include/asm/processor.h|1 +
 11 files changed, 202 insertions(+), 19 deletions(-)

diff --git a/arch/powerpc/cpu/ppc4xx/cpu.c b/arch/powerpc/cpu/ppc4xx/cpu.c
index 6009b0c..67f1fff 100644
--- a/arch/powerpc/cpu/ppc4xx/cpu.c
+++ b/arch/powerpc/cpu/ppc4xx/cpu.c
@@ -250,6 +250,20 @@ static char *bootstrap_str[] = {
 };
 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
 #endif
+#if defined(CONFIG_APM821XX)
+#define SDR0_PINSTP_SHIFT   29
+static char *bootstrap_str[] = {
+   "RESERVED",
+   "RESERVED",
+   "RESERVED",
+   "NAND (8 bits)",
+   "NOR  (8 bits)",
+   "NOR  (8 bits) w/PLL Bypassed",
+   "I2C (Addr 0x54)",
+   "I2C (Addr 0x52)",
+};
+static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' };
+#endif
 
 #if defined(SDR0_PINSTP_SHIFT)
 static int bootstrap_option(void)
@@ -590,6 +604,11 @@ int checkcpu (void)
strcpy(addstr, "No Security support");
break;
 
+   case PVR_APM821XX_RA:
+   puts("APM821XX Rev. A");
+   strcpy(addstr, "Security support");
+   break;
+
case PVR_VIRTEX5:
puts("440x5 VIRTEX5");
break;
diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c 
b/arch/powerpc/cpu/ppc4xx/cpu_init.c
index d54b30e..125241b 100644
--- a/arch/powerpc/cpu/ppc4xx/cpu_init.c
+++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c
@@ -237,7 +237,8 @@ cpu_init_f (void)
 
reconfigure_pll(CONFIG_SYS_PLL_RECONFIG);
 
-#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && 
!defined(CONFIG_SYS_4xx_GPIO_TABLE)
+#if !defined(CONFIG_APM821XX) && (defined(CONFIG_405EP) ||\
+   defined (CONFIG_405EX)) && !defined(CONFIG_SYS_4xx_GPIO_TABLE)
/*
 * GPIO0 setup (select GPIO or alternate function)
 */
@@ -393,7 +394,7 @@ cpu_init_f (void)
 #if defined(CONFIG_405EX) || \
 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
 defined(CONFIG_460EX) || defined(CONFIG_460GT)  || \
-defined(CONFIG_460SX)
+defined(CONFIG_460SX) || defined(CONFIG_APM821XX)
/*
 * Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read
 */
diff --git a/arch/powerpc/cpu/ppc4xx/speed.c b/arch/powerpc/cpu/ppc4xx/speed.c
index abd4e91..09d6671 100644
--- a/arch/powerpc/cpu/ppc4xx/speed.c
+++ b/arch/powerpc/cpu/ppc4xx/speed.c
@@ -189,7 +189,7 @@ ulong get_PCI_freq (void)
 #elif defined(CONFIG_440)
 
 #if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-defined(CONFIG_460SX)
+defined(CONFIG_460SX) || defined(CONFIG_APM821XX)
 static u8 pll_fwdv_multi_bits[] = {
/* values for:  1 - 16 */
0x00, 0x01, 0x0f, 0x04, 0x09, 0x0a, 0x0d, 0x0e, 0x03, 0x0c,
@@ -250,6 +250,78 @@ u32 get_cpr0_fbdv(unsigned long cpr_reg_fbdv)
return 0;
 }
 
+#if defined(CONFIG_APM821XX)
+
+void get_sys_info(sys_info_t *sysInfo)
+{
+   unsigned long plld;
+   unsigned long temp;
+   unsigned long mul;
+   unsigned long cpudv;
+   unsigned long plb2dv;
+   unsigned long ddr2dv;
+
+   /* Calculate Forward divisor A and Feeback divisor */
+   mfcpr(CPR0_PLLD, plld);
+
+   temp = CPR0_PLLD_FWDVA(plld);
+   sysInfo->pllFwdDivA = get_cpr0_fwdv(temp);
+
+   temp = CPR0_PLLD_FDV(plld);
+   sysInfo->pllFbkDiv = get_cpr0_fbdv(temp);
+
+   /* Calculate OPB clock divisor */
+   mfcpr(CPR0_OPBD, temp);
+   temp = CPR0_OPBD_OPBDV(temp);
+   sysInfo->pllOpbDiv = temp ? temp : 4;
+
+   /* Calculate Peripheral clock divisor */
+   mfcpr(CPR0_PERD, temp);
+   temp = CPR0_PERD_PERDV(temp);
+   sysInfo->pllExtBusDiv = temp ? temp : 4;
+
+   /* Calculate CPU clock divisor */
+   mfcpr(CPR0_CPUD, temp);
+   temp = CPR0_CPUD_CPUDV(temp);
+   cpudv = temp ? temp : 8;
+
+   /* Calculate PLB2 clock divisor */
+   mfcpr(CPR0_PLB2D, temp);
+   temp = CPR0_PLB2D_PLB2DV(temp);
+   plb2dv = temp ? temp : 4;
+
+   /* Calculate DDR2 clock divisor */
+   mfcpr(CPR0_DDR2D, temp);
+   temp = CPR0_DDR2D_

[U-Boot] [PATCH v6 2/2] APM821xx: Add bluestone board support

2010-09-28 Thread tmarri
From: Tirumala Marri 

Add support code for bluestone board wth APM821XX processor based.
This patch includes early board init, misc init, configure EBC,
initializes UIC, MAKEALL, board.cfg and MAINTAINERS file.

Signed-off-by: Tirumala R Marri 
 
inka4x0 MPC5200
 
+Tirumala Marri 
+
+   bluestone   APM821XX
+
 -
 
 Unknown / orphaned boards:
diff --git a/board/amcc/bluestone/Makefile b/board/amcc/bluestone/Makefile
new file mode 100644
index 000..41751c8
--- /dev/null
+++ b/board/amcc/bluestone/Makefile
@@ -0,0 +1,52 @@
+#
+# Copyright (c) 2010, Applied Micro Circuits Corporation
+# Author: Tirumala R Marri 
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).a
+
+COBJS-y:= $(BOARD).o
+SOBJS  := init.o
+
+COBJS   := $(COBJS-y)
+SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS))
+SOBJS  := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):$(OBJS) $(SOBJS)
+   $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+   rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+   rm -f $(LIB) core *.bak $(obj).depend
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/amcc/bluestone/bluestone.c b/board/amcc/bluestone/bluestone.c
new file mode 100644
index 000..fe8929c
--- /dev/null
+++ b/board/amcc/bluestone/bluestone.c
@@ -0,0 +1,111 @@
+/*
+ * Bluestone board support
+ *
+ * Copyright (c) 2010, Applied Micro Circuits Corporation
+ * Author: Tirumala R Marri 
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+int board_early_init_f(void)
+{
+   /*
+* Setup the interrupt controller polarities, triggers, etc.
+*/
+   mtdcr(UIC0SR, 0x);  /* clear all */
+   mtdcr(UIC0ER, 0x);  /* disable all */
+   mtdcr(UIC0CR, 0x0005);  /* ATI & UIC1 crit are critical */
+   mtdcr(UIC0PR, 0x);  /* per ref-board manual */
+   mtdcr(UIC0TR, 0x);  /* per ref-board manual */
+   mtdcr(UIC0VR, 0x);  /* int31 highest, base=0x000 */
+   mtdcr(UIC0SR, 0x);  /* clear all */
+
+   mtdcr(UIC1SR, 0x);  /* clear all */
+   mtdcr(UIC1ER, 0x);  /* disable all */
+   mtdcr(UIC1CR, 0x);  /* all non-critical */
+   mtdcr(UIC1PR, 0x);  /* per ref-board manual */
+   mtdcr(UIC1TR, 0x);  /* per ref-board manual */
+   mtdcr(UIC1VR, 0x);  /* int31 highest, base=0x000 */
+   mtdcr(UIC1SR, 0x);  /* clear all */
+
+   mtdcr(UIC2SR, 0x);  /* clear all */
+   mtdcr(UIC2ER, 0x);  /* disable all */
+   mtdcr(UIC2CR, 0x);  /* all non-critical */
+   mtdcr(UIC2PR, 0x);  /* per ref-board manual */
+   mtdcr(UIC2TR, 0x);  /* per ref-board manual */
+   mtdcr(UIC2VR, 0x);  /* int31 highest, base=0x000 */
+   mtdcr(UIC2SR, 0x);  /* clear all */
+
+   mtdcr(UIC3SR, 0x);  /* clear all */
+   mtdcr(UIC3ER, 0x);  /* disable all */
+   mtdcr(UIC3CR, 0x);  /* all non-criti

Re: [U-Boot] [PATCH V2 1/7] Expand POST memory test to support arch-depended implementation.

2010-09-28 Thread Wolfgang Denk
Dear York Sun,

In message <1285696512.30239.14.ca...@oslab-l1> you wrote:
> On Tue, 2010-09-28 at 19:31 +0200, Wolfgang Denk wrote:
> 
> > > -int memory_post_test (int flags)
> > > +__attribute__((weak))
> > > +int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t 
> > > *phys_offset)
> > 
> > phys_offset is unused here. Drop it?
> > 
> 
> The phys_offset is not used by _this_ weak function but it is used by
> another function implemented in the third patch. Is it OK to leave the
> unused phys_offset here?

What does the compiler say?

Best regards,

Wolfgang Denk

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Re: [U-Boot] [PATCH V2 1/7] Expand POST memory test to support arch-depended implementation.

2010-09-28 Thread Scott Wood
On Tue, 28 Sep 2010 19:31:30 +0200
Wolfgang Denk  wrote:

> > +__attribute__((weak))
> > +int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t 
> > *phys_offset)
> > +{
> > +   return 1;
> > +}
> 
> Unused arguments?
> 
> Don't you get compiler warnings for these?

Such warnings are not part of -Wall, which is a good thing, as
the arguments may be there to satisfy an interface (esp. with function
pointers or conditional compilation) and not because this instance of
the function actually needs them.  This seems to be the case here.

-Scott

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Re: [U-Boot] [PATCH v6 1/2] APM821xx: Add CPU support

2010-09-28 Thread Wolfgang Denk
Dear tma...@apm.com,

In message <1285698750-4943-1-git-send-email-tma...@apm.com> you wrote:
> From: Tirumala Marri 
> 
> APM821XX is a new line of SoCs which are derivatives of
> PPC44X family of processors. This patch adds support of CPU, cache,
> tlb, 32k ocm, bootstraps, PLB and AHB bus.
...
> -#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && 
> !defined(CONFIG_SYS_4xx_GPIO_TABLE)
> +#if !defined(CONFIG_APM821XX) && (defined(CONFIG_405EP) ||\
> + defined (CONFIG_405EX)) && !defined(CONFIG_SYS_4xx_GPIO_TABLE)

Please reorder to avoid breaking the expression in parens, and to
keep the list sorted (in the other places you also sort the 'A' after
the '4', as one would expect), for example:

#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && \\
!defined(CONFIG_APM821XX) && !defined(CONFIG_SYS_4xx_GPIO_TABLE)



Thanks.

Wolfgang Denk

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Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
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Re: [U-Boot] [PATCH v6 2/2] APM821xx: Add bluestone board support

2010-09-28 Thread Wolfgang Denk
Dear tma...@apm.com,

In message <1285698755-4972-1-git-send-email-tma...@apm.com> you wrote:
> From: Tirumala Marri 
> 
> Add support code for bluestone board wth APM821XX processor based.
> This patch includes early board init, misc init, configure EBC,
> initializes UIC, MAKEALL, board.cfg and MAINTAINERS file.
> 
> Signed-off-by: Tirumala R Marri  --- /dev/null
> +++ b/include/configs/bluestone.h
> @@ -0,0 +1,178 @@
> +/*
> + * bluestone.h - configuration for Blouestone (APM821XX)

s/Blouestone/Bluestone/ ?

...
> +#define SPD_EEPROM_ADDRESS   {0x53, 0x51}/* SPD i2c spd addresses */
...
> +#define CONFIG_SYS_I2C_SPEED 40  /* I2C speed*/
> +#define CONFIG_SYS_I2C_MULTI_EEPROMS
> +#define CONFIG_SYS_I2C_EEPROM_ADDR   (0xa8 >> 1)
...
> +#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR0x52

Please replace the "(0xa8 >> 1)" by a plain 0x54 like youdo for the
other I2C addresses as well. No need to make reading more difficult
than necessary.

Thanks.

Best regards,

Wolfgang Denk

-- 
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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Re: [U-Boot] [PATCH V2 1/7] Expand POST memory test to support arch-depended implementation.

2010-09-28 Thread York Sun
On Tue, 2010-09-28 at 20:50 +0200, Wolfgang Denk wrote:
> Dear York Sun,
> 
> In message <1285696512.30239.14.ca...@oslab-l1> you wrote:
> > On Tue, 2010-09-28 at 19:31 +0200, Wolfgang Denk wrote:
> > 
> > > > -int memory_post_test (int flags)
> > > > +__attribute__((weak))
> > > > +int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t 
> > > > *phys_offset)
> > > 
> > > phys_offset is unused here. Drop it?
> > > 
> > 
> > The phys_offset is not used by _this_ weak function but it is used by
> > another function implemented in the third patch. Is it OK to leave the
> > unused phys_offset here?
> 
> What does the compiler say?

I don't have any warning or error.

York



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Re: [U-Boot] [PATCH V2 1/7] Expand POST memory test to support arch-depended implementation.

2010-09-28 Thread Wolfgang Denk
Dear York Sun,

In message <1285701869.30239.16.ca...@oslab-l1> you wrote:
>
> > > The phys_offset is not used by _this_ weak function but it is used by
> > > another function implemented in the third patch. Is it OK to leave the
> > > unused phys_offset here?
> > 
> > What does the compiler say?
> 
> I don't have any warning or error.

Ok, fine. Thanks.

Best regards,

Wolfgang Denk

-- 
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
I am not now, nor have I ever been, a member of the demigodic party.
   -- Dennis Ritchie
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Re: [U-Boot] Please Pull u-boot-ti/master

2010-09-28 Thread Wolfgang Denk
Dear s-paul...@ti.com,

In message <1285697020-10191-1-git-send-email-s-paul...@ti.com> you wrote:
> The following changes since commit 85d3eba90df54bac27844221e2436550984c4d58:
>   Thomas Weber (1):
> ixp/npe: Remove duplicated comment
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-ti.git master
> 
> Aneesh V (1):
>   ARMV7: OMAP4: Calculate SDRAM size
> 
> Steve Sakoman (2):
>   ARMV7: OMAP4: Fix Panda pinmux setting to enable Wifi/BT Module
>   ARMV7: OMAP3: Update Beagle xM pinmux with USB hub and DVI gpio setup
> 
>  arch/arm/cpu/armv7/omap4/board.c|   30 +-
>  arch/arm/include/asm/arch-omap4/omap4.h |   10 ++
>  board/ti/beagle/beagle.h|4 
>  board/ti/panda/panda.h  |   18 +-
>  4 files changed, 52 insertions(+), 10 deletions(-)

Applied, thanks.

Best regards,

Wolfgang Denk

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:   I've tried (in vi) "g/[a-z]\n[a-z]/s//_/"...but that doesn't
: cut it.  Any ideas?  (I take it that it may be a two-pass sort of solution).
In the first pass, install perl. :-) Larry Wall <6...@jpl-devvax.jpl.nasa.gov>
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[U-Boot] [PATCH] mpc512x: fix build issues

2010-09-28 Thread Wolfgang Denk
Commit 800eb0964 "POST cleanup." removed file
arch/powerpc/cpu/mpc512x/common.c but failed to remove the reference
to it from arch/powerpc/cpu/mpc512x/Makefile which causes somewhat
obscure build errors:

make[1]: *** No rule to make target 
`/work/wd/tmp-ppc/arch/powerpc/cpu/mpc512x/.depend', needed by `_depend'.  Stop.

Fix these.

Signed-off-by: Wolfgang Denk 
---
 arch/powerpc/cpu/mpc512x/Makefile |1 -
 1 files changed, 0 insertions(+), 1 deletions(-)

diff --git a/arch/powerpc/cpu/mpc512x/Makefile 
b/arch/powerpc/cpu/mpc512x/Makefile
index 28926e0..ae2f6dc 100644
--- a/arch/powerpc/cpu/mpc512x/Makefile
+++ b/arch/powerpc/cpu/mpc512x/Makefile
@@ -29,7 +29,6 @@ LIB   = $(obj)lib$(CPU).a
 START  = start.o
 COBJS-y:= cpu.o
 COBJS-y+= traps.o
-COBJS-y += common.o
 COBJS-y += cpu_init.o
 COBJS-y += fixed_sdram.o
 COBJS-y += i2c.o
-- 
1.7.2.3

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[U-Boot] [PATCH v7 0/2] Add support for new SoC APM821XX

2010-09-28 Thread tmarri
From: Tirumala Marri 

APM821XX is Applied Micro Circuits Corporations naming
convention for new line of SoCs.

V6:
  * Correcting indentation.
V7:
  * Ordering defined(APM821XX) in cpu_init.c.
  * Correcting Typo Bloustone to Bluestone.

Tirumala Marri (2):
  APM821xx: Add CPU support
  APM821xx: Add bluestone board support

 MAINTAINERS |4 +
 arch/powerpc/cpu/ppc4xx/cpu.c   |   19 
 arch/powerpc/cpu/ppc4xx/cpu_init.c  |5 +-
 arch/powerpc/cpu/ppc4xx/speed.c |   75 +-
 arch/powerpc/cpu/ppc4xx/start.S |   11 ++-
 arch/powerpc/include/asm/apm821xx.h |   72 +
 arch/powerpc/include/asm/ppc4xx-ebc.h   |3 +-
 arch/powerpc/include/asm/ppc4xx-isram.h |   14 ++-
 arch/powerpc/include/asm/ppc4xx-sdram.h |   12 +-
 arch/powerpc/include/asm/ppc4xx-uic.h   |5 +-
 arch/powerpc/include/asm/ppc4xx.h   |4 +
 arch/powerpc/include/asm/processor.h|1 +
 board/amcc/bluestone/Makefile   |   52 +
 board/amcc/bluestone/bluestone.c|  111 +++
 board/amcc/bluestone/config.mk  |   40 +++
 board/amcc/bluestone/init.S |   60 +++
 boards.cfg  |1 +
 include/configs/bluestone.h |  178 +++
 18 files changed, 648 insertions(+), 19 deletions(-)
 create mode 100644 arch/powerpc/include/asm/apm821xx.h
 create mode 100644 board/amcc/bluestone/Makefile
 create mode 100644 board/amcc/bluestone/bluestone.c
 create mode 100644 board/amcc/bluestone/config.mk
 create mode 100644 board/amcc/bluestone/init.S
 create mode 100644 include/configs/bluestone.h

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[U-Boot] [PATCH v7 1/2] APM821xx: Add CPU support

2010-09-28 Thread tmarri
From: Tirumala Marri 

APM821XX is a new line of SoCs which are derivatives of
PPC44X family of processors. This patch adds support of CPU, cache,
tlb, 32k ocm, bootstraps, PLB and AHB bus.

Signed-off-by: Tirumala R Marri 
---
V6:
  * Correcting indentation.
V7:
  * Ordering defined(APM821XX) in cpu_init.c .
---
 arch/powerpc/cpu/ppc4xx/cpu.c   |   19 
 arch/powerpc/cpu/ppc4xx/cpu_init.c  |5 +-
 arch/powerpc/cpu/ppc4xx/speed.c |   75 ++-
 arch/powerpc/cpu/ppc4xx/start.S |   11 +++--
 arch/powerpc/include/asm/apm821xx.h |   72 +
 arch/powerpc/include/asm/ppc4xx-ebc.h   |3 +-
 arch/powerpc/include/asm/ppc4xx-isram.h |   14 +-
 arch/powerpc/include/asm/ppc4xx-sdram.h |   12 +++---
 arch/powerpc/include/asm/ppc4xx-uic.h   |5 +-
 arch/powerpc/include/asm/ppc4xx.h   |4 ++
 arch/powerpc/include/asm/processor.h|1 +
 11 files changed, 202 insertions(+), 19 deletions(-)

diff --git a/arch/powerpc/cpu/ppc4xx/cpu.c b/arch/powerpc/cpu/ppc4xx/cpu.c
index 6009b0c..67f1fff 100644
--- a/arch/powerpc/cpu/ppc4xx/cpu.c
+++ b/arch/powerpc/cpu/ppc4xx/cpu.c
@@ -250,6 +250,20 @@ static char *bootstrap_str[] = {
 };
 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
 #endif
+#if defined(CONFIG_APM821XX)
+#define SDR0_PINSTP_SHIFT   29
+static char *bootstrap_str[] = {
+   "RESERVED",
+   "RESERVED",
+   "RESERVED",
+   "NAND (8 bits)",
+   "NOR  (8 bits)",
+   "NOR  (8 bits) w/PLL Bypassed",
+   "I2C (Addr 0x54)",
+   "I2C (Addr 0x52)",
+};
+static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' };
+#endif
 
 #if defined(SDR0_PINSTP_SHIFT)
 static int bootstrap_option(void)
@@ -590,6 +604,11 @@ int checkcpu (void)
strcpy(addstr, "No Security support");
break;
 
+   case PVR_APM821XX_RA:
+   puts("APM821XX Rev. A");
+   strcpy(addstr, "Security support");
+   break;
+
case PVR_VIRTEX5:
puts("440x5 VIRTEX5");
break;
diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c 
b/arch/powerpc/cpu/ppc4xx/cpu_init.c
index d54b30e..2a727b1 100644
--- a/arch/powerpc/cpu/ppc4xx/cpu_init.c
+++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c
@@ -237,7 +237,8 @@ cpu_init_f (void)
 
reconfigure_pll(CONFIG_SYS_PLL_RECONFIG);
 
-#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && 
!defined(CONFIG_SYS_4xx_GPIO_TABLE)
+#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && \
+!defined(CONFIG_APM821XX) &&!defined(CONFIG_SYS_4xx_GPIO_TABLE)
/*
 * GPIO0 setup (select GPIO or alternate function)
 */
@@ -393,7 +394,7 @@ cpu_init_f (void)
 #if defined(CONFIG_405EX) || \
 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
 defined(CONFIG_460EX) || defined(CONFIG_460GT)  || \
-defined(CONFIG_460SX)
+defined(CONFIG_460SX) || defined(CONFIG_APM821XX)
/*
 * Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read
 */
diff --git a/arch/powerpc/cpu/ppc4xx/speed.c b/arch/powerpc/cpu/ppc4xx/speed.c
index abd4e91..09d6671 100644
--- a/arch/powerpc/cpu/ppc4xx/speed.c
+++ b/arch/powerpc/cpu/ppc4xx/speed.c
@@ -189,7 +189,7 @@ ulong get_PCI_freq (void)
 #elif defined(CONFIG_440)
 
 #if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-defined(CONFIG_460SX)
+defined(CONFIG_460SX) || defined(CONFIG_APM821XX)
 static u8 pll_fwdv_multi_bits[] = {
/* values for:  1 - 16 */
0x00, 0x01, 0x0f, 0x04, 0x09, 0x0a, 0x0d, 0x0e, 0x03, 0x0c,
@@ -250,6 +250,78 @@ u32 get_cpr0_fbdv(unsigned long cpr_reg_fbdv)
return 0;
 }
 
+#if defined(CONFIG_APM821XX)
+
+void get_sys_info(sys_info_t *sysInfo)
+{
+   unsigned long plld;
+   unsigned long temp;
+   unsigned long mul;
+   unsigned long cpudv;
+   unsigned long plb2dv;
+   unsigned long ddr2dv;
+
+   /* Calculate Forward divisor A and Feeback divisor */
+   mfcpr(CPR0_PLLD, plld);
+
+   temp = CPR0_PLLD_FWDVA(plld);
+   sysInfo->pllFwdDivA = get_cpr0_fwdv(temp);
+
+   temp = CPR0_PLLD_FDV(plld);
+   sysInfo->pllFbkDiv = get_cpr0_fbdv(temp);
+
+   /* Calculate OPB clock divisor */
+   mfcpr(CPR0_OPBD, temp);
+   temp = CPR0_OPBD_OPBDV(temp);
+   sysInfo->pllOpbDiv = temp ? temp : 4;
+
+   /* Calculate Peripheral clock divisor */
+   mfcpr(CPR0_PERD, temp);
+   temp = CPR0_PERD_PERDV(temp);
+   sysInfo->pllExtBusDiv = temp ? temp : 4;
+
+   /* Calculate CPU clock divisor */
+   mfcpr(CPR0_CPUD, temp);
+   temp = CPR0_CPUD_CPUDV(temp);
+   cpudv = temp ? temp : 8;
+
+   /* Calculate PLB2 clock divisor */
+   mfcpr(CPR0_PLB2D, temp);
+   temp = CPR0_PLB2D_PLB2DV(temp);
+   plb2dv = temp ? temp : 4;
+
+   /* Calculate DDR2 clock divisor */
+   mfcpr(CPR0_DDR2D, temp);
+   temp = CPR0_DDR2D_DDR2DV(temp);
+

[U-Boot] [PATCH v7 2/2] APM821xx: Add bluestone board support

2010-09-28 Thread tmarri
From: Tirumala Marri 

Add support code for bluestone board wth APM821XX processor based.
This patch includes early board init, misc init, configure EBC,
initializes UIC, MAKEALL, board.cfg and MAINTAINERS file.

Signed-off-by: Tirumala R Marri 
 
inka4x0 MPC5200
 
+Tirumala Marri 
+
+   bluestone   APM821XX
+
 -
 
 Unknown / orphaned boards:
diff --git a/board/amcc/bluestone/Makefile b/board/amcc/bluestone/Makefile
new file mode 100644
index 000..41751c8
--- /dev/null
+++ b/board/amcc/bluestone/Makefile
@@ -0,0 +1,52 @@
+#
+# Copyright (c) 2010, Applied Micro Circuits Corporation
+# Author: Tirumala R Marri 
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).a
+
+COBJS-y:= $(BOARD).o
+SOBJS  := init.o
+
+COBJS   := $(COBJS-y)
+SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS))
+SOBJS  := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):$(OBJS) $(SOBJS)
+   $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+   rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+   rm -f $(LIB) core *.bak $(obj).depend
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/amcc/bluestone/bluestone.c b/board/amcc/bluestone/bluestone.c
new file mode 100644
index 000..fe8929c
--- /dev/null
+++ b/board/amcc/bluestone/bluestone.c
@@ -0,0 +1,111 @@
+/*
+ * Bluestone board support
+ *
+ * Copyright (c) 2010, Applied Micro Circuits Corporation
+ * Author: Tirumala R Marri 
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+int board_early_init_f(void)
+{
+   /*
+* Setup the interrupt controller polarities, triggers, etc.
+*/
+   mtdcr(UIC0SR, 0x);  /* clear all */
+   mtdcr(UIC0ER, 0x);  /* disable all */
+   mtdcr(UIC0CR, 0x0005);  /* ATI & UIC1 crit are critical */
+   mtdcr(UIC0PR, 0x);  /* per ref-board manual */
+   mtdcr(UIC0TR, 0x);  /* per ref-board manual */
+   mtdcr(UIC0VR, 0x);  /* int31 highest, base=0x000 */
+   mtdcr(UIC0SR, 0x);  /* clear all */
+
+   mtdcr(UIC1SR, 0x);  /* clear all */
+   mtdcr(UIC1ER, 0x);  /* disable all */
+   mtdcr(UIC1CR, 0x);  /* all non-critical */
+   mtdcr(UIC1PR, 0x);  /* per ref-board manual */
+   mtdcr(UIC1TR, 0x);  /* per ref-board manual */
+   mtdcr(UIC1VR, 0x);  /* int31 highest, base=0x000 */
+   mtdcr(UIC1SR, 0x);  /* clear all */
+
+   mtdcr(UIC2SR, 0x);  /* clear all */
+   mtdcr(UIC2ER, 0x);  /* disable all */
+   mtdcr(UIC2CR, 0x);  /* all non-critical */
+   mtdcr(UIC2PR, 0x);  /* per ref-board manual */
+   mtdcr(UIC2TR, 0x);  /* per ref-board manual */
+   mtdcr(UIC2VR, 0x);  /* int31 highest, base=0x000 */
+   mtdcr(UIC2SR, 0x);  /* clear all */
+
+   mtdcr(UIC3SR, 0x);  /* clear all */
+   mtdcr(UIC3ER, 0x);  /* disable all */
+   mtdcr(UIC3CR, 0x);  /* all non-criti

Re: [U-Boot] [PATCH v7 1/2] APM821xx: Add CPU support

2010-09-28 Thread Wolfgang Denk
Dear tma...@apm.com,

In message <1285708514-5713-1-git-send-email-tma...@apm.com> you wrote:
> From: Tirumala Marri 
> 
> APM821XX is a new line of SoCs which are derivatives of
> PPC44X family of processors. This patch adds support of CPU, cache,
> tlb, 32k ocm, bootstraps, PLB and AHB bus.
> 
> Signed-off-by: Tirumala R Marri 
> ---
> V6:
>   * Correcting indentation.
> V7:
>   * Ordering defined(APM821XX) in cpu_init.c .
> ---
>  arch/powerpc/cpu/ppc4xx/cpu.c   |   19 
>  arch/powerpc/cpu/ppc4xx/cpu_init.c  |5 +-
>  arch/powerpc/cpu/ppc4xx/speed.c |   75 
> ++-
>  arch/powerpc/cpu/ppc4xx/start.S |   11 +++--
>  arch/powerpc/include/asm/apm821xx.h |   72 +
>  arch/powerpc/include/asm/ppc4xx-ebc.h   |3 +-
>  arch/powerpc/include/asm/ppc4xx-isram.h |   14 +-
>  arch/powerpc/include/asm/ppc4xx-sdram.h |   12 +++---
>  arch/powerpc/include/asm/ppc4xx-uic.h   |5 +-
>  arch/powerpc/include/asm/ppc4xx.h   |4 ++
>  arch/powerpc/include/asm/processor.h|1 +
>  11 files changed, 202 insertions(+), 19 deletions(-)

Reviewed-by: Wolfgang Denk 
Acked-by: Wolfgang Denk 

Best regards,

Wolfgang Denk

-- 
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
Fascinating is a word I use for the unexpected.
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Re: [U-Boot] [PATCH v7 2/2] APM821xx: Add bluestone board support

2010-09-28 Thread Wolfgang Denk
Dear tma...@apm.com,

In message <1285708521-5747-1-git-send-email-tma...@apm.com> you wrote:
> From: Tirumala Marri 
> 
> Add support code for bluestone board wth APM821XX processor based.
> This patch includes early board init, misc init, configure EBC,
> initializes UIC, MAKEALL, board.cfg and MAINTAINERS file.
> 
> Signed-off-by: Tirumala R Marri  ---
> V6:
>   * Correcting indentation.
> V7:
>   * Correcting Typo Bloustone to Bluestone.
> ---
>  MAINTAINERS  |4 +
>  board/amcc/bluestone/Makefile|   52 +++
>  board/amcc/bluestone/bluestone.c |  111 +++
>  board/amcc/bluestone/config.mk   |   40 +
>  board/amcc/bluestone/init.S  |   60 +
>  boards.cfg   |1 +
>  include/configs/bluestone.h  |  178 
> ++
>  7 files changed, 446 insertions(+), 0 deletions(-)

Reviewed-by: Wolfgang Denk 
Acked-by: Wolfgang Denk 


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
No, I'm not going to explain it. If you  can't  figure  it  out,  you
didn't want to know anyway... :-)
   - Larry Wall in <1991aug7.180856.2...@netlabs.com>
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[U-Boot] [Patch v3 4/7] Fix address for POST for 85xx with CPM

2010-09-28 Thread York Sun
The address used for post_word_load and post_word_store is in the dual port
RAM for processors with CPM.

Signed-off-by: York Sun 
---
 arch/powerpc/cpu/mpc85xx/commproc.c |8 
 1 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/commproc.c 
b/arch/powerpc/cpu/mpc85xx/commproc.c
index f0fd1cb..aa75494 100644
--- a/arch/powerpc/cpu/mpc85xx/commproc.c
+++ b/arch/powerpc/cpu/mpc85xx/commproc.c
@@ -188,16 +188,16 @@ m8560_cpm_extcbrg(uint brg, uint rate, uint extclk, int 
pinsel)
 
 void post_word_store (ulong a)
 {
-   volatile ulong *save_addr =
-   (volatile ulong *)(CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR);
+   volatile ulong *save_addr = (volatile ulong *)
+   (CONFIG_SYS_MPC85xx_CPM_ADDR + CPM_POST_WORD_ADDR);
 
*save_addr = a;
 }
 
 ulong post_word_load (void)
 {
-   volatile ulong *save_addr =
-   (volatile ulong *)(CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR);
+   volatile ulong *save_addr = (volatile ulong *)
+   (CONFIG_SYS_MPC85xx_CPM_ADDR + CPM_POST_WORD_ADDR);
 
return *save_addr;
 }
-- 
1.7.0.4


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[U-Boot] [Patch v3 3/7] Add memory test feature for mpc85xx POST.

2010-09-28 Thread York Sun
The memory test is performed after DDR initialization when U-boot stills runs
in flash and cache. On recent mpc85xx platforms, the total memory can be more
than 2GB. To cover whole memory, it needs be mapped 2GB at a time using a
sliding TLB window. After the testing, DDR is remapped with up to 2GB memory
from the lowest address as normal.

If memory test fails, DDR DIMM SPD and DDR controller registers are dumped for
further debugging.

Signed-off-by: York Sun 
---
 arch/powerpc/cpu/mpc85xx/cpu.c |  219 
 doc/README.fsl-ddr |   14 +++
 2 files changed, 233 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 3f80700..fc5d951 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -34,6 +34,9 @@
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -282,3 +285,219 @@ void mpc85xx_reginfo(void)
print_laws();
print_lbc_regs();
 }
+
+#if CONFIG_POST & CONFIG_SYS_POST_MEMORY
+
+/* Board-specific functions defined in each board's ddr.c */
+void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
+   unsigned int ctrl_num);
+void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
+  phys_addr_t *rpn);
+unsigned int
+   setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
+
+static void dump_spd_ddr_reg(void)
+{
+   int i, j, k, m;
+   u8 *p_8;
+   u32 *p_32;
+   ccsr_ddr_t *ddr[CONFIG_NUM_DDR_CONTROLLERS];
+   generic_spd_eeprom_t
+   spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR];
+
+   for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
+   fsl_ddr_get_spd(spd[i], i);
+
+   puts("SPD data of all dimms (zero vaule is omitted)...\n");
+   puts("Byte (hex)  ");
+   k = 1;
+   for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+   for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++)
+   printf("Dimm%d ", k++);
+   }
+   puts("\n");
+   for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) {
+   m = 0;
+   printf("%3d (0x%02x)  ", k, k);
+   for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+   for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
+   p_8 = (u8 *) &spd[i][j];
+   if (p_8[k]) {
+   printf("0x%02x  ", p_8[k]);
+   m++;
+   } else
+   puts("  ");
+   }
+   }
+   if (m)
+   puts("\n");
+   else
+   puts("\r");
+   }
+
+   for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+   switch (i) {
+   case 0:
+   ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
+   break;
+#ifdef CONFIG_SYS_MPC85xx_DDR2_ADDR
+   case 1:
+   ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR;
+   break;
+#endif
+   default:
+   printf("%s unexpected controller number = %u\n",
+   __func__, i);
+   return;
+   }
+   }
+   printf("DDR registers dump for all controllers "
+   "(zero vaule is omitted)...\n");
+   puts("Offset (hex)   ");
+   for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
+   printf(" Base + 0x%04x", (u32)ddr[i] & 0x);
+   puts("\n");
+   for (k = 0; k < sizeof(ccsr_ddr_t)/4; k++) {
+   m = 0;
+   printf("%6d (0x%04x)", k * 4, k * 4);
+   for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+   p_32 = (u32 *) ddr[i];
+   if (p_32[k]) {
+   printf("0x%08x", p_32[k]);
+   m++;
+   } else
+   puts("  ");
+   }
+   if (m)
+   puts("\n");
+   else
+   puts("\r");
+   }
+   puts("\n");
+}
+
+/* invalid the TLBs for DDR and setup new ones to cover p_addr */
+static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset)
+{
+   u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
+   unsigned long epn;
+   u32 tsize, valid, ptr;
+   phys_addr_t rpn = 0;
+   int ddr_esel;
+
+   ptr = vstart;
+
+   while (ptr < (vstart + size)) {
+   ddr_esel = find_tlb_idx((void *)ptr, 1);
+   if (ddr_esel != -1) {
+   read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
+   disable_tlb(ddr_ese

[U-Boot] [Patch v3 2/7] Adding more control to physical address mapping

2010-09-28 Thread York Sun
A worker function setup_ddr_tlbs_phys() is introduced to implement more
control on physical address mapping.

Signed-off-by: York Sun 
---
 arch/powerpc/cpu/mpc85xx/tlb.c |   16 ++--
 1 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c
index f2833a5..e3a71ae 100644
--- a/arch/powerpc/cpu/mpc85xx/tlb.c
+++ b/arch/powerpc/cpu/mpc85xx/tlb.c
@@ -245,7 +245,8 @@ void init_addr_map(void)
 }
 #endif
 
-unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
+unsigned int
+setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
 {
int i;
unsigned int tlb_size;
@@ -275,21 +276,24 @@ unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
 
tlb_size = (camsize - 10) / 2;
 
-   set_tlb(1, ram_tlb_address, ram_tlb_address,
+   set_tlb(1, ram_tlb_address, p_addr,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, ram_tlb_index, tlb_size, 1);
 
size -= 1ULL << camsize;
memsize -= 1ULL << camsize;
ram_tlb_address += 1UL << camsize;
+   p_addr += 1UL << camsize;
}
 
if (memsize)
print_size(memsize, " left unmapped\n");
-
-   /*
-* Confirm that the requested amount of memory was mapped.
-*/
return memsize_in_meg;
 }
+
+unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
+{
+   return
+   setup_ddr_tlbs_phys(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg);
+}
 #endif /* !CONFIG_NAND_SPL */
-- 
1.7.0.4


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[U-Boot] [Patch v3 7/7] Enable POST memory test for P2020DS

2010-09-28 Thread York Sun
Signed-off-by: York Sun 
---
 include/configs/P2020DS.h |5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h
index 79ce2c0..923072a 100644
--- a/include/configs/P2020DS.h
+++ b/include/configs/P2020DS.h
@@ -73,8 +73,9 @@
 #define CONFIG_SYS_NUM_ADDR_MAP16  /* number of TLB1 
entries */
 #endif
 
-#define CONFIG_SYS_MEMTEST_START   0x  /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x7fff
+#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
+#define CONFIG_SYS_MEMTEST_START   0x0020  /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x0040
 #define CONFIG_PANIC_HANG  /* do not reset board on panic */
 
 /*
-- 
1.7.0.4


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[U-Boot] [Patch v3 1/7] Expand POST memory test to support arch-depended implementation.

2010-09-28 Thread York Sun
Add weak functions to enable architecture depended preparation, address
advancing, cleaning up and error handling.

These weak functions provides the framwork to implemente arch/platform
dependent code for initializing/maintenance/restore the start address, size,
physical address as well as memory mapping before/between/after memory test.
arch_memory_failure_handle can also be implemented in case more care is needed
for arch/platform.

Signed-off-by: York Sun 
---
 post/drivers/memory.c |   68 +---
 1 files changed, 52 insertions(+), 16 deletions(-)

diff --git a/post/drivers/memory.c b/post/drivers/memory.c
index 0062360..3f47449 100644
--- a/post/drivers/memory.c
+++ b/post/drivers/memory.c
@@ -452,30 +452,66 @@ static int memory_post_tests (unsigned long start, 
unsigned long size)
return ret;
 }
 
-int memory_post_test (int flags)
+__attribute__((weak))
+int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
 {
-   int ret = 0;
bd_t *bd = gd->bd;
-   unsigned long memsize = (bd->bi_memsize >= 256 << 20 ?
-256 << 20 : bd->bi_memsize) - (1 << 20);
+   *vstart = CONFIG_SYS_SDRAM_BASE;
+   *size = (bd->bi_memsize >= 256 << 20 ?
+   256 << 20 : bd->bi_memsize) - (1 << 20);
 
/* Limit area to be tested with the board info struct */
-   if (CONFIG_SYS_SDRAM_BASE + memsize > (ulong)bd)
-   memsize = (ulong)bd - CONFIG_SYS_SDRAM_BASE;
+   if ((*vstart) + (*size) > (ulong)bd)
+   *size = (ulong)bd - *vstart;
+
+   return 0;
+}
 
-   if (flags & POST_SLOWTEST) {
-   ret = memory_post_tests (CONFIG_SYS_SDRAM_BASE, memsize);
-   } else {/* POST_NORMAL */
+__attribute__((weak))
+int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
+{
+   return 1;
+}
 
-   unsigned long i;
+__attribute__((weak))
+int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
+{
+   return 0;
+}
 
-   for (i = 0; i < (memsize >> 20) && ret == 0; i++) {
-   if (ret == 0)
-   ret = memory_post_tests (i << 20, 0x800);
-   if (ret == 0)
-   ret = memory_post_tests ((i << 20) + 0xff800, 
0x800);
+__attribute__((weak))
+void arch_memory_failure_handle(void)
+{
+   return;
+}
+
+int memory_post_test(int flags)
+{
+   int ret = 0;
+   phys_addr_t phys_offset = 0;
+   u32 memsize, vstart;
+
+   arch_memory_test_prepare(&vstart, &memsize, &phys_offset);
+
+   do {
+   if (flags & POST_SLOWTEST) {
+   ret = memory_post_tests(vstart, memsize);
+   } else {/* POST_NORMAL */
+   unsigned long i;
+   for (i = 0; i < (memsize >> 20) && ret == 0; i++) {
+   if (ret == 0)
+   ret = memory_post_tests(i << 20, 0x800);
+   if (ret == 0)
+   ret = memory_post_tests(
+   (i << 20) + 0xff800, 0x800);
+   }
}
-   }
+   } while (!ret &&
+   !arch_memory_test_advance(&vstart, &memsize, &phys_offset));
+
+   arch_memory_test_cleanup(&vstart, &memsize, &phys_offset);
+   if (ret)
+   arch_memory_failure_handle();
 
return ret;
 }
-- 
1.7.0.4


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[U-Boot] [Patch v3 5/7] Setup POST word for generic mpc85xx

2010-09-28 Thread York Sun
Using PIC TFRR register for post word load/store for generic MPC85xx.

Signed-off-by: York Sun 
---
 arch/powerpc/cpu/mpc85xx/cpu.c |   19 +++
 1 files changed, 19 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index fc5d951..bf3d899 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -286,6 +286,25 @@ void mpc85xx_reginfo(void)
print_lbc_regs();
 }
 
+#ifdef CONFIG_POST
+
+__attribute__((weak))
+void post_word_store(ulong a)
+{
+   void *save_addr = (void *)
+   (CONFIG_SYS_MPC8xxx_PIC_ADDR + offsetof(ccsr_pic_t, tfrr));
+   out_be32(save_addr, a);
+}
+__attribute__((weak))
+ulong post_word_load(void)
+{
+   void *save_addr = (void *)
+   (CONFIG_SYS_MPC8xxx_PIC_ADDR + offsetof(ccsr_pic_t, tfrr));
+   return in_be32(save_addr);
+}
+
+#endif /* CONFIG_POST */
+
 #if CONFIG_POST & CONFIG_SYS_POST_MEMORY
 
 /* Board-specific functions defined in each board's ddr.c */
-- 
1.7.0.4


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[U-Boot] [Patch v3 6/7] Enable POST memory test for corenet_ds

2010-09-28 Thread York Sun
Signed-off-by: York Sun 
---
 include/configs/corenet_ds.h |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index cbe5024..5ce0efd 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -86,6 +86,7 @@
 #define CONFIG_SYS_NUM_ADDR_MAP64  /* number of TLB1 
entries */
 #endif
 
+#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
 #define CONFIG_SYS_MEMTEST_START   0x0020  /* memtest works on */
 #define CONFIG_SYS_MEMTEST_END 0x0040
 #define CONFIG_SYS_ALT_MEMTEST
-- 
1.7.0.4


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[U-Boot] [PATCH 0/7] ARMV7: OMAP: Add new MMC driver, enable saveenv to eMMC

2010-09-28 Thread Steve Sakoman
This patch series implements a number of cleanups for the OMAP MMC support.

The first patch fixes a bug in the generic MMC driver that results in
erroneous capacity calculations for eMMC.

The second patch adds a CONFIG_GENERIC_MMC compatible driver for OMAP3
and OMAP4.  The old legacy OMAP MMC driver is left in place since a number of
boards still use it.  It should be removed when all boards move to the 
new driver.

The third through sixth patches move to the new MMC driver on Panda,
SDP4430, Beagle, and Overo.

The seventh patch enables saveenv to eMMC on the SDP4430.

These patches were tested on the above mentioned boards.  I also ran
MAKEALL ARMV7 with no errors or warnings. 

Steve Sakoman (2):
  ARMV7: OMAP4: Use generic mmc driver on Beagle
  ARMV7: OMAP4: Use generic mmc driver on Overo

Sukumar Ghorai (5):
  MMC: Fix for capacity calculation on eMMC
  ARMV7: OMAP: Add new mmc driver compatible with CONFIG_GENERIC_MMC
  ARMV7: OMAP4: Use generic mmc driver on Panda
  ARMV7: OMAP4: Use generic mmc driver on SDP4430
  ARMV7: OMAP4: Enable saveenv to eMMC for SDP4430

 arch/arm/include/asm/arch-omap3/mmc_host_def.h |   10 +
 arch/arm/include/asm/arch-omap4/mmc_host_def.h |   10 +
 board/overo/overo.c|9 +
 board/ti/beagle/beagle.c   |9 +
 board/ti/panda/panda.c |9 +
 board/ti/sdp4430/sdp.c |   10 +
 drivers/mmc/Makefile   |1 +
 drivers/mmc/mmc.c  |   11 +
 drivers/mmc/omap_hsmmc.c   |  415 
 include/configs/omap3_beagle.h |   10 +-
 include/configs/omap3_overo.h  |   10 +-
 include/configs/omap4_panda.h  |9 +-
 include/configs/omap4_sdp4430.h|   21 +-
 13 files changed, 512 insertions(+), 22 deletions(-)
 create mode 100644 drivers/mmc/omap_hsmmc.c

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[U-Boot] [PATCH 2/7] ARMV7: OMAP: Add new mmc driver compatible with CONFIG_GENERIC_MMC

2010-09-28 Thread Steve Sakoman
From: Sukumar Ghorai 

OMAP boards currently use a legacy mmc driver. This patch adds a new
mmc driver which will work with the generic mmc driver in u-boot.

This new driver will work with both OMAP3 and OMAP4 boards.

This patch does not remove the old driver.  It should remain in the
tree until all boards that use it switch to the new driver.

Signed-off-by: Sukumar Ghorai 
Tested-by: Steve Sakoman 
---
 arch/arm/include/asm/arch-omap3/mmc_host_def.h |   10 +
 arch/arm/include/asm/arch-omap4/mmc_host_def.h |   10 +
 drivers/mmc/Makefile   |1 +
 drivers/mmc/omap_hsmmc.c   |  415 
 4 files changed, 436 insertions(+), 0 deletions(-)
 create mode 100644 drivers/mmc/omap_hsmmc.c

diff --git a/arch/arm/include/asm/arch-omap3/mmc_host_def.h 
b/arch/arm/include/asm/arch-omap3/mmc_host_def.h
index 43dd705..ba1c2ff 100644
--- a/arch/arm/include/asm/arch-omap3/mmc_host_def.h
+++ b/arch/arm/include/asm/arch-omap3/mmc_host_def.h
@@ -102,12 +102,14 @@ typedef struct hsmmc {
 #define NBLK_STPCNT(0x0 << 16)
 #define DE_DISABLE (0x0 << 0)
 #define BCE_DISABLE(0x0 << 1)
+#define BCE_ENABLE (0x1 << 1)
 #define ACEN_DISABLE   (0x0 << 2)
 #define DDIR_OFFSET(4)
 #define DDIR_MASK  (0x1 << 4)
 #define DDIR_WRITE (0x0 << 4)
 #define DDIR_READ  (0x1 << 4)
 #define MSBS_SGLEBLK   (0x0 << 5)
+#define MSBS_MULTIBLK  (0x1 << 5)
 #define RSP_TYPE_OFFSET(16)
 #define RSP_TYPE_MASK  (0x3 << 16)
 #define RSP_TYPE_NORSP (0x0 << 16)
@@ -130,6 +132,7 @@ typedef struct hsmmc {
 #define DATI_CMDDIS(0x1 << 1)
 #define DTW_1_BITMODE  (0x0 << 1)
 #define DTW_4_BITMODE  (0x1 << 1)
+#define DTW_8_BITMODE   (0x1 << 5) /* CON[DW8]*/
 #define SDBP_PWROFF(0x0 << 8)
 #define SDBP_PWRON (0x1 << 8)
 #define SDVS_1V8   (0x5 << 9)
@@ -186,8 +189,15 @@ typedef struct {
unsigned int size;
unsigned int RCA;
 } mmc_card_data;
+#define RSP_TYPE_NONE  (RSP_TYPE_NORSP   | CCCE_NOCHECK | CICE_NOCHECK)
+#define MMC_CMD0   (INDEX(0)  | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
+
+/* Clock Configurations and Macros */
+#define MMC_CLOCK_REFERENCE96 /* MHz */
 
 #define mmc_reg_out(addr, mask, val)\
writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
 
+int omap_mmc_init(int dev_index);
+
 #endif /* MMC_HOST_DEF_H */
diff --git a/arch/arm/include/asm/arch-omap4/mmc_host_def.h 
b/arch/arm/include/asm/arch-omap4/mmc_host_def.h
index e5d8b53..733d8ed 100644
--- a/arch/arm/include/asm/arch-omap4/mmc_host_def.h
+++ b/arch/arm/include/asm/arch-omap4/mmc_host_def.h
@@ -80,12 +80,14 @@ typedef struct hsmmc {
 #define NBLK_STPCNT(0x0 << 16)
 #define DE_DISABLE (0x0 << 0)
 #define BCE_DISABLE(0x0 << 1)
+#define BCE_ENABLE (0x1 << 1)
 #define ACEN_DISABLE   (0x0 << 2)
 #define DDIR_OFFSET(4)
 #define DDIR_MASK  (0x1 << 4)
 #define DDIR_WRITE (0x0 << 4)
 #define DDIR_READ  (0x1 << 4)
 #define MSBS_SGLEBLK   (0x0 << 5)
+#define MSBS_MULTIBLK  (0x1 << 5)
 #define RSP_TYPE_OFFSET(16)
 #define RSP_TYPE_MASK  (0x3 << 16)
 #define RSP_TYPE_NORSP (0x0 << 16)
@@ -108,6 +110,7 @@ typedef struct hsmmc {
 #define DATI_CMDDIS(0x1 << 1)
 #define DTW_1_BITMODE  (0x0 << 1)
 #define DTW_4_BITMODE  (0x1 << 1)
+#define DTW_8_BITMODE   (0x1 << 5) /* CON[DW8]*/
 #define SDBP_PWROFF(0x0 << 8)
 #define SDBP_PWRON (0x1 << 8)
 #define SDVS_1V8   (0x5 << 9)
@@ -164,8 +167,15 @@ typedef struct {
unsigned int size;
unsigned int RCA;
 } mmc_card_data;
+#define RSP_TYPE_NONE  (RSP_TYPE_NORSP   | CCCE_NOCHECK | CICE_NOCHECK)
+#define MMC_CMD0   (INDEX(0)  | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
+
+/* Clock Configurations and Macros */
+#define MMC_CLOCK_REFERENCE96 /* MHz */
 
 #define mmc_reg_out(addr, mask, val)\
writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
 
+int omap_mmc_init(int dev_index);
+
 #endif /* MMC_HOST_DEF_H */
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 6603d74..2ead634 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -32,6 +32,7 @@ COBJS-$(CONFIG_GENERIC_MMC) += mmc.o
 COBJS-$(CONFIG_GENERIC_ATMEL_MCI) += gen_atmel_mci.o
 COBJS-$(CONFIG_MXC_MMC) += mxcmmc.o
 COBJS-$(CONFIG_OMAP3_MMC) += omap3_mmc.o
+COBJS-$(CONFIG_OMAP_HSMMC) +

[U-Boot] [PATCH 1/7] MMC: Fix for capacity calculation on eMMC

2010-09-28 Thread Steve Sakoman
From: Sukumar Ghorai 

  The current mmc driver returns erroneous capacity information for
  eMMC.  The capacity of eMMC devices is available only in the ext-CSD
  register.  This patch add code to read the ext-CDSD register and
  correctly calculate eMMC capacity.

Signed-off-by: Sukumar Ghorai 
Acked-by: Steve Sakoman 
---
 drivers/mmc/mmc.c |   11 +++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 80cd9bf..c543d83 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -627,6 +627,7 @@ int mmc_startup(struct mmc *mmc)
uint mult, freq;
u64 cmult, csize;
struct mmc_cmd cmd;
+   char ext_csd[512];
 
/* Put the Card in Identify Mode */
cmd.cmdidx = MMC_CMD_ALL_SEND_CID;
@@ -742,6 +743,16 @@ int mmc_startup(struct mmc *mmc)
if (err)
return err;
 
+   if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) {
+   /* check  ext_csd version and capacity */
+   err = mmc_send_ext_csd(mmc, ext_csd);
+   if (!err & (ext_csd[192] >= 2)) {
+   mmc->capacity = ext_csd[212] << 0 | ext_csd[213] << 8 |
+   ext_csd[214] << 16 | ext_csd[215] << 24;
+   mmc->capacity *= 512;
+   }
+   }
+
if (IS_SD(mmc))
err = sd_change_freq(mmc);
else
-- 
1.7.0.4

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[U-Boot] [PATCH 3/7] ARMV7: OMAP4: Use generic mmc driver on Panda

2010-09-28 Thread Steve Sakoman
From: Sukumar Ghorai 

This patch switches from the legacy mmc driver to the new generic mmc driver

Signed-off-by: Sukumar Ghorai 
Tested-by: Steve Sakoman 
---
 board/ti/panda/panda.c|9 +
 include/configs/omap4_panda.h |9 -
 2 files changed, 13 insertions(+), 5 deletions(-)

diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c
index 1b8153b..78e1910 100644
--- a/board/ti/panda/panda.c
+++ b/board/ti/panda/panda.c
@@ -23,6 +23,7 @@
  */
 #include 
 #include 
+#include 
 
 #include "panda.h"
 
@@ -87,3 +88,11 @@ void set_muxconf_regs(void)
   sizeof(wkup_padconf_array) /
   sizeof(struct pad_conf_entry));
 }
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+   omap_mmc_init(0);
+   return 0;
+}
+#endif
diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h
index d4a1d1c..2618f7d 100644
--- a/include/configs/omap4_panda.h
+++ b/include/configs/omap4_panda.h
@@ -89,7 +89,6 @@
 #define CONFIG_SYS_NS16550_COM3UART3_BASE
 
 #define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_OVERWRITE
 #define CONFIG_BAUDRATE115200
 #define CONFIG_SYS_BAUDRATE_TABLE  {4800, 9600, 19200, 38400, 57600,\
115200}
@@ -107,8 +106,9 @@
 #define CONFIG_TWL6030_POWER   1
 
 /* MMC */
+#define CONFIG_GENERIC_MMC 1
 #define CONFIG_MMC 1
-#define CONFIG_OMAP3_MMC   1
+#define CONFIG_OMAP_HSMMC  1
 #define CONFIG_SYS_MMC_SET_DEV 1
 #define CONFIG_DOS_PARTITION   1
 
@@ -150,7 +150,6 @@
 
 #define CONFIG_BOOTDELAY   3
 
-/* allow overwriting serial config and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
@@ -158,7 +157,7 @@
"console=ttyS2,115200n8\0" \
"usbtty=cdc_acm\0" \
"vram=16M\0" \
-   "mmcdev=1\0" \
+   "mmcdev=0\0" \
"mmcroot=/dev/mmcblk0p2 rw\0" \
"mmcrootfstype=ext3 rootwait\0" \
"mmcargs=setenv bootargs console=${console} " \
@@ -174,7 +173,7 @@
"bootm ${loadaddr}\0" \
 
 #define CONFIG_BOOTCOMMAND \
-   "if mmc init ${mmcdev}; then " \
+   "if mmc rescan ${mmcdev}; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
-- 
1.7.0.4

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[U-Boot] [PATCH 4/7] ARMV7: OMAP4: Use generic mmc driver on SDP4430

2010-09-28 Thread Steve Sakoman
From: Sukumar Ghorai 

This patch switches from the legacy mmc driver to the new generic mmc driver

Signed-off-by: Sukumar Ghorai 
Tested-by: Steve Sakoman 
---
 board/ti/sdp4430/sdp.c  |   10 ++
 include/configs/omap4_sdp4430.h |   10 +-
 2 files changed, 15 insertions(+), 5 deletions(-)

diff --git a/board/ti/sdp4430/sdp.c b/board/ti/sdp4430/sdp.c
index 7039bd5..01d5ce4 100644
--- a/board/ti/sdp4430/sdp.c
+++ b/board/ti/sdp4430/sdp.c
@@ -24,6 +24,7 @@
  */
 #include 
 #include 
+#include 
 
 #include "sdp.h"
 
@@ -88,3 +89,12 @@ void set_muxconf_regs(void)
   sizeof(wkup_padconf_array) /
   sizeof(struct pad_conf_entry));
 }
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+   omap_mmc_init(0);
+   omap_mmc_init(1);
+   return 0;
+}
+#endif
diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h
index 98a86c3..1241b1e 100644
--- a/include/configs/omap4_sdp4430.h
+++ b/include/configs/omap4_sdp4430.h
@@ -90,7 +90,7 @@
 #define CONFIG_SYS_NS16550_COM3UART3_BASE
 
 #define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_OVERWRITE
+
 #define CONFIG_BAUDRATE115200
 #define CONFIG_SYS_BAUDRATE_TABLE  {4800, 9600, 19200, 38400, 57600,\
115200}
@@ -108,8 +108,9 @@
 #define CONFIG_TWL6030_POWER   1
 
 /* MMC */
+#define CONFIG_GENERIC_MMC 1
 #define CONFIG_MMC 1
-#define CONFIG_OMAP3_MMC   1
+#define CONFIG_OMAP_HSMMC  1
 #define CONFIG_SYS_MMC_SET_DEV 1
 #define CONFIG_DOS_PARTITION   1
 
@@ -151,7 +152,6 @@
 
 #define CONFIG_BOOTDELAY   3
 
-/* allow overwriting serial config and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
@@ -159,7 +159,7 @@
"console=ttyS2,115200n8\0" \
"usbtty=cdc_acm\0" \
"vram=16M\0" \
-   "mmcdev=1\0" \
+   "mmcdev=0\0" \
"mmcroot=/dev/mmcblk0p2 rw\0" \
"mmcrootfstype=ext3 rootwait\0" \
"mmcargs=setenv bootargs console=${console} " \
@@ -175,7 +175,7 @@
"bootm ${loadaddr}\0" \
 
 #define CONFIG_BOOTCOMMAND \
-   "if mmc init ${mmcdev}; then " \
+   "if mmc rescan ${mmcdev}; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
-- 
1.7.0.4

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[U-Boot] [PATCH 5/7] ARMV7: OMAP4: Use generic mmc driver on Beagle

2010-09-28 Thread Steve Sakoman
This patch switches from the legacy mmc driver to the new generic mmc driver

Signed-off-by: Steve Sakoman 
---
 board/ti/beagle/beagle.c   |9 +
 include/configs/omap3_beagle.h |   10 ++
 2 files changed, 15 insertions(+), 4 deletions(-)

diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
index 4647908..c5d6679 100644
--- a/board/ti/beagle/beagle.c
+++ b/board/ti/beagle/beagle.c
@@ -32,6 +32,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -169,3 +170,11 @@ void set_muxconf_regs(void)
 {
MUX_BEAGLE();
 }
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+   omap_mmc_init(0);
+   return 0;
+}
+#endif
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index fbe96aa..3161a6e 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -95,8 +95,9 @@
 #define CONFIG_BAUDRATE115200
 #define CONFIG_SYS_BAUDRATE_TABLE  {4800, 9600, 19200, 38400, 57600,\
115200}
+#define CONFIG_GENERIC_MMC 1
 #define CONFIG_MMC 1
-#define CONFIG_OMAP3_MMC   1
+#define CONFIG_OMAP_HSMMC  1
 #define CONFIG_DOS_PARTITION   1
 
 /* DDR - I use Micron DDR */
@@ -183,6 +184,7 @@
"vram=12M\0" \
"dvimode=1024x768mr...@60\0" \
"defaultdisplay=dvi\0" \
+   "mmcdev=0\0" \
"mmcroot=/dev/mmcblk0p2 rw\0" \
"mmcrootfstype=ext3 rootwait\0" \
"nandroot=/dev/mtdblock4 rw\0" \
@@ -203,10 +205,10 @@
"omapdss.def_disp=${defaultdisplay} " \
"root=${nandroot} " \
"rootfstype=${nandrootfstype}\0" \
-   "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
+   "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"source ${loadaddr}\0" \
-   "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
+   "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
"bootm ${loadaddr}\0" \
@@ -216,7 +218,7 @@
"bootm ${loadaddr}\0" \
 
 #define CONFIG_BOOTCOMMAND \
-   "if mmc init; then " \
+   "if mmc rescan ${mmcdev}; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
-- 
1.7.0.4

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[U-Boot] [PATCH 6/7] ARMV7: OMAP4: Use generic mmc driver on Overo

2010-09-28 Thread Steve Sakoman
This patch switches from the legacy mmc driver to the new generic mmc driver

Signed-off-by: Steve Sakoman 
---
 board/overo/overo.c   |9 +
 include/configs/omap3_overo.h |   10 ++
 2 files changed, 15 insertions(+), 4 deletions(-)

diff --git a/board/overo/overo.c b/board/overo/overo.c
index 1b67f1f..9c92693 100644
--- a/board/overo/overo.c
+++ b/board/overo/overo.c
@@ -32,6 +32,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -225,3 +226,11 @@ int board_eth_init(bd_t *bis)
 #endif
return rc;
 }
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+   omap_mmc_init(0);
+   return 0;
+}
+#endif
diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
index a0e0f24..0d2ed44 100644
--- a/include/configs/omap3_overo.h
+++ b/include/configs/omap3_overo.h
@@ -87,8 +87,9 @@
 #define CONFIG_BAUDRATE115200
 #define CONFIG_SYS_BAUDRATE_TABLE  {4800, 9600, 19200, 38400, 57600, \
115200}
+#define CONFIG_GENERIC_MMC 1
 #define CONFIG_MMC 1
-#define CONFIG_OMAP3_MMC   1
+#define CONFIG_OMAP_HSMMC  1
 #define CONFIG_DOS_PARTITION   1
 
 /* DDR - I use Micron DDR */
@@ -158,6 +159,7 @@
"vram=12M\0" \
"dvimode=1024x768mr...@60\0" \
"defaultdisplay=dvi\0" \
+   "mmcdev=0\0" \
"mmcroot=/dev/mmcblk0p2 rw\0" \
"mmcrootfstype=ext3 rootwait\0" \
"nandroot=/dev/mtdblock4 rw\0" \
@@ -178,10 +180,10 @@
"omapdss.def_disp=${defaultdisplay} " \
"root=${nandroot} " \
"rootfstype=${nandrootfstype}\0" \
-   "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
+   "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"source ${loadaddr}\0" \
-   "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
+   "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
"bootm ${loadaddr}\0" \
@@ -191,7 +193,7 @@
"bootm ${loadaddr}\0" \
 
 #define CONFIG_BOOTCOMMAND \
-   "if mmc init; then " \
+   "if mmc rescan ${mmcdev}; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
-- 
1.7.0.4

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[U-Boot] [PATCH 7/7] ARMV7: OMAP4: Enable saveenv to eMMC for SDP4430

2010-09-28 Thread Steve Sakoman
From: Sukumar Ghorai 

The SDP4430 does not have onboard NAND, it has eMMC on the second
MMC slot.  This patch adds support for saving the u-boot environment
to eMMC.

Signed-off-by: Aneesh V 
Signed-off-by: Sukumar Ghorai 
Tested-by: Steve Sakoman 
---
 include/configs/omap4_sdp4430.h |   13 -
 1 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h
index 1241b1e..8274577 100644
--- a/include/configs/omap4_sdp4430.h
+++ b/include/configs/omap4_sdp4430.h
@@ -63,10 +63,10 @@
 
 /*
  * Size of malloc() pool
- * Total Size Environment - 256k
+ * Total Size Environment - 128k
  * Malloc - add 256k
  */
-#define CONFIG_ENV_SIZE(256 << 10)
+#define CONFIG_ENV_SIZE(128 << 10)
 #define CONFIG_SYS_MALLOC_LEN  (CONFIG_ENV_SIZE + (256 << 10))
 #define CONFIG_SYS_GBL_DATA_SIZE   128 /* bytes reserved for */
/* initial data */
@@ -89,12 +89,9 @@
 #define CONFIG_CONS_INDEX  3
 #define CONFIG_SYS_NS16550_COM3UART3_BASE
 
-#define CONFIG_ENV_IS_NOWHERE
-
 #define CONFIG_BAUDRATE115200
 #define CONFIG_SYS_BAUDRATE_TABLE  {4800, 9600, 19200, 38400, 57600,\
115200}
-
 /* I2C  */
 #define CONFIG_HARD_I2C1
 #define CONFIG_SYS_I2C_SPEED   10
@@ -114,6 +111,11 @@
 #define CONFIG_SYS_MMC_SET_DEV 1
 #define CONFIG_DOS_PARTITION   1
 
+/* MMC ENV related defines */
+#define CONFIG_ENV_IS_IN_MMC   1
+#define CONFIG_SYS_MMC_ENV_DEV 1   /* SLOT2: eMMC(1) */
+#define CONFIG_ENV_OFFSET  0xE
+
 /* USB */
 #define CONFIG_MUSB_UDC1
 #define CONFIG_USB_OMAP3   1
@@ -134,6 +136,7 @@
 #define CONFIG_CMD_FAT /* FAT support  */
 #define CONFIG_CMD_I2C /* I2C serial bus support   */
 #define CONFIG_CMD_MMC /* MMC support  */
+#define CONFIG_CMD_SAVEENV
 
 /* Disabled commands */
 #undef CONFIG_CMD_NET
-- 
1.7.0.4

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Re: [U-Boot] [RFC] [PATCH 0/4] Add support for Freescale's 85xx and P1/P2xxx eSPI controller

2010-09-28 Thread Can Aydin



On 28/09/2010 11:22 PM, Reinhard Meyer wrote:

Dear Wolfgang Denk, Can Aydin,

True, a GPIO pin could be re-purposed to serve as chip select, but that
would involve a soldering iron and a steady hand as the P1/P2xxRDB

That was not the question.

Reinhard asked if the SPI Chip Select Pins could be configured such so
that they can be used in GPIO mode instead of special function mode.
That would make code way simpler.

Exactly. Just have this pin work as GPIO, while the rest stays special
function. But then, some SoCs can not individually assign pins to special
functions but can only do that in groups. Maybe that's the issue here.
Yes, I realized that was the actual question after I sent the reply. 
Unfortunately GPIO is not an option for the SPI pins on these particular 
SoCs.

They can only be used either as SPI or as extra data pins for the SDHC.

And then: currently an "sf write" is not restricted in the length of data
written. It would be limited due to the malloc needed for the patch.

Reinhard



--

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Software Engineer
Locata Corporation
can.ay...@locatacorp.com

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Level 1, 111 Canberra Ave
Griffith ACT 2603 Australia
Phone +612 6126 5734
Fax +612 6126 5704

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Re: [U-Boot] [RFC] [PATCH 0/4] Add support for Freescale's 85xx and P1/P2xxx eSPI controller

2010-09-28 Thread Can Aydin
  Dear Wolfgang,

On 28/09/2010 10:46 PM, Wolfgang Denk wrote:
>
>
>> People could also choose to bitbang the SPI on their custom hardware but
>> again I feel that might defeat the purpose and spirit of u-boot. (Then
>> again, I'm new so don't quote me on that).
> Oops?  Where exactly do you see conflicts with "the purpose and
> spirit" of U-Boot?
I was mostly referring to u-boot's aim of being a universal boot loader. 
As an analogy to the Linux kernel, when attempting to support multiple 
architectures and platforms, there is often the inevitable case where 
unfortunate hardware quirks have to be handled by some sort of framework 
for dealing with special cases in the driver model.

As the SPI pins cannot be driven as GPIO, anyone who wants to use this 
particular feature will necessarily have to implement their own 
workarounds in the current u-boot code.

Would a better starting point be to just submit the driver(which works 
fine standalone with cmd_spi) and leave the discussions regarding 
spi_flash common code for further debate?

Can
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Re: [U-Boot] [PATCH v4 2/2] TI: DaVinci DA850 EVM: support passing maximum allowed cpu clock rate information to kernel

2010-09-28 Thread Nori, Sekhar
Hi Ben,

On Tue, Sep 28, 2010 at 19:31:02, Ben Gardiner wrote:
> On Fri, Sep 24, 2010 at 1:10 AM, Nori, Sekhar  wrote:
> > Hello All,
> >
> > On Fri, Aug 27, 2010 at 10:44:58, Nori, Sekhar wrote:
> >> The TI DA850/OMAP-L138/AM18x EVM can be populated with devices
> >> having different maximum allowed CPU clock rating.
> >>
> >> The maximum clock the chip can support can only be determined from
> >> the label on the package (not software readable).
> >>
> >> Introduce a method to pass the maximum allowed clock rate information
> >> to kernel using ATAG_REVISION. The kernel uses this information to
> >> determine the maximum cpu clock rate reachable using cpufreq.
> >>
> >> Note that U-Boot itself does not set the CPU clock rate. The CPU
> >> clock is setup by a primary bootloader ("UBL"). The rate setup by
> >> UBL could be different from the maximum clock rate supported by the
> >> device.
> >
> > Any more feedback on this patch? There are couple of kernel patches
> > which depend on this, that's why I ask.
>
> FWIW: it's fine with me.
>
> Applies cleanly to 3df61957938586c512c17e72d83551d190400981 of u-boot/next.
>
> Tested on da850evm -- bootm of linux uImage works with the patch
> 'da850evm: fix linux bootparam address' aplied.
>
> The kernel uImage used did not have support for parsing the
> ATAG_REVISION information since that patch has not been posted to the
> davinci-linux list.
>
> Tested-by: Ben Gardiner 

Thanks for the testing!

Regards,
Sekhar

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Re: [U-Boot] [PATCH V3 2/2] [NEXT] arm926ejs: reduce code size with -msingle-pic-base

2010-09-28 Thread Albert ARIBAUD
Le 28/09/2010 15:39, Ben Gardiner a écrit :
> On Tue, Sep 28, 2010 at 9:14 AM, Albert Aribaud  
> wrote:
>> Add -msingle-pic-base to the relocation flags, and compute the pic base
>> in start.S twice and for all -- once before relocation to run board_init_f,
>> and once after relocation to run board_init_r and the rest of u-boot.
>> This further reduces code size by 2.5% compared to -fPIE alone.
>>
>> Signed-off-by: Albert Aribaud
>
> Applies cleanly to 3df61957938586c512c17e72d83551d190400981 of u-boot/next.
>
> Tested on da850evm -- u-boot prompt is obtained and bootm of linux
> uImage is possible with the fix for bootparam address on the da850evm.
>
> Tested-by: Ben Gardiner

Thanks Ben.

Amicalement,
-- 
Albert.
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Re: [U-Boot] [PATCH V3 2/2] [NEXT] arm926ejs: reduce code size with -msingle-pic-base

2010-09-28 Thread Albert ARIBAUD
Le 28/09/2010 15:57, Heiko Schocher a écrit :
> Hello Albert,
>
> Albert Aribaud wrote:
>> Add -msingle-pic-base to the relocation flags, and compute the pic base
>> in start.S twice and for all -- once before relocation to run board_init_f,
>> and once after relocation to run board_init_r and the rest of u-boot.
>> This further reduces code size by 2.5% compared to -fPIE alone.
>>
>> Signed-off-by: Albert Aribaud
>
> Tested on the tx25 board.
>
> Tested-by: Heiko Schocher

Thanks Heiko.

BTW, I forgot to mention that patch 2/2 of this set, being partly 
written by Heiko for the tx25 part, is

Signed-off-by: Heiko Schocher

> bye,
> Heiko

Amicalement,
-- 
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Re: [U-Boot] [PATCH V3 2/2] [NEXT] arm926ejs: reduce code size with -msingle-pic-base

2010-09-28 Thread Wolfgang Denk
Dear Albert ARIBAUD,

In message <4ca2d6d0.1080...@free.fr> you wrote:
>
> > Tested-by: Heiko Schocher
> 
> Thanks Heiko.
> 
> BTW, I forgot to mention that patch 2/2 of this set, being partly =
> 
> written by Heiko for the tx25 part, is
> 
> Signed-off-by: Heiko Schocher

Do you expect any further work on this, or should we apply this to the
public repo now?

Best regards,

Wolfgang Denk

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