Re: [Mesa-dev] [PATCH 5/5] i965/vec4_nir: Properly handle integer multiplies on BDW+
On Monday, August 03, 2015 05:22:14 PM Jason Ekstrand wrote:
> ---
> src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 52
> --
> 1 file changed, 28 insertions(+), 24 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> index 1b7fb5e..7251ca0 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> @@ -775,31 +775,35 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
>break;
>
> case nir_op_imul: {
> - nir_const_value *value0 = nir_src_as_const_value(instr->src[0].src);
> - nir_const_value *value1 = nir_src_as_const_value(instr->src[1].src);
> -
> - /* For integer multiplication, the MUL uses the low 16 bits of one of
> - * the operands (src0 through SNB, src1 on IVB and later). The MACH
> - * accumulates in the contribution of the upper 16 bits of that
> - * operand. If we can determine that one of the args is in the low
> - * 16 bits, though, we can just emit a single MUL.
> - */
> - if (value0 && value0->u[0] < (1 << 16)) {
> - if (devinfo->gen < 7)
> -emit(MUL(dst, op[0], op[1]));
> - else
> -emit(MUL(dst, op[1], op[0]));
> - } else if (value1 && value1->u[0] < (1 << 16)) {
> - if (devinfo->gen < 7)
> -emit(MUL(dst, op[1], op[0]));
> - else
> -emit(MUL(dst, op[0], op[1]));
> - } else {
> - struct brw_reg acc = retype(brw_acc_reg(8), dst.type);
> + if (devinfo->gen < 8) {
> + nir_const_value *value0 = nir_src_as_const_value(instr->src[0].src);
> + nir_const_value *value1 = nir_src_as_const_value(instr->src[1].src);
> +
> + /* For integer multiplication, the MUL uses the low 16 bits of one
> of
> + * the operands (src0 through SNB, src1 on IVB and later). The MACH
> + * accumulates in the contribution of the upper 16 bits of that
> + * operand. If we can determine that one of the args is in the low
> + * 16 bits, though, we can just emit a single MUL.
> + */
> + if (value0 && value0->u[0] < (1 << 16)) {
> +if (devinfo->gen < 7)
> + emit(MUL(dst, op[0], op[1]));
> +else
> + emit(MUL(dst, op[1], op[0]));
> + } else if (value1 && value1->u[0] < (1 << 16)) {
> +if (devinfo->gen < 7)
> + emit(MUL(dst, op[1], op[0]));
> +else
> + emit(MUL(dst, op[0], op[1]));
> + } else {
> +struct brw_reg acc = retype(brw_acc_reg(8), dst.type);
>
> - emit(MUL(acc, op[0], op[1]));
> - emit(MACH(dst_null_d(), op[0], op[1]));
> - emit(MOV(dst, src_reg(acc)));
> +emit(MUL(acc, op[0], op[1]));
> +emit(MACH(dst_null_d(), op[0], op[1]));
> +emit(MOV(dst, src_reg(acc)));
> + }
> + } else {
> + emit(MUL(dst, op[0], op[1]));
Cherryview can't do D * D or UD * UD multiplication; you need MACH.
I doubt this will work there...
--Ken
>}
>break;
> }
>
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Re: [Mesa-dev] [PATCH 1/2] i965: Add SKL support to brw_miptree_get_horizontal_slice_pitch().
Jason Ekstrand writes:
> On Sat, Aug 8, 2015 at 2:58 AM, Francisco Jerez wrote:
>> Jason Ekstrand writes:
>>
>>> I'm not a huge fan of this patch. Really, given how complicated 3-D
>>> textures are on SKL, there really is no sensible horizontal slice
>>> pitch. We could return 0 as an "invalid value" but I think I'd rather
>>> keep it an assert. Code that is dealing with 3-D textures should no
>>> better than to just blindly call this function on SKL.
>>> --Jason
>>
>> How so? The sub-tile structure may indeed be more complicated on SKL,
>> but the way how Z-slices of whole tiles are laid out in 2D memory for 3D
>> textures is even simpler than on earlier generations -- Say a given
>> tile-slice of LOD l starts at 2D coordinates (x, y), the next tile-slice
>> will start at (x, y + qpitch), IOW the horizontal offset between
>> tile-slices is zero which is what this patch does. We could probably
>> keep the assertion I had but that would complicate
>> update_texture_image_param() a bit more so I'd rather do what AFAIUI is
>> the right thing here.
>
> Doing a little spelunking, it appears as if the code this patch is
> modifying is only used for setting up image uniforms (i.e., it's dead
> at the moment) and was pushed without review. *sigh*
>
> Given that, this patch certainly doesn't break anything and seems to
> do what you claim it does so I'm fine with it. That said, please do a
> follow-on patch that actually documents these new tex_layout
> entrypoints. In particular, it should be documented what value they
> compute/return. The above description, re-written in a form more
> appropriate for a comment, is probably sufficient for
> get_horizontal_slice_pitch. Assuming the follow-on will happen,
>
There is some documentation about them in the intel_mipmap_tree.h header
file, let me know if it's not sufficient for you so I write the
follow-up.
> Reviewed-by: Jason Ekstrand
>
> Go land things! You can also apply my R-B to the patch that enables
> the extension (I don't want dig through my e-mail so I can respond to
> the specific patch.)
>
Cool, thanks.
> --Jason
>
>>>
>>> On Wed, May 13, 2015 at 9:37 AM, Francisco Jerez
>>> wrote:
---
src/mesa/drivers/dri/i965/brw_tex_layout.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 72b02a2..6c6dc5c 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -281,9 +281,7 @@ brw_miptree_get_horizontal_slice_pitch(const struct
brw_context *brw,
const struct intel_mipmap_tree *mt,
unsigned level)
{
- assert(brw->gen < 9);
-
- if (mt->target == GL_TEXTURE_3D ||
+ if ((brw->gen < 9 && mt->target == GL_TEXTURE_3D) ||
(brw->gen == 4 && mt->target == GL_TEXTURE_CUBE_MAP)) {
return ALIGN(minify(mt->physical_width0, level), mt->align_w);
} else {
--
2.3.5
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Re: [Mesa-dev] [PATCH 2/5] i965/fs: Lower 32x32 bit multiplication on BXT.
Neil Roberts writes:
> Are you sure this patch is necessary? The documentation for the multiply
> instruction on BDW+ says:
>
> SourceType : *D
> DestinationType : *D
> Project : EXCLUDE(CHV)
>
> This to me implies that it should work on BXT because it doesn't say
> EXCLUDE(BXT).
>
In fact both CHV and BXT *can* support 32x32 multiplication, that's not
really the reason that motivated this patch -- The problem is that 32x32
multiplication has QWORD execution type which has several restrictions
on CHV and BXT, the annoying one is:
"CHV, BXT
When source or destination datatype is 64b or operation is integer DWord
multiply, regioning in Align1 must follow these rules:
Source and Destination horizontal stride must be aligned to the same
qword.
Example:
[...]
// mul (4) r10.0<2>:d r11.0<8;4,2>:d r12.0<8;4,2>:d // Source and
Destination stride must be 2 since the execution type is Qword."
So it sounds like we could use the native 32x32 multiply with some
additional effort to pass the arguments with the correct stride, but
it's not clear to me whether the solution would be any more better than
splitting up the multiply into 32x16 multiplies, so doing the same as in
CHV and pre-Gen8 seemed like the most KISS solution for now.
> I made a little test case and ran it on my BXT and it seems to work even
> without this patch. I looked at the assembler source and it is
> definitely doing a MUL instruction with D types for the dst and two
> sources.
>
> https://github.com/bpeel/piglit/blob/test-integer-multiply/tests/general/mult32.c
>
Hmm, I guess the docs could be wrong, but I'm not sure what the
consequences would be of violating the alignment rule, I guess the
failure may be non-deterministic. What stepping of BXT did you test
this on?
> Regards,
> - Neil
>
> Francisco Jerez writes:
>
>> AFAIK BXT has the same annoying alignment limitation as CHV on the
>> source register regions of 32x32 bit MULs, give it the same treatment.
>> ---
>> src/mesa/drivers/dri/i965/brw_fs.cpp | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
>> b/src/mesa/drivers/dri/i965/brw_fs.cpp
>> index 244f299..fc9f007 100644
>> --- a/src/mesa/drivers/dri/i965/brw_fs.cpp
>> +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
>> @@ -3126,9 +3126,9 @@ fs_visitor::lower_integer_multiplication()
>> bool progress = false;
>>
>> /* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit operation
>> -* directly, but Cherryview cannot.
>> +* directly, but CHV/BXT cannot.
>> */
>> - if (devinfo->gen >= 8 && !devinfo->is_cherryview)
>> + if (devinfo->gen >= 8 && !devinfo->is_cherryview && !devinfo->is_broxton)
>>return false;
>>
>> foreach_block_and_inst_safe(block, fs_inst, inst, cfg) {
>> --
>> 2.4.6
>>
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>> mesa-dev@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/mesa-dev
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Re: [Mesa-dev] [PATCHv2 07/14] i965: Implement surface state set-up for shader images.
Jason Ekstrand writes:
> On Sat, Aug 8, 2015 at 4:04 AM, Francisco Jerez wrote:
>> Jason Ekstrand writes:
>>
>>> On Wed, May 13, 2015 at 9:43 AM, Francisco Jerez
>>> wrote:
v2: Add SKL support.
---
src/mesa/drivers/dri/i965/brw_context.h | 2 +
src/mesa/drivers/dri/i965/brw_surface_formats.c | 109
+++
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 77
3 files changed, 188 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index 2dcc23c..c55dcec 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1741,6 +1741,8 @@ void brw_upload_abo_surfaces(struct brw_context *brw,
bool brw_render_target_supported(struct brw_context *brw,
struct gl_renderbuffer *rb);
uint32_t brw_depth_format(struct brw_context *brw, mesa_format format);
+mesa_format brw_lower_mesa_image_format(const struct brw_device_info
*devinfo,
+mesa_format format);
/* brw_performance_monitor.c */
void brw_init_performance_monitors(struct brw_context *brw);
diff --git a/src/mesa/drivers/dri/i965/brw_surface_formats.c
b/src/mesa/drivers/dri/i965/brw_surface_formats.c
index 016f87a..e0e7fb6 100644
--- a/src/mesa/drivers/dri/i965/brw_surface_formats.c
+++ b/src/mesa/drivers/dri/i965/brw_surface_formats.c
@@ -805,3 +805,112 @@ brw_depth_format(struct brw_context *brw,
mesa_format format)
unreachable("Unexpected depth format.");
}
}
+
+mesa_format
+brw_lower_mesa_image_format(const struct brw_device_info *devinfo,
+mesa_format format)
+{
+ switch (format) {
+ /* These are never lowered. Up to BDW we'll have to fall back to
untyped
+* surface access for 128bpp formats.
+*/
+ case MESA_FORMAT_RGBA_UINT32:
+ case MESA_FORMAT_RGBA_SINT32:
+ case MESA_FORMAT_RGBA_FLOAT32:
+ case MESA_FORMAT_R_UINT32:
+ case MESA_FORMAT_R_SINT32:
+ case MESA_FORMAT_R_FLOAT32:
+ return format;
>>>
>>> If it's an unsupported format, why not use MESA_FORMAT_NONE? That
>>> would make it easier for functions that call this function to know
>>> that it's just not supported and they shouldn't bother trying.
>>>
>> Because they are all supported. As the comment says these formats are
>> always accessed unlowered, the catch is that the shader may have to use
>> a different (much more painful) mechanism to access them depending on
>> the hardware generation -- But this function simply implements the
>> mapping between API image formats and what the 3D pipeline will see,
>> which is R(GBA)_*32 in this case regardless of whether untyped or typed
>> messages can be used.
>
> Ok, I failed to read. Sorry for the noise.
>
+
+ /* From HSW to BDW the only 64bpp format supported for typed access is
+* RGBA_UINT16. IVB falls back to untyped.
+*/
+ case MESA_FORMAT_RGBA_UINT16:
+ case MESA_FORMAT_RGBA_SINT16:
+ case MESA_FORMAT_RGBA_FLOAT16:
+ case MESA_FORMAT_RG_UINT32:
+ case MESA_FORMAT_RG_SINT32:
+ case MESA_FORMAT_RG_FLOAT32:
+ return (devinfo->gen >= 9 ? format :
+ devinfo->gen >= 8 || devinfo->is_haswell ?
+ MESA_FORMAT_RGBA_UINT16 : MESA_FORMAT_RG_UINT32);
+
+ /* Up to BDW no SINT or FLOAT formats of less than 32 bits per
component
+* are supported. IVB doesn't support formats with more than one
component
+* for typed access. For 8 and 16 bpp formats IVB relies on the
+* undocumented behavior that typed reads from R_UINT8 and R_UINT16
+* surfaces actually do a 32-bit misaligned read. The alternative
would be
+* to use two surface state entries with different formats for each
image,
+* one for reading (using R_UINT32) and another one for writing (using
+* R_UINT8 or R_UINT16), but that would complicate the shaders we
generate
+* even more.
+*/
>>>
>>> Let's make sure I'm understanding this correctly. On BDW and HSW, we
>>> can just use the UINT format for SINT and FLOAT. On IVB, we set the
>>> surface state to UINT32 and unpack the components in the shader? What
>>> happens with writes on IVB to 16-bpp images?
>>>
>> Heh, not exactly. On IVB we disobey the hardware spec and bind 16-bpp
>> formats as R16_UINT and 8-bpp formats as R8_UINT, which aren't
>> documented to work for typed reads. Writes work just fine and update
>> the right 8- or 16-bit word on the image. Reads *almost* do what one
>> would expect: The LSBs of the values returned from the data port will
>> contain the
Re: [Mesa-dev] [PATCH] mesa/formats: Fix swizzle flipping for big-endian targets
On Mon, Aug 10, 2015 at 9:50 AM, Jason Ekstrand wrote:
> The swizzle defines where in the format you should look for any given
> channel. When we flip the format around for BE targets, we need to change
> the destinations of the swizzles, not the sources. For example, say the
> format is an RGBX format with a swizzle of xyz1 on LE. Then it should be
> wzy1 on BE; however, the code as it was before, would have made it 1zyx on
> BE which is clearly wrong.
>
> Cc: Iago Toral
> Cc: Oded Gabbay
> ---
> src/mesa/main/formats.c | 16
> 1 file changed, 12 insertions(+), 4 deletions(-)
>
> diff --git a/src/mesa/main/formats.c b/src/mesa/main/formats.c
> index d927073..27590ed 100644
> --- a/src/mesa/main/formats.c
> +++ b/src/mesa/main/formats.c
> @@ -354,14 +354,22 @@ _mesa_array_format_flip_channels(mesa_array_format
> format)
>return format;
>
> if (num_channels == 2) {
> - _mesa_array_format_set_swizzle(&format, swizzle[1], swizzle[0],
> - swizzle[2], swizzle[3]);
> + /* Assert that the swizzle makes sense for 2 channels */
> + for (unsigned i = 0; i < 4; i++)
> + assert(swizzle[i] != 2 && swizzle[i] != 3);
> +
> + static const uint8_t flip_xy[6] = { 1, 0, 2, 3, 4, 5 };
> + _mesa_array_format_set_swizzle(&format,
> + flip_xy[swizzle[0]],
> flip_xy[swizzle[1]],
> + flip_xy[swizzle[2]],
> flip_xy[swizzle[3]]);
>return format;
> }
>
> if (num_channels == 4) {
> - _mesa_array_format_set_swizzle(&format, swizzle[3], swizzle[2],
> - swizzle[1], swizzle[0]);
> + static const uint8_t flip[6] = { 3, 2, 1, 0, 4, 5 };
> + _mesa_array_format_set_swizzle(&format,
> + flip[swizzle[0]], flip[swizzle[1]],
> + flip[swizzle[2]], flip[swizzle[3]]);
>return format;
> }
>
> --
> 2.4.3
>
Reviewed-by: Oded Gabbay
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Re: [Mesa-dev] [PATCH 4/4] r600g: use a bitfield to track dirty atoms
On Tue, Aug 11, 2015 at 2:20 AM, Grazvydas Ignotas wrote: > On Mon, Aug 10, 2015 at 1:47 PM, Marek Olšák wrote: >> Please never use "long" in Mesa. It only has 32 bits on 32-bit >> systems. uint64_t is generally used for all unsigned 64-bit variables >> and "llu" or "ull" is the number suffix. Also, the 64-bit ctz is ctzll >> and a proper HAVE macro should be added for it too. > > Well I intentionally chose long to have a machine-word sized type, for > uint64_t gcc would have to emit multiple instructions for bit setting > and ctzll on 32bit CPUs (actually a library call for ctzll from what I > see), so the idea was to use longer array there instead. Sounds good. > >> The general idea is nice, thanks. >> >> The number of atoms can be cut down by merging all scissors states >> into 1 atom (just as there is 1 atom for 16 textures, there can be 1 >> atom for 16 scissors) and the same applies to viewport states. This >> would simplify the code, because all dirty bits would fit into 64 bits >> and there would even be some space left. > > This sounds good, I'll try to work on it when I can find time. > > Also, do you know why the atoms start from 4 for r600, and 0-3 seem to > be unused? No idea. Maybe it's a typo. Marek ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 2/5] i965/fs: Lower 32x32 bit multiplication on BXT.
Francisco Jerez writes:
> Neil Roberts writes:
>
>> Are you sure this patch is necessary? The documentation for the multiply
>> instruction on BDW+ says:
>>
>> SourceType : *D
>> DestinationType :*D
>> Project :EXCLUDE(CHV)
>>
>> This to me implies that it should work on BXT because it doesn't say
>> EXCLUDE(BXT).
>>
>
> In fact both CHV and BXT *can* support 32x32 multiplication, that's not
> really the reason that motivated this patch -- The problem is that 32x32
> multiplication has QWORD execution type which has several restrictions
> on CHV and BXT, the annoying one is:
>
> "CHV, BXT
>
> When source or destination datatype is 64b or operation is integer DWord
> multiply, regioning in Align1 must follow these rules:
>
> Source and Destination horizontal stride must be aligned to the same
> qword.
>
> Example:
> [...]
> // mul (4) r10.0<2>:d r11.0<8;4,2>:d r12.0<8;4,2>:d // Source and
> Destination stride must be 2 since the execution type is Qword."
>
> So it sounds like we could use the native 32x32 multiply with some
> additional effort to pass the arguments with the correct stride, but
> it's not clear to me whether the solution would be any more better than
> splitting up the multiply into 32x16 multiplies, so doing the same as in
> CHV and pre-Gen8 seemed like the most KISS solution for now.
>
>> I made a little test case and ran it on my BXT and it seems to work even
>> without this patch. I looked at the assembler source and it is
>> definitely doing a MUL instruction with D types for the dst and two
>> sources.
>>
>> https://github.com/bpeel/piglit/blob/test-integer-multiply/tests/general/mult32.c
>>
> Hmm, I guess the docs could be wrong, but I'm not sure what the
> consequences would be of violating the alignment rule, I guess the
> failure may be non-deterministic. What stepping of BXT did you test
> this on?
>
I just tried this on the BXT simulator, and it doesn't seem to be too
happy about multiplies breaking the alignment rule:
| .aub:0x0> CEuExecUnit::CDecodeInst::RegionCheck>Instruction is:
| mul (16) r3.0<1>:dr2.3<0;1,0>:d0xe1ac99a1:d { Align1, N1,
NoCompact }.
| For 64-bit Align1 operation or multiplication of dwords in this
| device, destination horizontal stride must be aligned to qword.
|
| Fail
>> Regards,
>> - Neil
>>
>> Francisco Jerez writes:
>>
>>> AFAIK BXT has the same annoying alignment limitation as CHV on the
>>> source register regions of 32x32 bit MULs, give it the same treatment.
>>> ---
>>> src/mesa/drivers/dri/i965/brw_fs.cpp | 4 ++--
>>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
>>> b/src/mesa/drivers/dri/i965/brw_fs.cpp
>>> index 244f299..fc9f007 100644
>>> --- a/src/mesa/drivers/dri/i965/brw_fs.cpp
>>> +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
>>> @@ -3126,9 +3126,9 @@ fs_visitor::lower_integer_multiplication()
>>> bool progress = false;
>>>
>>> /* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit operation
>>> -* directly, but Cherryview cannot.
>>> +* directly, but CHV/BXT cannot.
>>> */
>>> - if (devinfo->gen >= 8 && !devinfo->is_cherryview)
>>> + if (devinfo->gen >= 8 && !devinfo->is_cherryview &&
>>> !devinfo->is_broxton)
>>>return false;
>>>
>>> foreach_block_and_inst_safe(block, fs_inst, inst, cfg) {
>>> --
>>> 2.4.6
>>>
>>> ___
>>> mesa-dev mailing list
>>> mesa-dev@lists.freedesktop.org
>>> http://lists.freedesktop.org/mailman/listinfo/mesa-dev
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Re: [Mesa-dev] [PATCH] i965/skl: Remove early platform support
Ben Widawsky writes: > Either of you opposed to doing it as a follow-on patch? (This failure > you speak of was the primary goal for removing it). Initially, I tried > to remove it, but we do still seem to use this logic pre-HSW, and so > things got messier than I initially anticipated. Doing a follow-on patch is fine by me. I'm not sure what you mean by the logic being used pre-HSW, but I guess I'll see when you post the patch :) > Neil, you said "if we go with this patch" - I haven't heard any > opposition, do you have any? No, it seems like a good idea to me. Reviewed-by: Neil Roberts - Neil ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] mesa/formats: Fix swizzle flipping for big-endian targets
Reviewed-by: Iago Toral Quiroga
El 2015-08-11 14:25, Oded Gabbay escribió:
On Mon, Aug 10, 2015 at 9:50 AM, Jason Ekstrand
wrote:
The swizzle defines where in the format you should look for any given
channel. When we flip the format around for BE targets, we need to
change
the destinations of the swizzles, not the sources. For example, say
the
format is an RGBX format with a swizzle of xyz1 on LE. Then it should
be
wzy1 on BE; however, the code as it was before, would have made it
1zyx on
BE which is clearly wrong.
Cc: Iago Toral
Cc: Oded Gabbay
---
src/mesa/main/formats.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/src/mesa/main/formats.c b/src/mesa/main/formats.c
index d927073..27590ed 100644
--- a/src/mesa/main/formats.c
+++ b/src/mesa/main/formats.c
@@ -354,14 +354,22 @@
mi_mesa_array_format_flip_channels(mesa_array_format format)
return format;
if (num_channels == 2) {
- _mesa_array_format_set_swizzle(&format, swizzle[1], swizzle[0],
- swizzle[2], swizzle[3]);
+ /* Assert that the swizzle makes sense for 2 channels */
+ for (unsigned i = 0; i < 4; i++)
+ assert(swizzle[i] != 2 && swizzle[i] != 3);
+
+ static const uint8_t flip_xy[6] = { 1, 0, 2, 3, 4, 5 };
+ _mesa_array_format_set_swizzle(&format,
+ flip_xy[swizzle[0]],
flip_xy[swizzle[1]],
+ flip_xy[swizzle[2]],
flip_xy[swizzle[3]]);
return format;
}
if (num_channels == 4) {
- _mesa_array_format_set_swizzle(&format, swizzle[3], swizzle[2],
- swizzle[1], swizzle[0]);
+ static const uint8_t flip[6] = { 3, 2, 1, 0, 4, 5 };
+ _mesa_array_format_set_swizzle(&format,
+ flip[swizzle[0]],
flip[swizzle[1]],
+ flip[swizzle[2]],
flip[swizzle[3]]);
return format;
}
--:-)
2.4.3
Reviewed-by: Oded Gabbay
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Re: [Mesa-dev] [PATCH] mesa/formats: Only do byteswapping for packed formats
Reviewed-by: Iago Toral Quiroga
El 2015-08-08 18:04, Jason Ekstrand escribió:
Cc: Iago Toral
Cc: Oded Gabbay
---
src/mesa/main/formats.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/mesa/main/formats.c b/src/mesa/main/formats.c
index baeb1bf..d927073 100644
--- a/src/mesa/main/formats.c
+++ b/src/mesa/main/formats.c
@@ -372,10 +372,10 @@ uint32_t
_mesa_format_to_array_format(mesa_format format)
{
const struct gl_format_info *info = _mesa_get_format_info(format);
- if (_mesa_little_endian())
- return info->ArrayFormat;
- else
+ if (!_mesa_little_endian() && info->Layout ==
MESA_FORMAT_LAYOUT_PACKED)
return _mesa_array_format_flip_channels(info->ArrayFormat);
+ else
+ return info->ArrayFormat;
}
static struct hash_table *format_array_format_table;
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[Mesa-dev] drm/i915/bxt: Pooled EU support
Hi, BXT supports Pooled EU feature using which EU can be pooled to process work collectively. It is mainly required for GPGPU, Media and compute shaders. I have completed the implementation in kernel and patches are sent to intel-gfx mailing list. These are already reviewed but we need an opensource use for them to be merged. http://lists.freedesktop.org/archives/intel-gfx/2015-July/072051.html Please let me know if anyone is working on adding this support in mesa? regards Arun ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 2/5] i965/fs: Lower 32x32 bit multiplication on BXT.
Ok, that makes sense, thanks for the detailed explanation. I think
you're right, given the extra restrictions avoiding the integer dword
multiplication seems like the simplest solution.
I can't say that I fully understand what the documentation is trying to
say here. Does it mean that the horizontal strides must be set such that
each element in the source is offset to the same qword within its
register as the corresponding element in the destination?
I tried changing the test case¹ so that one of the sources comes from a
uniform. That would make the register for the uniform source be a scalar
and thus all of its elements would come from the first qword, whereas
for the destination the elements would be written to different qwords.
That ends up with an instruction like this:
mul(16) g120<1>Dg9<8,8,1>D g6<0,1,0>D { align1
1H compacted };
However, the test still passes on my BXT so I've probably misunderstood
something. On the other hand this does look similar to the stride you
had in your example instruction that the simulator complained about.
Given that the documentation and simulator implies this shouldn't work
I'm happy to leave this patch and I'm not suggesting we do anything now.
Regards,
- Neil
1.
https://github.com/bpeel/piglit/blob/test-integer-multiply-uniform/tests/general/mult32.c
Francisco Jerez writes:
> Neil Roberts writes:
>
>> Are you sure this patch is necessary? The documentation for the multiply
>> instruction on BDW+ says:
>>
>> SourceType : *D
>> DestinationType :*D
>> Project :EXCLUDE(CHV)
>>
>> This to me implies that it should work on BXT because it doesn't say
>> EXCLUDE(BXT).
>>
>
> In fact both CHV and BXT *can* support 32x32 multiplication, that's not
> really the reason that motivated this patch -- The problem is that 32x32
> multiplication has QWORD execution type which has several restrictions
> on CHV and BXT, the annoying one is:
>
> "CHV, BXT
>
> When source or destination datatype is 64b or operation is integer DWord
> multiply, regioning in Align1 must follow these rules:
>
> Source and Destination horizontal stride must be aligned to the same
> qword.
>
> Example:
> [...]
> // mul (4) r10.0<2>:d r11.0<8;4,2>:d r12.0<8;4,2>:d // Source and
> Destination stride must be 2 since the execution type is Qword."
>
> So it sounds like we could use the native 32x32 multiply with some
> additional effort to pass the arguments with the correct stride, but
> it's not clear to me whether the solution would be any more better than
> splitting up the multiply into 32x16 multiplies, so doing the same as in
> CHV and pre-Gen8 seemed like the most KISS solution for now.
>
>> I made a little test case and ran it on my BXT and it seems to work even
>> without this patch. I looked at the assembler source and it is
>> definitely doing a MUL instruction with D types for the dst and two
>> sources.
>>
>> https://github.com/bpeel/piglit/blob/test-integer-multiply/tests/general/mult32.c
>>
> Hmm, I guess the docs could be wrong, but I'm not sure what the
> consequences would be of violating the alignment rule, I guess the
> failure may be non-deterministic. What stepping of BXT did you test
> this on?
>
>> Regards,
>> - Neil
>>
>> Francisco Jerez writes:
>>
>>> AFAIK BXT has the same annoying alignment limitation as CHV on the
>>> source register regions of 32x32 bit MULs, give it the same treatment.
>>> ---
>>> src/mesa/drivers/dri/i965/brw_fs.cpp | 4 ++--
>>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
>>> b/src/mesa/drivers/dri/i965/brw_fs.cpp
>>> index 244f299..fc9f007 100644
>>> --- a/src/mesa/drivers/dri/i965/brw_fs.cpp
>>> +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
>>> @@ -3126,9 +3126,9 @@ fs_visitor::lower_integer_multiplication()
>>> bool progress = false;
>>>
>>> /* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit operation
>>> -* directly, but Cherryview cannot.
>>> +* directly, but CHV/BXT cannot.
>>> */
>>> - if (devinfo->gen >= 8 && !devinfo->is_cherryview)
>>> + if (devinfo->gen >= 8 && !devinfo->is_cherryview &&
>>> !devinfo->is_broxton)
>>>return false;
>>>
>>> foreach_block_and_inst_safe(block, fs_inst, inst, cfg) {
>>> --
>>> 2.4.6
>>>
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>>> mesa-dev@lists.freedesktop.org
>>> http://lists.freedesktop.org/mailman/listinfo/mesa-dev
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[Mesa-dev] [PATCH 1/5] main: add extension GL_ARB_shader_image_size
Signed-off-by: Martin Peres
---
src/glsl/glcpp/glcpp-parse.y| 3 +++
src/glsl/glsl_parser_extras.cpp | 1 +
src/glsl/glsl_parser_extras.h | 2 ++
src/mesa/main/extensions.c | 1 +
src/mesa/main/mtypes.h | 1 +
5 files changed, 8 insertions(+)
diff --git a/src/glsl/glcpp/glcpp-parse.y b/src/glsl/glcpp/glcpp-parse.y
index dd5ec2a..18e50af 100644
--- a/src/glsl/glcpp/glcpp-parse.y
+++ b/src/glsl/glcpp/glcpp-parse.y
@@ -2478,6 +2478,9 @@ _glcpp_parser_handle_version_declaration(glcpp_parser_t
*parser, intmax_t versio
if (extensions->ARB_shader_image_load_store)
add_builtin_define(parser, "GL_ARB_shader_image_load_store",
1);
+ if (extensions->ARB_shader_image_size)
+ add_builtin_define(parser, "GL_ARB_shader_image_size", 1);
+
if (extensions->ARB_derivative_control)
add_builtin_define(parser, "GL_ARB_derivative_control", 1);
diff --git a/src/glsl/glsl_parser_extras.cpp b/src/glsl/glsl_parser_extras.cpp
index 46896d7..a4fbb33 100644
--- a/src/glsl/glsl_parser_extras.cpp
+++ b/src/glsl/glsl_parser_extras.cpp
@@ -599,6 +599,7 @@ static const _mesa_glsl_extension
_mesa_glsl_supported_extensions[] = {
EXT(ARB_shader_atomic_counters, true, false,
ARB_shader_atomic_counters),
EXT(ARB_shader_bit_encoding, true, false,
ARB_shader_bit_encoding),
EXT(ARB_shader_image_load_store, true, false,
ARB_shader_image_load_store),
+ EXT(ARB_shader_image_size,true, false,
ARB_shader_image_size),
EXT(ARB_shader_precision, true, false,
ARB_shader_precision),
EXT(ARB_shader_stencil_export,true, false,
ARB_shader_stencil_export),
EXT(ARB_shader_storage_buffer_object, true, false,
ARB_shader_storage_buffer_object),
diff --git a/src/glsl/glsl_parser_extras.h b/src/glsl/glsl_parser_extras.h
index eb325f0..f018f1d 100644
--- a/src/glsl/glsl_parser_extras.h
+++ b/src/glsl/glsl_parser_extras.h
@@ -495,6 +495,8 @@ struct _mesa_glsl_parse_state {
bool ARB_shader_bit_encoding_warn;
bool ARB_shader_image_load_store_enable;
bool ARB_shader_image_load_store_warn;
+ bool ARB_shader_image_size_enable;
+ bool ARB_shader_image_size_warn;
bool ARB_shader_precision_enable;
bool ARB_shader_precision_warn;
bool ARB_shader_stencil_export_enable;
diff --git a/src/mesa/main/extensions.c b/src/mesa/main/extensions.c
index 2dbfabd..038a438 100644
--- a/src/mesa/main/extensions.c
+++ b/src/mesa/main/extensions.c
@@ -152,6 +152,7 @@ static const struct extension extension_table[] = {
{ "GL_ARB_shader_atomic_counters",
o(ARB_shader_atomic_counters), GL, 2011 },
{ "GL_ARB_shader_bit_encoding", o(ARB_shader_bit_encoding),
GL, 2010 },
{ "GL_ARB_shader_image_load_store",
o(ARB_shader_image_load_store), GL, 2011 },
+ { "GL_ARB_shader_image_size", o(ARB_shader_image_size),
GL, 2012 },
{ "GL_ARB_shader_objects", o(dummy_true),
GL, 2002 },
{ "GL_ARB_shader_precision",o(ARB_shader_precision),
GL, 2010 },
{ "GL_ARB_shader_stencil_export",
o(ARB_shader_stencil_export), GL, 2009 },
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 4e00fb6..6a0065c 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -3862,6 +3862,7 @@ struct gl_extensions
GLboolean ARB_shader_atomic_counters;
GLboolean ARB_shader_bit_encoding;
GLboolean ARB_shader_image_load_store;
+ GLboolean ARB_shader_image_size;
GLboolean ARB_shader_precision;
GLboolean ARB_shader_stencil_export;
GLboolean ARB_shader_storage_buffer_object;
--
2.5.0
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[Mesa-dev] [PATCH 3/5] nir: convert the glsl intrinsic image_size to nir_intrinsic_image_size
Signed-off-by: Martin Peres
---
src/glsl/nir/glsl_to_nir.cpp | 18 --
src/glsl/nir/nir_intrinsics.h | 2 ++
2 files changed, 14 insertions(+), 6 deletions(-)
diff --git a/src/glsl/nir/glsl_to_nir.cpp b/src/glsl/nir/glsl_to_nir.cpp
index 77327b6..bae9d20 100644
--- a/src/glsl/nir/glsl_to_nir.cpp
+++ b/src/glsl/nir/glsl_to_nir.cpp
@@ -641,6 +641,8 @@ nir_visitor::visit(ir_call *ir)
op = nir_intrinsic_image_atomic_comp_swap;
} else if (strcmp(ir->callee_name(), "__intrinsic_memory_barrier") == 0)
{
op = nir_intrinsic_memory_barrier;
+ } else if (strcmp(ir->callee_name(), "__intrinsic_image_size") == 0) {
+ op = nir_intrinsic_image_size;
} else {
unreachable("not reached");
}
@@ -666,7 +668,8 @@ nir_visitor::visit(ir_call *ir)
case nir_intrinsic_image_atomic_or:
case nir_intrinsic_image_atomic_xor:
case nir_intrinsic_image_atomic_exchange:
- case nir_intrinsic_image_atomic_comp_swap: {
+ case nir_intrinsic_image_atomic_comp_swap:
+ case nir_intrinsic_image_size: {
nir_ssa_undef_instr *instr_undef =
nir_ssa_undef_instr_create(shader, 1);
nir_instr_insert_after_cf_list(this->cf_node_list,
@@ -681,6 +684,14 @@ nir_visitor::visit(ir_call *ir)
instr->variables[0] = evaluate_deref(&instr->instr, image);
param = param->get_next();
+ /* Set the intrinsic destination. */
+ if (ir->return_deref)
+nir_ssa_dest_init(&instr->instr, &instr->dest,
+ ir->return_deref->type->vector_elements, NULL);
+
+ if (op == nir_intrinsic_image_size)
+break;
+
/* Set the address argument, extending the coordinate vector to four
* components.
*/
@@ -721,11 +732,6 @@ nir_visitor::visit(ir_call *ir)
instr->src[3] = evaluate_rvalue((ir_dereference *)param);
param = param->get_next();
}
-
- /* Set the intrinsic destination. */
- if (ir->return_deref)
-nir_ssa_dest_init(&instr->instr, &instr->dest,
- ir->return_deref->type->vector_elements, NULL);
break;
}
case nir_intrinsic_memory_barrier:
diff --git a/src/glsl/nir/nir_intrinsics.h b/src/glsl/nir/nir_intrinsics.h
index bc6e6b8..6c7a61a 100644
--- a/src/glsl/nir/nir_intrinsics.h
+++ b/src/glsl/nir/nir_intrinsics.h
@@ -123,6 +123,8 @@ INTRINSIC(image_atomic_or, 3, ARR(4, 1, 1), true, 1, 1, 0,
0)
INTRINSIC(image_atomic_xor, 3, ARR(4, 1, 1), true, 1, 1, 0, 0)
INTRINSIC(image_atomic_exchange, 3, ARR(4, 1, 1), true, 1, 1, 0, 0)
INTRINSIC(image_atomic_comp_swap, 4, ARR(4, 1, 1, 1), true, 1, 1, 0, 0)
+INTRINSIC(image_size, 0, ARR(), true, 4, 1, 0,
+ NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER)
#define SYSTEM_VALUE(name, components) \
INTRINSIC(load_##name, 0, ARR(), true, components, 0, 0, \
--
2.5.0
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[Mesa-dev] [PATCH 0/5] Add support for ARB_shader_image_size
This series is enough to pass all the image-size piglit test. Martin Peres (5): main: add extension GL_ARB_shader_image_size glsl: add support for the imageSize builtin nir: convert the glsl intrinsic image_size to nir_intrinsic_image_size i965: handle nir_intrinsic_image_size i965: enable GL_ARB_shader_image_size docs/GL3.txt | 4 +- docs/relnotes/11.0.0.html| 1 + src/glsl/builtin_functions.cpp | 165 --- src/glsl/glcpp/glcpp-parse.y | 3 + src/glsl/glsl_parser_extras.cpp | 1 + src/glsl/glsl_parser_extras.h| 2 + src/glsl/nir/glsl_to_nir.cpp | 18 ++- src/glsl/nir/nir_intrinsics.h| 2 + src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 51 + src/mesa/drivers/dri/i965/intel_extensions.c | 1 + src/mesa/main/extensions.c | 1 + src/mesa/main/mtypes.h | 1 + 12 files changed, 199 insertions(+), 51 deletions(-) -- 2.5.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 2/5] glsl: add support for the imageSize builtin
The code is heavily inspired from Francisco Jerez's code supporting the
image_load_store extension.
I moved out image_types[] out of builtin_builder::add_image_function to
share it with the newly-added builtin_builder::add_image_size_functions.
Backends willing to support this builtin should handle
__intrinsic_image_size.
Signed-off-by: Martin Peres
---
src/glsl/builtin_functions.cpp | 165 ++---
1 file changed, 122 insertions(+), 43 deletions(-)
diff --git a/src/glsl/builtin_functions.cpp b/src/glsl/builtin_functions.cpp
index 2175c66..e8344f0 100644
--- a/src/glsl/builtin_functions.cpp
+++ b/src/glsl/builtin_functions.cpp
@@ -399,6 +399,13 @@ shader_image_load_store(const _mesa_glsl_parse_state
*state)
}
static bool
+shader_image_size(const _mesa_glsl_parse_state *state)
+{
+ return (state->is_version(430, 0) ||
+ state->ARB_shader_image_size_enable);
+}
+
+static bool
gs_streams(const _mesa_glsl_parse_state *state)
{
return gpu_shader5(state) && gs_only(state);
@@ -502,8 +509,8 @@ private:
};
/**
-* Create a new image built-in function for all known image types.
-* \p flags is a bitfield of \c image_function_flags flags.
+* Create a new image built-in function for image load/store for all known
+* image types. \p flags is a bitfield of \c image_function_flags flags.
*/
void add_image_function(const char *name,
const char *intrinsic_name,
@@ -511,14 +518,24 @@ private:
unsigned flags);
/**
-* Create new functions for all known image built-ins and types.
-* If \p glsl is \c true, use the GLSL built-in names and emit code
-* to call into the actual compiler intrinsic. If \p glsl is
+* Create a new image built-in function for image load/store for all known
+* image types. If \p glsl is \c true, use the GLSL built-in names and emit
+* code to call into the actual compiler intrinsic. If \p glsl is
* false, emit a function prototype with no body for each image
* intrinsic name.
*/
void add_image_functions(bool glsl);
+ /**
+* Create the imageSize built-in function for all known image built-ins and
+* types. If \p glsl is \c true, use the GLSL built-in names and emit code
+* to call into the actual compiler intrinsic. If \p glsl is
+* false, emit a function prototype with no body for each image
+* intrinsic name.
+*/
+ void add_image_size_functions(const char *name, const char *intrinsic_name,
+ unsigned flags);
+
ir_function_signature *new_sig(const glsl_type *return_type,
builtin_available_predicate avail,
int num_params, ...);
@@ -718,6 +735,10 @@ private:
ir_function_signature *_memory_barrier(
builtin_available_predicate avail);
+ ir_function_signature *_image_size(const glsl_type *image_type,
+ const char *intrinsic_name,
+ unsigned flags);
+
#undef B0
#undef B1
#undef B2
@@ -2549,53 +2570,54 @@ builtin_builder::add_function(const char *name, ...)
shader->symbols->add_function(f);
}
+static const glsl_type *const image_types[] = {
+ glsl_type::image1D_type,
+ glsl_type::image2D_type,
+ glsl_type::image3D_type,
+ glsl_type::image2DRect_type,
+ glsl_type::imageCube_type,
+ glsl_type::imageBuffer_type,
+ glsl_type::image1DArray_type,
+ glsl_type::image2DArray_type,
+ glsl_type::imageCubeArray_type,
+ glsl_type::image2DMS_type,
+ glsl_type::image2DMSArray_type,
+ glsl_type::iimage1D_type,
+ glsl_type::iimage2D_type,
+ glsl_type::iimage3D_type,
+ glsl_type::iimage2DRect_type,
+ glsl_type::iimageCube_type,
+ glsl_type::iimageBuffer_type,
+ glsl_type::iimage1DArray_type,
+ glsl_type::iimage2DArray_type,
+ glsl_type::iimageCubeArray_type,
+ glsl_type::iimage2DMS_type,
+ glsl_type::iimage2DMSArray_type,
+ glsl_type::uimage1D_type,
+ glsl_type::uimage2D_type,
+ glsl_type::uimage3D_type,
+ glsl_type::uimage2DRect_type,
+ glsl_type::uimageCube_type,
+ glsl_type::uimageBuffer_type,
+ glsl_type::uimage1DArray_type,
+ glsl_type::uimage2DArray_type,
+ glsl_type::uimageCubeArray_type,
+ glsl_type::uimage2DMS_type,
+ glsl_type::uimage2DMSArray_type
+};
+
void
builtin_builder::add_image_function(const char *name,
const char *intrinsic_name,
unsigned num_arguments,
unsigned flags)
{
- static const glsl_type *const types[] = {
- glsl_type::image1D_type,
- glsl_type::image2D_type,
- glsl_type::image3D_type,
- glsl_type::image2DRect_type,
- glsl_type::imageCube_type,
- glsl_type::imageBuffer_type,
- glsl_type::image1DArray_type,
- glsl_type::image2DArray_type,
- glsl_typ
[Mesa-dev] [PATCH 4/5] i965: handle nir_intrinsic_image_size
Signed-off-by: Martin Peres
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 51
1 file changed, 51 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index ce4153d..3d172ff 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -1406,6 +1406,57 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld,
nir_intrinsic_instr *instr
break;
}
+ case nir_intrinsic_image_size: {
+ bool isCubeMapImage = false, is1DArrayImage = false;
+
+ /* Get the referenced image variable and type. */
+ const nir_variable *var = instr->variables[0]->var;
+ const glsl_type *type = var->type->without_array();
+ const brw_reg_type base_type = get_image_base_type(type);
+
+ /* Get the size of the image. */
+ const fs_reg image = get_nir_image_deref(instr->variables[0]);
+ const fs_reg size = offset(image, bld, BRW_IMAGE_PARAM_SIZE_OFFSET);
+
+ /*
+ * For CubeMapArray images, we should count the number of cubes instead
+ * of the number of faces. Fix it by dividing the (Z component) by 6.
+ */
+ if (type == glsl_type::imageCubeArray_type ||
+ type == glsl_type::iimageCubeArray_type ||
+ type == glsl_type::uimageCubeArray_type) {
+ isCubeMapImage = true;
+ }
+
+ /*
+ * For 1DArray image types, the array index is stored in the Z component.
+ * Fix this by swizzling the Z component to the Y component.
+ */
+ if (type == glsl_type::image1DArray_type ||
+ type == glsl_type::iimage1DArray_type ||
+ type == glsl_type::uimage1DArray_type) {
+ is1DArrayImage = true;
+ }
+
+ /* Copy all the components. */
+ const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic];
+ for (unsigned c = 0; c < info->dest_components; ++c) {
+ if (c == 1 && is1DArrayImage) {
+bld.MOV(offset(retype(dest, base_type), bld, c),
+offset(size, bld, 2));
+ } else if (c == 2 && isCubeMapImage) {
+bld.emit(SHADER_OPCODE_INT_QUOTIENT,
+ offset(retype(dest, base_type), bld, c),
+ offset(size, bld, c), fs_reg(6));
+ } else {
+bld.MOV(offset(retype(dest, base_type), bld, c),
+offset(size, bld, c));
+ }
+ }
+
+ break;
+ }
+
case nir_intrinsic_load_front_face:
bld.MOV(retype(dest, BRW_REGISTER_TYPE_D),
*emit_frontfacing_interpolation());
--
2.5.0
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 5/5] i965: enable GL_ARB_shader_image_size
Signed-off-by: Martin Peres --- docs/GL3.txt | 4 ++-- docs/relnotes/11.0.0.html| 1 + src/mesa/drivers/dri/i965/intel_extensions.c | 1 + 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/docs/GL3.txt b/docs/GL3.txt index 54c0c5a..5319e06 100644 --- a/docs/GL3.txt +++ b/docs/GL3.txt @@ -163,7 +163,7 @@ GL 4.3, GLSL 4.30: GL_ARB_multi_draw_indirect DONE (i965, nvc0, r600, radeonsi, llvmpipe, softpipe) GL_ARB_program_interface_query DONE (all drivers) GL_ARB_robust_buffer_access_behavior not started - GL_ARB_shader_image_size in progress (Martin Peres) + GL_ARB_shader_image_size DONE (i965) GL_ARB_shader_storage_buffer_object in progress (Iago Toral, Samuel Iglesias) GL_ARB_stencil_texturing DONE (i965/gen8+, nv50, nvc0, r600, radeonsi, llvmpipe, softpipe) GL_ARB_texture_buffer_range DONE (nv50, nvc0, i965, r600, radeonsi, llvmpipe) @@ -211,7 +211,7 @@ GLES3.1, GLSL ES 3.1 GL_ARB_program_interface_query DONE (all drivers) GL_ARB_shader_atomic_countersDONE (i965) GL_ARB_shader_image_load_store in progress (curro) - GL_ARB_shader_image_size in progress (Martin Peres) + GL_ARB_shader_image_size DONE (i965) GL_ARB_shader_storage_buffer_object in progress (Iago Toral, Samuel Iglesias) GL_ARB_shading_language_packing DONE (all drivers) GL_ARB_separate_shader_objects DONE (all drivers) diff --git a/docs/relnotes/11.0.0.html b/docs/relnotes/11.0.0.html index 2d80198..45a1689 100644 --- a/docs/relnotes/11.0.0.html +++ b/docs/relnotes/11.0.0.html @@ -53,6 +53,7 @@ Note: some of the new features are only available with certain drivers. GL_ARB_gpu_shader5 on radeonsi GL_ARB_gpu_shader_fp64 on llvmpipe, radeonsi GL_ARB_shader_image_load_store on i965 +GL_ARB_shader_image_size on i965 GL_ARB_shader_stencil_export on llvmpipe GL_ARB_shader_subroutine on core profile all drivers GL_ARB_tessellation_shader on nvc0, radeonsi diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c index 0da528b..4365b71 100644 --- a/src/mesa/drivers/dri/i965/intel_extensions.c +++ b/src/mesa/drivers/dri/i965/intel_extensions.c @@ -326,6 +326,7 @@ intelInitExtensions(struct gl_context *ctx) ctx->Extensions.ARB_gpu_shader5 = true; ctx->Extensions.ARB_shader_atomic_counters = true; ctx->Extensions.ARB_shader_image_load_store = true; + ctx->Extensions.ARB_shader_image_size = true; ctx->Extensions.ARB_texture_compression_bptc = true; ctx->Extensions.ARB_texture_view = true; -- 2.5.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 2/5] glsl: add support for the imageSize builtin
On Tue, Aug 11, 2015 at 12:43 PM, Martin Peres
wrote:
> The code is heavily inspired from Francisco Jerez's code supporting the
> image_load_store extension.
>
> I moved out image_types[] out of builtin_builder::add_image_function to
> share it with the newly-added builtin_builder::add_image_size_functions.
>
> Backends willing to support this builtin should handle
> __intrinsic_image_size.
>
> Signed-off-by: Martin Peres
> ---
> src/glsl/builtin_functions.cpp | 165
> ++---
> 1 file changed, 122 insertions(+), 43 deletions(-)
>
> diff --git a/src/glsl/builtin_functions.cpp b/src/glsl/builtin_functions.cpp
> index 2175c66..e8344f0 100644
> --- a/src/glsl/builtin_functions.cpp
> +++ b/src/glsl/builtin_functions.cpp
> @@ -399,6 +399,13 @@ shader_image_load_store(const _mesa_glsl_parse_state
> *state)
> }
>
> static bool
> +shader_image_size(const _mesa_glsl_parse_state *state)
> +{
> + return (state->is_version(430, 0) ||
Isn't it also available in GLSL ES 3.10? i.e. this should be
state->is_version(430, 310). Or is the remaining image stuff not quite
ready for ES 3.10?
> + state->ARB_shader_image_size_enable);
> +}
> +
> +static bool
> gs_streams(const _mesa_glsl_parse_state *state)
> {
> return gpu_shader5(state) && gs_only(state);
> @@ -502,8 +509,8 @@ private:
> };
>
> /**
> -* Create a new image built-in function for all known image types.
> -* \p flags is a bitfield of \c image_function_flags flags.
> +* Create a new image built-in function for image load/store for all known
> +* image types. \p flags is a bitfield of \c image_function_flags flags.
> */
> void add_image_function(const char *name,
> const char *intrinsic_name,
> @@ -511,14 +518,24 @@ private:
> unsigned flags);
>
> /**
> -* Create new functions for all known image built-ins and types.
> -* If \p glsl is \c true, use the GLSL built-in names and emit code
> -* to call into the actual compiler intrinsic. If \p glsl is
> +* Create a new image built-in function for image load/store for all known
> +* image types. If \p glsl is \c true, use the GLSL built-in names and
> emit
> +* code to call into the actual compiler intrinsic. If \p glsl is
> * false, emit a function prototype with no body for each image
> * intrinsic name.
> */
> void add_image_functions(bool glsl);
>
> + /**
> +* Create the imageSize built-in function for all known image built-ins
> and
> +* types. If \p glsl is \c true, use the GLSL built-in names and emit code
> +* to call into the actual compiler intrinsic. If \p glsl is
> +* false, emit a function prototype with no body for each image
> +* intrinsic name.
> +*/
> + void add_image_size_functions(const char *name, const char
> *intrinsic_name,
> + unsigned flags);
> +
> ir_function_signature *new_sig(const glsl_type *return_type,
>builtin_available_predicate avail,
>int num_params, ...);
> @@ -718,6 +735,10 @@ private:
> ir_function_signature *_memory_barrier(
>builtin_available_predicate avail);
>
> + ir_function_signature *_image_size(const glsl_type *image_type,
> + const char *intrinsic_name,
> + unsigned flags);
> +
> #undef B0
> #undef B1
> #undef B2
> @@ -2549,53 +2570,54 @@ builtin_builder::add_function(const char *name, ...)
> shader->symbols->add_function(f);
> }
>
> +static const glsl_type *const image_types[] = {
> + glsl_type::image1D_type,
> + glsl_type::image2D_type,
> + glsl_type::image3D_type,
> + glsl_type::image2DRect_type,
> + glsl_type::imageCube_type,
> + glsl_type::imageBuffer_type,
> + glsl_type::image1DArray_type,
> + glsl_type::image2DArray_type,
> + glsl_type::imageCubeArray_type,
> + glsl_type::image2DMS_type,
> + glsl_type::image2DMSArray_type,
> + glsl_type::iimage1D_type,
> + glsl_type::iimage2D_type,
> + glsl_type::iimage3D_type,
> + glsl_type::iimage2DRect_type,
> + glsl_type::iimageCube_type,
> + glsl_type::iimageBuffer_type,
> + glsl_type::iimage1DArray_type,
> + glsl_type::iimage2DArray_type,
> + glsl_type::iimageCubeArray_type,
> + glsl_type::iimage2DMS_type,
> + glsl_type::iimage2DMSArray_type,
> + glsl_type::uimage1D_type,
> + glsl_type::uimage2D_type,
> + glsl_type::uimage3D_type,
> + glsl_type::uimage2DRect_type,
> + glsl_type::uimageCube_type,
> + glsl_type::uimageBuffer_type,
> + glsl_type::uimage1DArray_type,
> + glsl_type::uimage2DArray_type,
> + glsl_type::uimageCubeArray_type,
> + glsl_type::uimage2DMS_type,
> + glsl_type::uimage2DMSArray_type
> +};
> +
> void
> builtin_builder::add_image_function(const char *name,
> const char *intrinsic_name
Re: [Mesa-dev] [PATCH 2/5] glsl: add support for the imageSize builtin
On 11/08/15 19:52, Ilia Mirkin wrote:
On Tue, Aug 11, 2015 at 12:43 PM, Martin Peres
wrote:
The code is heavily inspired from Francisco Jerez's code supporting the
image_load_store extension.
I moved out image_types[] out of builtin_builder::add_image_function to
share it with the newly-added builtin_builder::add_image_size_functions.
Backends willing to support this builtin should handle
__intrinsic_image_size.
Signed-off-by: Martin Peres
---
src/glsl/builtin_functions.cpp | 165 ++---
1 file changed, 122 insertions(+), 43 deletions(-)
diff --git a/src/glsl/builtin_functions.cpp b/src/glsl/builtin_functions.cpp
index 2175c66..e8344f0 100644
--- a/src/glsl/builtin_functions.cpp
+++ b/src/glsl/builtin_functions.cpp
@@ -399,6 +399,13 @@ shader_image_load_store(const _mesa_glsl_parse_state
*state)
}
static bool
+shader_image_size(const _mesa_glsl_parse_state *state)
+{
+ return (state->is_version(430, 0) ||
Isn't it also available in GLSL ES 3.10? i.e. this should be
state->is_version(430, 310). Or is the remaining image stuff not quite
ready for ES 3.10?
Oh, right! ES 3.10 should be OK, but I will check in details tomorrow.
I wrote this patch series months ago so it is good to have a look at the
spec again anyway.
Thanks!
+ state->ARB_shader_image_size_enable);
+}
+
+static bool
gs_streams(const _mesa_glsl_parse_state *state)
{
return gpu_shader5(state) && gs_only(state);
@@ -502,8 +509,8 @@ private:
};
/**
-* Create a new image built-in function for all known image types.
-* \p flags is a bitfield of \c image_function_flags flags.
+* Create a new image built-in function for image load/store for all known
+* image types. \p flags is a bitfield of \c image_function_flags flags.
*/
void add_image_function(const char *name,
const char *intrinsic_name,
@@ -511,14 +518,24 @@ private:
unsigned flags);
/**
-* Create new functions for all known image built-ins and types.
-* If \p glsl is \c true, use the GLSL built-in names and emit code
-* to call into the actual compiler intrinsic. If \p glsl is
+* Create a new image built-in function for image load/store for all known
+* image types. If \p glsl is \c true, use the GLSL built-in names and emit
+* code to call into the actual compiler intrinsic. If \p glsl is
* false, emit a function prototype with no body for each image
* intrinsic name.
*/
void add_image_functions(bool glsl);
+ /**
+* Create the imageSize built-in function for all known image built-ins and
+* types. If \p glsl is \c true, use the GLSL built-in names and emit code
+* to call into the actual compiler intrinsic. If \p glsl is
+* false, emit a function prototype with no body for each image
+* intrinsic name.
+*/
+ void add_image_size_functions(const char *name, const char *intrinsic_name,
+ unsigned flags);
+
ir_function_signature *new_sig(const glsl_type *return_type,
builtin_available_predicate avail,
int num_params, ...);
@@ -718,6 +735,10 @@ private:
ir_function_signature *_memory_barrier(
builtin_available_predicate avail);
+ ir_function_signature *_image_size(const glsl_type *image_type,
+ const char *intrinsic_name,
+ unsigned flags);
+
#undef B0
#undef B1
#undef B2
@@ -2549,53 +2570,54 @@ builtin_builder::add_function(const char *name, ...)
shader->symbols->add_function(f);
}
+static const glsl_type *const image_types[] = {
+ glsl_type::image1D_type,
+ glsl_type::image2D_type,
+ glsl_type::image3D_type,
+ glsl_type::image2DRect_type,
+ glsl_type::imageCube_type,
+ glsl_type::imageBuffer_type,
+ glsl_type::image1DArray_type,
+ glsl_type::image2DArray_type,
+ glsl_type::imageCubeArray_type,
+ glsl_type::image2DMS_type,
+ glsl_type::image2DMSArray_type,
+ glsl_type::iimage1D_type,
+ glsl_type::iimage2D_type,
+ glsl_type::iimage3D_type,
+ glsl_type::iimage2DRect_type,
+ glsl_type::iimageCube_type,
+ glsl_type::iimageBuffer_type,
+ glsl_type::iimage1DArray_type,
+ glsl_type::iimage2DArray_type,
+ glsl_type::iimageCubeArray_type,
+ glsl_type::iimage2DMS_type,
+ glsl_type::iimage2DMSArray_type,
+ glsl_type::uimage1D_type,
+ glsl_type::uimage2D_type,
+ glsl_type::uimage3D_type,
+ glsl_type::uimage2DRect_type,
+ glsl_type::uimageCube_type,
+ glsl_type::uimageBuffer_type,
+ glsl_type::uimage1DArray_type,
+ glsl_type::uimage2DArray_type,
+ glsl_type::uimageCubeArray_type,
+ glsl_type::uimage2DMS_type,
+ glsl_type::uimage2DMSArray_type
+};
+
void
builtin_builder::add_image_function(const char *name,
const char *intrinsic_name,
Re: [Mesa-dev] Mesa 11.0.0 release plan
On 29/07/15 19:20, Emil Velikov wrote: > Hi all, > > Below is the preliminary release schedule for Mesa 11.0.0 > > August 21st 2015 - Feature freeze/Release candidate 1 > August 28th 2015 - Release candidate 2 > September 04th 2015 - Release candidate 3 > September 11th 2015 - Release candidate 4/Mesa 11.0.0 > Considering the quiet acknowledgement, the above schedule will be taking place. Reminder: do push all your feature changes before the end of 21st August if you'd want them in for the next release. Thanks Emil ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/2][RFC] docs: Update with GLES3.2 entries and status
Signed-off-by: Thomas Helland --- These are listed to the best of my knowledge, looking at the nvidia driver dropped yesterday, and a glance at the "what changed according to the ARB variant" section of each extension spec. Hopefully it should not be too far off. Feel free to leave your comments docs/GL3.txt | 25 + 1 file changed, 25 insertions(+) diff --git a/docs/GL3.txt b/docs/GL3.txt index 8124383..2148ca0 100644 --- a/docs/GL3.txt +++ b/docs/GL3.txt @@ -223,6 +223,31 @@ GLES3.1, GLSL ES 3.1 GS5 Packing/bitfield/conversion functionsDONE (i965, nvc0, r600, radeonsi) GL_EXT_shader_integer_mixDONE (all drivers that support GLSL) +GLES3.2, GLSL ES 3.2 + GL_EXT_color_buffer_floatDONE (all drivers) + GL_KHR_blend_equation_advanced not started + GL_KHR_debug DONE (all drivers) + GL_KHR_robustness90% done (the ARB variant) + GL_KHR_texture_compression_astc_hdr in progress (Nanley Chery) + GL_OES_copy_image60% done (based on parts of GL_ARB_copy_image, which is done for some drivers) + GL_OES_draw_buffers_indexed not started + GL_OES_draw_elements_base_vertex 90% done (based on GL_ARB_draw_elements_base_verte, which is done for all drivers) + GL_OES_geometry_shader 80% done (based on GL_ARB_geometry_shader4, which is done for all drivers) + GL_OES_gpu_shader5 90% done (based on parts of GL_ARB_gpu_shader5, which is done for some drivers) + GL_OES_primitive_bounding boxnot started + GL_OES_sample_shading90% done (based on parts of GL_ARB_sample_shading, which is done for some drivers) + GL_OES_sample_variables 90% done (based on parts of GL_ARB_sample_shading, which is done for some drivers) + GL_OES_shader_image_atomic 90% done (based on parts of GL_ARB_shader_image_load_store, which is done for some drivers) + GL_OES_shader_io_blocks not started + GL_OES_shader_multisample_interpolation started (based on parts of GL_ARB_gpu_shader5, which is done) + GL_OES_tessellation_shader 90% done (based on GL_ARB_tessellation_shader, which is done for some drivers) + GL_OES_texture_border_clamp 90% done (the ARB variant is done) + GL_OES_texture_buffer90% done (combination of ARB_texture_buffer_object, ARB_texture_buffer_range, and ARB_texture_buffer_object_rgb32 that are all done) + GL_OES_texture_cube_map_array90% done (based on GL_ARB_texture_cube_map_array, which is done for all drivers) + GL_OES_texture_stencil8 90% done (based on parts of GL_ARB_texture_stencil8, which is done for some drivers) + GL_OES_texture_storage_multisample_2d_array not started + + Additional functions not covered above: glMemoryBarrierByRegion glGetTexLevelParameter[fi]v - needs updates to restrict to GLES enums -- 2.5.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 2/2][RFC] docs: Add the 2015 ARB extensions
Signed-off-by: Thomas Helland --- This adds a section for the extensions nvidia has chosen to call the "GL ARB 2015 Extensions" unveiled at SIGGRAPH. Also some minor whitespace fixes for consistency. We might also want to add other extensions that are not part of the openGL core specs, but that we want to support. Feel free to leave your suggestions. GL_ARB_bindless_texture and GL_ARB_sparse_texture have been nominated. docs/GL3.txt | 20 1 file changed, 20 insertions(+) diff --git a/docs/GL3.txt b/docs/GL3.txt index 2148ca0..929aafd 100644 --- a/docs/GL3.txt +++ b/docs/GL3.txt @@ -185,6 +185,7 @@ GL 4.4, GLSL 4.40: GL_ARB_texture_stencil8 DONE (nv50, nvc0, r600, radeonsi, llvmpipe, softpipe) GL_ARB_vertex_type_10f_11f_11f_rev DONE (i965, nv50, nvc0, r600, radeonsi, llvmpipe, softpipe) + GL 4.5, GLSL 4.50: GL_ARB_ES3_1_compatibility not started @@ -201,6 +202,7 @@ GL 4.5, GLSL 4.50: GL_KHR_robustness90% done (the ARB variant) GL_EXT_shader_integer_mixDONE (all drivers that support GLSL) + These are the extensions cherry-picked to make GLES 3.1 GLES3.1, GLSL ES 3.1 GL_ARB_arrays_of_arrays started (Timothy) @@ -223,6 +225,7 @@ GLES3.1, GLSL ES 3.1 GS5 Packing/bitfield/conversion functionsDONE (i965, nvc0, r600, radeonsi) GL_EXT_shader_integer_mixDONE (all drivers that support GLSL) + GLES3.2, GLSL ES 3.2 GL_EXT_color_buffer_floatDONE (all drivers) GL_KHR_blend_equation_advanced not started @@ -248,6 +251,23 @@ GLES3.2, GLSL ES 3.2 GL_OES_texture_storage_multisample_2d_array not started +GL ARB 2015 (SIGGRAPH) Extensions: + + GL_ARB_ES3_2_compatibility not started + GL_ARB_fragment_shader_interlock not started + GL_ARB_gpu_shader_int64 not started + GL_ARB_parallel_shader_compile not started + GL_ARB_post_depth_coverage not started + GL_ARB_sample_locations not started + GL_ARB_shader_atomic_counter_ops not started + GL_ARB_shader_ballot not started + GL_ARB_shader_clock not started + GL_ARB_shader_viewport_layer_array not started + GL_ARB_sparse_texture2 not started + GL_ARB_sparse_texture_clamp not started + GL_ARB_texture_filter_minmax not started + + Additional functions not covered above: glMemoryBarrierByRegion glGetTexLevelParameter[fi]v - needs updates to restrict to GLES enums -- 2.5.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 1/4] gallium/radeon: use helper functions to mark atoms dirty
I pushed this series. Thanks.
Marek
On Sun, Aug 9, 2015 at 11:42 PM, Grazvydas Ignotas wrote:
> This is analogous to r300_mark_atom_dirty() used by r300, and will
> be used by later patches. For common radeon code, appropriate helper
> is called through a function pointer.
>
> No functional changes.
> ---
> src/gallium/drivers/r600/evergreen_compute.c| 2 +-
> src/gallium/drivers/r600/evergreen_state.c | 28 -
> src/gallium/drivers/r600/r600_blit.c| 16 +++---
> src/gallium/drivers/r600/r600_hw_context.c | 54 +-
> src/gallium/drivers/r600/r600_pipe.c| 1 +
> src/gallium/drivers/r600/r600_pipe.h| 25 +++--
> src/gallium/drivers/r600/r600_state.c | 28 -
> src/gallium/drivers/r600/r600_state_common.c| 75
> +
> src/gallium/drivers/radeon/r600_pipe_common.h | 3 +
> src/gallium/drivers/radeon/r600_streamout.c | 14 +++--
> src/gallium/drivers/radeon/r600_texture.c | 2 +-
> src/gallium/drivers/radeonsi/si_blit.c | 14 ++---
> src/gallium/drivers/radeonsi/si_descriptors.c | 6 +-
> src/gallium/drivers/radeonsi/si_hw_context.c| 12 ++--
> src/gallium/drivers/radeonsi/si_pipe.c | 1 +
> src/gallium/drivers/radeonsi/si_pipe.h | 14 +
> src/gallium/drivers/radeonsi/si_state.c | 18 +++---
> src/gallium/drivers/radeonsi/si_state_draw.c| 2 +-
> src/gallium/drivers/radeonsi/si_state_shaders.c | 12 ++--
> 19 files changed, 182 insertions(+), 145 deletions(-)
>
> diff --git a/src/gallium/drivers/r600/evergreen_compute.c
> b/src/gallium/drivers/r600/evergreen_compute.c
> index d89e3de..5100330 100644
> --- a/src/gallium/drivers/r600/evergreen_compute.c
> +++ b/src/gallium/drivers/r600/evergreen_compute.c
> @@ -163,7 +163,7 @@ static void evergreen_cs_set_vertex_buffer(
> rctx->b.flags |= R600_CONTEXT_INV_VERTEX_CACHE;
> state->enabled_mask |= 1 << vb_index;
> state->dirty_mask |= 1 << vb_index;
> - state->atom.dirty = true;
> + r600_mark_atom_dirty(rctx, &state->atom);
> }
>
> static void evergreen_cs_set_constant_buffer(
> diff --git a/src/gallium/drivers/r600/evergreen_state.c
> b/src/gallium/drivers/r600/evergreen_state.c
> index 13ecc46..bb53383 100644
> --- a/src/gallium/drivers/r600/evergreen_state.c
> +++ b/src/gallium/drivers/r600/evergreen_state.c
> @@ -896,7 +896,7 @@ static void evergreen_set_scissor_states(struct
> pipe_context *ctx,
>
> for (i = start_slot; i < start_slot + num_scissors; i++) {
> rctx->scissor[i].scissor = state[i - start_slot];
> - rctx->scissor[i].atom.dirty = true;
> + r600_mark_atom_dirty(rctx, &rctx->scissor[i].atom);
> }
> }
>
> @@ -1346,11 +1346,11 @@ static void evergreen_set_framebuffer_state(struct
> pipe_context *ctx,
>
> if (rctx->alphatest_state.bypass != alphatest_bypass) {
> rctx->alphatest_state.bypass = alphatest_bypass;
> - rctx->alphatest_state.atom.dirty = true;
> + r600_mark_atom_dirty(rctx,
> &rctx->alphatest_state.atom);
> }
> if (rctx->alphatest_state.cb0_export_16bpc != export_16bpc) {
> rctx->alphatest_state.cb0_export_16bpc = export_16bpc;
> - rctx->alphatest_state.atom.dirty = true;
> + r600_mark_atom_dirty(rctx,
> &rctx->alphatest_state.atom);
> }
> }
>
> @@ -1366,28 +1366,28 @@ static void evergreen_set_framebuffer_state(struct
> pipe_context *ctx,
>
> if (state->zsbuf->format !=
> rctx->poly_offset_state.zs_format) {
> rctx->poly_offset_state.zs_format =
> state->zsbuf->format;
> - rctx->poly_offset_state.atom.dirty = true;
> + r600_mark_atom_dirty(rctx,
> &rctx->poly_offset_state.atom);
> }
>
> if (rctx->db_state.rsurf != surf) {
> rctx->db_state.rsurf = surf;
> - rctx->db_state.atom.dirty = true;
> - rctx->db_misc_state.atom.dirty = true;
> + r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
> + r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
> }
> } else if (rctx->db_state.rsurf) {
> rctx->db_state.rsurf = NULL;
> - rctx->db_state.atom.dirty = true;
> - rctx->db_misc_state.atom.dirty = true;
> + r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
> + r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
> }
>
> if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
> rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
> - rctx->cb_misc_state.atom.dirty = true;
> + r600_ma
[Mesa-dev] Mesa 10.6.4
Mesa 10.6.4 is now available. In this release we have a few GL specific fixes (in both dri drivers and the EGL loader), an updated mesa.icd file and a crashfix for the standalone glcpp tool. Anuj Phogat (6): mesa: Turn get_readpixels_transfer_ops() in to a global function meta: Fix transfer operations check in meta pbo path for readpixels meta: Abort meta pbo path if readpixels need signed-unsigned conversion meta: Don't do fragment color clamping in _mesa_meta_pbo_GetTexSubImage mesa: Add a helper function _mesa_need_luminance_to_rgb_conversion() meta: Fix reading luminance texture as rgba in _mesa_meta_pbo_GetTexSubImage() Ben Widawsky (1): i965/skl: Add production thread counts and URB size Eduardo Lima Mitev (3): mesa: Fix errors values returned by glShaderBinary() mesa: Validate target before resolving tex obj in glTex(ture)SubImageXD mesa: Fix error returned by glCopyTexImage2D() upon an invalid internal format Emil Velikov (7): docs: Add checksums for mesa 10.6.3 tarballs configure.ac: do not set HAVE_DRI(23) when libdrm is missing egl/wayland: libdrm is a hard requirement, treat it as such winsys/radeon: don't leak the fd when it is 0 bugzilla_mesa.sh: sort the bugs list by number Update version to 10.6.4 docs: add release notes for 10.6.4 Francisco Jerez (1): i965/fs: Fix fs_inst::regs_read() for sources in the ATTR file. Frank Binns (2): egl/dri: Add error info needed for EGL_EXT_image_dma_buf_import extension egl: Add eglQuerySurface surface type check for EGL_LARGEST_PBUFFER attrib Igor Gnatenko (1): opencl: use versioned .so in mesa.icd Ilia Mirkin (1): nvc0: fix geometry program revalidation of clipping params Kenneth Graunke (1): glsl: Fix a bug where LHS swizzles of swizzles were too small. Marek Olšák (6): st/mesa: don't call st_validate_state in BlitFramebuffer radeonsi: upload shader rodata after updating scratch relocations st/mesa: don't ignore texture buffer state changes radeonsi: rework how shader pointers to descriptors are set radeonsi: completely rework updating descriptors without CP DMA r600g: fix the CB_SHADER_MASK setup Samuel Iglesias Gonsalvez (1): glsl/glcpp: fix SIGSEGV when checking error condition for macro redefinition Samuel Pitoiset (1): nv50: avoid segfault with enabled but unbound vertex attrib git tag: mesa-10.6.4 ftp://ftp.freedesktop.org/pub/mesa/10.6.4/mesa-10.6.4.tar.gz MD5: b1eb05f242661d318eda92321f0b04ee mesa-10.6.4.tar.gz SHA1: f31703e80538d7c5be7d1e425d5aa6599b9485cc mesa-10.6.4.tar.gz SHA256: 4960bf17d8b5d6a6503c6954ec6cf480b5cd930797bac901c60bea192675f85e mesa-10.6.4.tar.gz PGP: ftp://ftp.freedesktop.org/pub/mesa/10.6.4/mesa-10.6.4.tar.gz.sig ftp://ftp.freedesktop.org/pub/mesa/10.6.4/mesa-10.6.4.tar.xz MD5: 45092471f7abef40a7deab281d7954ba mesa-10.6.4.tar.xz SHA1: 78b96dcad8c71ad69feb0b89a6ec95d0346f116a mesa-10.6.4.tar.xz SHA256: 8f5ac103f0f503de2f7a985b0df349bd4ecdfe7f51c714be146fa5a9a3c07b77 mesa-10.6.4.tar.xz PGP: ftp://ftp.freedesktop.org/pub/mesa/10.6.4/mesa-10.6.4.tar.xz.sig -- -Emil signature.asc Description: OpenPGP digital signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 5/5] i965: enable GL_ARB_shader_image_size
On Tue, Aug 11, 2015 at 9:43 AM, Martin Peres wrote: > Signed-off-by: Martin Peres > --- > docs/GL3.txt | 4 ++-- > docs/relnotes/11.0.0.html| 1 + > src/mesa/drivers/dri/i965/intel_extensions.c | 1 + > 3 files changed, 4 insertions(+), 2 deletions(-) > > diff --git a/docs/GL3.txt b/docs/GL3.txt > index 54c0c5a..5319e06 100644 > --- a/docs/GL3.txt > +++ b/docs/GL3.txt > @@ -163,7 +163,7 @@ GL 4.3, GLSL 4.30: >GL_ARB_multi_draw_indirect DONE (i965, nvc0, > r600, radeonsi, llvmpipe, softpipe) >GL_ARB_program_interface_query DONE (all drivers) >GL_ARB_robust_buffer_access_behavior not started > - GL_ARB_shader_image_size in progress (Martin > Peres) > + GL_ARB_shader_image_size DONE (i965) >GL_ARB_shader_storage_buffer_object in progress (Iago > Toral, Samuel Iglesias) >GL_ARB_stencil_texturing DONE (i965/gen8+, > nv50, nvc0, r600, radeonsi, llvmpipe, softpipe) >GL_ARB_texture_buffer_range DONE (nv50, nvc0, > i965, r600, radeonsi, llvmpipe) > @@ -211,7 +211,7 @@ GLES3.1, GLSL ES 3.1 >GL_ARB_program_interface_query DONE (all drivers) >GL_ARB_shader_atomic_countersDONE (i965) >GL_ARB_shader_image_load_store in progress (curro) Would you mind fixing this^ up to say DONE (i965) while you're here? > - GL_ARB_shader_image_size in progress (Martin > Peres) > + GL_ARB_shader_image_size DONE (i965) >GL_ARB_shader_storage_buffer_object in progress (Iago > Toral, Samuel Iglesias) >GL_ARB_shading_language_packing DONE (all drivers) >GL_ARB_separate_shader_objects DONE (all drivers) ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] Reworking mesa mapi (Was Re: [PATCH 2/2] glapi: remap_helper.py: remove unused argument 'es')
Hi Dylan, On 21/06/15 22:20, Dylan Baker wrote: > Cleanups are definitely party of the plan. I'm doing three phases. First > is going to mako for generation. Second is using the khronos XML. > Finally I want to clean things up and hybridize for python 3 > I'm thinking about doing some cleanup+fixes in mapi so I want to check with you, to minimise clashes. I will likely have to go through both makefiles and sources, so if you want to get your latest patches send/upstreamed that will be great. Alternatively if you have some plans/tips that'll be appreciated. Thanks Emil ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 2/2] nir: Don't try to scalarize unpack ops.
Avoids regressions in vc4 when trying to do our blending in NIR. v2: Add the other unpack ops I meant to when writing the original commit message. --- src/glsl/nir/nir_lower_alu_to_scalar.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/src/glsl/nir/nir_lower_alu_to_scalar.c b/src/glsl/nir/nir_lower_alu_to_scalar.c index 5d15fb2..efbe9e7 100644 --- a/src/glsl/nir/nir_lower_alu_to_scalar.c +++ b/src/glsl/nir/nir_lower_alu_to_scalar.c @@ -100,6 +100,21 @@ lower_alu_instr_scalar(nir_alu_instr *instr, void *mem_ctx) */ return; + case nir_op_unpack_unorm_4x8: + case nir_op_unpack_snorm_4x8: + case nir_op_unpack_unorm_2x16: + case nir_op_unpack_snorm_2x16: + /* There is no scalar version of these ops, unless we were to break it + * down to bitshifts and math (which is definitely not intended). + */ + return; + + case nir_op_unpack_half_2x16: + /* We could split this into unpack_half_2x16_split_[xy], but should + * we? + */ + return; + LOWER_REDUCTION(nir_op_fdot, nir_op_fmul, nir_op_fadd); LOWER_REDUCTION(nir_op_ball_fequal, nir_op_feq, nir_op_iand); LOWER_REDUCTION(nir_op_ball_iequal, nir_op_ieq, nir_op_iand); -- 2.1.4 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/2] nir: Add a nir_opt_undef() to handle csels with undef.
We may find a cause to do more undef optimization in the future, but for
now this fixes up things after if flattening. vc4 was handling this
internally most of the time, but a GLB2.7 shader that did a conditional
discard and assign gl_FragColor in the else was still emitting some extra
code.
total instructions in shared programs: 100809 -> 100795 (-0.01%)
instructions in affected programs: 37 -> 23 (-37.84%)
---
src/gallium/drivers/vc4/vc4_program.c | 1 +
src/glsl/Makefile.sources | 1 +
src/glsl/nir/nir.h| 2 +
src/glsl/nir/nir_opt_undef.c | 93 +++
4 files changed, 97 insertions(+)
create mode 100644 src/glsl/nir/nir_opt_undef.c
diff --git a/src/gallium/drivers/vc4/vc4_program.c
b/src/gallium/drivers/vc4/vc4_program.c
index e9120b7..4a3a277 100644
--- a/src/gallium/drivers/vc4/vc4_program.c
+++ b/src/gallium/drivers/vc4/vc4_program.c
@@ -1627,6 +1627,7 @@ vc4_optimize_nir(struct nir_shader *s)
progress = nir_opt_peephole_select(s) || progress;
progress = nir_opt_algebraic(s) || progress;
progress = nir_opt_constant_folding(s) || progress;
+progress = nir_opt_undef(s) || progress;
} while (progress);
}
diff --git a/src/glsl/Makefile.sources b/src/glsl/Makefile.sources
index a0e85ed..0b77244 100644
--- a/src/glsl/Makefile.sources
+++ b/src/glsl/Makefile.sources
@@ -56,6 +56,7 @@ NIR_FILES = \
nir/nir_opt_peephole_ffma.c \
nir/nir_opt_peephole_select.c \
nir/nir_opt_remove_phis.c \
+ nir/nir_opt_undef.c \
nir/nir_print.c \
nir/nir_remove_dead_variables.c \
nir/nir_search.c \
diff --git a/src/glsl/nir/nir.h b/src/glsl/nir/nir.h
index 9aae6d7..222a219 100644
--- a/src/glsl/nir/nir.h
+++ b/src/glsl/nir/nir.h
@@ -1704,6 +1704,8 @@ bool nir_opt_peephole_ffma(nir_shader *shader);
bool nir_opt_remove_phis(nir_shader *shader);
+bool nir_opt_undef(nir_shader *shader);
+
void nir_sweep(nir_shader *shader);
#ifdef __cplusplus
diff --git a/src/glsl/nir/nir_opt_undef.c b/src/glsl/nir/nir_opt_undef.c
new file mode 100644
index 000..89a75c4
--- /dev/null
+++ b/src/glsl/nir/nir_opt_undef.c
@@ -0,0 +1,93 @@
+/*
+ * Copyright © 2015 Broadcom
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "nir.h"
+
+/** @file nir_opt_undef.c
+ *
+ * Handles optimization of operations involving ssa_undef. For now, we just
+ * make sure that csels between undef and some other value just give the other
+ * value (on the assumption that the condition's going to be choosing the
+ * defined value). This reduces work after if flattening when each side of
+ * the if is defining a variable.
+ *
+ * Some day, we may find some use for making other operations consuming an
+ * undef arg output undef, but I don't know of any cases currently.
+ */
+
+static bool
+opt_undef_alu(nir_alu_instr *instr)
+{
+ if (instr->op != nir_op_bcsel && instr->op != nir_op_fcsel)
+ return false;
+
+ assert(instr->dest.dest.is_ssa);
+
+ for (int i = 1; i <= 2; i++) {
+ if (!instr->src[i].src.is_ssa)
+ continue;
+
+ nir_instr *parent = instr->src[i].src.ssa->parent_instr;
+ if (parent->type != nir_instr_type_ssa_undef)
+ continue;
+
+ nir_alu_src_copy(&instr->src[0], &instr->src[i == 1 ? 2 : 1],
+ ralloc_parent(instr));
+ nir_src empty_src;
+ memset(&empty_src, 0, sizeof(empty_src));
+ nir_instr_rewrite_src(&instr->instr, &instr->src[1].src, empty_src);
+ nir_instr_rewrite_src(&instr->instr, &instr->src[2].src, empty_src);
+ instr->op = nir_op_imov;
+
+ return true;
+ }
+
+ return false;
+}
+
+static bool
+opt_undef_block(nir_block *block, void *data)
+{
+ bool *progress = data;
+
+ nir_foreach_instr_safe(block, instr) {
+ if (instr->type == nir_instr_type_al
Re: [Mesa-dev] [PATCH 5/5] i965: enable GL_ARB_shader_image_size
Matt Turner writes: > On Tue, Aug 11, 2015 at 9:43 AM, Martin Peres > wrote: >> Signed-off-by: Martin Peres >> --- >> docs/GL3.txt | 4 ++-- >> docs/relnotes/11.0.0.html| 1 + >> src/mesa/drivers/dri/i965/intel_extensions.c | 1 + >> 3 files changed, 4 insertions(+), 2 deletions(-) >> >> diff --git a/docs/GL3.txt b/docs/GL3.txt >> index 54c0c5a..5319e06 100644 >> --- a/docs/GL3.txt >> +++ b/docs/GL3.txt >> @@ -163,7 +163,7 @@ GL 4.3, GLSL 4.30: >>GL_ARB_multi_draw_indirect DONE (i965, nvc0, >> r600, radeonsi, llvmpipe, softpipe) >>GL_ARB_program_interface_query DONE (all drivers) >>GL_ARB_robust_buffer_access_behavior not started >> - GL_ARB_shader_image_size in progress (Martin >> Peres) >> + GL_ARB_shader_image_size DONE (i965) >>GL_ARB_shader_storage_buffer_object in progress (Iago >> Toral, Samuel Iglesias) >>GL_ARB_stencil_texturing DONE (i965/gen8+, >> nv50, nvc0, r600, radeonsi, llvmpipe, softpipe) >>GL_ARB_texture_buffer_range DONE (nv50, nvc0, >> i965, r600, radeonsi, llvmpipe) >> @@ -211,7 +211,7 @@ GLES3.1, GLSL ES 3.1 >>GL_ARB_program_interface_query DONE (all drivers) >>GL_ARB_shader_atomic_countersDONE (i965) >>GL_ARB_shader_image_load_store in progress (curro) > > Would you mind fixing this^ up to say DONE (i965) while you're here? > It's not done :), there are a number of subtle differences and restrictions that apply to the GLES image load store API only, expect a series addressing those in a couple of days. >> - GL_ARB_shader_image_size in progress (Martin >> Peres) >> + GL_ARB_shader_image_size DONE (i965) >>GL_ARB_shader_storage_buffer_object in progress (Iago >> Toral, Samuel Iglesias) >>GL_ARB_shading_language_packing DONE (all drivers) >>GL_ARB_separate_shader_objects DONE (all drivers) > ___ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/mesa-dev signature.asc Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 2/2] nir: Don't try to scalarize unpack ops.
On Tue, Aug 11, 2015 at 11:25 AM, Eric Anholt wrote: > Avoids regressions in vc4 when trying to do our blending in NIR. > > v2: Add the other unpack ops I meant to when writing the original commit > message. > --- > src/glsl/nir/nir_lower_alu_to_scalar.c | 15 +++ > 1 file changed, 15 insertions(+) > > diff --git a/src/glsl/nir/nir_lower_alu_to_scalar.c > b/src/glsl/nir/nir_lower_alu_to_scalar.c > index 5d15fb2..efbe9e7 100644 > --- a/src/glsl/nir/nir_lower_alu_to_scalar.c > +++ b/src/glsl/nir/nir_lower_alu_to_scalar.c > @@ -100,6 +100,21 @@ lower_alu_instr_scalar(nir_alu_instr *instr, void > *mem_ctx) > */ >return; > > + case nir_op_unpack_unorm_4x8: > + case nir_op_unpack_snorm_4x8: > + case nir_op_unpack_unorm_2x16: > + case nir_op_unpack_snorm_2x16: > + /* There is no scalar version of these ops, unless we were to break it > + * down to bitshifts and math (which is definitely not intended). > + */ > + return; > + > + case nir_op_unpack_half_2x16: > + /* We could split this into unpack_half_2x16_split_[xy], but should > + * we? > + */ > + return; > + Reviewed-by: Matt Turner Seems like we should we add the pack opcodes as well? ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 1/2] nir: Add a nir_opt_undef() to handle csels with undef.
2015-08-11 20:25 GMT+02:00 Eric Anholt :
> We may find a cause to do more undef optimization in the future, but for
> now this fixes up things after if flattening. vc4 was handling this
> internally most of the time, but a GLB2.7 shader that did a conditional
> discard and assign gl_FragColor in the else was still emitting some extra
> code.
>
> total instructions in shared programs: 100809 -> 100795 (-0.01%)
> instructions in affected programs: 37 -> 23 (-37.84%)
> ---
> src/gallium/drivers/vc4/vc4_program.c | 1 +
> src/glsl/Makefile.sources | 1 +
> src/glsl/nir/nir.h| 2 +
> src/glsl/nir/nir_opt_undef.c | 93
> +++
> 4 files changed, 97 insertions(+)
> create mode 100644 src/glsl/nir/nir_opt_undef.c
>
> diff --git a/src/gallium/drivers/vc4/vc4_program.c
> b/src/gallium/drivers/vc4/vc4_program.c
> index e9120b7..4a3a277 100644
> --- a/src/gallium/drivers/vc4/vc4_program.c
> +++ b/src/gallium/drivers/vc4/vc4_program.c
> @@ -1627,6 +1627,7 @@ vc4_optimize_nir(struct nir_shader *s)
> progress = nir_opt_peephole_select(s) || progress;
> progress = nir_opt_algebraic(s) || progress;
> progress = nir_opt_constant_folding(s) || progress;
> +progress = nir_opt_undef(s) || progress;
> } while (progress);
> }
>
> diff --git a/src/glsl/Makefile.sources b/src/glsl/Makefile.sources
> index a0e85ed..0b77244 100644
> --- a/src/glsl/Makefile.sources
> +++ b/src/glsl/Makefile.sources
> @@ -56,6 +56,7 @@ NIR_FILES = \
> nir/nir_opt_peephole_ffma.c \
> nir/nir_opt_peephole_select.c \
> nir/nir_opt_remove_phis.c \
> + nir/nir_opt_undef.c \
> nir/nir_print.c \
> nir/nir_remove_dead_variables.c \
> nir/nir_search.c \
> diff --git a/src/glsl/nir/nir.h b/src/glsl/nir/nir.h
> index 9aae6d7..222a219 100644
> --- a/src/glsl/nir/nir.h
> +++ b/src/glsl/nir/nir.h
> @@ -1704,6 +1704,8 @@ bool nir_opt_peephole_ffma(nir_shader *shader);
>
> bool nir_opt_remove_phis(nir_shader *shader);
>
> +bool nir_opt_undef(nir_shader *shader);
> +
> void nir_sweep(nir_shader *shader);
>
> #ifdef __cplusplus
> diff --git a/src/glsl/nir/nir_opt_undef.c b/src/glsl/nir/nir_opt_undef.c
> new file mode 100644
> index 000..89a75c4
> --- /dev/null
> +++ b/src/glsl/nir/nir_opt_undef.c
> @@ -0,0 +1,93 @@
> +/*
> + * Copyright © 2015 Broadcom
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +#include "nir.h"
> +
> +/** @file nir_opt_undef.c
> + *
> + * Handles optimization of operations involving ssa_undef. For now, we just
> + * make sure that csels between undef and some other value just give the
> other
> + * value (on the assumption that the condition's going to be choosing the
> + * defined value). This reduces work after if flattening when each side of
> + * the if is defining a variable.
> + *
> + * Some day, we may find some use for making other operations consuming an
> + * undef arg output undef, but I don't know of any cases currently.
> + */
> +
> +static bool
> +opt_undef_alu(nir_alu_instr *instr)
> +{
> + if (instr->op != nir_op_bcsel && instr->op != nir_op_fcsel)
> + return false;
> +
> + assert(instr->dest.dest.is_ssa);
> +
> + for (int i = 1; i <= 2; i++) {
> + if (!instr->src[i].src.is_ssa)
> + continue;
> +
> + nir_instr *parent = instr->src[i].src.ssa->parent_instr;
> + if (parent->type != nir_instr_type_ssa_undef)
> + continue;
> +
> + nir_alu_src_copy(&instr->src[0], &instr->src[i == 1 ? 2 : 1],
> + ralloc_parent(instr));
> + nir_src empty_src;
> + memset(&empty_src, 0, sizeof(empty_src));
> + nir_instr_rewrite_src(&instr->instr, &instr->src[1].src, empty_src);
> + nir_instr_rewrite_src(&instr->instr, &instr->src[2].sr
Re: [Mesa-dev] [PATCH 2/2] nir: Don't try to scalarize unpack ops.
Matt Turner writes: > On Tue, Aug 11, 2015 at 11:25 AM, Eric Anholt wrote: >> Avoids regressions in vc4 when trying to do our blending in NIR. >> >> v2: Add the other unpack ops I meant to when writing the original commit >> message. >> --- >> src/glsl/nir/nir_lower_alu_to_scalar.c | 15 +++ >> 1 file changed, 15 insertions(+) >> >> diff --git a/src/glsl/nir/nir_lower_alu_to_scalar.c >> b/src/glsl/nir/nir_lower_alu_to_scalar.c >> index 5d15fb2..efbe9e7 100644 >> --- a/src/glsl/nir/nir_lower_alu_to_scalar.c >> +++ b/src/glsl/nir/nir_lower_alu_to_scalar.c >> @@ -100,6 +100,21 @@ lower_alu_instr_scalar(nir_alu_instr *instr, void >> *mem_ctx) >> */ >>return; >> >> + case nir_op_unpack_unorm_4x8: >> + case nir_op_unpack_snorm_4x8: >> + case nir_op_unpack_unorm_2x16: >> + case nir_op_unpack_snorm_2x16: >> + /* There is no scalar version of these ops, unless we were to break it >> + * down to bitshifts and math (which is definitely not intended). >> + */ >> + return; >> + >> + case nir_op_unpack_half_2x16: >> + /* We could split this into unpack_half_2x16_split_[xy], but should >> + * we? >> + */ >> + return; >> + > > Reviewed-by: Matt Turner > > Seems like we should we add the pack opcodes as well? I don't think any of the pack opcodes produce a vector value. signature.asc Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 1/2] i965: Add SKL support to brw_miptree_get_horizontal_slice_pitch().
On Tue, Aug 11, 2015 at 2:45 AM, Francisco Jerez wrote:
> Jason Ekstrand writes:
>
>> On Sat, Aug 8, 2015 at 2:58 AM, Francisco Jerez
>> wrote:
>>> Jason Ekstrand writes:
>>>
I'm not a huge fan of this patch. Really, given how complicated 3-D
textures are on SKL, there really is no sensible horizontal slice
pitch. We could return 0 as an "invalid value" but I think I'd rather
keep it an assert. Code that is dealing with 3-D textures should no
better than to just blindly call this function on SKL.
--Jason
>>>
>>> How so? The sub-tile structure may indeed be more complicated on SKL,
>>> but the way how Z-slices of whole tiles are laid out in 2D memory for 3D
>>> textures is even simpler than on earlier generations -- Say a given
>>> tile-slice of LOD l starts at 2D coordinates (x, y), the next tile-slice
>>> will start at (x, y + qpitch), IOW the horizontal offset between
>>> tile-slices is zero which is what this patch does. We could probably
>>> keep the assertion I had but that would complicate
>>> update_texture_image_param() a bit more so I'd rather do what AFAIUI is
>>> the right thing here.
>>
>> Doing a little spelunking, it appears as if the code this patch is
>> modifying is only used for setting up image uniforms (i.e., it's dead
>> at the moment) and was pushed without review. *sigh*
>>
>> Given that, this patch certainly doesn't break anything and seems to
>> do what you claim it does so I'm fine with it. That said, please do a
>> follow-on patch that actually documents these new tex_layout
>> entrypoints. In particular, it should be documented what value they
>> compute/return. The above description, re-written in a form more
>> appropriate for a comment, is probably sufficient for
>> get_horizontal_slice_pitch. Assuming the follow-on will happen,
>>
>
> There is some documentation about them in the intel_mipmap_tree.h header
> file, let me know if it's not sufficient for you so I write the
> follow-up.
Hrm... I thought we usually put documentation in the C file; I guess
not in the case of miptree code... oh, well.
Yes, I do think it should be expanded. Especially since the comment
explicitly mentions 2-d miptree layout but it's really for 3-d
textures. :-)
--Jason
>> Reviewed-by: Jason Ekstrand
>>
>> Go land things! You can also apply my R-B to the patch that enables
>> the extension (I don't want dig through my e-mail so I can respond to
>> the specific patch.)
>>
> Cool, thanks.
>
>> --Jason
>>
On Wed, May 13, 2015 at 9:37 AM, Francisco Jerez
wrote:
> ---
> src/mesa/drivers/dri/i965/brw_tex_layout.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
> b/src/mesa/drivers/dri/i965/brw_tex_layout.c
> index 72b02a2..6c6dc5c 100644
> --- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
> +++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
> @@ -281,9 +281,7 @@ brw_miptree_get_horizontal_slice_pitch(const struct
> brw_context *brw,
> const struct intel_mipmap_tree
> *mt,
> unsigned level)
> {
> - assert(brw->gen < 9);
> -
> - if (mt->target == GL_TEXTURE_3D ||
> + if ((brw->gen < 9 && mt->target == GL_TEXTURE_3D) ||
> (brw->gen == 4 && mt->target == GL_TEXTURE_CUBE_MAP)) {
>return ALIGN(minify(mt->physical_width0, level), mt->align_w);
> } else {
> --
> 2.3.5
>
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Re: [Mesa-dev] [PATCH] r600, compute: setup compute sampler states and views
On Mon, Aug 10, 2015 at 8:30 PM, Zoltan Gilian wrote:
> ---
> src/gallium/drivers/r600/evergreen_compute.c | 25 ++
> src/gallium/drivers/r600/evergreen_state.c | 30 --
> src/gallium/drivers/r600/evergreend.h| 5 +
> src/gallium/drivers/r600/r600_pipe.h | 7 +-
> src/gallium/drivers/r600/r600_state_common.c | 32
> ++--
> 5 files changed, 60 insertions(+), 39 deletions(-)
>
> diff --git a/src/gallium/drivers/r600/evergreen_compute.c
> b/src/gallium/drivers/r600/evergreen_compute.c
> index d71eeb9..e886847 100644
> --- a/src/gallium/drivers/r600/evergreen_compute.c
> +++ b/src/gallium/drivers/r600/evergreen_compute.c
> @@ -504,6 +504,12 @@ static void compute_emit_cs(struct r600_context *ctx,
> const uint *block_layout,
> /* Emit constant buffer state */
> r600_emit_atom(ctx, &ctx->constbuf_state[PIPE_SHADER_COMPUTE].atom);
>
> + /* Emit sampler state */
> + r600_emit_atom(ctx, &ctx->samplers[PIPE_SHADER_COMPUTE].states.atom);
> +
> + /* Emit sampler view (texture resource) state */
> + r600_emit_atom(ctx, &ctx->samplers[PIPE_SHADER_COMPUTE].views.atom);
> +
> /* Emit compute shader state */
> r600_emit_atom(ctx, &ctx->cs_shader_state.atom);
>
> @@ -674,25 +680,6 @@ static void evergreen_set_compute_resources(struct
> pipe_context * ctx_,
> }
> }
>
> -void evergreen_set_cs_sampler_view(struct pipe_context *ctx_,
> - unsigned start_slot, unsigned count,
> - struct pipe_sampler_view **views)
> -{
> - struct r600_pipe_sampler_view **resource =
> - (struct r600_pipe_sampler_view **)views;
> -
> - for (unsigned i = 0; i < count; i++){
> - if (resource[i]) {
> - assert(i+1 < 12);
> - /* XXX: Implement */
> - assert(!"Compute samplers not implemented.");
> - ///FETCH0 = VTX0 (param buffer),
> - //FETCH1 = VTX1 (global buffer pool), FETCH2... = TEX
> - }
> - }
> -}
> -
> -
> static void evergreen_set_global_binding(
> struct pipe_context *ctx_, unsigned first, unsigned n,
> struct pipe_resource **resources,
> diff --git a/src/gallium/drivers/r600/evergreen_state.c
> b/src/gallium/drivers/r600/evergreen_state.c
> index 688a092..5f68e08 100644
> --- a/src/gallium/drivers/r600/evergreen_state.c
> +++ b/src/gallium/drivers/r600/evergreen_state.c
> @@ -2029,7 +2029,7 @@ static void evergreen_emit_cs_constant_buffers(struct
> r600_context *rctx, struct
>
> static void evergreen_emit_sampler_views(struct r600_context *rctx,
> struct r600_samplerview_state *state,
> -unsigned resource_id_base)
> +unsigned resource_id_base, unsigned
> pkt_flags)
> {
> struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
> uint32_t dirty_mask = state->dirty_mask;
> @@ -2042,7 +2042,7 @@ static void evergreen_emit_sampler_views(struct
> r600_context *rctx,
> rview = state->views[resource_index];
> assert(rview);
>
> - radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
> + radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
> radeon_emit(cs, (resource_id_base + resource_index) * 8);
> radeon_emit_array(cs, rview->tex_resource_words, 8);
>
> @@ -2051,11 +2051,11 @@ static void evergreen_emit_sampler_views(struct
> r600_context *rctx,
>
> rview->tex_resource->b.b.nr_samples > 1 ?
>
> RADEON_PRIO_SHADER_TEXTURE_MSAA :
>
> RADEON_PRIO_SHADER_TEXTURE_RO);
> - radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
> + radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
> radeon_emit(cs, reloc);
>
> if (!rview->skip_mip_address_reloc) {
> - radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
> + radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
> radeon_emit(cs, reloc);
> }
> }
> @@ -2064,17 +2064,26 @@ static void evergreen_emit_sampler_views(struct
> r600_context *rctx,
>
> static void evergreen_emit_vs_sampler_views(struct r600_context *rctx,
> struct r600_atom *atom)
> {
> - evergreen_emit_sampler_views(rctx,
> &rctx->samplers[PIPE_SHADER_VERTEX].views, 176 + R600_MAX_CONST_BUFFERS);
> + evergreen_emit_sampler_views(rctx,
> &rctx->samplers[PIPE_SHADER_VERTEX].views,
> +176 + R600_MAX_CONST_BUFFERS, 0);
> }
>
> static void evergreen_emit_gs_sampler_views(struct r600_context *rctx,
> struct r600_atom *atom)
[Mesa-dev] [Bug 91596] EGL_KHR_gl_colorspace (v2) causes problem with Android-x86 GUI
https://bugs.freedesktop.org/show_bug.cgi?id=91596 --- Comment #3 from Mauro Rossi --- Hi, as a confirmation the described Android-x86 GUI problems are solved by reverting commit c2c2e9ab604793c6e01f85497f3f5bf645f962fa. I am available if you need further information or to test upcoming patches to EGL_KHR_gl_colorspace code. Mauro -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/2] i965: Optimize brw_inst_bits() and brw_compact_inst_bits().
Cuts about 1k of .text.
text data bss dec hex filename
5018165 19716027672 5242997 500075 i965_dri.so before
5017141 19716027672 5241973 4ffc75 i965_dri.so after
---
src/mesa/drivers/dri/i965/brw_inst.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_inst.h
b/src/mesa/drivers/dri/i965/brw_inst.h
index 7a8c210..5feea38 100644
--- a/src/mesa/drivers/dri/i965/brw_inst.h
+++ b/src/mesa/drivers/dri/i965/brw_inst.h
@@ -683,9 +683,9 @@ brw_inst_bits(const brw_inst *inst, unsigned high, unsigned
low)
high %= 64;
low %= 64;
- const uint64_t mask = (((1ull << (high - low + 1)) - 1) << low);
+ const uint64_t mask = ((1ull << (high - low + 1)) - 1);
- return (inst->data[word] & mask) >> low;
+ return ((inst->data[word] >> low) & mask);
}
/**
@@ -731,9 +731,9 @@ typedef struct {
static inline unsigned
brw_compact_inst_bits(brw_compact_inst *inst, unsigned high, unsigned low)
{
- const uint64_t mask = (((1ull << (high - low + 1)) - 1) << low);
+ const uint64_t mask = ((1ull << (high - low + 1)) - 1);
- return (inst->data & mask) >> low;
+ return ((inst->data >> low) & mask);
}
/**
--
2.4.6
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[Mesa-dev] [PATCH 2/2] i965: Optimize brw_inst_set_bits() and brw_compact_inst_set_bits().
Cuts about 2k of .text. text data bss dec hex filename 5017141 19716027672 5241973 4ffc75 i965_dri.so before 5014981 19716027672 5239813 4ff405 i965_dri.so after --- src/mesa/drivers/dri/i965/brw_inst.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_inst.h b/src/mesa/drivers/dri/i965/brw_inst.h index 5feea38..8fa70a8 100644 --- a/src/mesa/drivers/dri/i965/brw_inst.h +++ b/src/mesa/drivers/dri/i965/brw_inst.h @@ -707,7 +707,7 @@ brw_inst_set_bits(brw_inst *inst, unsigned high, unsigned low, uint64_t value) /* Make sure the supplied value actually fits in the given bitfield. */ assert((value & (mask >> low)) == value); - inst->data[word] = (inst->data[word] & ~mask) | ((value << low) & mask); + inst->data[word] = (inst->data[word] & ~mask) | (value << low); } #undef BRW_IA16_ADDR_IMM @@ -750,7 +750,7 @@ brw_compact_inst_set_bits(brw_compact_inst *inst, unsigned high, unsigned low, /* Make sure the supplied value actually fits in the given bitfield. */ assert((value & (mask >> low)) == value); - inst->data = (inst->data & ~mask) | ((value << low) & mask); + inst->data = (inst->data & ~mask) | (value << low); } #define F(name, high, low) \ -- 2.4.6 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 1/2] nir: Add a nir_opt_undef() to handle csels with undef.
2015-08-11 20:25 GMT+02:00 Eric Anholt :
> We may find a cause to do more undef optimization in the future, but for
> now this fixes up things after if flattening. vc4 was handling this
> internally most of the time, but a GLB2.7 shader that did a conditional
> discard and assign gl_FragColor in the else was still emitting some extra
> code.
>
> total instructions in shared programs: 100809 -> 100795 (-0.01%)
> instructions in affected programs: 37 -> 23 (-37.84%)
> ---
> src/gallium/drivers/vc4/vc4_program.c | 1 +
> src/glsl/Makefile.sources | 1 +
> src/glsl/nir/nir.h| 2 +
> src/glsl/nir/nir_opt_undef.c | 93
> +++
> 4 files changed, 97 insertions(+)
> create mode 100644 src/glsl/nir/nir_opt_undef.c
>
> diff --git a/src/gallium/drivers/vc4/vc4_program.c
> b/src/gallium/drivers/vc4/vc4_program.c
> index e9120b7..4a3a277 100644
> --- a/src/gallium/drivers/vc4/vc4_program.c
> +++ b/src/gallium/drivers/vc4/vc4_program.c
> @@ -1627,6 +1627,7 @@ vc4_optimize_nir(struct nir_shader *s)
> progress = nir_opt_peephole_select(s) || progress;
> progress = nir_opt_algebraic(s) || progress;
> progress = nir_opt_constant_folding(s) || progress;
> +progress = nir_opt_undef(s) || progress;
> } while (progress);
> }
>
> diff --git a/src/glsl/Makefile.sources b/src/glsl/Makefile.sources
> index a0e85ed..0b77244 100644
> --- a/src/glsl/Makefile.sources
> +++ b/src/glsl/Makefile.sources
> @@ -56,6 +56,7 @@ NIR_FILES = \
> nir/nir_opt_peephole_ffma.c \
> nir/nir_opt_peephole_select.c \
> nir/nir_opt_remove_phis.c \
> + nir/nir_opt_undef.c \
> nir/nir_print.c \
> nir/nir_remove_dead_variables.c \
> nir/nir_search.c \
> diff --git a/src/glsl/nir/nir.h b/src/glsl/nir/nir.h
> index 9aae6d7..222a219 100644
> --- a/src/glsl/nir/nir.h
> +++ b/src/glsl/nir/nir.h
> @@ -1704,6 +1704,8 @@ bool nir_opt_peephole_ffma(nir_shader *shader);
>
> bool nir_opt_remove_phis(nir_shader *shader);
>
> +bool nir_opt_undef(nir_shader *shader);
> +
> void nir_sweep(nir_shader *shader);
>
> #ifdef __cplusplus
> diff --git a/src/glsl/nir/nir_opt_undef.c b/src/glsl/nir/nir_opt_undef.c
> new file mode 100644
> index 000..89a75c4
> --- /dev/null
> +++ b/src/glsl/nir/nir_opt_undef.c
> @@ -0,0 +1,93 @@
> +/*
> + * Copyright © 2015 Broadcom
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +#include "nir.h"
> +
> +/** @file nir_opt_undef.c
> + *
> + * Handles optimization of operations involving ssa_undef. For now, we just
> + * make sure that csels between undef and some other value just give the
> other
> + * value (on the assumption that the condition's going to be choosing the
> + * defined value). This reduces work after if flattening when each side of
> + * the if is defining a variable.
> + *
> + * Some day, we may find some use for making other operations consuming an
> + * undef arg output undef, but I don't know of any cases currently.
> + */
> +
> +static bool
> +opt_undef_alu(nir_alu_instr *instr)
> +{
> + if (instr->op != nir_op_bcsel && instr->op != nir_op_fcsel)
> + return false;
> +
> + assert(instr->dest.dest.is_ssa);
> +
> + for (int i = 1; i <= 2; i++) {
> + if (!instr->src[i].src.is_ssa)
> + continue;
> +
> + nir_instr *parent = instr->src[i].src.ssa->parent_instr;
> + if (parent->type != nir_instr_type_ssa_undef)
> + continue;
> +
> + nir_alu_src_copy(&instr->src[0], &instr->src[i == 1 ? 2 : 1],
> + ralloc_parent(instr));
With this changed to:
nir_instr_rewrite_src(&instr->instr, &instr->src[0].src,
instr->src[i == 1 ? 2 : 1].src);
this patch is
Reviewed-by: Thomas Helland
Shader-db without vec4 on i
Re: [Mesa-dev] [PATCH 1/2] i965: Optimize brw_inst_bits() and brw_compact_inst_bits().
On Tuesday, August 11, 2015 01:29:46 PM Matt Turner wrote:
> Cuts about 1k of .text.
>
>text data bss dec hex filename
> 5018165 19716027672 5242997 500075 i965_dri.so before
> 5017141 19716027672 5241973 4ffc75 i965_dri.so after
> ---
> src/mesa/drivers/dri/i965/brw_inst.h | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_inst.h
> b/src/mesa/drivers/dri/i965/brw_inst.h
> index 7a8c210..5feea38 100644
> --- a/src/mesa/drivers/dri/i965/brw_inst.h
> +++ b/src/mesa/drivers/dri/i965/brw_inst.h
> @@ -683,9 +683,9 @@ brw_inst_bits(const brw_inst *inst, unsigned high,
> unsigned low)
> high %= 64;
> low %= 64;
>
> - const uint64_t mask = (((1ull << (high - low + 1)) - 1) << low);
> + const uint64_t mask = ((1ull << (high - low + 1)) - 1);
Every + line in this patch has bonus parens around the entire
expression, which are unnecessary - personally, I'd drop them.
But that's a stylistic preference, and it's totally your call.
Both patches are:
Reviewed-by: Kenneth Graunke
Nice find!
>
> - return (inst->data[word] & mask) >> low;
> + return ((inst->data[word] >> low) & mask);
> }
>
> /**
> @@ -731,9 +731,9 @@ typedef struct {
> static inline unsigned
> brw_compact_inst_bits(brw_compact_inst *inst, unsigned high, unsigned low)
> {
> - const uint64_t mask = (((1ull << (high - low + 1)) - 1) << low);
> + const uint64_t mask = ((1ull << (high - low + 1)) - 1);
>
> - return (inst->data & mask) >> low;
> + return ((inst->data >> low) & mask);
> }
>
> /**
>
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[Mesa-dev] [PATCH] gallium: add support for GLES texture float extensions
From: Marek Olšák --- src/gallium/docs/source/screen.rst | 2 ++ src/gallium/drivers/freedreno/freedreno_screen.c | 1 + src/gallium/drivers/i915/i915_screen.c | 1 + src/gallium/drivers/ilo/ilo_screen.c | 1 + src/gallium/drivers/llvmpipe/lp_screen.c | 1 + src/gallium/drivers/nouveau/nv30/nv30_screen.c | 1 + src/gallium/drivers/nouveau/nv50/nv50_screen.c | 1 + src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 1 + src/gallium/drivers/r300/r300_screen.c | 1 + src/gallium/drivers/r600/r600_pipe.c | 1 + src/gallium/drivers/radeonsi/si_pipe.c | 1 + src/gallium/drivers/softpipe/sp_screen.c | 1 + src/gallium/drivers/svga/svga_screen.c | 1 + src/gallium/drivers/vc4/vc4_screen.c | 1 + src/gallium/include/pipe/p_defines.h | 1 + src/mesa/state_tracker/st_extensions.c | 12 16 files changed, 28 insertions(+) diff --git a/src/gallium/docs/source/screen.rst b/src/gallium/docs/source/screen.rst index dbdccc7..3b2a470 100644 --- a/src/gallium/docs/source/screen.rst +++ b/src/gallium/docs/source/screen.rst @@ -258,6 +258,8 @@ The integer capabilities: How many per-patch outputs and inputs are supported between tessellation control and tessellation evaluation shaders, not counting in TESSINNER and TESSOUTER. The minimum allowed value for OpenGL is 30. +* ``PIPE_CAP_TEXTURE_FLOAT_LINEAR``: Whether the linear minification and + magnification filters are supported with floating-point textures. .. _pipe_capf: diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c b/src/gallium/drivers/freedreno/freedreno_screen.c index 417d7c6..4cc6494 100644 --- a/src/gallium/drivers/freedreno/freedreno_screen.c +++ b/src/gallium/drivers/freedreno/freedreno_screen.c @@ -222,6 +222,7 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_RESOURCE_FROM_USER_MEMORY: case PIPE_CAP_DEVICE_RESET_STATUS_QUERY: case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS: + case PIPE_CAP_TEXTURE_FLOAT_LINEAR: return 0; case PIPE_CAP_MAX_VIEWPORTS: diff --git a/src/gallium/drivers/i915/i915_screen.c b/src/gallium/drivers/i915/i915_screen.c index 6083687..05691be 100644 --- a/src/gallium/drivers/i915/i915_screen.c +++ b/src/gallium/drivers/i915/i915_screen.c @@ -244,6 +244,7 @@ i915_get_param(struct pipe_screen *screen, enum pipe_cap cap) case PIPE_CAP_RESOURCE_FROM_USER_MEMORY: case PIPE_CAP_DEVICE_RESET_STATUS_QUERY: case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS: + case PIPE_CAP_TEXTURE_FLOAT_LINEAR: return 0; case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: diff --git a/src/gallium/drivers/ilo/ilo_screen.c b/src/gallium/drivers/ilo/ilo_screen.c index 338643e..12c538a 100644 --- a/src/gallium/drivers/ilo/ilo_screen.c +++ b/src/gallium/drivers/ilo/ilo_screen.c @@ -451,6 +451,7 @@ ilo_get_param(struct pipe_screen *screen, enum pipe_cap param) case PIPE_CAP_TEXTURE_GATHER_SM5: return 0; case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT: + case PIPE_CAP_TEXTURE_FLOAT_LINEAR: return true; case PIPE_CAP_FAKE_SW_MSAA: case PIPE_CAP_TEXTURE_QUERY_LOD: diff --git a/src/gallium/drivers/llvmpipe/lp_screen.c b/src/gallium/drivers/llvmpipe/lp_screen.c index 1c6c82e..a935e20 100644 --- a/src/gallium/drivers/llvmpipe/lp_screen.c +++ b/src/gallium/drivers/llvmpipe/lp_screen.c @@ -288,6 +288,7 @@ llvmpipe_get_param(struct pipe_screen *screen, enum pipe_cap param) case PIPE_CAP_VERTEXID_NOBASE: return 0; case PIPE_CAP_POLYGON_OFFSET_CLAMP: + case PIPE_CAP_TEXTURE_FLOAT_LINEAR: return 1; case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: case PIPE_CAP_RESOURCE_FROM_USER_MEMORY: diff --git a/src/gallium/drivers/nouveau/nv30/nv30_screen.c b/src/gallium/drivers/nouveau/nv30/nv30_screen.c index 97cf058..3a03843 100644 --- a/src/gallium/drivers/nouveau/nv30/nv30_screen.c +++ b/src/gallium/drivers/nouveau/nv30/nv30_screen.c @@ -164,6 +164,7 @@ nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_RESOURCE_FROM_USER_MEMORY: case PIPE_CAP_DEVICE_RESET_STATUS_QUERY: case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS: + case PIPE_CAP_TEXTURE_FLOAT_LINEAR: return 0; case PIPE_CAP_VENDOR_ID: diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.c b/src/gallium/drivers/nouveau/nv50/nv50_screen.c index d869544..1107bef 100644 --- a/src/gallium/drivers/nouveau/nv50/nv50_screen.c +++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.c @@ -176,6 +176,7 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_CLIP_HALFZ: case PIPE_CAP_POLYGON_OFFSET_CLAMP: case PIPE_CAP_QUERY_PIPELINE_STATISTICS: + case PIPE_CAP_TEXTURE_FLOAT_LINEAR: return 1; case PIPE_CAP_SEAMLESS_CUBE_MAP: return 1; /* class_3d >= NVA0_3D_CLASS; */ diff --git a/src/galliu
[Mesa-dev] [PATCH] st/mesa: small cleanup in st_extensions.c
From: Marek Olšák
---
src/mesa/state_tracker/st_extensions.c | 40 --
1 file changed, 9 insertions(+), 31 deletions(-)
diff --git a/src/mesa/state_tracker/st_extensions.c
b/src/mesa/state_tracker/st_extensions.c
index 5459891..77d6201 100644
--- a/src/mesa/state_tracker/st_extensions.c
+++ b/src/mesa/state_tracker/st_extensions.c
@@ -434,12 +434,14 @@ void st_init_extensions(struct pipe_screen *screen,
static const struct st_extension_cap_mapping cap_mapping[] = {
{ o(ARB_base_instance),PIPE_CAP_START_INSTANCE
},
- { o(ARB_buffer_storage),
PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT },
+ { o(ARB_buffer_storage),
PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT },
+ { o(ARB_color_buffer_float), PIPE_CAP_VERTEX_COLOR_UNCLAMPED
},
{ o(ARB_depth_clamp), PIPE_CAP_DEPTH_CLIP_DISABLE
},
{ o(ARB_depth_texture),PIPE_CAP_TEXTURE_SHADOW_MAP
},
{ o(ARB_draw_buffers_blend), PIPE_CAP_INDEP_BLEND_FUNC
},
{ o(ARB_draw_instanced), PIPE_CAP_TGSI_INSTANCEID
},
{ o(ARB_fragment_program_shadow), PIPE_CAP_TEXTURE_SHADOW_MAP
},
+ { o(ARB_framebuffer_object), PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
},
{ o(ARB_instanced_arrays),
PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR },
{ o(ARB_occlusion_query), PIPE_CAP_OCCLUSION_QUERY
},
{ o(ARB_occlusion_query2), PIPE_CAP_OCCLUSION_QUERY
},
@@ -449,6 +451,8 @@ void st_init_extensions(struct pipe_screen *screen,
{ o(ARB_shader_stencil_export),PIPE_CAP_SHADER_STENCIL_EXPORT
},
{ o(ARB_shader_texture_lod), PIPE_CAP_SM3
},
{ o(ARB_shadow), PIPE_CAP_TEXTURE_SHADOW_MAP
},
+ { o(ARB_texture_buffer_object),PIPE_CAP_TEXTURE_BUFFER_OBJECTS
},
+ { o(ARB_texture_gather),
PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS},
{ o(ARB_texture_mirror_clamp_to_edge), PIPE_CAP_TEXTURE_MIRROR_CLAMP
},
{ o(ARB_texture_non_power_of_two), PIPE_CAP_NPOT_TEXTURES
},
{ o(ARB_timer_query), PIPE_CAP_QUERY_TIMESTAMP
},
@@ -469,6 +473,7 @@ void st_init_extensions(struct pipe_screen *screen,
{ o(ATI_separate_stencil), PIPE_CAP_TWO_SIDED_STENCIL
},
{ o(ATI_texture_mirror_once), PIPE_CAP_TEXTURE_MIRROR_CLAMP
},
{ o(NV_conditional_render),PIPE_CAP_CONDITIONAL_RENDER
},
+ { o(NV_primitive_restart), PIPE_CAP_PRIMITIVE_RESTART
},
{ o(NV_texture_barrier), PIPE_CAP_TEXTURE_BARRIER
},
/* GL_NV_point_sprite is not supported by gallium because we don't
* support the GL_POINT_SPRITE_R_MODE_NV option. */
@@ -579,7 +584,8 @@ void st_init_extensions(struct pipe_screen *screen,
PIPE_FORMAT_R8G8B8A8_UNORM },
GL_TRUE }, /* at least one format must be supported */
- { { o(ARB_stencil_texturing) },
+ { { o(ARB_stencil_texturing),
+ o(ARB_texture_stencil8) },
{ PIPE_FORMAT_X24S8_UINT,
PIPE_FORMAT_S8X24_UINT },
GL_TRUE }, /* at least one format must be supported */
@@ -673,9 +679,6 @@ void st_init_extensions(struct pipe_screen *screen,
ARRAY_SIZE(vertex_mapping), PIPE_BUFFER,
PIPE_BIND_VERTEX_BUFFER);
- if (extensions->ARB_stencil_texturing)
- extensions->ARB_texture_stencil8 = GL_TRUE;
-
if (screen->get_param(screen, PIPE_CAP_TEXTURE_FLOAT_LINEAR)) {
extensions->OES_texture_float_linear = extensions->OES_texture_float;
extensions->OES_texture_half_float_linear =
@@ -753,27 +756,11 @@ void st_init_extensions(struct pipe_screen *screen,
extensions->ANGLE_texture_compression_dxt = GL_FALSE;
}
- if (screen->get_shader_param(screen, PIPE_SHADER_GEOMETRY,
-PIPE_SHADER_CAP_MAX_INSTRUCTIONS) > 0) {
-#if 0 /* XXX re-enable when GLSL compiler again supports geometry shaders */
- extensions->ARB_geometry_shader4 = GL_TRUE;
-#endif
- }
-
if (screen->get_shader_param(screen, PIPE_SHADER_TESS_CTRL,
PIPE_SHADER_CAP_MAX_INSTRUCTIONS) > 0) {
extensions->ARB_tessellation_shader = GL_TRUE;
}
- if (screen->get_param(screen, PIPE_CAP_PRIMITIVE_RESTART)) {
- extensions->NV_primitive_restart = GL_TRUE;
- }
-
- /* ARB_color_buffer_float. */
- if (screen->get_param(screen, PIPE_CAP_VERTEX_COLOR_UNCLAMPED)) {
- extensions->ARB_color_buffer_float = GL_TRUE
Re: [Mesa-dev] [PATCH] gallium: add support for GLES texture float extensions
Marek, take a look at http://people.freedesktop.org/~imirkin/glxinfo/glxinfo.html#p=es&v=Vendor Note that a4xx supports all 4 exts, but a3xx supports half_float_linear but not float_linear. Thoughts? On Tue, Aug 11, 2015 at 5:25 PM, Marek Olšák wrote: > From: Marek Olšák > > --- > src/gallium/docs/source/screen.rst | 2 ++ > src/gallium/drivers/freedreno/freedreno_screen.c | 1 + > src/gallium/drivers/i915/i915_screen.c | 1 + > src/gallium/drivers/ilo/ilo_screen.c | 1 + > src/gallium/drivers/llvmpipe/lp_screen.c | 1 + > src/gallium/drivers/nouveau/nv30/nv30_screen.c | 1 + > src/gallium/drivers/nouveau/nv50/nv50_screen.c | 1 + > src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 1 + > src/gallium/drivers/r300/r300_screen.c | 1 + > src/gallium/drivers/r600/r600_pipe.c | 1 + > src/gallium/drivers/radeonsi/si_pipe.c | 1 + > src/gallium/drivers/softpipe/sp_screen.c | 1 + > src/gallium/drivers/svga/svga_screen.c | 1 + > src/gallium/drivers/vc4/vc4_screen.c | 1 + > src/gallium/include/pipe/p_defines.h | 1 + > src/mesa/state_tracker/st_extensions.c | 12 > 16 files changed, 28 insertions(+) > > diff --git a/src/gallium/docs/source/screen.rst > b/src/gallium/docs/source/screen.rst > index dbdccc7..3b2a470 100644 > --- a/src/gallium/docs/source/screen.rst > +++ b/src/gallium/docs/source/screen.rst > @@ -258,6 +258,8 @@ The integer capabilities: >How many per-patch outputs and inputs are supported between tessellation >control and tessellation evaluation shaders, not counting in TESSINNER and >TESSOUTER. The minimum allowed value for OpenGL is 30. > +* ``PIPE_CAP_TEXTURE_FLOAT_LINEAR``: Whether the linear minification and > + magnification filters are supported with floating-point textures. > > > .. _pipe_capf: > diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c > b/src/gallium/drivers/freedreno/freedreno_screen.c > index 417d7c6..4cc6494 100644 > --- a/src/gallium/drivers/freedreno/freedreno_screen.c > +++ b/src/gallium/drivers/freedreno/freedreno_screen.c > @@ -222,6 +222,7 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum > pipe_cap param) > case PIPE_CAP_RESOURCE_FROM_USER_MEMORY: > case PIPE_CAP_DEVICE_RESET_STATUS_QUERY: > case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS: > + case PIPE_CAP_TEXTURE_FLOAT_LINEAR: > return 0; > > case PIPE_CAP_MAX_VIEWPORTS: > diff --git a/src/gallium/drivers/i915/i915_screen.c > b/src/gallium/drivers/i915/i915_screen.c > index 6083687..05691be 100644 > --- a/src/gallium/drivers/i915/i915_screen.c > +++ b/src/gallium/drivers/i915/i915_screen.c > @@ -244,6 +244,7 @@ i915_get_param(struct pipe_screen *screen, enum pipe_cap > cap) > case PIPE_CAP_RESOURCE_FROM_USER_MEMORY: > case PIPE_CAP_DEVICE_RESET_STATUS_QUERY: > case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS: > + case PIPE_CAP_TEXTURE_FLOAT_LINEAR: >return 0; > > case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: > diff --git a/src/gallium/drivers/ilo/ilo_screen.c > b/src/gallium/drivers/ilo/ilo_screen.c > index 338643e..12c538a 100644 > --- a/src/gallium/drivers/ilo/ilo_screen.c > +++ b/src/gallium/drivers/ilo/ilo_screen.c > @@ -451,6 +451,7 @@ ilo_get_param(struct pipe_screen *screen, enum pipe_cap > param) > case PIPE_CAP_TEXTURE_GATHER_SM5: >return 0; > case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT: > + case PIPE_CAP_TEXTURE_FLOAT_LINEAR: >return true; > case PIPE_CAP_FAKE_SW_MSAA: > case PIPE_CAP_TEXTURE_QUERY_LOD: > diff --git a/src/gallium/drivers/llvmpipe/lp_screen.c > b/src/gallium/drivers/llvmpipe/lp_screen.c > index 1c6c82e..a935e20 100644 > --- a/src/gallium/drivers/llvmpipe/lp_screen.c > +++ b/src/gallium/drivers/llvmpipe/lp_screen.c > @@ -288,6 +288,7 @@ llvmpipe_get_param(struct pipe_screen *screen, enum > pipe_cap param) > case PIPE_CAP_VERTEXID_NOBASE: >return 0; > case PIPE_CAP_POLYGON_OFFSET_CLAMP: > + case PIPE_CAP_TEXTURE_FLOAT_LINEAR: >return 1; > case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: > case PIPE_CAP_RESOURCE_FROM_USER_MEMORY: > diff --git a/src/gallium/drivers/nouveau/nv30/nv30_screen.c > b/src/gallium/drivers/nouveau/nv30/nv30_screen.c > index 97cf058..3a03843 100644 > --- a/src/gallium/drivers/nouveau/nv30/nv30_screen.c > +++ b/src/gallium/drivers/nouveau/nv30/nv30_screen.c > @@ -164,6 +164,7 @@ nv30_screen_get_param(struct pipe_screen *pscreen, enum > pipe_cap param) > case PIPE_CAP_RESOURCE_FROM_USER_MEMORY: > case PIPE_CAP_DEVICE_RESET_STATUS_QUERY: > case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS: > + case PIPE_CAP_TEXTURE_FLOAT_LINEAR: >return 0; > > case PIPE_CAP_VENDOR_ID: > diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.c > b/src/gallium/drivers/nouveau/nv50/nv50_screen.c > index d869544..1107bef 100644 > --- a/src/gallium/d
Re: [Mesa-dev] [PATCH] st/mesa: small cleanup in st_extensions.c
Reviewed-by: Ilia Mirkin
On Tue, Aug 11, 2015 at 5:26 PM, Marek Olšák wrote:
> From: Marek Olšák
>
> ---
> src/mesa/state_tracker/st_extensions.c | 40
> --
> 1 file changed, 9 insertions(+), 31 deletions(-)
>
> diff --git a/src/mesa/state_tracker/st_extensions.c
> b/src/mesa/state_tracker/st_extensions.c
> index 5459891..77d6201 100644
> --- a/src/mesa/state_tracker/st_extensions.c
> +++ b/src/mesa/state_tracker/st_extensions.c
> @@ -434,12 +434,14 @@ void st_init_extensions(struct pipe_screen *screen,
>
> static const struct st_extension_cap_mapping cap_mapping[] = {
>{ o(ARB_base_instance),PIPE_CAP_START_INSTANCE
> },
> - { o(ARB_buffer_storage),
> PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT },
> + { o(ARB_buffer_storage),
> PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT },
> + { o(ARB_color_buffer_float), PIPE_CAP_VERTEX_COLOR_UNCLAMPED
> },
>{ o(ARB_depth_clamp), PIPE_CAP_DEPTH_CLIP_DISABLE
> },
>{ o(ARB_depth_texture),PIPE_CAP_TEXTURE_SHADOW_MAP
> },
>{ o(ARB_draw_buffers_blend), PIPE_CAP_INDEP_BLEND_FUNC
> },
>{ o(ARB_draw_instanced), PIPE_CAP_TGSI_INSTANCEID
> },
>{ o(ARB_fragment_program_shadow), PIPE_CAP_TEXTURE_SHADOW_MAP
> },
> + { o(ARB_framebuffer_object),
> PIPE_CAP_MIXED_FRAMEBUFFER_SIZES },
>{ o(ARB_instanced_arrays),
> PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR },
>{ o(ARB_occlusion_query), PIPE_CAP_OCCLUSION_QUERY
> },
>{ o(ARB_occlusion_query2), PIPE_CAP_OCCLUSION_QUERY
> },
> @@ -449,6 +451,8 @@ void st_init_extensions(struct pipe_screen *screen,
>{ o(ARB_shader_stencil_export),PIPE_CAP_SHADER_STENCIL_EXPORT
> },
>{ o(ARB_shader_texture_lod), PIPE_CAP_SM3
> },
>{ o(ARB_shadow), PIPE_CAP_TEXTURE_SHADOW_MAP
> },
> + { o(ARB_texture_buffer_object),PIPE_CAP_TEXTURE_BUFFER_OBJECTS
> },
> + { o(ARB_texture_gather),
> PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS},
>{ o(ARB_texture_mirror_clamp_to_edge), PIPE_CAP_TEXTURE_MIRROR_CLAMP
> },
>{ o(ARB_texture_non_power_of_two), PIPE_CAP_NPOT_TEXTURES
> },
>{ o(ARB_timer_query), PIPE_CAP_QUERY_TIMESTAMP
> },
> @@ -469,6 +473,7 @@ void st_init_extensions(struct pipe_screen *screen,
>{ o(ATI_separate_stencil), PIPE_CAP_TWO_SIDED_STENCIL
> },
>{ o(ATI_texture_mirror_once), PIPE_CAP_TEXTURE_MIRROR_CLAMP
> },
>{ o(NV_conditional_render),PIPE_CAP_CONDITIONAL_RENDER
> },
> + { o(NV_primitive_restart), PIPE_CAP_PRIMITIVE_RESTART
> },
>{ o(NV_texture_barrier), PIPE_CAP_TEXTURE_BARRIER
> },
>/* GL_NV_point_sprite is not supported by gallium because we don't
> * support the GL_POINT_SPRITE_R_MODE_NV option. */
> @@ -579,7 +584,8 @@ void st_init_extensions(struct pipe_screen *screen,
>PIPE_FORMAT_R8G8B8A8_UNORM },
> GL_TRUE }, /* at least one format must be supported */
>
> - { { o(ARB_stencil_texturing) },
> + { { o(ARB_stencil_texturing),
> + o(ARB_texture_stencil8) },
> { PIPE_FORMAT_X24S8_UINT,
>PIPE_FORMAT_S8X24_UINT },
> GL_TRUE }, /* at least one format must be supported */
> @@ -673,9 +679,6 @@ void st_init_extensions(struct pipe_screen *screen,
>ARRAY_SIZE(vertex_mapping), PIPE_BUFFER,
>PIPE_BIND_VERTEX_BUFFER);
>
> - if (extensions->ARB_stencil_texturing)
> - extensions->ARB_texture_stencil8 = GL_TRUE;
> -
> if (screen->get_param(screen, PIPE_CAP_TEXTURE_FLOAT_LINEAR)) {
>extensions->OES_texture_float_linear = extensions->OES_texture_float;
>extensions->OES_texture_half_float_linear =
> @@ -753,27 +756,11 @@ void st_init_extensions(struct pipe_screen *screen,
>extensions->ANGLE_texture_compression_dxt = GL_FALSE;
> }
>
> - if (screen->get_shader_param(screen, PIPE_SHADER_GEOMETRY,
> -PIPE_SHADER_CAP_MAX_INSTRUCTIONS) > 0) {
> -#if 0 /* XXX re-enable when GLSL compiler again supports geometry shaders */
> - extensions->ARB_geometry_shader4 = GL_TRUE;
> -#endif
> - }
> -
> if (screen->get_shader_param(screen, PIPE_SHADER_TESS_CTRL,
> PIPE_SHADER_CAP_MAX_INSTRUCTIONS) > 0) {
>extensions->ARB_tessellation_shader = GL_TRUE;
>
Re: [Mesa-dev] [PATCH] gallium: add support for GLES texture float extensions
FWIW d3d10 has the same requirements, the "any filter" needs to be supported for half float formats, but is optional for float formats (d3d10.1 made it required for floats). https://msdn.microsoft.com/en-us/library/windows/desktop/cc627090%28v=vs.85%29.aspx So there might well be some more hw where this distinction matters. (I am actually not sure if some hw exists which can support fp16 textures but not filter those, but it may well exist as well...) Roland Am 11.08.2015 um 23:31 schrieb Ilia Mirkin: > Marek, take a look at > > https://urldefense.proofpoint.com/v2/url?u=http-3A__people.freedesktop.org_-7Eimirkin_glxinfo_glxinfo.html-23p-3Des-26v-3DVendor&d=BQIGaQ&c=Sqcl0Ez6M0X8aeM67LKIiDJAXVeAw-YihVMNtXt-uEs&r=Vjtt0vs_iqoI31UfJxBl7yv9I2FeiaeAYgMTLKRBc_I&m=OkMiJkJEj5ds-m5m2oxrnCCFE3bMkkKpNEmbVjwlc5Q&s=d7nQU9RZIsjSWR1o4YW4E55BXoW-Pw6v3UFDh5sivrY&e= > > > Note that a4xx supports all 4 exts, but a3xx supports > half_float_linear but not float_linear. Thoughts? > > On Tue, Aug 11, 2015 at 5:25 PM, Marek Olšák wrote: >> From: Marek Olšák >> >> --- >> src/gallium/docs/source/screen.rst | 2 ++ >> src/gallium/drivers/freedreno/freedreno_screen.c | 1 + >> src/gallium/drivers/i915/i915_screen.c | 1 + >> src/gallium/drivers/ilo/ilo_screen.c | 1 + >> src/gallium/drivers/llvmpipe/lp_screen.c | 1 + >> src/gallium/drivers/nouveau/nv30/nv30_screen.c | 1 + >> src/gallium/drivers/nouveau/nv50/nv50_screen.c | 1 + >> src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 1 + >> src/gallium/drivers/r300/r300_screen.c | 1 + >> src/gallium/drivers/r600/r600_pipe.c | 1 + >> src/gallium/drivers/radeonsi/si_pipe.c | 1 + >> src/gallium/drivers/softpipe/sp_screen.c | 1 + >> src/gallium/drivers/svga/svga_screen.c | 1 + >> src/gallium/drivers/vc4/vc4_screen.c | 1 + >> src/gallium/include/pipe/p_defines.h | 1 + >> src/mesa/state_tracker/st_extensions.c | 12 >> 16 files changed, 28 insertions(+) >> >> diff --git a/src/gallium/docs/source/screen.rst >> b/src/gallium/docs/source/screen.rst >> index dbdccc7..3b2a470 100644 >> --- a/src/gallium/docs/source/screen.rst >> +++ b/src/gallium/docs/source/screen.rst >> @@ -258,6 +258,8 @@ The integer capabilities: >>How many per-patch outputs and inputs are supported between tessellation >>control and tessellation evaluation shaders, not counting in TESSINNER and >>TESSOUTER. The minimum allowed value for OpenGL is 30. >> +* ``PIPE_CAP_TEXTURE_FLOAT_LINEAR``: Whether the linear minification and >> + magnification filters are supported with floating-point textures. >> >> >> .. _pipe_capf: >> diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c >> b/src/gallium/drivers/freedreno/freedreno_screen.c >> index 417d7c6..4cc6494 100644 >> --- a/src/gallium/drivers/freedreno/freedreno_screen.c >> +++ b/src/gallium/drivers/freedreno/freedreno_screen.c >> @@ -222,6 +222,7 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum >> pipe_cap param) >> case PIPE_CAP_RESOURCE_FROM_USER_MEMORY: >> case PIPE_CAP_DEVICE_RESET_STATUS_QUERY: >> case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS: >> + case PIPE_CAP_TEXTURE_FLOAT_LINEAR: >> return 0; >> >> case PIPE_CAP_MAX_VIEWPORTS: >> diff --git a/src/gallium/drivers/i915/i915_screen.c >> b/src/gallium/drivers/i915/i915_screen.c >> index 6083687..05691be 100644 >> --- a/src/gallium/drivers/i915/i915_screen.c >> +++ b/src/gallium/drivers/i915/i915_screen.c >> @@ -244,6 +244,7 @@ i915_get_param(struct pipe_screen *screen, enum pipe_cap >> cap) >> case PIPE_CAP_RESOURCE_FROM_USER_MEMORY: >> case PIPE_CAP_DEVICE_RESET_STATUS_QUERY: >> case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS: >> + case PIPE_CAP_TEXTURE_FLOAT_LINEAR: >>return 0; >> >> case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: >> diff --git a/src/gallium/drivers/ilo/ilo_screen.c >> b/src/gallium/drivers/ilo/ilo_screen.c >> index 338643e..12c538a 100644 >> --- a/src/gallium/drivers/ilo/ilo_screen.c >> +++ b/src/gallium/drivers/ilo/ilo_screen.c >> @@ -451,6 +451,7 @@ ilo_get_param(struct pipe_screen *screen, enum pipe_cap >> param) >> case PIPE_CAP_TEXTURE_GATHER_SM5: >>return 0; >> case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT: >> + case PIPE_CAP_TEXTURE_FLOAT_LINEAR: >>return true; >> case PIPE_CAP_FAKE_SW_MSAA: >> case PIPE_CAP_TEXTURE_QUERY_LOD: >> diff --git a/src/gallium/drivers/llvmpipe/lp_screen.c >> b/src/gallium/drivers/llvmpipe/lp_screen.c >> index 1c6c82e..a935e20 100644 >> --- a/src/gallium/drivers/llvmpipe/lp_screen.c >> +++ b/src/gallium/drivers/llvmpipe/lp_screen.c >> @@ -288,6 +288,7 @@ llvmpipe_get_param(struct pipe_screen *screen, enum >> pipe_cap param) >> case PIPE_CAP_VERTEXID_NOBASE: >>return 0; >> case PIPE_CAP_POLYGON_OFFSET_CLAMP: >> + case PIPE_CAP_TEXTURE_FLOAT_LIN
Re: [Mesa-dev] [PATCH] gallium: add support for GLES texture float extensions
On Tue, Aug 11, 2015 at 2:25 PM, Marek Olšák wrote: > From: Marek Olšák > > --- Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74329 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 1/2] nir: Add a nir_opt_undef() to handle csels with undef.
On Tue, Aug 11, 2015 at 1:31 PM, Thomas Helland
wrote:
> 2015-08-11 20:25 GMT+02:00 Eric Anholt :
>> We may find a cause to do more undef optimization in the future, but for
>> now this fixes up things after if flattening. vc4 was handling this
>> internally most of the time, but a GLB2.7 shader that did a conditional
>> discard and assign gl_FragColor in the else was still emitting some extra
>> code.
>>
>> total instructions in shared programs: 100809 -> 100795 (-0.01%)
>> instructions in affected programs: 37 -> 23 (-37.84%)
>> ---
>> src/gallium/drivers/vc4/vc4_program.c | 1 +
>> src/glsl/Makefile.sources | 1 +
>> src/glsl/nir/nir.h| 2 +
>> src/glsl/nir/nir_opt_undef.c | 93
>> +++
>> 4 files changed, 97 insertions(+)
>> create mode 100644 src/glsl/nir/nir_opt_undef.c
>>
>> diff --git a/src/gallium/drivers/vc4/vc4_program.c
>> b/src/gallium/drivers/vc4/vc4_program.c
>> index e9120b7..4a3a277 100644
>> --- a/src/gallium/drivers/vc4/vc4_program.c
>> +++ b/src/gallium/drivers/vc4/vc4_program.c
>> @@ -1627,6 +1627,7 @@ vc4_optimize_nir(struct nir_shader *s)
>> progress = nir_opt_peephole_select(s) || progress;
>> progress = nir_opt_algebraic(s) || progress;
>> progress = nir_opt_constant_folding(s) || progress;
>> +progress = nir_opt_undef(s) || progress;
>> } while (progress);
>> }
>>
>> diff --git a/src/glsl/Makefile.sources b/src/glsl/Makefile.sources
>> index a0e85ed..0b77244 100644
>> --- a/src/glsl/Makefile.sources
>> +++ b/src/glsl/Makefile.sources
>> @@ -56,6 +56,7 @@ NIR_FILES = \
>> nir/nir_opt_peephole_ffma.c \
>> nir/nir_opt_peephole_select.c \
>> nir/nir_opt_remove_phis.c \
>> + nir/nir_opt_undef.c \
>> nir/nir_print.c \
>> nir/nir_remove_dead_variables.c \
>> nir/nir_search.c \
>> diff --git a/src/glsl/nir/nir.h b/src/glsl/nir/nir.h
>> index 9aae6d7..222a219 100644
>> --- a/src/glsl/nir/nir.h
>> +++ b/src/glsl/nir/nir.h
>> @@ -1704,6 +1704,8 @@ bool nir_opt_peephole_ffma(nir_shader *shader);
>>
>> bool nir_opt_remove_phis(nir_shader *shader);
>>
>> +bool nir_opt_undef(nir_shader *shader);
>> +
>> void nir_sweep(nir_shader *shader);
>>
>> #ifdef __cplusplus
>> diff --git a/src/glsl/nir/nir_opt_undef.c b/src/glsl/nir/nir_opt_undef.c
>> new file mode 100644
>> index 000..89a75c4
>> --- /dev/null
>> +++ b/src/glsl/nir/nir_opt_undef.c
>> @@ -0,0 +1,93 @@
>> +/*
>> + * Copyright © 2015 Broadcom
>> + *
>> + * Permission is hereby granted, free of charge, to any person obtaining a
>> + * copy of this software and associated documentation files (the
>> "Software"),
>> + * to deal in the Software without restriction, including without limitation
>> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>> + * and/or sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice (including the next
>> + * paragraph) shall be included in all copies or substantial portions of the
>> + * Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
>> OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
>> OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
>> DEALINGS
>> + * IN THE SOFTWARE.
>> + */
>> +
>> +#include "nir.h"
>> +
>> +/** @file nir_opt_undef.c
>> + *
>> + * Handles optimization of operations involving ssa_undef. For now, we just
>> + * make sure that csels between undef and some other value just give the
>> other
>> + * value (on the assumption that the condition's going to be choosing the
>> + * defined value). This reduces work after if flattening when each side of
>> + * the if is defining a variable.
>> + *
>> + * Some day, we may find some use for making other operations consuming an
>> + * undef arg output undef, but I don't know of any cases currently.
>> + */
>> +
>> +static bool
>> +opt_undef_alu(nir_alu_instr *instr)
>> +{
>> + if (instr->op != nir_op_bcsel && instr->op != nir_op_fcsel)
>> + return false;
>> +
>> + assert(instr->dest.dest.is_ssa);
>> +
>> + for (int i = 1; i <= 2; i++) {
>> + if (!instr->src[i].src.is_ssa)
>> + continue;
>> +
>> + nir_instr *parent = instr->src[i].src.ssa->parent_instr;
>> + if (parent->type != nir_instr_type_ssa_undef)
>> + continue;
>> +
>> + nir_alu_src_copy(&instr->src[0], &instr->src[i == 1 ? 2 : 1],
>> + ralloc_parent(instr));
>
> With this changed to:
>
> ni
[Mesa-dev] [Bug 85203] [DRI2][RadeonSI] Pageflip completion event has impossible msc.
https://bugs.freedesktop.org/show_bug.cgi?id=85203 Andrei Slavoiu changed: What|Removed |Added CC||ansl...@yahoo.com -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 73465] latest mesa from git doesn't compile on powerpc
https://bugs.freedesktop.org/show_bug.cgi?id=73465 Matt Turner changed: What|Removed |Added Status|NEW |RESOLVED Resolution|--- |WORKSFORME --- Comment #1 from Matt Turner --- Likely fixed by now. -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 91591] rounding.h:102:2: error: #error "Unsupported or undefined LONG_BIT"
https://bugs.freedesktop.org/show_bug.cgi?id=91591 Matt Turner changed: What|Removed |Added Status|NEW |RESOLVED Resolution|--- |FIXED --- Comment #15 from Matt Turner --- Thanks. Pushed as commit 02a4fe22b137d4bc8378bedd8319109fd23a50e3 Author: Matt Turner Date: Tue Aug 11 15:21:03 2015 -0700 configure.ac: Always define __STDC_LIMIT_MACROS. -- You are receiving this mail because: You are the QA Contact for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH v2 21/21] i965/gen7: Resolve GCC sign-compare warning.
2015-08-06 10:47 GMT+02:00 Rhys Kidd :
> That is correct Thomas. I do not have commit access to push these myself.
>
Oh, wow. Top-quoting is bad. Sorry about that.
After a discussion with Matt we decided that I'll pull these
down, add my R-b, and put it in a branch with some of my
own reviewed patches. I'll then get someone to merge the
patches some time before the 11.0 branchpoint (21st August).
BR,
Thomas
> On 6 August 2015 at 18:35, Thomas Helland wrote:
>>
>> The series looks good. You could probably s/GLuint/unsigned
>> in patch three as it is not "in the API", but that's a nitpick.
>> (You're fixing warnings, and not making things worse)
>> Either way the series is:
>>
>> Reviewed-by: Thomas Helland
>>
>> Someone else needs to push these for you (?).
>> AFAIK you don't have commit access, and neither do I.
>>
>> 2015-08-06 8:34 GMT+02:00 Rhys Kidd :
>> > mesa/src/mesa/drivers/dri/i965/gen7_sol_state.c: In function
>> > 'gen7_upload_3dstate_so_decl_list':
>> > mesa/src/mesa/drivers/dri/i965/gen7_sol_state.c:119:22: warning:
>> > comparison between signed and unsigned integer expressions [-Wsign-compare]
>> > for (int i = 0; i < linked_xfb_info->NumOutputs; i++) {
>> > ^
>> >
>> > Signed-off-by: Rhys Kidd
>> > ---
>> > src/mesa/drivers/dri/i965/gen7_sol_state.c | 2 +-
>> > 1 file changed, 1 insertion(+), 1 deletion(-)
>> >
>> > diff --git a/src/mesa/drivers/dri/i965/gen7_sol_state.c
>> > b/src/mesa/drivers/dri/i965/gen7_sol_state.c
>> > index 41573a8..8cd2fc4 100644
>> > --- a/src/mesa/drivers/dri/i965/gen7_sol_state.c
>> > +++ b/src/mesa/drivers/dri/i965/gen7_sol_state.c
>> > @@ -116,7 +116,7 @@ gen7_upload_3dstate_so_decl_list(struct brw_context
>> > *brw,
>> > /* Construct the list of SO_DECLs to be emitted. The formatting of
>> > the
>> > * command is feels strange -- each dword pair contains a SO_DECL
>> > per stream.
>> > */
>> > - for (int i = 0; i < linked_xfb_info->NumOutputs; i++) {
>> > + for (unsigned i = 0; i < linked_xfb_info->NumOutputs; i++) {
>> >int buffer = linked_xfb_info->Outputs[i].OutputBuffer;
>> >uint16_t decl = 0;
>> >int varying = linked_xfb_info->Outputs[i].OutputRegister;
>> > --
>> > 2.1.4
>> >
>> > ___
>> > mesa-dev mailing list
>> > mesa-dev@lists.freedesktop.org
>> > http://lists.freedesktop.org/mailman/listinfo/mesa-dev
>> ___
>> mesa-dev mailing list
>> mesa-dev@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/mesa-dev
>
>
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 2/5] radeonsi: add support for gl_PrimitiveID in the fragment shader
From: Marek Olšák
It must be obtained from the VS.
The GS scenario A must be enabled for PrimID to be generated for the VS.
+ 4 piglits
---
src/gallium/drivers/radeonsi/si_shader.c| 22 +++---
src/gallium/drivers/radeonsi/si_shader.h| 12
src/gallium/drivers/radeonsi/si_state.c | 1 -
src/gallium/drivers/radeonsi/si_state_shaders.c | 23 ++-
4 files changed, 49 insertions(+), 9 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_shader.c
b/src/gallium/drivers/radeonsi/si_shader.c
index 9c3b59c..4288e9b 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -73,6 +73,7 @@ struct si_shader_context
int param_streamout_offset[4];
int param_vertex_id;
int param_rel_auto_id;
+ int param_vs_prim_id;
int param_instance_id;
int param_tes_u;
int param_tes_v;
@@ -486,6 +487,9 @@ static LLVMValueRef get_primitive_id(struct
lp_build_tgsi_context *bld_base,
return bld_base->uint_bld.zero;
switch (si_shader_ctx->type) {
+ case TGSI_PROCESSOR_VERTEX:
+ return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
+ si_shader_ctx->param_vs_prim_id);
case TGSI_PROCESSOR_TESS_CTRL:
return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
SI_PARAM_PATCH_ID);
@@ -2027,7 +2031,7 @@ static void si_llvm_emit_vs_epilogue(struct
lp_build_tgsi_context * bld_base)
struct si_shader_output_values *outputs = NULL;
int i,j;
- outputs = MALLOC(info->num_outputs * sizeof(outputs[0]));
+ outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
for (i = 0; i < info->num_outputs; i++) {
outputs[i].name = info->output_semantic_name[i];
@@ -2040,7 +2044,19 @@ static void si_llvm_emit_vs_epilogue(struct
lp_build_tgsi_context * bld_base)
"");
}
- si_llvm_export_vs(bld_base, outputs, info->num_outputs);
+ /* Export PrimitiveID when PS needs it. */
+ if (si_vs_exports_prim_id(si_shader_ctx->shader)) {
+ outputs[i].name = TGSI_SEMANTIC_PRIMID;
+ outputs[i].sid = 0;
+ outputs[i].values[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
+ get_primitive_id(bld_base, 0));
+ outputs[i].values[1] = bld_base->base.undef;
+ outputs[i].values[2] = bld_base->base.undef;
+ outputs[i].values[3] = bld_base->base.undef;
+ i++;
+ }
+
+ si_llvm_export_vs(bld_base, outputs, i);
FREE(outputs);
}
@@ -3432,7 +3448,7 @@ static void create_function(struct si_shader_context
*si_shader_ctx)
/* VGPRs */
params[si_shader_ctx->param_vertex_id = num_params++] = i32;
params[si_shader_ctx->param_rel_auto_id = num_params++] = i32;
- params[num_params++] = i32; /* unused */
+ params[si_shader_ctx->param_vs_prim_id = num_params++] = i32;
params[si_shader_ctx->param_instance_id = num_params++] = i32;
break;
diff --git a/src/gallium/drivers/radeonsi/si_shader.h
b/src/gallium/drivers/radeonsi/si_shader.h
index 82e9c91..cd845c1 100644
--- a/src/gallium/drivers/radeonsi/si_shader.h
+++ b/src/gallium/drivers/radeonsi/si_shader.h
@@ -221,6 +221,7 @@ union si_shader_key {
uint64_tes_enabled_outputs;
unsignedas_es:1; /* export shader */
unsignedas_ls:1; /* local shader */
+ unsignedexport_prim_id; /* when PS needs it and GS is
disabled */
} vs;
struct {
unsignedprim_mode:3;
@@ -231,6 +232,7 @@ union si_shader_key {
* This describes how outputs are laid out in memory. */
uint64_tes_enabled_outputs;
unsignedas_es:1; /* export shader */
+ unsignedexport_prim_id; /* when PS needs it and GS is
disabled */
} tes; /* tessellation evaluation shader */
};
@@ -289,6 +291,16 @@ static inline struct si_shader* si_get_vs_state(struct
si_context *sctx)
return sctx->vs_shader->current;
}
+static inline bool si_vs_exports_prim_id(struct si_shader *shader)
+{
+ if (shader->selector->type == PIPE_SHADER_VERTEX)
+ return shader->key.vs.export_prim_id;
+ else if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
+ return shader->key.tes.export_prim_id;
+ else
+ return false;
+}
+
/* radeonsi_shader.c */
int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
struct si_shader *shader);
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/galliu
[Mesa-dev] [PATCH 4/5] radeonsi: revert a wrong DB bug workaround for VI
From: Marek Olšák The bug was misunderstood. Besides that, the bug affects a DB feature we don't use yet. --- src/gallium/drivers/radeonsi/si_state.c | 4 1 file changed, 4 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 863991c..c628288 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -1990,10 +1990,6 @@ static void si_init_depth_surface(struct si_context *sctx, db_htile_surface = 0; } - /* Bug workaround. */ - if (sctx->b.chip_class >= VI) - s_info |= S_028044_TILE_STENCIL_DISABLE(1); - assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0); surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) | -- 2.1.4 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 5/5] radeonsi: fix polygon offset scale
From: Marek Olšák The value was copied from r300g, which uses 1/12 subpixels, but this hw uses 1/16 subpixels. Fixes piglit: gl-1.4-polygon-offset (formerly a glean test) --- src/gallium/drivers/radeonsi/si_state.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index c628288..d768305 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -666,7 +666,7 @@ static void *si_create_rs_state(struct pipe_context *ctx, /* offset */ rs->offset_units = state->offset_units; - rs->offset_scale = state->offset_scale * 12.0f; + rs->offset_scale = state->offset_scale * 16.0f; si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, S_0286D4_FLAT_SHADE_ENA(1) | -- 2.1.4 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/5] radeonsi: move VGT_GS_MODE to the VS state
From: Marek Olšák The VS will want to select GS scenario A here (VS with PrimitiveID). --- src/gallium/drivers/radeonsi/si_state_shaders.c | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c index 854cf1e..19efbbf 100644 --- a/src/gallium/drivers/radeonsi/si_state_shaders.c +++ b/src/gallium/drivers/radeonsi/si_state_shaders.c @@ -314,6 +314,12 @@ static void si_shader_vs(struct si_shader *shader) if (pm4 == NULL) return; + /* If this is the GS copy shader, the GS state writes this register. +* Otherwise, the VS state writes it. +*/ + if (!shader->is_gs_copy_shader) + si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, 0); + va = shader->bo->gpu_address; si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA); @@ -1293,8 +1299,6 @@ static void si_update_vgt_shader_config(struct si_context *sctx) } si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages); - if (!sctx->gs_shader) - si_pm4_set_reg(*pm4, R_028A40_VGT_GS_MODE, 0); } si_pm4_bind_state(sctx, vgt_shader_config, *pm4); } -- 2.1.4 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 3/5] radeonsi: enable VS_OUT_MISC_SIDE_BUS_ENA
From: Marek Olšák This is recommended for better performance. Diag tests always enable this. --- src/gallium/drivers/radeonsi/si_state.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index bd11c4b..863991c 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -496,6 +496,7 @@ static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom) info->writes_edgeflag || info->writes_layer || info->writes_viewport_index) | + S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1) | (sctx->queued.named.rasterizer->clip_plane_enable & clipdist_mask)); r600_write_context_reg(cs, R_028810_PA_CL_CLIP_CNTL, -- 2.1.4 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/2] r600g: fix polygon offset scale
From: Marek Olšák
The value was copied from r300g, which uses 1/12 subpixels, but this hw
uses 1/16 subpixels.
Should fix piglit: gl-1.4-polygon-offset (formerly a glean test)
(untested, ported from radeonsi)
---
src/gallium/drivers/r600/evergreen_state.c | 2 +-
src/gallium/drivers/r600/r600_state.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index f7a76f6..95987ee 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -485,7 +485,7 @@ static void *evergreen_create_rs_state(struct pipe_context
*ctx,
/* offset */
rs->offset_units = state->offset_units;
- rs->offset_scale = state->offset_scale * 12.0f;
+ rs->offset_scale = state->offset_scale * 16.0f;
rs->offset_enable = state->offset_point || state->offset_line ||
state->offset_tri;
if (state->point_size_per_vertex) {
diff --git a/src/gallium/drivers/r600/r600_state.c
b/src/gallium/drivers/r600/r600_state.c
index 8488188..5cc2283 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -473,7 +473,7 @@ static void *r600_create_rs_state(struct pipe_context *ctx,
/* offset */
rs->offset_units = state->offset_units;
- rs->offset_scale = state->offset_scale * 12.0f;
+ rs->offset_scale = state->offset_scale * 16.0f;
rs->offset_enable = state->offset_point || state->offset_line ||
state->offset_tri;
if (state->point_size_per_vertex) {
--
2.1.4
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[Mesa-dev] [PATCH 2/2] r600g: allow setting geometry shader sampler states
From: Marek Olšák
We were ignoring them. This is both hilarious and sad.
Cc: mesa-sta...@lists.freedesktop.org
---
src/gallium/drivers/r600/r600_state_common.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_state_common.c
b/src/gallium/drivers/r600/r600_state_common.c
index 8d0942f..ee47791 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -407,11 +407,6 @@ static void r600_bind_sampler_states(struct pipe_context
*pipe,
assert(start == 0); /* XXX fix below */
- if (shader != PIPE_SHADER_VERTEX &&
- shader != PIPE_SHADER_FRAGMENT) {
- return;
- }
-
for (i = 0; i < count; i++) {
struct r600_pipe_sampler_state *rstate = rstates[i];
--
2.1.4
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[Mesa-dev] [PATCH 2/4] mesa/formats: refactor by removing compressed formats
From: Nanley Chery All compressed formats return GL_FALSE. Remove all switch cases for compressed formats. Compressed formats should be at the bottom of the switch statement, so ordering is still preserved. Cc: Jason Ekstrand Signed-off-by: Nanley Chery --- src/mesa/main/formats.c | 47 ++- 1 file changed, 2 insertions(+), 45 deletions(-) diff --git a/src/mesa/main/formats.c b/src/mesa/main/formats.c index 97b74fe..90fa75b 100644 --- a/src/mesa/main/formats.c +++ b/src/mesa/main/formats.c @@ -1552,6 +1552,8 @@ _mesa_format_matches_format_and_type(mesa_format mesa_format, * significant. A type with _REV indicates that the assignments are * swapped, so they are listed from least significant to most significant. * +* Compressed formats will fall through and return GL_FALSE. +* * For sanity, please keep this switch statement ordered the same as the * enums in formats.h. */ @@ -1812,26 +1814,6 @@ _mesa_format_matches_format_and_type(mesa_format mesa_format, case MESA_FORMAT_S_UINT8: return format == GL_STENCIL_INDEX && type == GL_UNSIGNED_BYTE; - case MESA_FORMAT_SRGB_DXT1: - case MESA_FORMAT_SRGBA_DXT1: - case MESA_FORMAT_SRGBA_DXT3: - case MESA_FORMAT_SRGBA_DXT5: - return GL_FALSE; - - case MESA_FORMAT_RGB_FXT1: - case MESA_FORMAT_RGBA_FXT1: - case MESA_FORMAT_RGB_DXT1: - case MESA_FORMAT_RGBA_DXT1: - case MESA_FORMAT_RGBA_DXT3: - case MESA_FORMAT_RGBA_DXT5: - return GL_FALSE; - - case MESA_FORMAT_BPTC_RGBA_UNORM: - case MESA_FORMAT_BPTC_SRGB_ALPHA_UNORM: - case MESA_FORMAT_BPTC_RGB_SIGNED_FLOAT: - case MESA_FORMAT_BPTC_RGB_UNSIGNED_FLOAT: - return GL_FALSE; - case MESA_FORMAT_RGBA_FLOAT32: return format == GL_RGBA && type == GL_FLOAT && !swapBytes; case MESA_FORMAT_RGBA_FLOAT16: @@ -2028,31 +2010,6 @@ _mesa_format_matches_format_and_type(mesa_format mesa_format, return format == GL_RGBA && type == GL_UNSIGNED_SHORT && !swapBytes; - case MESA_FORMAT_R_RGTC1_UNORM: - case MESA_FORMAT_R_RGTC1_SNORM: - case MESA_FORMAT_RG_RGTC2_UNORM: - case MESA_FORMAT_RG_RGTC2_SNORM: - return GL_FALSE; - - case MESA_FORMAT_L_LATC1_UNORM: - case MESA_FORMAT_L_LATC1_SNORM: - case MESA_FORMAT_LA_LATC2_UNORM: - case MESA_FORMAT_LA_LATC2_SNORM: - return GL_FALSE; - - case MESA_FORMAT_ETC1_RGB8: - case MESA_FORMAT_ETC2_RGB8: - case MESA_FORMAT_ETC2_SRGB8: - case MESA_FORMAT_ETC2_RGBA8_EAC: - case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC: - case MESA_FORMAT_ETC2_R11_EAC: - case MESA_FORMAT_ETC2_RG11_EAC: - case MESA_FORMAT_ETC2_SIGNED_R11_EAC: - case MESA_FORMAT_ETC2_SIGNED_RG11_EAC: - case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1: - case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1: - return GL_FALSE; - case MESA_FORMAT_A_SNORM8: return format == GL_ALPHA && type == GL_BYTE; case MESA_FORMAT_L_SNORM8: -- 2.5.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 3/4] mesa/formats: add more MESA_FORMAT_LAYOUTs
From: Nanley Chery
Add the classes of compressed formats as layouts. This will make determining if
a texture is an ASTC format simpler.
Cc: Jason Ekstrand
Signed-off-by: Nanley Chery
---
src/mesa/main/format_info.py | 4 +++-
src/mesa/main/formats.c | 6 ++
src/mesa/main/formats.h | 6 ++
src/mesa/main/texcompress.c | 30 ++
4 files changed, 21 insertions(+), 25 deletions(-)
diff --git a/src/mesa/main/format_info.py b/src/mesa/main/format_info.py
index 3bae57e..b9f12f3 100644
--- a/src/mesa/main/format_info.py
+++ b/src/mesa/main/format_info.py
@@ -103,8 +103,10 @@ def get_mesa_layout(fmat):
return 'MESA_FORMAT_LAYOUT_ARRAY'
elif fmat.layout == 'packed':
return 'MESA_FORMAT_LAYOUT_PACKED'
- else:
+ elif fmat.layout == 'other':
return 'MESA_FORMAT_LAYOUT_OTHER'
+ else:
+ return 'MESA_FORMAT_LAYOUT_' + fmat.layout.upper()
def get_channel_bits(fmat, chan_name):
if fmat.is_compressed():
diff --git a/src/mesa/main/formats.c b/src/mesa/main/formats.c
index 90fa75b..cb5ad21 100644
--- a/src/mesa/main/formats.c
+++ b/src/mesa/main/formats.c
@@ -188,6 +188,12 @@ _mesa_get_format_max_bits(mesa_format format)
* The return value will be one of:
*MESA_FORMAT_LAYOUT_ARRAY
*MESA_FORMAT_LAYOUT_PACKED
+ *MESA_FORMAT_LAYOUT_S3TC
+ *MESA_FORMAT_LAYOUT_RGTC
+ *MESA_FORMAT_LAYOUT_FXT1
+ *MESA_FORMAT_LAYOUT_ETC1
+ *MESA_FORMAT_LAYOUT_ETC2
+ *MESA_FORMAT_LAYOUT_BPTC
*MESA_FORMAT_LAYOUT_OTHER
*/
extern enum mesa_format_layout
diff --git a/src/mesa/main/formats.h b/src/mesa/main/formats.h
index e08247e..2fdd9bf 100644
--- a/src/mesa/main/formats.h
+++ b/src/mesa/main/formats.h
@@ -64,6 +64,12 @@ extern "C" {
enum mesa_format_layout {
MESA_FORMAT_LAYOUT_ARRAY,
MESA_FORMAT_LAYOUT_PACKED,
+ MESA_FORMAT_LAYOUT_S3TC,
+ MESA_FORMAT_LAYOUT_RGTC,
+ MESA_FORMAT_LAYOUT_FXT1,
+ MESA_FORMAT_LAYOUT_ETC1,
+ MESA_FORMAT_LAYOUT_ETC2,
+ MESA_FORMAT_LAYOUT_BPTC,
MESA_FORMAT_LAYOUT_OTHER,
};
diff --git a/src/mesa/main/texcompress.c b/src/mesa/main/texcompress.c
index 0fd1a36..edfb036 100644
--- a/src/mesa/main/texcompress.c
+++ b/src/mesa/main/texcompress.c
@@ -586,34 +586,16 @@ _mesa_compressed_image_address(GLint col, GLint row,
GLint img,
compressed_fetch_func
_mesa_get_compressed_fetch_func(mesa_format format)
{
- switch (format) {
- case MESA_FORMAT_RGB_DXT1:
- case MESA_FORMAT_RGBA_DXT1:
- case MESA_FORMAT_RGBA_DXT3:
- case MESA_FORMAT_RGBA_DXT5:
- case MESA_FORMAT_SRGB_DXT1:
- case MESA_FORMAT_SRGBA_DXT1:
- case MESA_FORMAT_SRGBA_DXT3:
- case MESA_FORMAT_SRGBA_DXT5:
+ switch (_mesa_get_format_layout(format)) {
+ case MESA_FORMAT_LAYOUT_S3TC:
return _mesa_get_dxt_fetch_func(format);
- case MESA_FORMAT_RGB_FXT1:
- case MESA_FORMAT_RGBA_FXT1:
+ case MESA_FORMAT_LAYOUT_FXT1:
return _mesa_get_fxt_fetch_func(format);
- case MESA_FORMAT_R_RGTC1_UNORM:
- case MESA_FORMAT_L_LATC1_UNORM:
- case MESA_FORMAT_R_RGTC1_SNORM:
- case MESA_FORMAT_L_LATC1_SNORM:
- case MESA_FORMAT_RG_RGTC2_UNORM:
- case MESA_FORMAT_LA_LATC2_UNORM:
- case MESA_FORMAT_RG_RGTC2_SNORM:
- case MESA_FORMAT_LA_LATC2_SNORM:
+ case MESA_FORMAT_LAYOUT_RGTC:
return _mesa_get_compressed_rgtc_func(format);
- case MESA_FORMAT_ETC1_RGB8:
+ case MESA_FORMAT_LAYOUT_ETC1:
return _mesa_get_etc_fetch_func(format);
- case MESA_FORMAT_BPTC_RGBA_UNORM:
- case MESA_FORMAT_BPTC_SRGB_ALPHA_UNORM:
- case MESA_FORMAT_BPTC_RGB_SIGNED_FLOAT:
- case MESA_FORMAT_BPTC_RGB_UNSIGNED_FLOAT:
+ case MESA_FORMAT_LAYOUT_BPTC:
return _mesa_get_bptc_fetch_func(format);
default:
return NULL;
--
2.5.0
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[Mesa-dev] [PATCH 4/4] mesa/formats: refactor by globbing on types in switch statement
From: Nanley Chery Combine the adjacent cases which have the same GL type in the switch statemnt. Signed-off-by: Nanley Chery --- src/mesa/main/formats.c | 152 ++-- 1 file changed, 17 insertions(+), 135 deletions(-) diff --git a/src/mesa/main/formats.c b/src/mesa/main/formats.c index cb5ad21..9b9d79b 100644 --- a/src/mesa/main/formats.c +++ b/src/mesa/main/formats.c @@ -1005,13 +1005,10 @@ _mesa_uncompressed_format_to_type_and_comps(mesa_format format, case MESA_FORMAT_R8G8B8X8_UNORM: case MESA_FORMAT_B8G8R8X8_UNORM: case MESA_FORMAT_X8R8G8B8_UNORM: - *datatype = GL_UNSIGNED_BYTE; - *comps = 4; - return; case MESA_FORMAT_BGR_UNORM8: case MESA_FORMAT_RGB_UNORM8: *datatype = GL_UNSIGNED_BYTE; - *comps = 3; + *comps = _mesa_format_num_components(format); return; case MESA_FORMAT_B5G6R5_UNORM: case MESA_FORMAT_R5G6B5_UNORM: @@ -1060,16 +1057,12 @@ _mesa_uncompressed_format_to_type_and_comps(mesa_format format, case MESA_FORMAT_A16L16_UNORM: case MESA_FORMAT_R16G16_UNORM: case MESA_FORMAT_G16R16_UNORM: - *datatype = GL_UNSIGNED_SHORT; - *comps = 2; - return; - case MESA_FORMAT_R_UNORM16: case MESA_FORMAT_A_UNORM16: case MESA_FORMAT_L_UNORM16: case MESA_FORMAT_I_UNORM16: *datatype = GL_UNSIGNED_SHORT; - *comps = 1; + *comps = _mesa_format_num_components(format); return; case MESA_FORMAT_R3G3B2_UNORM: @@ -1077,10 +1070,6 @@ _mesa_uncompressed_format_to_type_and_comps(mesa_format format, *comps = 3; return; case MESA_FORMAT_A4B4G4R4_UNORM: - *datatype = GL_UNSIGNED_SHORT_4_4_4_4; - *comps = 4; - return; - case MESA_FORMAT_R4G4B4A4_UNORM: *datatype = GL_UNSIGNED_SHORT_4_4_4_4; *comps = 4; @@ -1091,9 +1080,6 @@ _mesa_uncompressed_format_to_type_and_comps(mesa_format format, return; case MESA_FORMAT_A2B10G10R10_UNORM: case MESA_FORMAT_A2B10G10R10_UINT: - *datatype = GL_UNSIGNED_INT_10_10_10_2; - *comps = 4; - return; case MESA_FORMAT_A2R10G10B10_UNORM: case MESA_FORMAT_A2R10G10B10_UINT: *datatype = GL_UNSIGNED_INT_10_10_10_2; @@ -1136,15 +1122,7 @@ _mesa_uncompressed_format_to_type_and_comps(mesa_format format, return; case MESA_FORMAT_Z24_UNORM_X8_UINT: - *datatype = GL_UNSIGNED_INT; - *comps = 1; - return; - case MESA_FORMAT_X8_UINT_Z24_UNORM: - *datatype = GL_UNSIGNED_INT; - *comps = 1; - return; - case MESA_FORMAT_Z_UNORM32: *datatype = GL_UNSIGNED_INT; *comps = 1; @@ -1164,20 +1142,14 @@ _mesa_uncompressed_format_to_type_and_comps(mesa_format format, case MESA_FORMAT_A_SNORM8: case MESA_FORMAT_L_SNORM8: case MESA_FORMAT_I_SNORM8: - *datatype = GL_BYTE; - *comps = 1; - return; case MESA_FORMAT_R8G8_SNORM: case MESA_FORMAT_L8A8_SNORM: case MESA_FORMAT_A8L8_SNORM: - *datatype = GL_BYTE; - *comps = 2; - return; case MESA_FORMAT_A8B8G8R8_SNORM: case MESA_FORMAT_R8G8B8A8_SNORM: case MESA_FORMAT_X8B8G8R8_SNORM: *datatype = GL_BYTE; - *comps = 4; + *comps = _mesa_format_num_components(format); return; case MESA_FORMAT_RGBA_UNORM16: @@ -1189,42 +1161,24 @@ _mesa_uncompressed_format_to_type_and_comps(mesa_format format, case MESA_FORMAT_A_SNORM16: case MESA_FORMAT_L_SNORM16: case MESA_FORMAT_I_SNORM16: - *datatype = GL_SHORT; - *comps = 1; - return; case MESA_FORMAT_R16G16_SNORM: case MESA_FORMAT_LA_SNORM16: - *datatype = GL_SHORT; - *comps = 2; - return; case MESA_FORMAT_RGB_SNORM16: - *datatype = GL_SHORT; - *comps = 3; - return; case MESA_FORMAT_RGBA_SNORM16: *datatype = GL_SHORT; - *comps = 4; + *comps = _mesa_format_num_components(format); return; case MESA_FORMAT_BGR_SRGB8: - *datatype = GL_UNSIGNED_BYTE; - *comps = 3; - return; case MESA_FORMAT_A8B8G8R8_SRGB: case MESA_FORMAT_B8G8R8A8_SRGB: case MESA_FORMAT_A8R8G8B8_SRGB: case MESA_FORMAT_R8G8B8A8_SRGB: - *datatype = GL_UNSIGNED_BYTE; - *comps = 4; - return; case MESA_FORMAT_L_SRGB8: - *datatype = GL_UNSIGNED_BYTE; - *comps = 1; - return; case MESA_FORMAT_L8A8_SRGB: case MESA_FORMAT_A8L8_SRGB: *datatype = GL_UNSIGNED_BYTE; - *comps = 2; + *comps = _mesa_format_num_components(format); return; case MESA_FORMAT_RGBA_FLOAT32: @@ -1271,166 +1225,94 @@ _mesa_uncompressed_format_to_type_and_comps(mesa_format format, case MESA_FORMAT_A_UINT8: case MESA_FORMAT_L_UINT8: case MESA_FORMAT_I_UINT8: - *datatype = GL_UNSIGNED_BYTE; - *comps = 1; - return; case MESA_FORMAT_LA_UINT8: *datatype = GL_UNSIGNED_BYTE; - *comps = 2; + *comps = _mesa_format_num_components(format); retu
[Mesa-dev] [PATCH 1/4] mesa/formats: only do type and component lookup for uncompressed formats
From: Nanley Chery
Only uncompressed formats have a non-void type and actual components per pixel.
Rename _mesa_format_to_type_and_comps to
_mesa_uncompressed_format_to_type_and_comps and require callers to check if
the format is not compressed.
Cc: Jason Ekstrand
Signed-off-by: Nanley Chery
---
src/mesa/main/format_utils.c | 2 +-
src/mesa/main/formats.c | 55
src/mesa/main/formats.h | 2 +-
src/mesa/main/mipmap.c | 2 +-
4 files changed, 12 insertions(+), 49 deletions(-)
diff --git a/src/mesa/main/format_utils.c b/src/mesa/main/format_utils.c
index 810bb16..5fdabd5 100644
--- a/src/mesa/main/format_utils.c
+++ b/src/mesa/main/format_utils.c
@@ -602,7 +602,7 @@ _mesa_format_to_array(mesa_format format, GLenum *type, int
*num_components,
*normalized = !_mesa_is_format_integer(format);
- _mesa_format_to_type_and_comps(format, type, &format_components);
+ _mesa_uncompressed_format_to_type_and_comps(format, type,
&format_components);
switch (_mesa_get_format_layout(format)) {
case MESA_FORMAT_LAYOUT_ARRAY:
diff --git a/src/mesa/main/formats.c b/src/mesa/main/formats.c
index baeb1bf..97b74fe 100644
--- a/src/mesa/main/formats.c
+++ b/src/mesa/main/formats.c
@@ -870,9 +870,9 @@ _mesa_format_row_stride(mesa_format format, GLsizei width)
/**
- * Debug/test: check that all formats are handled in the
- * _mesa_format_to_type_and_comps() function. When new pixel formats
- * are added to Mesa, that function needs to be updated.
+ * Debug/test: check that all uncompressed formats are handled in the
+ * _mesa_uncompressed_format_to_type_and_comps() function. When new pixel
+ * formats are added to Mesa, that function needs to be updated.
* This is a no-op after the first call.
*/
static void
@@ -886,7 +886,8 @@ check_format_to_type_and_comps(void)
/* This function will emit a problem/warning if the format is
* not handled.
*/
- _mesa_format_to_type_and_comps(f, &datatype, &comps);
+ if (!_mesa_is_format_compressed(f))
+ _mesa_uncompressed_format_to_type_and_comps(f, &datatype, &comps);
}
}
@@ -982,11 +983,11 @@ _mesa_test_formats(void)
/**
- * Return datatype and number of components per texel for the given
mesa_format.
- * Only used for mipmap generation code.
+ * Return datatype and number of components per texel for the given
+ * uncompressed mesa_format. Only used for mipmap generation code.
*/
void
-_mesa_format_to_type_and_comps(mesa_format format,
+_mesa_uncompressed_format_to_type_and_comps(mesa_format format,
GLenum *datatype, GLuint *comps)
{
switch (format) {
@@ -1220,44 +1221,6 @@ _mesa_format_to_type_and_comps(mesa_format format,
*comps = 2;
return;
- case MESA_FORMAT_RGB_FXT1:
- case MESA_FORMAT_RGBA_FXT1:
- case MESA_FORMAT_RGB_DXT1:
- case MESA_FORMAT_RGBA_DXT1:
- case MESA_FORMAT_RGBA_DXT3:
- case MESA_FORMAT_RGBA_DXT5:
- case MESA_FORMAT_SRGB_DXT1:
- case MESA_FORMAT_SRGBA_DXT1:
- case MESA_FORMAT_SRGBA_DXT3:
- case MESA_FORMAT_SRGBA_DXT5:
- case MESA_FORMAT_R_RGTC1_UNORM:
- case MESA_FORMAT_R_RGTC1_SNORM:
- case MESA_FORMAT_RG_RGTC2_UNORM:
- case MESA_FORMAT_RG_RGTC2_SNORM:
- case MESA_FORMAT_L_LATC1_UNORM:
- case MESA_FORMAT_L_LATC1_SNORM:
- case MESA_FORMAT_LA_LATC2_UNORM:
- case MESA_FORMAT_LA_LATC2_SNORM:
- case MESA_FORMAT_ETC1_RGB8:
- case MESA_FORMAT_ETC2_RGB8:
- case MESA_FORMAT_ETC2_SRGB8:
- case MESA_FORMAT_ETC2_RGBA8_EAC:
- case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC:
- case MESA_FORMAT_ETC2_R11_EAC:
- case MESA_FORMAT_ETC2_RG11_EAC:
- case MESA_FORMAT_ETC2_SIGNED_R11_EAC:
- case MESA_FORMAT_ETC2_SIGNED_RG11_EAC:
- case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1:
- case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1:
- case MESA_FORMAT_BPTC_RGBA_UNORM:
- case MESA_FORMAT_BPTC_SRGB_ALPHA_UNORM:
- case MESA_FORMAT_BPTC_RGB_SIGNED_FLOAT:
- case MESA_FORMAT_BPTC_RGB_UNSIGNED_FLOAT:
- /* XXX generate error instead? */
- *datatype = GL_UNSIGNED_BYTE;
- *comps = 0;
- return;
-
case MESA_FORMAT_RGBA_FLOAT32:
*datatype = GL_FLOAT;
*comps = 4;
@@ -1561,7 +1524,7 @@ _mesa_format_to_type_and_comps(mesa_format format,
#ifdef DEBUG
default:
#endif
- _mesa_problem(NULL, "bad format %s in _mesa_format_to_type_and_comps",
+ _mesa_problem(NULL, "bad format %s in
_mesa_uncompressed_format_to_type_and_comps",
_mesa_get_format_name(format));
*datatype = 0;
*comps = 1;
diff --git a/src/mesa/main/formats.h b/src/mesa/main/formats.h
index 7e451ca..e08247e 100644
--- a/src/mesa/main/formats.h
+++ b/src/mesa/main/formats.h
@@ -654,7 +654,7 @@ extern GLint
_mesa_format_row_stride(mesa_format format, GLsizei width);
extern void
-_mesa_format_to_type_and_comps(mesa_format format,
+_mesa_uncompressed_format_to_type_and_comps(mesa_format format,
[Mesa-dev] [Bug 91591] rounding.h:102:2: error: #error "Unsupported or undefined LONG_BIT"
https://bugs.freedesktop.org/show_bug.cgi?id=91591 Vinson Lee changed: What|Removed |Added Status|RESOLVED|REOPENED Resolution|FIXED |--- --- Comment #16 from Vinson Lee --- mesa: 02a4fe22b137d4bc8378bedd8319109fd23a50e3 (master 11.0.0-devel) SCons build without LLVM is still broken. Compiling src/mesa/main/ff_fragment_shader.cpp ... In file included from src/mesa/main/macros.h:36, from src/mesa/main/ff_fragment_shader.cpp:34: src/util/rounding.h:105:2: error: #error "Unsupported long size" src/util/rounding.h:125:2: error: #error "Unsupported long size" In file included from src/mesa/main/macros.h:36, from src/mesa/main/ff_fragment_shader.cpp:34: src/util/rounding.h: In function ‘long int _mesa_lroundevenf(float)’: src/util/rounding.h:110: warning: no return statement in function returning non-void src/util/rounding.h: In function ‘long int _mesa_lroundeven(double)’: src/util/rounding.h:130: warning: no return statement in function returning non-void -- You are receiving this mail because: You are the QA Contact for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 3/4] mesa/formats: add more MESA_FORMAT_LAYOUTs
On Tue, Aug 11, 2015 at 7:07 PM, Nanley Chery wrote: > From: Nanley Chery > > Add the classes of compressed formats as layouts. This will make determining > if > a texture is an ASTC format simpler. > > Cc: Jason Ekstrand > Signed-off-by: Nanley Chery > --- > src/mesa/main/format_info.py | 4 +++- > src/mesa/main/formats.c | 6 ++ > src/mesa/main/formats.h | 6 ++ > src/mesa/main/texcompress.c | 30 ++ > 4 files changed, 21 insertions(+), 25 deletions(-) > > diff --git a/src/mesa/main/format_info.py b/src/mesa/main/format_info.py > index 3bae57e..b9f12f3 100644 > --- a/src/mesa/main/format_info.py > +++ b/src/mesa/main/format_info.py > @@ -103,8 +103,10 @@ def get_mesa_layout(fmat): >return 'MESA_FORMAT_LAYOUT_ARRAY' > elif fmat.layout == 'packed': >return 'MESA_FORMAT_LAYOUT_PACKED' > - else: > + elif fmat.layout == 'other': >return 'MESA_FORMAT_LAYOUT_OTHER' > + else: > + return 'MESA_FORMAT_LAYOUT_' + fmat.layout.upper() This should cover basically every format layout, right? i.e. why not just make this function be return 'MESA_FORMAT_LAYOUT_' + fmat.layout.upper() ? ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH v2] mesa: don't enable online compression for ASTC formats
From: Nanley Chery
In agreement with the ASTC spec, this makes calls to TexImage*D unsuccessful.
Implied by the spec, Generate[Texture]Mipmap and [Copy]TexSubImage*D calls
must be unsuccessful as well.
v2. actually force attempts to compress online to fail.
Signed-off-by: Nanley Chery
---
src/mesa/main/genmipmap.c | 1 +
src/mesa/main/glformats.c | 41 +
src/mesa/main/glformats.h | 3 +++
src/mesa/main/texcompress.c | 22 ++
src/mesa/main/teximage.c| 15 ---
5 files changed, 79 insertions(+), 3 deletions(-)
diff --git a/src/mesa/main/genmipmap.c b/src/mesa/main/genmipmap.c
index c18f9d5..4ec8385 100644
--- a/src/mesa/main/genmipmap.c
+++ b/src/mesa/main/genmipmap.c
@@ -111,6 +111,7 @@ _mesa_generate_texture_mipmap(struct gl_context *ctx,
if (_mesa_is_enum_format_integer(srcImage->InternalFormat) ||
_mesa_is_depthstencil_format(srcImage->InternalFormat) ||
+ _mesa_is_astc_format(srcImage->InternalFormat) ||
_mesa_is_stencil_format(srcImage->InternalFormat)) {
_mesa_unlock_texture(ctx, texObj);
_mesa_error(ctx, GL_INVALID_OPERATION,
diff --git a/src/mesa/main/glformats.c b/src/mesa/main/glformats.c
index c3fd734..2240fa9 100644
--- a/src/mesa/main/glformats.c
+++ b/src/mesa/main/glformats.c
@@ -820,6 +820,47 @@ _mesa_is_enum_format_signed_int(GLenum format)
}
}
+/**
+ * Test if the given format is an ASTC format.
+ */
+GLboolean
+_mesa_is_astc_format(GLenum internalFormat)
+{
+ switch (internalFormat) {
+ case GL_COMPRESSED_RGBA_ASTC_4x4_KHR:
+ case GL_COMPRESSED_RGBA_ASTC_5x4_KHR:
+ case GL_COMPRESSED_RGBA_ASTC_5x5_KHR:
+ case GL_COMPRESSED_RGBA_ASTC_6x5_KHR:
+ case GL_COMPRESSED_RGBA_ASTC_6x6_KHR:
+ case GL_COMPRESSED_RGBA_ASTC_8x5_KHR:
+ case GL_COMPRESSED_RGBA_ASTC_8x6_KHR:
+ case GL_COMPRESSED_RGBA_ASTC_8x8_KHR:
+ case GL_COMPRESSED_RGBA_ASTC_10x5_KHR:
+ case GL_COMPRESSED_RGBA_ASTC_10x6_KHR:
+ case GL_COMPRESSED_RGBA_ASTC_10x8_KHR:
+ case GL_COMPRESSED_RGBA_ASTC_10x10_KHR:
+ case GL_COMPRESSED_RGBA_ASTC_12x10_KHR:
+ case GL_COMPRESSED_RGBA_ASTC_12x12_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_4x4_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_5x4_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_5x5_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_6x5_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_6x6_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_8x5_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_8x6_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_8x8_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_10x5_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_10x6_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_10x8_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_10x10_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_12x10_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_12x12_KHR:
+ return true;
+ default:
+ return false;
+ }
+}
+
/**
* Test if the given format is an integer (non-normalized) format.
diff --git a/src/mesa/main/glformats.h b/src/mesa/main/glformats.h
index 419955a..aec905d 100644
--- a/src/mesa/main/glformats.h
+++ b/src/mesa/main/glformats.h
@@ -57,6 +57,9 @@ extern GLint
_mesa_bytes_per_vertex_attrib(GLint comps, GLenum type);
extern GLboolean
+_mesa_is_astc_format(GLenum internalFormat);
+
+extern GLboolean
_mesa_is_type_unsigned(GLenum type);
extern GLboolean
diff --git a/src/mesa/main/texcompress.c b/src/mesa/main/texcompress.c
index 0fd1a36..1654fc6 100644
--- a/src/mesa/main/texcompress.c
+++ b/src/mesa/main/texcompress.c
@@ -229,6 +229,28 @@ _mesa_gl_compressed_format_base_format(GLenum format)
*what GL_NUM_COMPRESSED_TEXTURE_FORMATS and
*GL_COMPRESSED_TEXTURE_FORMATS return."
*
+ * The KHR_texture_compression_astc_hdr spec says:
+ *
+ *"Interactions with OpenGL 4.2
+ *
+ *OpenGL 4.2 supports the feature that compressed textures can be
+ *compressed online, by passing the compressed texture format enum as
+ *the internal format when uploading a texture using TexImage1D,
+ *TexImage2D or TexImage3D (see Section 3.9.3, Texture Image
+ *Specification, subsection Encoding of Special Internal Formats).
+ *
+ *Due to the complexity of the ASTC compression algorithm, it is not
+ *usually suitable for online use, and therefore ASTC support will be
+ *limited to pre-compressed textures only. Where on-device compression
+ *is required, a domain-specific limited compressor will typically
+ *be used, and this is therefore not suitable for implementation in
+ *the driver.
+ *
+ *In particular, the ASTC format specifiers will not be added to
+ *Table 3.14, and thus will not be accepted by the TexImage*D
+ *functions, and will not be returned by the (already deprecated)
+ *COMPRESSED_TEXTURE_FORMATS query."
+ *
* There is no formal spec for GL_ATI_texture_compression_3dc. Since the
*
[Mesa-dev] [PATCH v3] mesa/teximage: accept ASTC formats for 3D texture specification
From: Nanley Chery
The ASTC spec was revised as follows:
Revision 2, April 28, 2015 - added CompressedTex{Sub,}Image3D to
commands accepting ASTC format tokens in the New Tokens section [...].
Support only exists in the HDR submode:
Add a second new column "3D Tex." which is empty for all non-ASTC
formats. If only the LDR profile is supported by the implementation,
this column is also empty for all ASTC formats. If both the LDR and HDR
profiles are supported only, this column is checked for all ASTC
formats.
LDR-only systems should generate an INVALID_OPERATION error when
attempting to call CompressedTexImage3D with the TEXTURE_3D target.
v2. return the proper error for LDR-only systems.
v3. update is_astc_format().
Signed-off-by: Nanley Chery
---
src/mesa/main/teximage.c | 49 +++-
1 file changed, 48 insertions(+), 1 deletion(-)
diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c
index 5fa0332..a04e5ee 100644
--- a/src/mesa/main/teximage.c
+++ b/src/mesa/main/teximage.c
@@ -1828,6 +1828,35 @@ _mesa_target_can_be_compressed(const struct gl_context
*ctx, GLenum target,
case GL_COMPRESSED_RGB_BPTC_SIGNED_FLOAT:
case GL_COMPRESSED_RGB_BPTC_UNSIGNED_FLOAT:
return ctx->Extensions.ARB_texture_compression_bptc;
+ case GL_COMPRESSED_RGBA_ASTC_4x4_KHR:
+ case GL_COMPRESSED_RGBA_ASTC_5x4_KHR:
+ case GL_COMPRESSED_RGBA_ASTC_5x5_KHR:
+ case GL_COMPRESSED_RGBA_ASTC_6x5_KHR:
+ case GL_COMPRESSED_RGBA_ASTC_6x6_KHR:
+ case GL_COMPRESSED_RGBA_ASTC_8x5_KHR:
+ case GL_COMPRESSED_RGBA_ASTC_8x6_KHR:
+ case GL_COMPRESSED_RGBA_ASTC_8x8_KHR:
+ case GL_COMPRESSED_RGBA_ASTC_10x5_KHR:
+ case GL_COMPRESSED_RGBA_ASTC_10x6_KHR:
+ case GL_COMPRESSED_RGBA_ASTC_10x8_KHR:
+ case GL_COMPRESSED_RGBA_ASTC_10x10_KHR:
+ case GL_COMPRESSED_RGBA_ASTC_12x10_KHR:
+ case GL_COMPRESSED_RGBA_ASTC_12x12_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_4x4_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_5x4_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_5x5_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_6x5_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_6x6_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_8x5_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_8x6_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_8x8_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_10x5_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_10x6_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_10x8_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_10x10_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_12x10_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_12x12_KHR:
+ return ctx->Extensions.KHR_texture_compression_astc_hdr;
default:
return GL_FALSE;
}
@@ -2330,6 +2359,13 @@ texture_error_check( struct gl_context *ctx,
return GL_FALSE;
}
+static inline bool
+is_astc_format(const struct gl_context *ctx, GLenum internalFormat)
+{
+ return ctx->Extensions.KHR_texture_compression_astc_ldr &&
+ _mesa_is_astc_format(internalFormat);
+}
+
/**
* Error checking for glCompressedTexImage[123]D().
@@ -2358,7 +2394,18 @@ compressed_texture_error_check(struct gl_context *ctx,
GLint dimensions,
* CompressedTexImage3D will generate an INVALID_OPERATION error if
* target is not TEXTURE_2D_ARRAY."
*/
- error = _mesa_is_desktop_gl(ctx) ? GL_INVALID_ENUM :
GL_INVALID_OPERATION;
+ /* From the KHR_texture_compression_astc_hdr spec:
+ *
+ * 'An INVALID_OPERATION error is generated by CompressedTexImage3D
+ * if is TEXTURE_CUBE_MAP_ARRAY and the
+ * "Cube Map Array" column of table 8.19 is *not* checked, or if
+ * is TEXTURE_3D and the "3D Tex." column of table
+ * 8.19 is *not* checked'
+ *
+ * The instances of above should say .
+ */
+ error = _mesa_is_desktop_gl(ctx) && !is_astc_format(ctx, internalFormat)
?
+ GL_INVALID_ENUM : GL_INVALID_OPERATION;
goto error;
}
--
2.4.2
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Re: [Mesa-dev] [PATCH 3/4] mesa/formats: add more MESA_FORMAT_LAYOUTs
On Tue, Aug 11, 2015 at 4:16 PM, Ilia Mirkin wrote: > On Tue, Aug 11, 2015 at 7:07 PM, Nanley Chery > wrote: > > From: Nanley Chery > > > > Add the classes of compressed formats as layouts. This will make > determining if > > a texture is an ASTC format simpler. > > > > Cc: Jason Ekstrand > > Signed-off-by: Nanley Chery > > --- > > src/mesa/main/format_info.py | 4 +++- > > src/mesa/main/formats.c | 6 ++ > > src/mesa/main/formats.h | 6 ++ > > src/mesa/main/texcompress.c | 30 ++ > > 4 files changed, 21 insertions(+), 25 deletions(-) > > > > diff --git a/src/mesa/main/format_info.py b/src/mesa/main/format_info.py > > index 3bae57e..b9f12f3 100644 > > --- a/src/mesa/main/format_info.py > > +++ b/src/mesa/main/format_info.py > > @@ -103,8 +103,10 @@ def get_mesa_layout(fmat): > >return 'MESA_FORMAT_LAYOUT_ARRAY' > > elif fmat.layout == 'packed': > >return 'MESA_FORMAT_LAYOUT_PACKED' > > - else: > > + elif fmat.layout == 'other': > >return 'MESA_FORMAT_LAYOUT_OTHER' > > + else: > > + return 'MESA_FORMAT_LAYOUT_' + fmat.layout.upper() > > This should cover basically every format layout, right? i.e. why not > just make this function be > > return 'MESA_FORMAT_LAYOUT_' + fmat.layout.upper() ? > Good idea. Thanks, Nanley ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH v2] mesa: don't enable online compression for ASTC formats
On Tue, Aug 11, 2015 at 4:14 PM, Nanley Chery wrote:
> +static bool
> +_mesa_format_no_online_compression(const struct gl_context *ctx, GLenum
> format)
> +{
> + return _mesa_is_astc_format(format) ||
> + compressedteximage_only_format(ctx, format);
Needs one more space of indentation.
> +}
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[Mesa-dev] [PATCH v2] mesa/formats: add more MESA_FORMAT_LAYOUTs
From: Nanley Chery
Add the classes of compressed formats as layouts. This will make determining if
a texture is an ASTC format simpler.
v2. simplify layout name construction (Ilia).
Cc: Jason Ekstrand
Signed-off-by: Nanley Chery
---
src/mesa/main/format_info.py | 10 +-
src/mesa/main/formats.c | 6 ++
src/mesa/main/formats.h | 6 ++
src/mesa/main/texcompress.c | 30 ++
4 files changed, 19 insertions(+), 33 deletions(-)
diff --git a/src/mesa/main/format_info.py b/src/mesa/main/format_info.py
index 3bae57e..c249e73 100644
--- a/src/mesa/main/format_info.py
+++ b/src/mesa/main/format_info.py
@@ -98,14 +98,6 @@ def get_gl_data_type(fmat):
else:
assert False
-def get_mesa_layout(fmat):
- if fmat.layout == 'array':
- return 'MESA_FORMAT_LAYOUT_ARRAY'
- elif fmat.layout == 'packed':
- return 'MESA_FORMAT_LAYOUT_PACKED'
- else:
- return 'MESA_FORMAT_LAYOUT_OTHER'
-
def get_channel_bits(fmat, chan_name):
if fmat.is_compressed():
# These values are pretty-much bogus, but OpenGL requires that we
@@ -179,7 +171,7 @@ for fmat in formats:
print ' {'
print ' {0},'.format(fmat.name)
print ' "{0}",'.format(fmat.name)
- print ' {0},'.format(get_mesa_layout(fmat))
+ print ' {0},'.format('MESA_FORMAT_LAYOUT_' + fmat.layout.upper())
print ' {0},'.format(get_gl_base_format(fmat))
print ' {0},'.format(get_gl_data_type(fmat))
diff --git a/src/mesa/main/formats.c b/src/mesa/main/formats.c
index 90fa75b..cb5ad21 100644
--- a/src/mesa/main/formats.c
+++ b/src/mesa/main/formats.c
@@ -188,6 +188,12 @@ _mesa_get_format_max_bits(mesa_format format)
* The return value will be one of:
*MESA_FORMAT_LAYOUT_ARRAY
*MESA_FORMAT_LAYOUT_PACKED
+ *MESA_FORMAT_LAYOUT_S3TC
+ *MESA_FORMAT_LAYOUT_RGTC
+ *MESA_FORMAT_LAYOUT_FXT1
+ *MESA_FORMAT_LAYOUT_ETC1
+ *MESA_FORMAT_LAYOUT_ETC2
+ *MESA_FORMAT_LAYOUT_BPTC
*MESA_FORMAT_LAYOUT_OTHER
*/
extern enum mesa_format_layout
diff --git a/src/mesa/main/formats.h b/src/mesa/main/formats.h
index e08247e..2fdd9bf 100644
--- a/src/mesa/main/formats.h
+++ b/src/mesa/main/formats.h
@@ -64,6 +64,12 @@ extern "C" {
enum mesa_format_layout {
MESA_FORMAT_LAYOUT_ARRAY,
MESA_FORMAT_LAYOUT_PACKED,
+ MESA_FORMAT_LAYOUT_S3TC,
+ MESA_FORMAT_LAYOUT_RGTC,
+ MESA_FORMAT_LAYOUT_FXT1,
+ MESA_FORMAT_LAYOUT_ETC1,
+ MESA_FORMAT_LAYOUT_ETC2,
+ MESA_FORMAT_LAYOUT_BPTC,
MESA_FORMAT_LAYOUT_OTHER,
};
diff --git a/src/mesa/main/texcompress.c b/src/mesa/main/texcompress.c
index 0fd1a36..edfb036 100644
--- a/src/mesa/main/texcompress.c
+++ b/src/mesa/main/texcompress.c
@@ -586,34 +586,16 @@ _mesa_compressed_image_address(GLint col, GLint row,
GLint img,
compressed_fetch_func
_mesa_get_compressed_fetch_func(mesa_format format)
{
- switch (format) {
- case MESA_FORMAT_RGB_DXT1:
- case MESA_FORMAT_RGBA_DXT1:
- case MESA_FORMAT_RGBA_DXT3:
- case MESA_FORMAT_RGBA_DXT5:
- case MESA_FORMAT_SRGB_DXT1:
- case MESA_FORMAT_SRGBA_DXT1:
- case MESA_FORMAT_SRGBA_DXT3:
- case MESA_FORMAT_SRGBA_DXT5:
+ switch (_mesa_get_format_layout(format)) {
+ case MESA_FORMAT_LAYOUT_S3TC:
return _mesa_get_dxt_fetch_func(format);
- case MESA_FORMAT_RGB_FXT1:
- case MESA_FORMAT_RGBA_FXT1:
+ case MESA_FORMAT_LAYOUT_FXT1:
return _mesa_get_fxt_fetch_func(format);
- case MESA_FORMAT_R_RGTC1_UNORM:
- case MESA_FORMAT_L_LATC1_UNORM:
- case MESA_FORMAT_R_RGTC1_SNORM:
- case MESA_FORMAT_L_LATC1_SNORM:
- case MESA_FORMAT_RG_RGTC2_UNORM:
- case MESA_FORMAT_LA_LATC2_UNORM:
- case MESA_FORMAT_RG_RGTC2_SNORM:
- case MESA_FORMAT_LA_LATC2_SNORM:
+ case MESA_FORMAT_LAYOUT_RGTC:
return _mesa_get_compressed_rgtc_func(format);
- case MESA_FORMAT_ETC1_RGB8:
+ case MESA_FORMAT_LAYOUT_ETC1:
return _mesa_get_etc_fetch_func(format);
- case MESA_FORMAT_BPTC_RGBA_UNORM:
- case MESA_FORMAT_BPTC_SRGB_ALPHA_UNORM:
- case MESA_FORMAT_BPTC_RGB_SIGNED_FLOAT:
- case MESA_FORMAT_BPTC_RGB_UNSIGNED_FLOAT:
+ case MESA_FORMAT_LAYOUT_BPTC:
return _mesa_get_bptc_fetch_func(format);
default:
return NULL;
--
2.5.0
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[Mesa-dev] [PATCH v3] mesa: don't enable online compression for ASTC formats
From: Nanley Chery
In agreement with the ASTC spec, this makes calls to TexImage*D unsuccessful.
Implied by the spec, Generate[Texture]Mipmap and [Copy]TexSubImage*D calls
must be unsuccessful as well.
v2. actually force attempts to compress online to fail.
v3. indentation (Matt).
Signed-off-by: Nanley Chery
---
src/mesa/main/genmipmap.c | 1 +
src/mesa/main/glformats.c | 41 +
src/mesa/main/glformats.h | 3 +++
src/mesa/main/texcompress.c | 22 ++
src/mesa/main/teximage.c| 15 ---
5 files changed, 79 insertions(+), 3 deletions(-)
diff --git a/src/mesa/main/genmipmap.c b/src/mesa/main/genmipmap.c
index c18f9d5..4ec8385 100644
--- a/src/mesa/main/genmipmap.c
+++ b/src/mesa/main/genmipmap.c
@@ -111,6 +111,7 @@ _mesa_generate_texture_mipmap(struct gl_context *ctx,
if (_mesa_is_enum_format_integer(srcImage->InternalFormat) ||
_mesa_is_depthstencil_format(srcImage->InternalFormat) ||
+ _mesa_is_astc_format(srcImage->InternalFormat) ||
_mesa_is_stencil_format(srcImage->InternalFormat)) {
_mesa_unlock_texture(ctx, texObj);
_mesa_error(ctx, GL_INVALID_OPERATION,
diff --git a/src/mesa/main/glformats.c b/src/mesa/main/glformats.c
index c3fd734..2240fa9 100644
--- a/src/mesa/main/glformats.c
+++ b/src/mesa/main/glformats.c
@@ -820,6 +820,47 @@ _mesa_is_enum_format_signed_int(GLenum format)
}
}
+/**
+ * Test if the given format is an ASTC format.
+ */
+GLboolean
+_mesa_is_astc_format(GLenum internalFormat)
+{
+ switch (internalFormat) {
+ case GL_COMPRESSED_RGBA_ASTC_4x4_KHR:
+ case GL_COMPRESSED_RGBA_ASTC_5x4_KHR:
+ case GL_COMPRESSED_RGBA_ASTC_5x5_KHR:
+ case GL_COMPRESSED_RGBA_ASTC_6x5_KHR:
+ case GL_COMPRESSED_RGBA_ASTC_6x6_KHR:
+ case GL_COMPRESSED_RGBA_ASTC_8x5_KHR:
+ case GL_COMPRESSED_RGBA_ASTC_8x6_KHR:
+ case GL_COMPRESSED_RGBA_ASTC_8x8_KHR:
+ case GL_COMPRESSED_RGBA_ASTC_10x5_KHR:
+ case GL_COMPRESSED_RGBA_ASTC_10x6_KHR:
+ case GL_COMPRESSED_RGBA_ASTC_10x8_KHR:
+ case GL_COMPRESSED_RGBA_ASTC_10x10_KHR:
+ case GL_COMPRESSED_RGBA_ASTC_12x10_KHR:
+ case GL_COMPRESSED_RGBA_ASTC_12x12_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_4x4_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_5x4_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_5x5_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_6x5_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_6x6_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_8x5_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_8x6_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_8x8_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_10x5_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_10x6_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_10x8_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_10x10_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_12x10_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_12x12_KHR:
+ return true;
+ default:
+ return false;
+ }
+}
+
/**
* Test if the given format is an integer (non-normalized) format.
diff --git a/src/mesa/main/glformats.h b/src/mesa/main/glformats.h
index 419955a..aec905d 100644
--- a/src/mesa/main/glformats.h
+++ b/src/mesa/main/glformats.h
@@ -57,6 +57,9 @@ extern GLint
_mesa_bytes_per_vertex_attrib(GLint comps, GLenum type);
extern GLboolean
+_mesa_is_astc_format(GLenum internalFormat);
+
+extern GLboolean
_mesa_is_type_unsigned(GLenum type);
extern GLboolean
diff --git a/src/mesa/main/texcompress.c b/src/mesa/main/texcompress.c
index 0fd1a36..1654fc6 100644
--- a/src/mesa/main/texcompress.c
+++ b/src/mesa/main/texcompress.c
@@ -229,6 +229,28 @@ _mesa_gl_compressed_format_base_format(GLenum format)
*what GL_NUM_COMPRESSED_TEXTURE_FORMATS and
*GL_COMPRESSED_TEXTURE_FORMATS return."
*
+ * The KHR_texture_compression_astc_hdr spec says:
+ *
+ *"Interactions with OpenGL 4.2
+ *
+ *OpenGL 4.2 supports the feature that compressed textures can be
+ *compressed online, by passing the compressed texture format enum as
+ *the internal format when uploading a texture using TexImage1D,
+ *TexImage2D or TexImage3D (see Section 3.9.3, Texture Image
+ *Specification, subsection Encoding of Special Internal Formats).
+ *
+ *Due to the complexity of the ASTC compression algorithm, it is not
+ *usually suitable for online use, and therefore ASTC support will be
+ *limited to pre-compressed textures only. Where on-device compression
+ *is required, a domain-specific limited compressor will typically
+ *be used, and this is therefore not suitable for implementation in
+ *the driver.
+ *
+ *In particular, the ASTC format specifiers will not be added to
+ *Table 3.14, and thus will not be accepted by the TexImage*D
+ *functions, and will not be returned by the (already deprecated)
+ *COMPRESSED_TEXTURE_FORMATS query."
+ *
* There is no formal spec for GL_ATI_texture_compres
Re: [Mesa-dev] [PATCH 1/2] nir: Add a nir_opt_undef() to handle csels with undef.
Thomas Helland writes:
> 2015-08-11 20:25 GMT+02:00 Eric Anholt :
>> We may find a cause to do more undef optimization in the future, but for
>> now this fixes up things after if flattening. vc4 was handling this
>> internally most of the time, but a GLB2.7 shader that did a conditional
>> discard and assign gl_FragColor in the else was still emitting some extra
>> code.
>>
>> total instructions in shared programs: 100809 -> 100795 (-0.01%)
>> instructions in affected programs: 37 -> 23 (-37.84%)
>> ---
>> src/gallium/drivers/vc4/vc4_program.c | 1 +
>> src/glsl/Makefile.sources | 1 +
>> src/glsl/nir/nir.h| 2 +
>> src/glsl/nir/nir_opt_undef.c | 93
>> +++
>> 4 files changed, 97 insertions(+)
>> create mode 100644 src/glsl/nir/nir_opt_undef.c
>>
>> diff --git a/src/gallium/drivers/vc4/vc4_program.c
>> b/src/gallium/drivers/vc4/vc4_program.c
>> index e9120b7..4a3a277 100644
>> --- a/src/gallium/drivers/vc4/vc4_program.c
>> +++ b/src/gallium/drivers/vc4/vc4_program.c
>> @@ -1627,6 +1627,7 @@ vc4_optimize_nir(struct nir_shader *s)
>> progress = nir_opt_peephole_select(s) || progress;
>> progress = nir_opt_algebraic(s) || progress;
>> progress = nir_opt_constant_folding(s) || progress;
>> +progress = nir_opt_undef(s) || progress;
>> } while (progress);
>> }
>>
>> diff --git a/src/glsl/Makefile.sources b/src/glsl/Makefile.sources
>> index a0e85ed..0b77244 100644
>> --- a/src/glsl/Makefile.sources
>> +++ b/src/glsl/Makefile.sources
>> @@ -56,6 +56,7 @@ NIR_FILES = \
>> nir/nir_opt_peephole_ffma.c \
>> nir/nir_opt_peephole_select.c \
>> nir/nir_opt_remove_phis.c \
>> + nir/nir_opt_undef.c \
>> nir/nir_print.c \
>> nir/nir_remove_dead_variables.c \
>> nir/nir_search.c \
>> diff --git a/src/glsl/nir/nir.h b/src/glsl/nir/nir.h
>> index 9aae6d7..222a219 100644
>> --- a/src/glsl/nir/nir.h
>> +++ b/src/glsl/nir/nir.h
>> @@ -1704,6 +1704,8 @@ bool nir_opt_peephole_ffma(nir_shader *shader);
>>
>> bool nir_opt_remove_phis(nir_shader *shader);
>>
>> +bool nir_opt_undef(nir_shader *shader);
>> +
>> void nir_sweep(nir_shader *shader);
>>
>> #ifdef __cplusplus
>> diff --git a/src/glsl/nir/nir_opt_undef.c b/src/glsl/nir/nir_opt_undef.c
>> new file mode 100644
>> index 000..89a75c4
>> --- /dev/null
>> +++ b/src/glsl/nir/nir_opt_undef.c
>> @@ -0,0 +1,93 @@
>> +/*
>> + * Copyright © 2015 Broadcom
>> + *
>> + * Permission is hereby granted, free of charge, to any person obtaining a
>> + * copy of this software and associated documentation files (the
>> "Software"),
>> + * to deal in the Software without restriction, including without limitation
>> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>> + * and/or sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice (including the next
>> + * paragraph) shall be included in all copies or substantial portions of the
>> + * Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
>> OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
>> OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
>> DEALINGS
>> + * IN THE SOFTWARE.
>> + */
>> +
>> +#include "nir.h"
>> +
>> +/** @file nir_opt_undef.c
>> + *
>> + * Handles optimization of operations involving ssa_undef. For now, we just
>> + * make sure that csels between undef and some other value just give the
>> other
>> + * value (on the assumption that the condition's going to be choosing the
>> + * defined value). This reduces work after if flattening when each side of
>> + * the if is defining a variable.
>> + *
>> + * Some day, we may find some use for making other operations consuming an
>> + * undef arg output undef, but I don't know of any cases currently.
>> + */
>> +
>> +static bool
>> +opt_undef_alu(nir_alu_instr *instr)
>> +{
>> + if (instr->op != nir_op_bcsel && instr->op != nir_op_fcsel)
>> + return false;
>> +
>> + assert(instr->dest.dest.is_ssa);
>> +
>> + for (int i = 1; i <= 2; i++) {
>> + if (!instr->src[i].src.is_ssa)
>> + continue;
>> +
>> + nir_instr *parent = instr->src[i].src.ssa->parent_instr;
>> + if (parent->type != nir_instr_type_ssa_undef)
>> + continue;
>> +
>> + nir_alu_src_copy(&instr->src[0], &instr->src[i == 1 ? 2 : 1],
>> + ralloc_parent(instr));
>
> With this changed to:
>
> nir_instr_rewrite_src(&instr->ins
Re: [Mesa-dev] [PATCH v3] mesa: don't enable online compression for ASTC formats
This patch is a followup on this:
http://lists.freedesktop.org/archives/mesa-dev/2015-June/087055.html
On Tue, Aug 11, 2015 at 4:54 PM, Nanley Chery wrote:
> From: Nanley Chery
>
> In agreement with the ASTC spec, this makes calls to TexImage*D
> unsuccessful.
> Implied by the spec, Generate[Texture]Mipmap and [Copy]TexSubImage*D calls
> must be unsuccessful as well.
>
> v2. actually force attempts to compress online to fail.
> v3. indentation (Matt).
>
> Signed-off-by: Nanley Chery
> ---
> src/mesa/main/genmipmap.c | 1 +
> src/mesa/main/glformats.c | 41 +
> src/mesa/main/glformats.h | 3 +++
> src/mesa/main/texcompress.c | 22 ++
> src/mesa/main/teximage.c| 15 ---
> 5 files changed, 79 insertions(+), 3 deletions(-)
>
> diff --git a/src/mesa/main/genmipmap.c b/src/mesa/main/genmipmap.c
> index c18f9d5..4ec8385 100644
> --- a/src/mesa/main/genmipmap.c
> +++ b/src/mesa/main/genmipmap.c
> @@ -111,6 +111,7 @@ _mesa_generate_texture_mipmap(struct gl_context *ctx,
>
> if (_mesa_is_enum_format_integer(srcImage->InternalFormat) ||
> _mesa_is_depthstencil_format(srcImage->InternalFormat) ||
> + _mesa_is_astc_format(srcImage->InternalFormat) ||
> _mesa_is_stencil_format(srcImage->InternalFormat)) {
>_mesa_unlock_texture(ctx, texObj);
>_mesa_error(ctx, GL_INVALID_OPERATION,
> diff --git a/src/mesa/main/glformats.c b/src/mesa/main/glformats.c
> index c3fd734..2240fa9 100644
> --- a/src/mesa/main/glformats.c
> +++ b/src/mesa/main/glformats.c
> @@ -820,6 +820,47 @@ _mesa_is_enum_format_signed_int(GLenum format)
> }
> }
>
> +/**
> + * Test if the given format is an ASTC format.
> + */
> +GLboolean
> +_mesa_is_astc_format(GLenum internalFormat)
> +{
> + switch (internalFormat) {
> + case GL_COMPRESSED_RGBA_ASTC_4x4_KHR:
> + case GL_COMPRESSED_RGBA_ASTC_5x4_KHR:
> + case GL_COMPRESSED_RGBA_ASTC_5x5_KHR:
> + case GL_COMPRESSED_RGBA_ASTC_6x5_KHR:
> + case GL_COMPRESSED_RGBA_ASTC_6x6_KHR:
> + case GL_COMPRESSED_RGBA_ASTC_8x5_KHR:
> + case GL_COMPRESSED_RGBA_ASTC_8x6_KHR:
> + case GL_COMPRESSED_RGBA_ASTC_8x8_KHR:
> + case GL_COMPRESSED_RGBA_ASTC_10x5_KHR:
> + case GL_COMPRESSED_RGBA_ASTC_10x6_KHR:
> + case GL_COMPRESSED_RGBA_ASTC_10x8_KHR:
> + case GL_COMPRESSED_RGBA_ASTC_10x10_KHR:
> + case GL_COMPRESSED_RGBA_ASTC_12x10_KHR:
> + case GL_COMPRESSED_RGBA_ASTC_12x12_KHR:
> + case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_4x4_KHR:
> + case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_5x4_KHR:
> + case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_5x5_KHR:
> + case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_6x5_KHR:
> + case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_6x6_KHR:
> + case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_8x5_KHR:
> + case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_8x6_KHR:
> + case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_8x8_KHR:
> + case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_10x5_KHR:
> + case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_10x6_KHR:
> + case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_10x8_KHR:
> + case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_10x10_KHR:
> + case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_12x10_KHR:
> + case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_12x12_KHR:
> + return true;
> + default:
> + return false;
> + }
> +}
> +
>
> /**
> * Test if the given format is an integer (non-normalized) format.
> diff --git a/src/mesa/main/glformats.h b/src/mesa/main/glformats.h
> index 419955a..aec905d 100644
> --- a/src/mesa/main/glformats.h
> +++ b/src/mesa/main/glformats.h
> @@ -57,6 +57,9 @@ extern GLint
> _mesa_bytes_per_vertex_attrib(GLint comps, GLenum type);
>
> extern GLboolean
> +_mesa_is_astc_format(GLenum internalFormat);
> +
> +extern GLboolean
> _mesa_is_type_unsigned(GLenum type);
>
> extern GLboolean
> diff --git a/src/mesa/main/texcompress.c b/src/mesa/main/texcompress.c
> index 0fd1a36..1654fc6 100644
> --- a/src/mesa/main/texcompress.c
> +++ b/src/mesa/main/texcompress.c
> @@ -229,6 +229,28 @@ _mesa_gl_compressed_format_base_format(GLenum format)
> *what GL_NUM_COMPRESSED_TEXTURE_FORMATS and
> *GL_COMPRESSED_TEXTURE_FORMATS return."
> *
> + * The KHR_texture_compression_astc_hdr spec says:
> + *
> + *"Interactions with OpenGL 4.2
> + *
> + *OpenGL 4.2 supports the feature that compressed textures can be
> + *compressed online, by passing the compressed texture format
> enum as
> + *the internal format when uploading a texture using TexImage1D,
> + *TexImage2D or TexImage3D (see Section 3.9.3, Texture Image
> + *Specification, subsection Encoding of Special Internal Formats).
> + *
> + *Due to the complexity of the ASTC compression algorithm, it is
> not
> + *usually suitable for online use, and therefore ASTC support
> will be
> + *limited to pre-compressed textures only. Where on-device
> compression
> + *is required, a domain-specific limited compressor will typically
> + *be used, and this is the
[Mesa-dev] [PATCH] mesa/teximage: report the correct function which triggered the error
From: Nanley Chery
This function would always report that a dimension or size error occurred
in glTexImage even when it was called from glCompressedTexImage. Replace
the static string with the dynamically determined caller name.
Signed-off-by: Nanley Chery
---
src/mesa/main/teximage.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c
index 03e45fc..d519fa5 100644
--- a/src/mesa/main/teximage.c
+++ b/src/mesa/main/teximage.c
@@ -3428,15 +3428,15 @@ teximage(struct gl_context *ctx, GLboolean compressed,
GLuint dims,
if (!dimensionsOK) {
_mesa_error(ctx, GL_INVALID_VALUE,
- "glTexImage%uD(invalid width or height or depth)",
- dims);
+ "%s%uD(invalid width or height or depth)",
+ func, dims);
return;
}
if (!sizeOK) {
_mesa_error(ctx, GL_OUT_OF_MEMORY,
- "glTexImage%uD(image too large: %d x %d x %d, %s format)",
- dims, width, height, depth,
+ "%s%uD(image too large: %d x %d x %d, %s format)",
+ func, dims, width, height, depth,
_mesa_enum_to_string(internalFormat));
return;
}
--
2.4.2
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[Mesa-dev] [PATCH 2/2] i965: add support for textureSamples function
Signed-off-by: Ilia Mirkin
---
src/mesa/drivers/dri/i965/brw_defines.h | 3 +++
src/mesa/drivers/dri/i965/brw_disasm.c | 1 +
src/mesa/drivers/dri/i965/brw_fs.cpp | 7 +++
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 4
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 1 +
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 3 +++
src/mesa/drivers/dri/i965/brw_shader.cpp | 4
src/mesa/drivers/dri/i965/brw_vec4.cpp | 1 +
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 4
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 1 +
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 10 +-
11 files changed, 38 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index 82a3635..f209440 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -946,6 +946,8 @@ enum opcode {
SHADER_OPCODE_TG4_LOGICAL,
SHADER_OPCODE_TG4_OFFSET,
SHADER_OPCODE_TG4_OFFSET_LOGICAL,
+ SHADER_OPCODE_SAMPLEINFO,
+ SHADER_OPCODE_SAMPLEINFO_LOGICAL,
/**
* Combines multiple sources of size 1 into a larger virtual GRF.
@@ -1478,6 +1480,7 @@ enum brw_message_target {
#define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4 8
#define GEN5_SAMPLER_MESSAGE_LOD 9
#define GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO 10
+#define GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO 11
#define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C16
#define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO 17
#define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C 18
diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c
b/src/mesa/drivers/dri/i965/brw_disasm.c
index 1075c5a..1453a59 100644
--- a/src/mesa/drivers/dri/i965/brw_disasm.c
+++ b/src/mesa/drivers/dri/i965/brw_disasm.c
@@ -601,6 +601,7 @@ static const char *const gen5_sampler_msg_type[] = {
[GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4] = "gather4",
[GEN5_SAMPLER_MESSAGE_LOD] = "lod",
[GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO] = "resinfo",
+ [GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO] = "sampleinfo",
[GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C]= "gather4_c",
[GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO] = "gather4_po",
[GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C] = "gather4_po_c",
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 82cb499..40fd375 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -699,6 +699,7 @@ fs_inst::components_read(unsigned i) const
case SHADER_OPCODE_LOD_LOGICAL:
case SHADER_OPCODE_TG4_LOGICAL:
case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
+ case SHADER_OPCODE_SAMPLEINFO_LOGICAL:
assert(src[8].file == IMM && src[9].file == IMM);
/* Texture coordinates. */
if (i == 0)
@@ -875,6 +876,7 @@ fs_visitor::implied_mrf_writes(fs_inst *inst)
case SHADER_OPCODE_TXL:
case SHADER_OPCODE_TXS:
case SHADER_OPCODE_LOD:
+ case SHADER_OPCODE_SAMPLEINFO:
return 1;
case FS_OPCODE_FB_WRITE:
return 2;
@@ -3730,6 +3732,7 @@ lower_sampler_logical_send_gen7(const fs_builder &bld,
fs_inst *inst, opcode op,
sources[i] = bld.vgrf(BRW_REGISTER_TYPE_F);
if (op == SHADER_OPCODE_TG4 || op == SHADER_OPCODE_TG4_OFFSET ||
+ op == SHADER_OPCODE_SAMPLEINFO ||
offset_value.file != BAD_FILE ||
is_high_sampler(devinfo, sampler)) {
/* For general texture offsets (no txf workaround), we need a header to
@@ -4075,6 +4078,10 @@ fs_visitor::lower_logical_sends()
lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_TG4_OFFSET);
break;
+ case SHADER_OPCODE_SAMPLEINFO_LOGICAL:
+ lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_SAMPLEINFO);
+ break;
+
case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
lower_surface_logical_send(ibld, inst,
SHADER_OPCODE_UNTYPED_SURFACE_READ,
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index c86ca04..90805e4 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -646,6 +646,9 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg
dst, struct brw_reg src
msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
}
break;
+ case SHADER_OPCODE_SAMPLEINFO:
+ msg_type = GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO;
+ break;
default:
unreachable("not reached");
}
@@ -1920,6 +1923,7 @@ fs_generator::generate_code(const cfg_t *cfg, int
dispatch_width)
case SHADER_OPCODE_LOD:
case SHADER_OPCODE_TG4:
case SHADER_OPCODE_TG4_OFFSET:
+ case SHADER_OPCODE_SAMPLEINFO:
generate_tex(inst, dst, src[0], src[1]);
break;
case FS_OPCODE_DDX_C
[Mesa-dev] [PATCH 1/2] glsl: add support for textureSamples function
---
src/glsl/builtin_functions.cpp | 32 +-
src/glsl/glcpp/glcpp-parse.y | 3 +++
src/glsl/glsl_parser_extras.cpp| 1 +
src/glsl/glsl_parser_extras.h | 2 ++
src/glsl/ir.cpp| 5 +++--
src/glsl/ir.h | 3 ++-
src/glsl/ir_clone.cpp | 1 +
src/glsl/ir_equals.cpp | 1 +
src/glsl/ir_hv_accept.cpp | 1 +
src/glsl/ir_print_visitor.cpp | 6 --
src/glsl/ir_reader.cpp | 6 +-
src/glsl/ir_rvalue_visitor.cpp | 1 +
src/glsl/nir/glsl_to_nir.cpp | 5 +
src/glsl/nir/nir.h | 4 +++-
src/glsl/nir/nir_print.c | 3 +++
src/glsl/opt_tree_grafting.cpp | 1 +
src/mesa/main/mtypes.h | 1 +
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 2 ++
18 files changed, 70 insertions(+), 8 deletions(-)
diff --git a/src/glsl/builtin_functions.cpp b/src/glsl/builtin_functions.cpp
index 2175c66..1a71d74 100644
--- a/src/glsl/builtin_functions.cpp
+++ b/src/glsl/builtin_functions.cpp
@@ -399,6 +399,13 @@ shader_image_load_store(const _mesa_glsl_parse_state
*state)
}
static bool
+shader_samples(const _mesa_glsl_parse_state *state)
+{
+ return state->is_version(450, 0) ||
+ state->ARB_shader_texture_image_samples_enable;
+}
+
+static bool
gs_streams(const _mesa_glsl_parse_state *state)
{
return gpu_shader5(state) && gs_only(state);
@@ -630,10 +637,10 @@ private:
B1(any);
B1(all);
B1(not);
- B2(textureSize);
ir_function_signature *_textureSize(builtin_available_predicate avail,
const glsl_type *return_type,
const glsl_type *sampler_type);
+ B1(textureSamples);
/** Flags to _texture() */
#define TEX_PROJECT 1
@@ -1372,6 +1379,16 @@ builtin_builder::create_builtins()
_textureSize(texture_multisample, glsl_type::ivec3_type,
glsl_type::usampler2DMSArray_type),
NULL);
+ add_function("textureSamples",
+_textureSamples(glsl_type::sampler2DMS_type),
+_textureSamples(glsl_type::isampler2DMS_type),
+_textureSamples(glsl_type::usampler2DMS_type),
+
+_textureSamples(glsl_type::sampler2DMSArray_type),
+_textureSamples(glsl_type::isampler2DMSArray_type),
+_textureSamples(glsl_type::usampler2DMSArray_type),
+NULL);
+
add_function("texture",
_texture(ir_tex, v130, glsl_type::vec4_type,
glsl_type::sampler1D_type, glsl_type::float_type),
_texture(ir_tex, v130, glsl_type::ivec4_type,
glsl_type::isampler1D_type, glsl_type::float_type),
@@ -4079,6 +4096,19 @@
builtin_builder::_textureSize(builtin_available_predicate avail,
}
ir_function_signature *
+builtin_builder::_textureSamples(const glsl_type *sampler_type)
+{
+ ir_variable *s = in_var(sampler_type, "sampler");
+ MAKE_SIG(glsl_type::int_type, shader_samples, 1, s);
+
+ ir_texture *tex = new(mem_ctx) ir_texture(ir_texture_samples);
+ tex->set_sampler(new(mem_ctx) ir_dereference_variable(s),
glsl_type::int_type);
+ body.emit(ret(tex));
+
+ return sig;
+}
+
+ir_function_signature *
builtin_builder::_texture(ir_texture_opcode opcode,
builtin_available_predicate avail,
const glsl_type *return_type,
diff --git a/src/glsl/glcpp/glcpp-parse.y b/src/glsl/glcpp/glcpp-parse.y
index dd5ec2a..52cae08 100644
--- a/src/glsl/glcpp/glcpp-parse.y
+++ b/src/glsl/glcpp/glcpp-parse.y
@@ -2478,6 +2478,9 @@ _glcpp_parser_handle_version_declaration(glcpp_parser_t
*parser, intmax_t versio
if (extensions->ARB_shader_image_load_store)
add_builtin_define(parser, "GL_ARB_shader_image_load_store",
1);
+ if (extensions->ARB_shader_texture_image_samples)
+add_builtin_define(parser,
"GL_ARB_shader_texture_image_samples", 1);
+
if (extensions->ARB_derivative_control)
add_builtin_define(parser, "GL_ARB_derivative_control", 1);
diff --git a/src/glsl/glsl_parser_extras.cpp b/src/glsl/glsl_parser_extras.cpp
index 46896d7..530cdcc 100644
--- a/src/glsl/glsl_parser_extras.cpp
+++ b/src/glsl/glsl_parser_extras.cpp
@@ -599,6 +599,7 @@ static const _mesa_glsl_extension
_mesa_glsl_supported_extensions[] = {
EXT(ARB_shader_atomic_counters, true, false,
ARB_shader_atomic_counters),
EXT(ARB_shader_bit_encoding, true, false,
ARB_shader_bit_encoding),
EXT(ARB_shader_image_load_store, true, false,
ARB_shader_image_load_store),
+ EXT(ARB_shader_texture_image_samples, true, false,
ARB_shader_texture_image_samples),
EXT(ARB_shader_precision, true, false,
ARB_
Re: [Mesa-dev] [PATCH 2/2][RFC] docs: Add the 2015 ARB extensions
Reviewed-by: Edward O'Callaghan -- Edward O'Callaghan edward.ocallag...@koparo.com On Wed, Aug 12, 2015, at 03:48 AM, Thomas Helland wrote: > Signed-off-by: Thomas Helland > --- > This adds a section for the extensions nvidia has chosen to > call the "GL ARB 2015 Extensions" unveiled at SIGGRAPH. > Also some minor whitespace fixes for consistency. > > We might also want to add other extensions that are not part > of the openGL core specs, but that we want to support. Feel > free to leave your suggestions. GL_ARB_bindless_texture > and GL_ARB_sparse_texture have been nominated. > > docs/GL3.txt | 20 > 1 file changed, 20 insertions(+) > > diff --git a/docs/GL3.txt b/docs/GL3.txt > index 2148ca0..929aafd 100644 > --- a/docs/GL3.txt > +++ b/docs/GL3.txt > @@ -185,6 +185,7 @@ GL 4.4, GLSL 4.40: >GL_ARB_texture_stencil8 DONE (nv50, nvc0, >r600, radeonsi, llvmpipe, softpipe) >GL_ARB_vertex_type_10f_11f_11f_rev DONE (i965, nv50, >nvc0, r600, radeonsi, llvmpipe, softpipe) > > + > GL 4.5, GLSL 4.50: > >GL_ARB_ES3_1_compatibility not started > @@ -201,6 +202,7 @@ GL 4.5, GLSL 4.50: >GL_KHR_robustness90% done (the ARB >variant) >GL_EXT_shader_integer_mixDONE (all drivers >that support GLSL) > > + > These are the extensions cherry-picked to make GLES 3.1 > GLES3.1, GLSL ES 3.1 >GL_ARB_arrays_of_arrays started (Timothy) > @@ -223,6 +225,7 @@ GLES3.1, GLSL ES 3.1 >GS5 Packing/bitfield/conversion functionsDONE (i965, nvc0, >r600, radeonsi) >GL_EXT_shader_integer_mixDONE (all drivers >that support GLSL) > > + > GLES3.2, GLSL ES 3.2 >GL_EXT_color_buffer_floatDONE (all >drivers) >GL_KHR_blend_equation_advanced not started > @@ -248,6 +251,23 @@ GLES3.2, GLSL ES 3.2 >GL_OES_texture_storage_multisample_2d_array not started > > > +GL ARB 2015 (SIGGRAPH) Extensions: > + > + GL_ARB_ES3_2_compatibility not started > + GL_ARB_fragment_shader_interlock not started > + GL_ARB_gpu_shader_int64 not started > + GL_ARB_parallel_shader_compile not started > + GL_ARB_post_depth_coverage not started > + GL_ARB_sample_locations not started > + GL_ARB_shader_atomic_counter_ops not started > + GL_ARB_shader_ballot not started > + GL_ARB_shader_clock not started > + GL_ARB_shader_viewport_layer_array not started > + GL_ARB_sparse_texture2 not started > + GL_ARB_sparse_texture_clamp not started > + GL_ARB_texture_filter_minmax not started > + > + >Additional functions not covered above: >glMemoryBarrierByRegion >glGetTexLevelParameter[fi]v - needs updates to restrict to GLES >enums > -- > 2.5.0 > > ___ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 1/5] main: add extension GL_ARB_shader_image_size
Reviewed-by: Edward O'Callaghan
--
Edward O'Callaghan
edward.ocallag...@koparo.com
On Wed, Aug 12, 2015, at 02:43 AM, Martin Peres wrote:
> Signed-off-by: Martin Peres
> ---
> src/glsl/glcpp/glcpp-parse.y| 3 +++
> src/glsl/glsl_parser_extras.cpp | 1 +
> src/glsl/glsl_parser_extras.h | 2 ++
> src/mesa/main/extensions.c | 1 +
> src/mesa/main/mtypes.h | 1 +
> 5 files changed, 8 insertions(+)
>
> diff --git a/src/glsl/glcpp/glcpp-parse.y b/src/glsl/glcpp/glcpp-parse.y
> index dd5ec2a..18e50af 100644
> --- a/src/glsl/glcpp/glcpp-parse.y
> +++ b/src/glsl/glcpp/glcpp-parse.y
> @@ -2478,6 +2478,9 @@
> _glcpp_parser_handle_version_declaration(glcpp_parser_t *parser, intmax_t
> versio
> if (extensions->ARB_shader_image_load_store)
>add_builtin_define(parser, "GL_ARB_shader_image_load_store",
> 1);
>
> + if (extensions->ARB_shader_image_size)
> + add_builtin_define(parser, "GL_ARB_shader_image_size",
> 1);
> +
>if (extensions->ARB_derivative_control)
> add_builtin_define(parser, "GL_ARB_derivative_control",
> 1);
>
> diff --git a/src/glsl/glsl_parser_extras.cpp
> b/src/glsl/glsl_parser_extras.cpp
> index 46896d7..a4fbb33 100644
> --- a/src/glsl/glsl_parser_extras.cpp
> +++ b/src/glsl/glsl_parser_extras.cpp
> @@ -599,6 +599,7 @@ static const _mesa_glsl_extension
> _mesa_glsl_supported_extensions[] = {
> EXT(ARB_shader_atomic_counters, true, false,
> ARB_shader_atomic_counters),
> EXT(ARB_shader_bit_encoding, true, false,
> ARB_shader_bit_encoding),
> EXT(ARB_shader_image_load_store, true, false,
> ARB_shader_image_load_store),
> + EXT(ARB_shader_image_size,true, false,
> ARB_shader_image_size),
> EXT(ARB_shader_precision, true, false,
> ARB_shader_precision),
> EXT(ARB_shader_stencil_export,true, false,
> ARB_shader_stencil_export),
> EXT(ARB_shader_storage_buffer_object, true, false,
> ARB_shader_storage_buffer_object),
> diff --git a/src/glsl/glsl_parser_extras.h
> b/src/glsl/glsl_parser_extras.h
> index eb325f0..f018f1d 100644
> --- a/src/glsl/glsl_parser_extras.h
> +++ b/src/glsl/glsl_parser_extras.h
> @@ -495,6 +495,8 @@ struct _mesa_glsl_parse_state {
> bool ARB_shader_bit_encoding_warn;
> bool ARB_shader_image_load_store_enable;
> bool ARB_shader_image_load_store_warn;
> + bool ARB_shader_image_size_enable;
> + bool ARB_shader_image_size_warn;
> bool ARB_shader_precision_enable;
> bool ARB_shader_precision_warn;
> bool ARB_shader_stencil_export_enable;
> diff --git a/src/mesa/main/extensions.c b/src/mesa/main/extensions.c
> index 2dbfabd..038a438 100644
> --- a/src/mesa/main/extensions.c
> +++ b/src/mesa/main/extensions.c
> @@ -152,6 +152,7 @@ static const struct extension extension_table[] = {
> { "GL_ARB_shader_atomic_counters",
> o(ARB_shader_atomic_counters), GL, 2011 },
> { "GL_ARB_shader_bit_encoding",
> o(ARB_shader_bit_encoding), GL, 2010 },
> { "GL_ARB_shader_image_load_store",
> o(ARB_shader_image_load_store), GL, 2011 },
> + { "GL_ARB_shader_image_size",
> o(ARB_shader_image_size), GL, 2012 },
> { "GL_ARB_shader_objects", o(dummy_true),
> GL, 2002 },
> { "GL_ARB_shader_precision",
> o(ARB_shader_precision),GL, 2010 },
> { "GL_ARB_shader_stencil_export",
> o(ARB_shader_stencil_export), GL, 2009 },
> diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
> index 4e00fb6..6a0065c 100644
> --- a/src/mesa/main/mtypes.h
> +++ b/src/mesa/main/mtypes.h
> @@ -3862,6 +3862,7 @@ struct gl_extensions
> GLboolean ARB_shader_atomic_counters;
> GLboolean ARB_shader_bit_encoding;
> GLboolean ARB_shader_image_load_store;
> + GLboolean ARB_shader_image_size;
> GLboolean ARB_shader_precision;
> GLboolean ARB_shader_stencil_export;
> GLboolean ARB_shader_storage_buffer_object;
> --
> 2.5.0
>
> ___
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/mesa-dev
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 1/2] r600g: fix polygon offset scale
Reviewed-by: Edward O'Callaghan
--
Edward O'Callaghan
edward.ocallag...@koparo.com
On Wed, Aug 12, 2015, at 09:02 AM, Marek Olšák wrote:
> From: Marek Olšák
>
> The value was copied from r300g, which uses 1/12 subpixels, but this hw
> uses 1/16 subpixels.
>
> Should fix piglit: gl-1.4-polygon-offset (formerly a glean test)
> (untested, ported from radeonsi)
> ---
> src/gallium/drivers/r600/evergreen_state.c | 2 +-
> src/gallium/drivers/r600/r600_state.c | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/src/gallium/drivers/r600/evergreen_state.c
> b/src/gallium/drivers/r600/evergreen_state.c
> index f7a76f6..95987ee 100644
> --- a/src/gallium/drivers/r600/evergreen_state.c
> +++ b/src/gallium/drivers/r600/evergreen_state.c
> @@ -485,7 +485,7 @@ static void *evergreen_create_rs_state(struct
> pipe_context *ctx,
>
> /* offset */
> rs->offset_units = state->offset_units;
> - rs->offset_scale = state->offset_scale * 12.0f;
> + rs->offset_scale = state->offset_scale * 16.0f;
> rs->offset_enable = state->offset_point || state->offset_line ||
> state->offset_tri;
>
> if (state->point_size_per_vertex) {
> diff --git a/src/gallium/drivers/r600/r600_state.c
> b/src/gallium/drivers/r600/r600_state.c
> index 8488188..5cc2283 100644
> --- a/src/gallium/drivers/r600/r600_state.c
> +++ b/src/gallium/drivers/r600/r600_state.c
> @@ -473,7 +473,7 @@ static void *r600_create_rs_state(struct pipe_context
> *ctx,
>
> /* offset */
> rs->offset_units = state->offset_units;
> - rs->offset_scale = state->offset_scale * 12.0f;
> + rs->offset_scale = state->offset_scale * 16.0f;
> rs->offset_enable = state->offset_point || state->offset_line ||
> state->offset_tri;
>
> if (state->point_size_per_vertex) {
> --
> 2.1.4
>
> ___
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/mesa-dev
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 2/2] r600g: allow setting geometry shader sampler states
Reviewed-by: Edward O'Callaghan
--
Edward O'Callaghan
edward.ocallag...@koparo.com
On Wed, Aug 12, 2015, at 09:03 AM, Marek Olšák wrote:
> From: Marek Olšák
>
> We were ignoring them. This is both hilarious and sad.
>
> Cc: mesa-sta...@lists.freedesktop.org
> ---
> src/gallium/drivers/r600/r600_state_common.c | 5 -
> 1 file changed, 5 deletions(-)
>
> diff --git a/src/gallium/drivers/r600/r600_state_common.c
> b/src/gallium/drivers/r600/r600_state_common.c
> index 8d0942f..ee47791 100644
> --- a/src/gallium/drivers/r600/r600_state_common.c
> +++ b/src/gallium/drivers/r600/r600_state_common.c
> @@ -407,11 +407,6 @@ static void r600_bind_sampler_states(struct
> pipe_context *pipe,
>
> assert(start == 0); /* XXX fix below */
>
> - if (shader != PIPE_SHADER_VERTEX &&
> - shader != PIPE_SHADER_FRAGMENT) {
> - return;
> - }
> -
> for (i = 0; i < count; i++) {
> struct r600_pipe_sampler_state *rstate = rstates[i];
>
> --
> 2.1.4
>
> ___
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/mesa-dev
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] r600, compute: setup compute sampler states and views
--
Edward O'Callaghan
edward.ocallag...@koparo.com
On Wed, Aug 12, 2015, at 05:54 AM, Marek Olšák wrote:
> On Mon, Aug 10, 2015 at 8:30 PM, Zoltan Gilian
> wrote:
> > ---
> > src/gallium/drivers/r600/evergreen_compute.c | 25 ++
> > src/gallium/drivers/r600/evergreen_state.c | 30
> > --
> > src/gallium/drivers/r600/evergreend.h| 5 +
> > src/gallium/drivers/r600/r600_pipe.h | 7 +-
> > src/gallium/drivers/r600/r600_state_common.c | 32
> > ++--
> > 5 files changed, 60 insertions(+), 39 deletions(-)
> >
> > diff --git a/src/gallium/drivers/r600/evergreen_compute.c
> > b/src/gallium/drivers/r600/evergreen_compute.c
> > index d71eeb9..e886847 100644
> > --- a/src/gallium/drivers/r600/evergreen_compute.c
> > +++ b/src/gallium/drivers/r600/evergreen_compute.c
> > @@ -504,6 +504,12 @@ static void compute_emit_cs(struct r600_context *ctx,
> > const uint *block_layout,
> > /* Emit constant buffer state */
> > r600_emit_atom(ctx, &ctx->constbuf_state[PIPE_SHADER_COMPUTE].atom);
> >
> > + /* Emit sampler state */
> > + r600_emit_atom(ctx,
> > &ctx->samplers[PIPE_SHADER_COMPUTE].states.atom);
> > +
> > + /* Emit sampler view (texture resource) state */
> > + r600_emit_atom(ctx, &ctx->samplers[PIPE_SHADER_COMPUTE].views.atom);
> > +
> > /* Emit compute shader state */
> > r600_emit_atom(ctx, &ctx->cs_shader_state.atom);
> >
> > @@ -674,25 +680,6 @@ static void evergreen_set_compute_resources(struct
> > pipe_context * ctx_,
> > }
> > }
> >
> > -void evergreen_set_cs_sampler_view(struct pipe_context *ctx_,
> > - unsigned start_slot, unsigned count,
> > - struct pipe_sampler_view **views)
> > -{
> > - struct r600_pipe_sampler_view **resource =
> > - (struct r600_pipe_sampler_view **)views;
> > -
> > - for (unsigned i = 0; i < count; i++){
> > - if (resource[i]) {
> > - assert(i+1 < 12);
> > - /* XXX: Implement */
> > - assert(!"Compute samplers not implemented.");
> > - ///FETCH0 = VTX0 (param buffer),
> > - //FETCH1 = VTX1 (global buffer pool), FETCH2... =
> > TEX
> > - }
> > - }
> > -}
> > -
> > -
> > static void evergreen_set_global_binding(
> > struct pipe_context *ctx_, unsigned first, unsigned n,
> > struct pipe_resource **resources,
> > diff --git a/src/gallium/drivers/r600/evergreen_state.c
> > b/src/gallium/drivers/r600/evergreen_state.c
> > index 688a092..5f68e08 100644
> > --- a/src/gallium/drivers/r600/evergreen_state.c
> > +++ b/src/gallium/drivers/r600/evergreen_state.c
> > @@ -2029,7 +2029,7 @@ static void evergreen_emit_cs_constant_buffers(struct
> > r600_context *rctx, struct
> >
> > static void evergreen_emit_sampler_views(struct r600_context *rctx,
> > struct r600_samplerview_state
> > *state,
> > -unsigned resource_id_base)
> > +unsigned resource_id_base,
> > unsigned pkt_flags)
> > {
> > struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
> > uint32_t dirty_mask = state->dirty_mask;
> > @@ -2042,7 +2042,7 @@ static void evergreen_emit_sampler_views(struct
> > r600_context *rctx,
> > rview = state->views[resource_index];
> > assert(rview);
> >
> > - radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
> > + radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
> > radeon_emit(cs, (resource_id_base + resource_index) * 8);
> > radeon_emit_array(cs, rview->tex_resource_words, 8);
> >
> > @@ -2051,11 +2051,11 @@ static void evergreen_emit_sampler_views(struct
> > r600_context *rctx,
> >
> > rview->tex_resource->b.b.nr_samples > 1 ?
> >
> > RADEON_PRIO_SHADER_TEXTURE_MSAA :
> >
> > RADEON_PRIO_SHADER_TEXTURE_RO);
> > - radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
> > + radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
> > radeon_emit(cs, reloc);
> >
> > if (!rview->skip_mip_address_reloc) {
> > - radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
> > + radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
> > radeon_emit(cs, reloc);
> > }
> > }
> > @@ -2064,17 +2064,26 @@ static void evergreen_emit_sampler_views(struct
> > r600_context *rctx,
> >
> > static void evergreen_emit_vs_sampler_views(struct r600_context *rctx,
> > struct r600_atom *atom)
> > {
> > - evergreen_emit_sampler_views(r
Re: [Mesa-dev] [PATCH] st/mesa: small cleanup in st_extensions.c
Reviewed-by: Edward O'Callaghan
--
Edward O'Callaghan
edward.ocallag...@koparo.com
On Wed, Aug 12, 2015, at 07:34 AM, Ilia Mirkin wrote:
> Reviewed-by: Ilia Mirkin
>
> On Tue, Aug 11, 2015 at 5:26 PM, Marek Olšák wrote:
> > From: Marek Olšák
> >
> > ---
> > src/mesa/state_tracker/st_extensions.c | 40
> > --
> > 1 file changed, 9 insertions(+), 31 deletions(-)
> >
> > diff --git a/src/mesa/state_tracker/st_extensions.c
> > b/src/mesa/state_tracker/st_extensions.c
> > index 5459891..77d6201 100644
> > --- a/src/mesa/state_tracker/st_extensions.c
> > +++ b/src/mesa/state_tracker/st_extensions.c
> > @@ -434,12 +434,14 @@ void st_init_extensions(struct pipe_screen *screen,
> >
> > static const struct st_extension_cap_mapping cap_mapping[] = {
> >{ o(ARB_base_instance),PIPE_CAP_START_INSTANCE
> > },
> > - { o(ARB_buffer_storage),
> > PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT },
> > + { o(ARB_buffer_storage),
> > PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT },
> > + { o(ARB_color_buffer_float),
> > PIPE_CAP_VERTEX_COLOR_UNCLAMPED },
> >{ o(ARB_depth_clamp), PIPE_CAP_DEPTH_CLIP_DISABLE
> > },
> >{ o(ARB_depth_texture),PIPE_CAP_TEXTURE_SHADOW_MAP
> > },
> >{ o(ARB_draw_buffers_blend), PIPE_CAP_INDEP_BLEND_FUNC
> > },
> >{ o(ARB_draw_instanced), PIPE_CAP_TGSI_INSTANCEID
> > },
> >{ o(ARB_fragment_program_shadow), PIPE_CAP_TEXTURE_SHADOW_MAP
> > },
> > + { o(ARB_framebuffer_object),
> > PIPE_CAP_MIXED_FRAMEBUFFER_SIZES },
> >{ o(ARB_instanced_arrays),
> > PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR },
> >{ o(ARB_occlusion_query), PIPE_CAP_OCCLUSION_QUERY
> > },
> >{ o(ARB_occlusion_query2), PIPE_CAP_OCCLUSION_QUERY
> > },
> > @@ -449,6 +451,8 @@ void st_init_extensions(struct pipe_screen *screen,
> >{ o(ARB_shader_stencil_export),
> > PIPE_CAP_SHADER_STENCIL_EXPORT},
> >{ o(ARB_shader_texture_lod), PIPE_CAP_SM3
> > },
> >{ o(ARB_shadow), PIPE_CAP_TEXTURE_SHADOW_MAP
> > },
> > + { o(ARB_texture_buffer_object),
> > PIPE_CAP_TEXTURE_BUFFER_OBJECTS },
> > + { o(ARB_texture_gather),
> > PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS},
> >{ o(ARB_texture_mirror_clamp_to_edge), PIPE_CAP_TEXTURE_MIRROR_CLAMP
> > },
> >{ o(ARB_texture_non_power_of_two), PIPE_CAP_NPOT_TEXTURES
> > },
> >{ o(ARB_timer_query), PIPE_CAP_QUERY_TIMESTAMP
> > },
> > @@ -469,6 +473,7 @@ void st_init_extensions(struct pipe_screen *screen,
> >{ o(ATI_separate_stencil), PIPE_CAP_TWO_SIDED_STENCIL
> > },
> >{ o(ATI_texture_mirror_once), PIPE_CAP_TEXTURE_MIRROR_CLAMP
> > },
> >{ o(NV_conditional_render),PIPE_CAP_CONDITIONAL_RENDER
> > },
> > + { o(NV_primitive_restart), PIPE_CAP_PRIMITIVE_RESTART
> > },
> >{ o(NV_texture_barrier), PIPE_CAP_TEXTURE_BARRIER
> > },
> >/* GL_NV_point_sprite is not supported by gallium because we don't
> > * support the GL_POINT_SPRITE_R_MODE_NV option. */
> > @@ -579,7 +584,8 @@ void st_init_extensions(struct pipe_screen *screen,
> >PIPE_FORMAT_R8G8B8A8_UNORM },
> > GL_TRUE }, /* at least one format must be supported */
> >
> > - { { o(ARB_stencil_texturing) },
> > + { { o(ARB_stencil_texturing),
> > + o(ARB_texture_stencil8) },
> > { PIPE_FORMAT_X24S8_UINT,
> >PIPE_FORMAT_S8X24_UINT },
> > GL_TRUE }, /* at least one format must be supported */
> > @@ -673,9 +679,6 @@ void st_init_extensions(struct pipe_screen *screen,
> >ARRAY_SIZE(vertex_mapping), PIPE_BUFFER,
> >PIPE_BIND_VERTEX_BUFFER);
> >
> > - if (extensions->ARB_stencil_texturing)
> > - extensions->ARB_texture_stencil8 = GL_TRUE;
> > -
> > if (screen->get_param(screen, PIPE_CAP_TEXTURE_FLOAT_LINEAR)) {
> >extensions->OES_texture_float_linear = extensions->OES_texture_float;
> >extensions->OES_texture_half_float_linear =
> > @@ -753,27 +756,11 @@ void st_init_extensions(struct pipe_screen *screen,
> >extensions->ANGLE_texture_compression_dxt = GL_FALSE;
> > }
> >
> > - if (screen->get_shader_param(screen, PIPE_SHADER_GEOMETRY,
> > -PIPE_SHADER_CAP_MAX_INSTRUCTIONS) > 0) {
> > -#if 0 /*
Re: [Mesa-dev] [PATCH] i965/fs: Clamp image array indices to the array bounds on IVB.
On Mon, 2015-07-27 at 16:01 +0300, Francisco Jerez wrote:
> This fixes the spec@arb_shader_image_load_store@invalid index bounds
> piglit tests on IVB, which were causing a GPU hang and then a crash
> due to the invalid binding table index result of the array index
> calculation. Other generations seem to behave sensibly when an
> invalid surface is provided so it doesn't look like we need to care.
> ---
> src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 25 +
> 1 file changed, 21 insertions(+), 4 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> index 1671595..b69e96b 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> @@ -1216,14 +1216,31 @@ fs_visitor::get_nir_image_deref(const nir_deref_var
> *deref)
> nir_deref_as_array(deref->deref.child);
>assert(deref->deref.child->deref_type == nir_deref_type_array &&
> deref_array->deref.child == NULL);
> + const unsigned size = glsl_get_length(deref->var->type);
> + const unsigned base = MIN2(deref_array->base_offset, size - 1);
>
> - image = offset(image, bld,
> - deref_array->base_offset * BRW_IMAGE_PARAM_SIZE);
> + image = offset(image, bld, base * BRW_IMAGE_PARAM_SIZE);
>
>if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
> fs_reg *tmp = new(mem_ctx) fs_reg(vgrf(glsl_type::int_type));
> - bld.MUL(*tmp, get_nir_src(deref_array->indirect),
> - fs_reg(BRW_IMAGE_PARAM_SIZE));
> +
> + if (devinfo->gen == 7 && !devinfo->is_haswell) {
> +/* IVB hangs when trying to access an invalid surface index
> with
> + * the dataport. According to the spec "if the index used to
> + * select an individual element is negative or greater than or
> + * equal to the size of the array, the results of the operation
> + * are undefined but may not lead to termination" -- which is
> one
> + * of the possible outcomes of the hang. Clamp the index to
> + * prevent access outside of the array bounds.
> + */
> +bld.emit_minmax(*tmp, retype(get_nir_src(deref_array
> ->indirect),
> + BRW_REGISTER_TYPE_UD),
> +fs_reg(size - base - 1), BRW_CONDITIONAL_L);
I know this was just pushed but I'm working on AoA support for this, and notic
ed something. Isn't base always going to be 0 in the above line? As it will
only be set to another value for direct indexing.
> + } else {
> +bld.MOV(*tmp, get_nir_src(deref_array->indirect));
> + }
> +
> + bld.MUL(*tmp, *tmp, fs_reg(BRW_IMAGE_PARAM_SIZE));
> image.reladdr = tmp;
>}
> }
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Re: [Mesa-dev] [PATCH 1/2][RFC] docs: Update with GLES3.2 entries and status
On 08/11/2015 08:48 PM, Thomas Helland wrote: Signed-off-by: Thomas Helland --- These are listed to the best of my knowledge, looking at the nvidia driver dropped yesterday, and a glance at the "what changed according to the ARB variant" section of each extension spec. Hopefully it should not be too far off. Feel free to leave your comments docs/GL3.txt | 25 + 1 file changed, 25 insertions(+) diff --git a/docs/GL3.txt b/docs/GL3.txt index 8124383..2148ca0 100644 --- a/docs/GL3.txt +++ b/docs/GL3.txt @@ -223,6 +223,31 @@ GLES3.1, GLSL ES 3.1 GS5 Packing/bitfield/conversion functionsDONE (i965, nvc0, r600, radeonsi) GL_EXT_shader_integer_mixDONE (all drivers that support GLSL) +GLES3.2, GLSL ES 3.2 + GL_EXT_color_buffer_floatDONE (all drivers) + GL_KHR_blend_equation_advanced not started + GL_KHR_debug DONE (all drivers) + GL_KHR_robustness90% done (the ARB variant) + GL_KHR_texture_compression_astc_hdr in progress (Nanley Chery) + GL_OES_copy_image60% done (based on parts of GL_ARB_copy_image, which is done for some drivers) + GL_OES_draw_buffers_indexed not started + GL_OES_draw_elements_base_vertex 90% done (based on GL_ARB_draw_elements_base_verte, which is done for all drivers) + GL_OES_geometry_shader 80% done (based on GL_ARB_geometry_shader4, which is done for all drivers) + GL_OES_gpu_shader5 90% done (based on parts of GL_ARB_gpu_shader5, which is done for some drivers) + GL_OES_primitive_bounding boxnot started + GL_OES_sample_shading90% done (based on parts of GL_ARB_sample_shading, which is done for some drivers) + GL_OES_sample_variables 90% done (based on parts of GL_ARB_sample_shading, which is done for some drivers) + GL_OES_shader_image_atomic 90% done (based on parts of GL_ARB_shader_image_load_store, which is done for some drivers) + GL_OES_shader_io_blocks not started + GL_OES_shader_multisample_interpolation started (based on parts of GL_ARB_gpu_shader5, which is done) + GL_OES_tessellation_shader 90% done (based on GL_ARB_tessellation_shader, which is done for some drivers) + GL_OES_texture_border_clamp 90% done (the ARB variant is done) + GL_OES_texture_buffer90% done (combination of ARB_texture_buffer_object, ARB_texture_buffer_range, and ARB_texture_buffer_object_rgb32 that are all done) + GL_OES_texture_cube_map_array90% done (based on GL_ARB_texture_cube_map_array, which is done for all drivers) + GL_OES_texture_stencil8 90% done (based on parts of GL_ARB_texture_stencil8, which is done for some drivers) + GL_OES_texture_storage_multisample_2d_array not started BTW I've started GL_OES_texture_storage_multisample_2d_array, it's available at http://cgit.freedesktop.org/~tpalli/mesa/log/?h=OES_texture_storage_ms_2d_array In general, I would prefer 'not started' instead of a percentage for these new entries. These values give impression that someone is actually working on item and is going to finish it soon? However if others don't mind then I guess it's ok. Extension list looks correct for me, for the series: Reviewed-by: Tapani Pälli + + Additional functions not covered above: glMemoryBarrierByRegion glGetTexLevelParameter[fi]v - needs updates to restrict to GLES enums ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] mesa/teximage: report the correct function which triggered the error
Reviewed-by: Tapani Pälli
On 08/12/2015 03:09 AM, Nanley Chery wrote:
From: Nanley Chery
This function would always report that a dimension or size error occurred
in glTexImage even when it was called from glCompressedTexImage. Replace
the static string with the dynamically determined caller name.
Signed-off-by: Nanley Chery
---
src/mesa/main/teximage.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c
index 03e45fc..d519fa5 100644
--- a/src/mesa/main/teximage.c
+++ b/src/mesa/main/teximage.c
@@ -3428,15 +3428,15 @@ teximage(struct gl_context *ctx, GLboolean compressed,
GLuint dims,
if (!dimensionsOK) {
_mesa_error(ctx, GL_INVALID_VALUE,
- "glTexImage%uD(invalid width or height or depth)",
- dims);
+ "%s%uD(invalid width or height or depth)",
+ func, dims);
return;
}
if (!sizeOK) {
_mesa_error(ctx, GL_OUT_OF_MEMORY,
- "glTexImage%uD(image too large: %d x %d x %d, %s format)",
- dims, width, height, depth,
+ "%s%uD(image too large: %d x %d x %d, %s format)",
+ func, dims, width, height, depth,
_mesa_enum_to_string(internalFormat));
return;
}
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Re: [Mesa-dev] [PATCH 1/2] glsl: add support for textureSamples function
Hi Ilia;
Some comments below;
On 08/12/2015 04:51 AM, Ilia Mirkin wrote:
---
src/glsl/builtin_functions.cpp | 32 +-
src/glsl/glcpp/glcpp-parse.y | 3 +++
src/glsl/glsl_parser_extras.cpp| 1 +
src/glsl/glsl_parser_extras.h | 2 ++
src/glsl/ir.cpp| 5 +++--
src/glsl/ir.h | 3 ++-
src/glsl/ir_clone.cpp | 1 +
src/glsl/ir_equals.cpp | 1 +
src/glsl/ir_hv_accept.cpp | 1 +
src/glsl/ir_print_visitor.cpp | 6 --
src/glsl/ir_reader.cpp | 6 +-
src/glsl/ir_rvalue_visitor.cpp | 1 +
src/glsl/nir/glsl_to_nir.cpp | 5 +
src/glsl/nir/nir.h | 4 +++-
src/glsl/nir/nir_print.c | 3 +++
src/glsl/opt_tree_grafting.cpp | 1 +
src/mesa/main/mtypes.h | 1 +
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 2 ++
18 files changed, 70 insertions(+), 8 deletions(-)
diff --git a/src/glsl/builtin_functions.cpp b/src/glsl/builtin_functions.cpp
index 2175c66..1a71d74 100644
--- a/src/glsl/builtin_functions.cpp
+++ b/src/glsl/builtin_functions.cpp
@@ -399,6 +399,13 @@ shader_image_load_store(const _mesa_glsl_parse_state
*state)
}
static bool
+shader_samples(const _mesa_glsl_parse_state *state)
+{
+ return state->is_version(450, 0) ||
+ state->ARB_shader_texture_image_samples_enable;
According to the extension spec, 4.30 should be enough for this.
+}
+
+static bool
gs_streams(const _mesa_glsl_parse_state *state)
{
return gpu_shader5(state) && gs_only(state);
@@ -630,10 +637,10 @@ private:
B1(any);
B1(all);
B1(not);
- B2(textureSize);
unrelated cleanup?
ir_function_signature *_textureSize(builtin_available_predicate avail,
const glsl_type *return_type,
const glsl_type *sampler_type);
+ B1(textureSamples);
/** Flags to _texture() */
#define TEX_PROJECT 1
@@ -1372,6 +1379,16 @@ builtin_builder::create_builtins()
_textureSize(texture_multisample, glsl_type::ivec3_type,
glsl_type::usampler2DMSArray_type),
NULL);
+ add_function("textureSamples",
+_textureSamples(glsl_type::sampler2DMS_type),
+_textureSamples(glsl_type::isampler2DMS_type),
+_textureSamples(glsl_type::usampler2DMS_type),
+
+_textureSamples(glsl_type::sampler2DMSArray_type),
+_textureSamples(glsl_type::isampler2DMSArray_type),
+_textureSamples(glsl_type::usampler2DMSArray_type),
+NULL);
+
add_function("texture",
_texture(ir_tex, v130, glsl_type::vec4_type,
glsl_type::sampler1D_type, glsl_type::float_type),
_texture(ir_tex, v130, glsl_type::ivec4_type,
glsl_type::isampler1D_type, glsl_type::float_type),
@@ -4079,6 +4096,19 @@
builtin_builder::_textureSize(builtin_available_predicate avail,
}
ir_function_signature *
+builtin_builder::_textureSamples(const glsl_type *sampler_type)
+{
+ ir_variable *s = in_var(sampler_type, "sampler");
+ MAKE_SIG(glsl_type::int_type, shader_samples, 1, s);
+
+ ir_texture *tex = new(mem_ctx) ir_texture(ir_texture_samples);
+ tex->set_sampler(new(mem_ctx) ir_dereference_variable(s),
glsl_type::int_type);
+ body.emit(ret(tex));
+
+ return sig;
+}
+
+ir_function_signature *
builtin_builder::_texture(ir_texture_opcode opcode,
builtin_available_predicate avail,
const glsl_type *return_type,
diff --git a/src/glsl/glcpp/glcpp-parse.y b/src/glsl/glcpp/glcpp-parse.y
index dd5ec2a..52cae08 100644
--- a/src/glsl/glcpp/glcpp-parse.y
+++ b/src/glsl/glcpp/glcpp-parse.y
@@ -2478,6 +2478,9 @@ _glcpp_parser_handle_version_declaration(glcpp_parser_t
*parser, intmax_t versio
if (extensions->ARB_shader_image_load_store)
add_builtin_define(parser, "GL_ARB_shader_image_load_store",
1);
+ if (extensions->ARB_shader_texture_image_samples)
+add_builtin_define(parser,
"GL_ARB_shader_texture_image_samples", 1);
+
Now that we have GL_ARB_shader_image_load_store, before exposing this
extension we should have imageSamples() supported too. Otherwise these
changes look good for me.
if (extensions->ARB_derivative_control)
add_builtin_define(parser, "GL_ARB_derivative_control", 1);
diff --git a/src/glsl/glsl_parser_extras.cpp b/src/glsl/glsl_parser_extras.cpp
index 46896d7..530cdcc 100644
--- a/src/glsl/glsl_parser_extras.cpp
+++ b/src/glsl/glsl_parser_extras.cpp
@@ -599,6 +599,7 @@ static const _mesa_glsl_extension
_mesa_glsl_supported_extensions[] = {
EXT(ARB_shader_atomic_counters, true,
