Re: [Mesa-dev] [PATCH] scons: add target gallium-osmesa
Hi,
Something wrong with the corrected patch I sent ?
-Message d'origine-
De : mesa-dev [mailto:mesa-dev-boun...@lists.freedesktop.org] De la part de
Olivier PENA
Envoyé : vendredi 10 avril 2015 11:38
À : Jose Fonseca; Emil Velikov; olivier.pena...@gmail.com
Cc : ML mesa-dev
Objet : Re: [Mesa-dev] [PATCH] scons: add target gallium-osmesa
Hi,
I treated your requests and I'm going to send another patch.
Thanks
-Message d'origine-
De : mesa-dev [mailto:mesa-dev-boun...@lists.freedesktop.org] De la part de
Jose Fonseca
Envoyé : mercredi 8 avril 2015 21:55
À : Emil Velikov; olivier.pena...@gmail.com
Cc : ML mesa-dev
Objet : Re: [Mesa-dev] [PATCH] scons: add target gallium-osmesa
Besides the issue Emil mentioned, one minor request: lets call the
target just "osmesa". As we don't plan to have any other "osmesa" target.
Jose
On 08/04/15 18:18, Emil Velikov wrote:
> Hi Olivier
>
> Thanks for the patch !
>
> Adding Jose to the Cc list as I believe he'll have some input on the topic.
>
> On 3 April 2015 at 15:06, wrote:
>> From: Olivier Pena
>>
>> ---
>> src/gallium/SConscript | 5
>> src/gallium/state_trackers/osmesa/SConscript | 25 +
>> src/gallium/state_trackers/osmesa/osmesa.def | 16 +++
>> src/gallium/targets/osmesa/SConscript| 41
>>
>> 4 files changed, 87 insertions(+)
>> create mode 100644 src/gallium/state_trackers/osmesa/SConscript
>> create mode 100644 src/gallium/state_trackers/osmesa/osmesa.def
>> create mode 100644 src/gallium/targets/osmesa/SConscript
>>
> Can you add the three new files into the EXTRA_DIST variable in the
> relevant Makefile.am ? This way one we can build scons gallium-osmesa
> from a release tarball :-)
>
>> diff --git a/src/gallium/SConscript b/src/gallium/SConscript
>> index 680ad92..eeb1c78 100644
>> --- a/src/gallium/SConscript
>> +++ b/src/gallium/SConscript
>> @@ -60,6 +60,11 @@ SConscript([
>> ])
>>
>> if not env['embedded']:
>> +SConscript([
>> +'state_trackers/osmesa/SConscript',
>> +'targets/osmesa/SConscript',
>> +])
>> +
>> if env['x11']:
>> SConscript([
>> 'state_trackers/glx/xlib/SConscript',
>> diff --git a/src/gallium/state_trackers/osmesa/SConscript
>> b/src/gallium/state_trackers/osmesa/SConscript
>> new file mode 100644
>> index 000..fa7c968
>> --- /dev/null
>> +++ b/src/gallium/state_trackers/osmesa/SConscript
>> @@ -0,0 +1,25 @@
>> +import os
>> +
>> +Import('*')
>> +
>> +env = env.Clone()
>> +
>> +env.Append(CPPPATH = [
>> +'#src/mapi',
>> +'#src/mesa',
>> +'.',
>> +])
>> +
>> +env.AppendUnique(CPPDEFINES = [
>> +'BUILD_GL32', # declare gl* as __declspec(dllexport) in Mesa headers
>> +'WIN32_LEAN_AND_MEAN', #
>> https://urldefense.proofpoint.com/v2/url?u=http-3A__msdn2.microsoft.com_en-2Dus_library_6dwk3a1z.aspx&d=AwIBaQ&c=Sqcl0Ez6M0X8aeM67LKIiDJAXVeAw-YihVMNtXt-uEs&r=zfmBZnnVGHeYde45pMKNnVyzeaZbdIqVLprmZCM2zzE&m=V7sOetAjivzNtMiJzzOh63AXslqGWPwHWPoxHrHKbGs&s=2ddtnvnyotNzbqM7WTXS_y4myuI1d-lxwzZA9RPX34o&e=
>> +])
>> +if not env['gles']:
>> +# prevent _glapi_* from being declared __declspec(dllimport)
>> +env.Append(CPPDEFINES = ['_GLAPI_NO_EXPORTS'])
>> +
> Shouldn't these be used when building for windows only ?
>
>> +st_osmesa = env.ConvenienceLibrary(
>> +target ='st_osmesa',
>> +source = env.ParseSourceList('Makefile.sources', 'C_SOURCES'),
>> +)
>> +Export('st_osmesa')
>> diff --git a/src/gallium/state_trackers/osmesa/osmesa.def
>> b/src/gallium/state_trackers/osmesa/osmesa.def
>> new file mode 100644
>> index 000..e2a31ab
>> --- /dev/null
>> +++ b/src/gallium/state_trackers/osmesa/osmesa.def
> Can we move this file next to it's only user - i.e. into targets/osmesa/ ?
>
>> @@ -0,0 +1,16 @@
>> +;DESCRIPTION 'Mesa OSMesa lib for Win32'
>> +VERSION 4.1
>> +
>> +EXPORTS
>> + OSMesaCreateContext
>> + OSMesaCreateContextExt
>> + OSMesaDestroyContext
>> + OSMesaMakeCurrent
>> + OSMesaGetCurrentContext
>> + OSMesaPixelStore
>> + OSMesaGetIntegerv
>> + OSMesaGetDepthBuffer
>> + OSMesaGetColorBuffer
>> + OSMesaGetProcAddress
>> + OSMesaColorClamp
>> + OSMesaPostprocess
>> diff --git a/src/gallium/targets/osmesa/SConscript
>> b/src/gallium/targets/osmesa/SConscript
>> new file mode 100644
>> index 000..2c936cf
>> --- /dev/null
>> +++ b/src/gallium/targets/osmesa/SConscript
>> @@ -0,0 +1,41 @@
>> +Import('*')
>> +
>> +env = env.Clone()
>> +
>> +env.Prepend(CPPPATH = [
>> +'#src/mapi',
>> +'#src/mesa',
>> +#Dir('../../../mapi'), # src/mapi build path for python-generated GL
>> API files/headers
>> +])
>> +
>> +sources = [
>> +'target.c',
>> +]
>> +sources += ['#src/gallium/state_trackers/osmesa/osmesa.def']
>> +
> Afaict this should be included only if the target is Windows.
>
>> +drivers = []
>> +
>> +if env['llvm']:
>> +env.Append(CPPDEFI
[Mesa-dev] [PATCH] softpipe: fix stencil write to use an integer value
From: Dave Airlie This fixes a number of regressions since 61393bdcdc3b63624bf6e9730444f5e9deeedfc8 u_tile: fix stencil texturing tests under softpipe should fix: https://bugs.freedesktop.org/show_bug.cgi?id=89960 Signed-off-by: Dave Airlie --- src/gallium/drivers/softpipe/sp_fs_exec.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/softpipe/sp_fs_exec.c b/src/gallium/drivers/softpipe/sp_fs_exec.c index f3814fd..369ab6e 100644 --- a/src/gallium/drivers/softpipe/sp_fs_exec.c +++ b/src/gallium/drivers/softpipe/sp_fs_exec.c @@ -164,7 +164,7 @@ exec_run( const struct sp_fragment_shader_variant *var, uint j; for (j = 0; j < 4; j++) - quad->output.stencil[j] = (unsigned)machine->Outputs[i].xyzw[1].f[j]; + quad->output.stencil[j] = (unsigned)machine->Outputs[i].xyzw[1].u[j]; } break; } -- 2.1.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 2/4] st/mesa: add ARB_texture_stencil8 support (v4)
Reviewed-by: Marek Olšák
Marek
On Wed, Apr 22, 2015 at 3:43 AM, Dave Airlie wrote:
> if we support stencil texturing, enable texture_stencil8
> there is no requirement to support native S8 for this,
> the texture can be converted to x24s8 fine.
>
> v2: fold fixes from Marek in:
>a) put S8 last in the list
>b) fix renderable to always test for d/s renderable
> fixup the texture case to use a stencil only format
> for picking the format for the texture view.
> v3: hit fallback for getteximage
> v4: put s8 back in front, it shouldn't get picked now (Ilia)
>
> Signed-off-by: Dave Airlie
> ---
> src/mesa/state_tracker/st_atom_texture.c | 14 ++
> src/mesa/state_tracker/st_cb_texture.c | 2 +-
> src/mesa/state_tracker/st_extensions.c | 3 +++
> src/mesa/state_tracker/st_format.c | 19 ---
> 4 files changed, 22 insertions(+), 16 deletions(-)
>
> diff --git a/src/mesa/state_tracker/st_atom_texture.c
> b/src/mesa/state_tracker/st_atom_texture.c
> index eff28fc..04ba864 100644
> --- a/src/mesa/state_tracker/st_atom_texture.c
> +++ b/src/mesa/state_tracker/st_atom_texture.c
> @@ -287,16 +287,22 @@ st_get_texture_sampler_view_from_stobj(struct
> st_context *st,
>enum pipe_format format)
> {
> struct pipe_sampler_view **sv;
> -
> + const struct st_texture_image *firstImage;
> if (!stObj || !stObj->pt) {
>return NULL;
> }
>
> sv = st_texture_get_sampler_view(st, stObj);
>
> - if (stObj->base.StencilSampling &&
> - util_format_is_depth_and_stencil(format))
> - format = util_format_stencil_only(format);
> + if (util_format_is_depth_and_stencil(format)) {
> + if (stObj->base.StencilSampling)
> + format = util_format_stencil_only(format);
> + else {
> + firstImage =
> st_texture_image_const(_mesa_base_tex_image(&stObj->base));
> + if (firstImage->base._BaseFormat == GL_STENCIL_INDEX)
> +format = util_format_stencil_only(format);
> + }
> + }
>
> /* if sampler view has changed dereference it */
> if (*sv) {
> diff --git a/src/mesa/state_tracker/st_cb_texture.c
> b/src/mesa/state_tracker/st_cb_texture.c
> index bdf236e..7ea3846 100644
> --- a/src/mesa/state_tracker/st_cb_texture.c
> +++ b/src/mesa/state_tracker/st_cb_texture.c
> @@ -950,7 +950,7 @@ st_GetTexImage(struct gl_context * ctx,
>
> /* XXX Fallback to _mesa_GetTexImage_sw for depth-stencil formats
> * due to an incomplete stencil blit implementation in some drivers. */
> - if (format == GL_DEPTH_STENCIL) {
> + if (format == GL_DEPTH_STENCIL || format == GL_STENCIL_INDEX) {
>goto fallback;
> }
>
> diff --git a/src/mesa/state_tracker/st_extensions.c
> b/src/mesa/state_tracker/st_extensions.c
> index bc20f73..25932dd 100644
> --- a/src/mesa/state_tracker/st_extensions.c
> +++ b/src/mesa/state_tracker/st_extensions.c
> @@ -650,6 +650,9 @@ void st_init_extensions(struct pipe_screen *screen,
>ARRAY_SIZE(vertex_mapping), PIPE_BUFFER,
>PIPE_BIND_VERTEX_BUFFER);
>
> + if (extensions->ARB_stencil_texturing)
> + extensions->ARB_texture_stencil8 = GL_TRUE;
> +
> /* Figure out GLSL support. */
> glsl_feature_level = screen->get_param(screen,
> PIPE_CAP_GLSL_FEATURE_LEVEL);
>
> diff --git a/src/mesa/state_tracker/st_format.c
> b/src/mesa/state_tracker/st_format.c
> index 72dbf3b..181465d 100644
> --- a/src/mesa/state_tracker/st_format.c
> +++ b/src/mesa/state_tracker/st_format.c
> @@ -1942,11 +1942,6 @@ st_ChooseTextureFormat(struct gl_context *ctx, GLenum
> target,
> GLint internalFormat,
> GLenum format, GLenum type)
> {
> - const boolean want_renderable =
> - internalFormat == 3 || internalFormat == 4 ||
> - internalFormat == GL_RGB || internalFormat == GL_RGBA ||
> - internalFormat == GL_RGB8 || internalFormat == GL_RGBA8 ||
> - internalFormat == GL_BGRA;
> struct st_context *st = st_context(ctx);
> enum pipe_format pFormat;
> unsigned bindings;
> @@ -1962,15 +1957,17 @@ st_ChooseTextureFormat(struct gl_context *ctx, GLenum
> target,
> }
>
> /* GL textures may wind up being render targets, but we don't know
> -* that in advance. Specify potential render target flags now.
> +* that in advance. Specify potential render target flags now for formats
> +* that we know should always be renderable.
> */
> bindings = PIPE_BIND_SAMPLER_VIEW;
> - if (want_renderable) {
> - if (_mesa_is_depth_or_stencil_format(internalFormat))
> -bindings |= PIPE_BIND_DEPTH_STENCIL;
> - else
> + if (_mesa_is_depth_or_stencil_format(internalFormat))
> + bindings |= PIPE_BIND_DEPTH_STENCIL;
> + else if (internalFormat == 3 || internalFormat == 4 ||
> +internalFormat == GL_RGB || internalFormat == GL_RGBA ||
> +internalFormat == GL_RGB8 ||
[Mesa-dev] Patch: typo fixing
Hi! I took the liberty of fixing a few typos. If anyone's interested, you can download the Git patch from http://bytenoise.co.uk/misc/fix-a-few-typos.patch . I've never had much luck compiling other people's projects, so this warrants vetting by someone smarter than me, I'm afraid. Still, I hope it's of use to you! All the best, Zoë. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] Patch: typo fixing
Zoë Blade writes: > Hi! > > I took the liberty of fixing a few typos. If anyone's interested, you can > download the Git patch from http://bytenoise.co.uk/misc/fix-a-few-typos.patch > . I've never had much luck compiling other people's projects, so this > warrants vetting by someone smarter than me, I'm afraid. Still, I hope it's > of use to you! > Looks fine to me, just one minor comment. | diff --git a/src/mesa/drivers/dri/i965/brw_clip_unfilled.c | b/src/mesa/drivers/dri/i965/brw_clip_unfilled.c | index 82d7b64..974b61d 100644 | --- a/src/mesa/drivers/dri/i965/brw_clip_unfilled.c | +++ b/src/mesa/drivers/dri/i965/brw_clip_unfilled.c | @@ -135,9 +135,9 @@ static void copy_bfc( struct brw_clip_compile *c ) | brw_clip_have_varying(c, VARYING_SLOT_BFC1))) | return; | | - /* In some wierd degnerate cases we can end up testing the | + /* In some weird degnerate cases we can end up testing the In this line there is a second typo in "degnerate". | * direction twice, once for culling and once for bfc copying. Oh | -* well, that's what you get for setting wierd GL state. | +* well, that's what you get for setting weird GL state. | */ With that fixed, Reviewed-by: Francisco Jerez > All the best, > Zoë. Thanks! > ___ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/mesa-dev signature.asc Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] scons: add target gallium-osmesa
Yes, it fails with Mingw (I only tried with Linux cross-compilation):
$ scons platform=windows osmesa
scons: Reading SConscript files ...
Checking for GCC ... yes
Checking for Clang ... no
scons: Using build cache in /home/jfonseca/.sconscache.
Checking for X11 (x11 xext xdamage xfixes glproto >= 1.4.13)... no
Checking for XCB (x11-xcb xcb-glx >= 1.8.1 xcb-dri2 >= 1.8)... no
Checking for XF86VIDMODE (xxf86vm)... no
Checking for DRM (libdrm >= 2.4.38)... no
Checking for UDEV (libudev >= 151)... no
Checking for GCC ... yes
Checking for Clang ... no
scons: Using build cache in /home/jfonseca/.sconscache.
Checking for X11 (x11 xext xdamage xfixes glproto >= 1.4.13)... yes
Checking for XCB (x11-xcb xcb-glx >= 1.8.1 xcb-dri2 >= 1.8)... yes
Checking for XF86VIDMODE (xxf86vm)... yes
Checking for DRM (libdrm >= 2.4.38)... yes
Checking for UDEV (libudev >= 151)... yes
warning: LLVM disabled: not building llvmpipe
scons: done reading SConscript files.
scons: Building targets ...
Linking build/windows-x86-debug/gallium/targets/osmesa/osmesa.dll ...
Cannot export OSMesaColorClamp: symbol not defined
Cannot export OSMesaCreateContext: symbol not defined
Cannot export OSMesaCreateContextExt: symbol not defined
Cannot export OSMesaDestroyContext: symbol not defined
Cannot export OSMesaGetColorBuffer: symbol not defined
Cannot export OSMesaGetCurrentContext: symbol not defined
Cannot export OSMesaGetDepthBuffer: symbol not defined
Cannot export OSMesaGetIntegerv: symbol not defined
Cannot export OSMesaGetProcAddress: symbol not defined
Cannot export OSMesaMakeCurrent: symbol not defined
Cannot export OSMesaPixelStore: symbol not defined
Cannot export OSMesaPostprocess: symbol not defined
collect2: ld returned 1 exit status
scons: *** [build/windows-x86-debug/gallium/targets/osmesa/osmesa.dll]
Error 1
scons: building terminated because of errors.
I suspect the order that libries is set is wrong (because GNU linker is
sensitve to the order of libaries.)
But I haven;t had time to figure it out.
My recommendatino would be to match what
src/gallium/targets/libgl-gdi/SConscript does. It's known to work. (Yes,
that basically means go back on Emil's suggestion.)
Jose
On 22/04/15 08:39, Olivier PENA wrote:
Hi,
Something wrong with the corrected patch I sent ?
-Message d'origine-
De : mesa-dev [mailto:mesa-dev-boun...@lists.freedesktop.org] De la part de
Olivier PENA
Envoyé : vendredi 10 avril 2015 11:38
À : Jose Fonseca; Emil Velikov; olivier.pena...@gmail.com
Cc : ML mesa-dev
Objet : Re: [Mesa-dev] [PATCH] scons: add target gallium-osmesa
Hi,
I treated your requests and I'm going to send another patch.
Thanks
-Message d'origine-
De : mesa-dev [mailto:mesa-dev-boun...@lists.freedesktop.org] De la part de
Jose Fonseca
Envoyé : mercredi 8 avril 2015 21:55
À : Emil Velikov; olivier.pena...@gmail.com
Cc : ML mesa-dev
Objet : Re: [Mesa-dev] [PATCH] scons: add target gallium-osmesa
Besides the issue Emil mentioned, one minor request: lets call the
target just "osmesa". As we don't plan to have any other "osmesa" target.
Jose
On 08/04/15 18:18, Emil Velikov wrote:
Hi Olivier
Thanks for the patch !
Adding Jose to the Cc list as I believe he'll have some input on the topic.
On 3 April 2015 at 15:06, wrote:
From: Olivier Pena
---
src/gallium/SConscript | 5
src/gallium/state_trackers/osmesa/SConscript | 25 +
src/gallium/state_trackers/osmesa/osmesa.def | 16 +++
src/gallium/targets/osmesa/SConscript| 41
4 files changed, 87 insertions(+)
create mode 100644 src/gallium/state_trackers/osmesa/SConscript
create mode 100644 src/gallium/state_trackers/osmesa/osmesa.def
create mode 100644 src/gallium/targets/osmesa/SConscript
Can you add the three new files into the EXTRA_DIST variable in the
relevant Makefile.am ? This way one we can build scons gallium-osmesa
from a release tarball :-)
diff --git a/src/gallium/SConscript b/src/gallium/SConscript
index 680ad92..eeb1c78 100644
--- a/src/gallium/SConscript
+++ b/src/gallium/SConscript
@@ -60,6 +60,11 @@ SConscript([
])
if not env['embedded']:
+SConscript([
+'state_trackers/osmesa/SConscript',
+'targets/osmesa/SConscript',
+])
+
if env['x11']:
SConscript([
'state_trackers/glx/xlib/SConscript',
diff --git a/src/gallium/state_trackers/osmesa/SConscript
b/src/gallium/state_trackers/osmesa/SConscript
new file mode 100644
index 000..fa7c968
--- /dev/null
+++ b/src/gallium/state_trackers/osmesa/SConscript
@@ -0,0 +1,25 @@
+import os
+
+Import('*')
+
+env = env.Clone()
+
+env.Append(CPPPATH = [
+'#src/mapi',
+'#src/mesa',
+'.',
+])
+
+env.AppendUnique(CPPDEFINES = [
+'BUILD_GL32', # declare gl* as __declspec(dllexport) in Mesa headers
+'WIN32_LEAN_AND_MEAN', #
https://urldefense.proofpoint.com/v2/url?u=http-3A__msdn2.microsoft.com_en-2Dus_library_6
Re: [Mesa-dev] Patch: typo fixing
Hi! > In this line there is a second typo in "degnerate". Very well spotted, thank you! I've now fixed that particular typo, which appears in two different places: src/mesa/drivers/dri/i965/brw_clip_unfilled.c src/mesa/vbo/vbo_save_draw.c While I was at it, I spotted two more typos, now fixed: docs/relnotes/10.0.3.html src/gallium/drivers/llvmpipe/lp_scene.h I've amended http://bytenoise.co.uk/misc/fix-a-few-typos.patch with these additions. Thanks, Zoë. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] softpipe: fix stencil write to use an integer value
Reviewed-by: Roland Scheidegger Am 22.04.2015 um 09:41 schrieb Dave Airlie: > From: Dave Airlie > > This fixes a number of regressions since > 61393bdcdc3b63624bf6e9730444f5e9deeedfc8 > u_tile: fix stencil texturing tests under softpipe > > should fix: > https://bugs.freedesktop.org/show_bug.cgi?id=89960 > > Signed-off-by: Dave Airlie > --- > src/gallium/drivers/softpipe/sp_fs_exec.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/src/gallium/drivers/softpipe/sp_fs_exec.c > b/src/gallium/drivers/softpipe/sp_fs_exec.c > index f3814fd..369ab6e 100644 > --- a/src/gallium/drivers/softpipe/sp_fs_exec.c > +++ b/src/gallium/drivers/softpipe/sp_fs_exec.c > @@ -164,7 +164,7 @@ exec_run( const struct sp_fragment_shader_variant *var, > uint j; > > for (j = 0; j < 4; j++) > - quad->output.stencil[j] = > (unsigned)machine->Outputs[i].xyzw[1].f[j]; > + quad->output.stencil[j] = > (unsigned)machine->Outputs[i].xyzw[1].u[j]; > } > break; > } > ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 90130] gl_PrimitiveId seems to reset at 340
https://bugs.freedesktop.org/show_bug.cgi?id=90130 --- Comment #6 from Ken Martin --- Created attachment 115271 --> https://bugs.freedesktop.org/attachment.cgi?id=115271&action=edit apitrace file Here is the apitrace file -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 90130] gl_PrimitiveId seems to reset at 340
https://bugs.freedesktop.org/show_bug.cgi?id=90130 --- Comment #7 from Ken Martin --- And here is the driver using the propoer LD_LIBRARY_PATH OpenGL vendor string: VMware, Inc. OpenGL renderer string: Gallium 0.4 on llvmpipe (LLVM 3.5, 128 bits) OpenGL version string: 3.0 Mesa 10.5.3 OpenGL shading language version string: 1.30 OpenGL context flags: (none) So I guess thast means llvmpipe with mesa 10.5.3 -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] softpipe: fix stencil write to use an integer value
On 04/22/2015 01:41 AM, Dave Airlie wrote: From: Dave Airlie This fixes a number of regressions since 61393bdcdc3b63624bf6e9730444f5e9deeedfc8 u_tile: fix stencil texturing tests under softpipe should fix: https://bugs.freedesktop.org/show_bug.cgi?id=89960 Signed-off-by: Dave Airlie --- src/gallium/drivers/softpipe/sp_fs_exec.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/softpipe/sp_fs_exec.c b/src/gallium/drivers/softpipe/sp_fs_exec.c index f3814fd..369ab6e 100644 --- a/src/gallium/drivers/softpipe/sp_fs_exec.c +++ b/src/gallium/drivers/softpipe/sp_fs_exec.c @@ -164,7 +164,7 @@ exec_run( const struct sp_fragment_shader_variant *var, uint j; for (j = 0; j < 4; j++) - quad->output.stencil[j] = (unsigned)machine->Outputs[i].xyzw[1].f[j]; + quad->output.stencil[j] = (unsigned)machine->Outputs[i].xyzw[1].u[j]; } break; } Reviewed-by: Brian Paul ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 90130] gl_PrimitiveId seems to reset at 340
https://bugs.freedesktop.org/show_bug.cgi?id=90130 --- Comment #8 from Ken Martin --- Created attachment 115274 --> https://bugs.freedesktop.org/attachment.cgi?id=115274&action=edit Valid Image Here is what the image should look like, the cells are colored with the red channel being gl_PrimitiveId%256 and the green channel being ((gl_PrimitiveID/256)%6)/5.0 Just did that to try to see what is happening with the primitive ID. -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] softpipe: fix stencil write to use an integer value
On Wed, Apr 22, 2015 at 12:41 AM, Dave Airlie wrote: > From: Dave Airlie > > This fixes a number of regressions since > 61393bdcdc3b63624bf6e9730444f5e9deeedfc8 > u_tile: fix stencil texturing tests under softpipe > > should fix: > https://bugs.freedesktop.org/show_bug.cgi?id=89960 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89960 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] scons: add target gallium-osmesa
I setted up a virtual machine working on linux in order to reproduce (we only works on windows platform here). The libraries order doesn't matter, a verbose compilation shows --start-group and --end-group linker flags. It seems the def file is not well understood by the linker. I workaround like in the libgl-gdi targets. I'll send another patch, please tell me if something is wrong. -Message d'origine- De : Jose Fonseca [mailto:jfons...@vmware.com] Envoyé : mercredi 22 avril 2015 14:04 À : Olivier PENA; Emil Velikov Cc : ML mesa-dev Objet : Re: [Mesa-dev] [PATCH] scons: add target gallium-osmesa Yes, it fails with Mingw (I only tried with Linux cross-compilation): $ scons platform=windows osmesa scons: Reading SConscript files ... Checking for GCC ... yes Checking for Clang ... no scons: Using build cache in /home/jfonseca/.sconscache. Checking for X11 (x11 xext xdamage xfixes glproto >= 1.4.13)... no Checking for XCB (x11-xcb xcb-glx >= 1.8.1 xcb-dri2 >= 1.8)... no Checking for XF86VIDMODE (xxf86vm)... no Checking for DRM (libdrm >= 2.4.38)... no Checking for UDEV (libudev >= 151)... no Checking for GCC ... yes Checking for Clang ... no scons: Using build cache in /home/jfonseca/.sconscache. Checking for X11 (x11 xext xdamage xfixes glproto >= 1.4.13)... yes Checking for XCB (x11-xcb xcb-glx >= 1.8.1 xcb-dri2 >= 1.8)... yes Checking for XF86VIDMODE (xxf86vm)... yes Checking for DRM (libdrm >= 2.4.38)... yes Checking for UDEV (libudev >= 151)... yes warning: LLVM disabled: not building llvmpipe scons: done reading SConscript files. scons: Building targets ... Linking build/windows-x86-debug/gallium/targets/osmesa/osmesa.dll ... Cannot export OSMesaColorClamp: symbol not defined Cannot export OSMesaCreateContext: symbol not defined Cannot export OSMesaCreateContextExt: symbol not defined Cannot export OSMesaDestroyContext: symbol not defined Cannot export OSMesaGetColorBuffer: symbol not defined Cannot export OSMesaGetCurrentContext: symbol not defined Cannot export OSMesaGetDepthBuffer: symbol not defined Cannot export OSMesaGetIntegerv: symbol not defined Cannot export OSMesaGetProcAddress: symbol not defined Cannot export OSMesaMakeCurrent: symbol not defined Cannot export OSMesaPixelStore: symbol not defined Cannot export OSMesaPostprocess: symbol not defined collect2: ld returned 1 exit status scons: *** [build/windows-x86-debug/gallium/targets/osmesa/osmesa.dll] Error 1 scons: building terminated because of errors. I suspect the order that libries is set is wrong (because GNU linker is sensitve to the order of libaries.) But I haven;t had time to figure it out. My recommendatino would be to match what src/gallium/targets/libgl-gdi/SConscript does. It's known to work. (Yes, that basically means go back on Emil's suggestion.) Jose On 22/04/15 08:39, Olivier PENA wrote: > Hi, > Something wrong with the corrected patch I sent ? > > > -Message d'origine- > De : mesa-dev [mailto:mesa-dev-boun...@lists.freedesktop.org] De la part de > Olivier PENA > Envoyé : vendredi 10 avril 2015 11:38 > À : Jose Fonseca; Emil Velikov; olivier.pena...@gmail.com > Cc : ML mesa-dev > Objet : Re: [Mesa-dev] [PATCH] scons: add target gallium-osmesa > > Hi, > I treated your requests and I'm going to send another patch. > Thanks > > -Message d'origine- > De : mesa-dev [mailto:mesa-dev-boun...@lists.freedesktop.org] De la part de > Jose Fonseca > Envoyé : mercredi 8 avril 2015 21:55 > À : Emil Velikov; olivier.pena...@gmail.com > Cc : ML mesa-dev > Objet : Re: [Mesa-dev] [PATCH] scons: add target gallium-osmesa > > Besides the issue Emil mentioned, one minor request: lets call the > target just "osmesa". As we don't plan to have any other "osmesa" target. > > Jose > > On 08/04/15 18:18, Emil Velikov wrote: >> Hi Olivier >> >> Thanks for the patch ! >> >> Adding Jose to the Cc list as I believe he'll have some input on the topic. >> >> On 3 April 2015 at 15:06, wrote: >>> From: Olivier Pena >>> >>> --- >>>src/gallium/SConscript | 5 >>>src/gallium/state_trackers/osmesa/SConscript | 25 + >>>src/gallium/state_trackers/osmesa/osmesa.def | 16 +++ >>>src/gallium/targets/osmesa/SConscript| 41 >>> >>>4 files changed, 87 insertions(+) >>>create mode 100644 src/gallium/state_trackers/osmesa/SConscript >>>create mode 100644 src/gallium/state_trackers/osmesa/osmesa.def >>>create mode 100644 src/gallium/targets/osmesa/SConscript >>> >> Can you add the three new files into the EXTRA_DIST variable in the >> relevant Makefile.am ? This way one we can build scons gallium-osmesa >> from a release tarball :-) >> >>> diff --git a/src/gallium/SConscript b/src/gallium/SConscript >>> index 680ad92..eeb1c78 100644 >>> --- a/src/gallium/SConscript >>> +++ b/src/gallium/SConscript >>> @@ -60,6 +60,11 @@ SConscript([ >>>]) >>> >>>if not env['embedded']: >>> +SConscript([
[Mesa-dev] [Bug 90130] gl_PrimitiveId seems to reset at 340
https://bugs.freedesktop.org/show_bug.cgi?id=90130
--- Comment #9 from Ken Martin ---
(In reply to Roland Scheidegger from comment #5)
> Or even better, a piglit test :-).
>
> I suspect there's an issue with the prim assembler in draw.
> Since from a quick look it seems like the prim assembler would always reset
> the prim_id it's going to inject whenever it's run, and that's going to
> happen per chunk (as we don't process all vertices in a draw call at once if
> there's too many). Probably would need to fix that somehow so it's only
> reset per instance.
> We possibly (?) handle this correctly if there's a gs.
(In reply to Roland Scheidegger from comment #5)
> Or even better, a piglit test :-).
>
> I suspect there's an issue with the prim assembler in draw.
> Since from a quick look it seems like the prim assembler would always reset
> the prim_id it's going to inject whenever it's run, and that's going to
> happen per chunk (as we don't process all vertices in a draw call at once if
> there's too many). Probably would need to fix that somehow so it's only
> reset per instance.
> We possibly (?) handle this correctly if there's a gs.
Any suggestion on a piglit test to use as a starting point? It would need
OpenGL 3.2 and the basic test would be
draw say 1 triangles each covering the entire window with this fragment
shader
#version 150
main
{
// throw out the first triangles (0 to 9998)
if (glPrimitiveID < ) { discard; }
// for the last triangle create the color based on glPrimitiveId
gl_FragColor = vec4(glPrimitiveId%256,glPrimitiveId/256,0.0,1.0);
}
Then test the color of a pixel to see if it is RGBA (15,39,0,255) or the equiv
in float.
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[Mesa-dev] [Bug 90130] gl_PrimitiveId seems to reset at 340
https://bugs.freedesktop.org/show_bug.cgi?id=90130 --- Comment #10 from Ken Martin --- Bah how do you edit comments? Both of the above comments should be glPrimitiveId%256/255.0 etc to make sure the resulting value is in the range of 0.0 to 1.0 of course. -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 90130] gl_PrimitiveId seems to reset at 340
https://bugs.freedesktop.org/show_bug.cgi?id=90130 --- Comment #11 from Roland Scheidegger --- Well I think there's already piglit tests which test this functionality (primitive-id-no-gs and similar), but they might not hit it because they only test a couple of primitives and not that many. Not sure though if they could be extended to test larger draw calls easily. I did some very quick hack with the prim assembler (not resetting the prim id at all when it is run, which is at least as wrong but I think should work with this example) and it indeed looked quite a bit different. Still not the same as the comparison image though (circle seemed to have way more segments???) -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 90130] gl_PrimitiveId seems to reset at 340
https://bugs.freedesktop.org/show_bug.cgi?id=90130 --- Comment #12 from Ken Martin --- Created attachment 115275 --> https://bugs.freedesktop.org/attachment.cgi?id=115275&action=edit Even More Valid Image Doh. I am working from two different source trees and I suspect I had the resolution of the sphere set differently on those two runs. Maybe this image matches your patched run. -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 90130] gl_PrimitiveId seems to reset at 340
https://bugs.freedesktop.org/show_bug.cgi?id=90130 --- Comment #13 from Ilia Mirkin --- FWIW this is what I get with nouveau on a nvc1: http://i.imgur.com/8QS20cp.png Matches your "even more valid image" attachment, I think. -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 22.5/23] mesa: remove the gl_sl_pragmas structure
This code was added by Brian Paul in 2009 but, as far as Matt and I can
tell, it's been dead ever since the new GLSL compiler was added.
---
src/glsl/standalone_scaffolding.cpp | 3 ---
src/mesa/main/mtypes.h | 13 -
src/mesa/main/shaderapi.c | 6 --
3 files changed, 22 deletions(-)
diff --git a/src/glsl/standalone_scaffolding.cpp
b/src/glsl/standalone_scaffolding.cpp
index 6f5a27f..a109c4e 100644
--- a/src/glsl/standalone_scaffolding.cpp
+++ b/src/glsl/standalone_scaffolding.cpp
@@ -189,9 +189,6 @@ void initialize_context_to_defaults(struct gl_context *ctx,
gl_api api)
options.MaxUnrollIterations = 32;
options.MaxIfDepth = UINT_MAX;
- /* Default pragma settings */
- options.DefaultPragmas.Optimize = true;
-
for (int sh = 0; sh < MESA_SHADER_STAGES; ++sh)
memcpy(&ctx->Const.ShaderCompilerOptions[sh], &options, sizeof(options));
}
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 1c751cf..fb41430 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -2365,16 +2365,6 @@ struct gl_ati_fragment_shader_state
};
-/** Set by #pragma directives */
-struct gl_sl_pragmas
-{
- GLboolean IgnoreOptimize; /**< ignore #pragma optimize(on/off) ? */
- GLboolean IgnoreDebug; /**< ignore #pragma debug(on/off) ? */
- GLboolean Optimize; /**< defaults on */
- GLboolean Debug; /**< defaults off */
-};
-
-
/**
* A GLSL vertex or fragment shader object.
*/
@@ -2397,7 +2387,6 @@ struct gl_shader
struct gl_program *Program; /**< Post-compile assembly code */
GLchar *InfoLog;
- struct gl_sl_pragmas Pragmas;
unsigned Version; /**< GLSL version used for linking */
@@ -2903,8 +2892,6 @@ struct gl_shader_compiler_options
*/
GLboolean OptimizeForAOS;
- struct gl_sl_pragmas DefaultPragmas; /**< Default #pragma settings */
-
const struct nir_shader_compiler_options *NirOptions;
};
diff --git a/src/mesa/main/shaderapi.c b/src/mesa/main/shaderapi.c
index 77e2b87..cc001ba 100644
--- a/src/mesa/main/shaderapi.c
+++ b/src/mesa/main/shaderapi.c
@@ -115,9 +115,6 @@ _mesa_init_shader_state(struct gl_context *ctx)
options.MaxUnrollIterations = 32;
options.MaxIfDepth = UINT_MAX;
- /* Default pragma settings */
- options.DefaultPragmas.Optimize = GL_TRUE;
-
for (sh = 0; sh < MESA_SHADER_STAGES; ++sh)
memcpy(&ctx->Const.ShaderCompilerOptions[sh], &options, sizeof(options));
@@ -872,9 +869,6 @@ compile_shader(struct gl_context *ctx, GLuint shaderObj)
options = &ctx->Const.ShaderCompilerOptions[sh->Stage];
- /* set default pragma state for shader */
- sh->Pragmas = options->DefaultPragmas;
-
if (!sh->Source) {
/* If the user called glCompileShader without first calling
* glShaderSource, we should fail to compile, but not raise a GL_ERROR.
--
2.3.5
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[Mesa-dev] [Bug 90130] gl_PrimitiveId seems to reset at 340
https://bugs.freedesktop.org/show_bug.cgi?id=90130 --- Comment #14 from Roland Scheidegger --- (In reply to Ken Martin from comment #12) > Created attachment 115275 [details] > Even More Valid Image > > Doh. I am working from two different source trees and I suspect I had the > resolution of the sphere set differently on those two runs. Maybe this image > matches your patched run. Yeah looks like it (only the first frame though the trace redraws the same thing and then it looks different presumably because the prim id didn't get reset for the second draw...). Not sure yet how to fix it properly, those prim ids are slightly annoying because how they are created differs completely if there's a gs or not in our code. But somehow the primid really needs to happen per instance. -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] i965: Remove end-of-thread SEND alignment code.
On Tue, Apr 21, 2015 at 10:08 PM, Kenneth Graunke wrote: > On Tuesday, April 21, 2015 03:25:07 PM Matt Turner wrote: >> This was present in Eric's initial implementation of the compaction code >> for Sandybridge (commit 077d01b6). There is no documentation saying this >> is necessary, and removing it causes no regressions in piglit on any >> platform. >> >> In fact, the BSpec says >> >>- "[Nop and Illegal] cannot be compressed."; and > > That's "compression", not "compaction" - it doesn't seem related. Right, that's the millionth time someone has made that mistake :) > Compressed NOPs or ILLEGALs (nop(16) that decodes as two nop(8)s?) do > seem entirely pointless. Compacted NOPs make sense. > >>- "Currently, there is no need for between-instruction padding." > > This text appears in the original 965 PRM...and that platform didn't > support instruction compaction at all. So I expect the text has been > carried forward from generation to generation without much thought, > rather than intended to convey something about compacted NOPs. Yeah, that's probably true. I'll drop both of these quotes. > The fact that this hasn't broken anything is compelling, though...I > wonder if we had a bug in the code to create padding between SIMD8 and > SIMD16 programs, and aligning the EOT on the SIMD8 prevented the entire > SIMD16 program from getting misaligned? I think that seems like the most plausible reason. After my commit that stopped passing over the SIMD8 program when compacting the SIMD16 program I bet if that was the problem stopped existing. commit 9976294e867785ea480f52178a3d3dc67ac72d32 Author: Matt Turner Date: Thu May 15 16:56:13 2014 -0700 i965: Pass in start_offset to brw_compact_instructions(). Let's us avoid recompacting the SIMD8 instructions when we compact the SIMD16 program. Reviewed-by: Eric Anholt > I can't find any documentation indicating it's necessary either. Yeah, that was Paul's assessment when he reviewed the original patch as well. Reviewed-by/Acked-by? ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 90130] gl_PrimitiveId seems to reset at 340
https://bugs.freedesktop.org/show_bug.cgi?id=90130 --- Comment #15 from Ken Martin --- (In reply to Ilia Mirkin from comment #13) > FWIW this is what I get with nouveau on a nvc1: > http://i.imgur.com/8QS20cp.png > > Matches your "even more valid image" attachment, I think. Yes that matches and shows that the primitiveID is going up as it should. -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [RFC PATCH 1/2] glsl: Transform pow(x, 4) into (x*x)*(x*x).
On Fri, Apr 17, 2015 at 1:56 PM, Matt Turner wrote: > Updated numbers look a lot better! > > On Tue, Mar 17, 2015 at 4:23 PM, Matt Turner wrote: >> Without NIR: >> >> total instructions in shared programs: 6190374 -> 6190153 (-0.00%) >> instructions in affected programs: 61126 -> 60905 (-0.36%) >> helped:156 > > total instructions in shared programs: 6191351 -> 6191130 (-0.00%) > instructions in affected programs: 61032 -> 60811 (-0.36%) > helped:156 > >> With NIR: >> >> total instructions in shared programs: 6271584 -> 6271471 (-0.00%) >> instructions in affected programs: 47656 -> 47543 (-0.24%) >> helped:113 >> GAINED:4 >> LOST: 41 > > total instructions in shared programs: 6099580 -> 6099443 (-0.00%) > instructions in affected programs: 47526 -> 47389 (-0.29%) > helped:137 Ping. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] scons: add target osmesa using gallium state tracker.
From: Olivier Pena
---
src/gallium/SConscript| 5
src/gallium/state_trackers/osmesa/Makefile.am | 2 ++
src/gallium/state_trackers/osmesa/SConscript | 26
src/gallium/targets/osmesa/Makefile.am| 6 +++-
src/gallium/targets/osmesa/SConscript | 43 +++
src/gallium/targets/osmesa/osmesa.def | 16 ++
src/gallium/targets/osmesa/osmesa.mingw.def | 13
7 files changed, 110 insertions(+), 1 deletion(-)
create mode 100644 src/gallium/state_trackers/osmesa/SConscript
create mode 100644 src/gallium/targets/osmesa/SConscript
create mode 100644 src/gallium/targets/osmesa/osmesa.def
create mode 100644 src/gallium/targets/osmesa/osmesa.mingw.def
diff --git a/src/gallium/SConscript b/src/gallium/SConscript
index 680ad92..eeb1c78 100644
--- a/src/gallium/SConscript
+++ b/src/gallium/SConscript
@@ -60,6 +60,11 @@ SConscript([
])
if not env['embedded']:
+SConscript([
+'state_trackers/osmesa/SConscript',
+'targets/osmesa/SConscript',
+])
+
if env['x11']:
SConscript([
'state_trackers/glx/xlib/SConscript',
diff --git a/src/gallium/state_trackers/osmesa/Makefile.am
b/src/gallium/state_trackers/osmesa/Makefile.am
index 4ba6c20..22e65c8 100644
--- a/src/gallium/state_trackers/osmesa/Makefile.am
+++ b/src/gallium/state_trackers/osmesa/Makefile.am
@@ -39,3 +39,5 @@ AM_CPPFLAGS = \
noinst_LTLIBRARIES = libosmesa.la
libosmesa_la_SOURCES = $(C_SOURCES)
+
+EXTRA_DIST = SConscript
diff --git a/src/gallium/state_trackers/osmesa/SConscript
b/src/gallium/state_trackers/osmesa/SConscript
new file mode 100644
index 000..f5519f1
--- /dev/null
+++ b/src/gallium/state_trackers/osmesa/SConscript
@@ -0,0 +1,26 @@
+import os
+
+Import('*')
+
+env = env.Clone()
+
+env.Append(CPPPATH = [
+'#src/mapi',
+'#src/mesa',
+'.',
+])
+
+if env['platform'] == 'windows':
+env.AppendUnique(CPPDEFINES = [
+'BUILD_GL32', # declare gl* as __declspec(dllexport) in Mesa headers
+'WIN32_LEAN_AND_MEAN', #
http://msdn2.microsoft.com/en-us/library/6dwk3a1z.aspx
+])
+if not env['gles']:
+# prevent _glapi_* from being declared __declspec(dllimport)
+env.Append(CPPDEFINES = ['_GLAPI_NO_EXPORTS'])
+
+st_osmesa = env.ConvenienceLibrary(
+target ='st_osmesa',
+source = env.ParseSourceList('Makefile.sources', 'C_SOURCES'),
+)
+Export('st_osmesa')
diff --git a/src/gallium/targets/osmesa/Makefile.am
b/src/gallium/targets/osmesa/Makefile.am
index f53823a..2c09736 100644
--- a/src/gallium/targets/osmesa/Makefile.am
+++ b/src/gallium/targets/osmesa/Makefile.am
@@ -76,7 +76,11 @@ lib@OSMESA_LIB@_la_LIBADD +=
$(top_builddir)/src/gallium/drivers/llvmpipe/libllv
endif
EXTRA_lib@OSMESA_LIB@_la_DEPENDENCIES = osmesa.sym
-EXTRA_DIST = osmesa.sym
+EXTRA_DIST = \
+ osmesa.sym \
+ osmesa.def \
+ osmesa.mingw.def \
+ SConscript
include $(top_srcdir)/install-gallium-links.mk
diff --git a/src/gallium/targets/osmesa/SConscript
b/src/gallium/targets/osmesa/SConscript
new file mode 100644
index 000..4a9115b
--- /dev/null
+++ b/src/gallium/targets/osmesa/SConscript
@@ -0,0 +1,43 @@
+Import('*')
+
+env = env.Clone()
+
+env.Prepend(CPPPATH = [
+'#src/mapi',
+'#src/mesa',
+#Dir('../../../mapi'), # src/mapi build path for python-generated GL API
files/headers
+])
+
+env.Prepend(LIBS = [
+st_osmesa,
+ws_null,
+glapi,
+mesa,
+gallium,
+trace,
+glsl,
+mesautil,
+softpipe
+])
+
+env.Append(CPPDEFINES = ['GALLIUM_TRACE', 'GALLIUM_SOFTPIPE'])
+
+sources = ['target.c']
+
+if env['llvm']:
+env.Append(CPPDEFINES = 'GALLIUM_LLVMPIPE')
+env.Prepend(LIBS = [llvmpipe])
+
+if env['platform'] == 'windows':
+if env['gcc'] and env['machine'] != 'x86_64':
+sources += ['osmesa.mingw.def']
+else:
+sources += ['osmesa.def']
+
+gallium_osmesa = env.SharedLibrary(
+target ='osmesa',
+source = sources,
+LIBS = env['LIBS'],
+)
+
+env.Alias('osmesa', gallium_osmesa)
diff --git a/src/gallium/targets/osmesa/osmesa.def
b/src/gallium/targets/osmesa/osmesa.def
new file mode 100644
index 000..e2a31ab
--- /dev/null
+++ b/src/gallium/targets/osmesa/osmesa.def
@@ -0,0 +1,16 @@
+;DESCRIPTION 'Mesa OSMesa lib for Win32'
+VERSION 4.1
+
+EXPORTS
+ OSMesaCreateContext
+ OSMesaCreateContextExt
+ OSMesaDestroyContext
+ OSMesaMakeCurrent
+ OSMesaGetCurrentContext
+ OSMesaPixelStore
+ OSMesaGetIntegerv
+ OSMesaGetDepthBuffer
+ OSMesaGetColorBuffer
+ OSMesaGetProcAddress
+ OSMesaColorClamp
+ OSMesaPostprocess
diff --git a/src/gallium/targets/osmesa/osmesa.mingw.def
b/src/gallium/targets/osmesa/osmesa.mingw.def
new file mode 100644
index 000..874ac54
--- /dev/null
+++ b/src/gallium/targets/osmesa/osmesa.mingw.def
@@ -0,0 +1,13 @@
+EXPORTS
+ OSMesaCreateContext = OSMesaCreateContext
Re: [Mesa-dev] [PATCH 22.5/23] mesa: remove the gl_sl_pragmas structure
Reviewed-by: Brian Paul
On 04/22/2015 10:41 AM, Jason Ekstrand wrote:
This code was added by Brian Paul in 2009 but, as far as Matt and I can
tell, it's been dead ever since the new GLSL compiler was added.
---
src/glsl/standalone_scaffolding.cpp | 3 ---
src/mesa/main/mtypes.h | 13 -
src/mesa/main/shaderapi.c | 6 --
3 files changed, 22 deletions(-)
diff --git a/src/glsl/standalone_scaffolding.cpp
b/src/glsl/standalone_scaffolding.cpp
index 6f5a27f..a109c4e 100644
--- a/src/glsl/standalone_scaffolding.cpp
+++ b/src/glsl/standalone_scaffolding.cpp
@@ -189,9 +189,6 @@ void initialize_context_to_defaults(struct gl_context *ctx,
gl_api api)
options.MaxUnrollIterations = 32;
options.MaxIfDepth = UINT_MAX;
- /* Default pragma settings */
- options.DefaultPragmas.Optimize = true;
-
for (int sh = 0; sh < MESA_SHADER_STAGES; ++sh)
memcpy(&ctx->Const.ShaderCompilerOptions[sh], &options,
sizeof(options));
}
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 1c751cf..fb41430 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -2365,16 +2365,6 @@ struct gl_ati_fragment_shader_state
};
-/** Set by #pragma directives */
-struct gl_sl_pragmas
-{
- GLboolean IgnoreOptimize; /**< ignore #pragma optimize(on/off) ? */
- GLboolean IgnoreDebug; /**< ignore #pragma debug(on/off) ? */
- GLboolean Optimize; /**< defaults on */
- GLboolean Debug; /**< defaults off */
-};
-
-
/**
* A GLSL vertex or fragment shader object.
*/
@@ -2397,7 +2387,6 @@ struct gl_shader
struct gl_program *Program; /**< Post-compile assembly code */
GLchar *InfoLog;
- struct gl_sl_pragmas Pragmas;
unsigned Version; /**< GLSL version used for linking */
@@ -2903,8 +2892,6 @@ struct gl_shader_compiler_options
*/
GLboolean OptimizeForAOS;
- struct gl_sl_pragmas DefaultPragmas; /**< Default #pragma settings */
-
const struct nir_shader_compiler_options *NirOptions;
};
diff --git a/src/mesa/main/shaderapi.c b/src/mesa/main/shaderapi.c
index 77e2b87..cc001ba 100644
--- a/src/mesa/main/shaderapi.c
+++ b/src/mesa/main/shaderapi.c
@@ -115,9 +115,6 @@ _mesa_init_shader_state(struct gl_context *ctx)
options.MaxUnrollIterations = 32;
options.MaxIfDepth = UINT_MAX;
- /* Default pragma settings */
- options.DefaultPragmas.Optimize = GL_TRUE;
-
for (sh = 0; sh < MESA_SHADER_STAGES; ++sh)
memcpy(&ctx->Const.ShaderCompilerOptions[sh], &options,
sizeof(options));
@@ -872,9 +869,6 @@ compile_shader(struct gl_context *ctx, GLuint shaderObj)
options = &ctx->Const.ShaderCompilerOptions[sh->Stage];
- /* set default pragma state for shader */
- sh->Pragmas = options->DefaultPragmas;
-
if (!sh->Source) {
/* If the user called glCompileShader without first calling
* glShaderSource, we should fail to compile, but not raise a GL_ERROR.
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[Mesa-dev] [Bug 90130] gl_PrimitiveId seems to reset at 340
https://bugs.freedesktop.org/show_bug.cgi?id=90130 --- Comment #16 from Ken Martin --- Created attachment 115276 --> https://bugs.freedesktop.org/attachment.cgi?id=115276&action=edit New piglit test Here is a piglit test to go in piglit/tests/spec/glsl-150/execution/primitive-id-no-gs-high-count.shader_test I believe it exposes the issue. -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 90130] gl_PrimitiveId seems to reset at 340
https://bugs.freedesktop.org/show_bug.cgi?id=90130 --- Comment #17 from Roland Scheidegger --- (In reply to Ken Martin from comment #16) > Created attachment 115276 [details] > New piglit test > > Here is a piglit test to go in > > piglit/tests/spec/glsl-150/execution/primitive-id-no-gs-high-count. > shader_test > > I believe it exposes the issue. Hmm doesn't look very practical indeed. I guess those shader tests aren't really prepared for testing something like this... -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] mesa: Fix typo in a comment
Signed-off-by: Anuj Phogat --- src/mesa/main/texgetimage.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mesa/main/texgetimage.c b/src/mesa/main/texgetimage.c index 255d365..908bb9b 100644 --- a/src/mesa/main/texgetimage.c +++ b/src/mesa/main/texgetimage.c @@ -285,7 +285,7 @@ get_tex_rgba_compressed(struct gl_context *ctx, GLuint dimensions, } /* Depending on the base format involved we may need to apply a rebase -* tranaform (for example: if we download to a Luminance format we want +* transform (for example: if we download to a Luminance format we want * G=0 and B=0). */ if (baseFormat == GL_LUMINANCE || @@ -388,7 +388,7 @@ get_tex_rgba_uncompressed(struct gl_context *ctx, GLuint dimensions, } /* Depending on the base format involved we may need to apply a rebase -* tranaform (for example: if we download to a Luminance format we want +* transform (for example: if we download to a Luminance format we want * G=0 and B=0). */ if (texImage->_BaseFormat == GL_LUMINANCE || -- 1.9.3 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] mesa: Fix typo in a comment
On 04/22/2015 01:15 PM, Anuj Phogat wrote: Signed-off-by: Anuj Phogat --- src/mesa/main/texgetimage.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mesa/main/texgetimage.c b/src/mesa/main/texgetimage.c index 255d365..908bb9b 100644 --- a/src/mesa/main/texgetimage.c +++ b/src/mesa/main/texgetimage.c @@ -285,7 +285,7 @@ get_tex_rgba_compressed(struct gl_context *ctx, GLuint dimensions, } /* Depending on the base format involved we may need to apply a rebase -* tranaform (for example: if we download to a Luminance format we want +* transform (for example: if we download to a Luminance format we want * G=0 and B=0). */ if (baseFormat == GL_LUMINANCE || @@ -388,7 +388,7 @@ get_tex_rgba_uncompressed(struct gl_context *ctx, GLuint dimensions, } /* Depending on the base format involved we may need to apply a rebase -* tranaform (for example: if we download to a Luminance format we want +* transform (for example: if we download to a Luminance format we want * G=0 and B=0). */ if (texImage->_BaseFormat == GL_LUMINANCE || Reviewed-by: Brian Paul Though, I don't think comment typo fixes require reviews. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 01/18] i965: Refactor rb surface setup to allow caller to store offsets
Notice that in gen7_wm_surface_state.c there is also indentation
change in the surrounding code removing tabs.
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_context.h | 8 +++
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 28 ---
src/mesa/drivers/dri/i965/gen6_surface_state.c| 17 +++---
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 20
src/mesa/drivers/dri/i965/gen8_surface_state.c| 18 +++
5 files changed, 46 insertions(+), 45 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index a6d6787..9f4eddd 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -966,10 +966,10 @@ struct brw_context
unsigned unit,
uint32_t *surf_offset,
bool for_gather);
- void (*update_renderbuffer_surface)(struct brw_context *brw,
- struct gl_renderbuffer *rb,
- bool layered,
- unsigned unit);
+ uint32_t (*update_renderbuffer_surface)(struct brw_context *brw,
+ struct gl_renderbuffer *rb,
+ bool layered, unsigned unit,
+ uint32_t surf_index);
void (*emit_buffer_surface_state)(struct brw_context *brw,
uint32_t *out_offset,
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 161d140..959d6c2 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -626,11 +626,11 @@ brw_emit_null_surface_state(struct brw_context *brw,
* While it is only used for the front/back buffer currently, it should be
* usable for further buffers when doing ARB_draw_buffer support.
*/
-static void
+static uint32_t
brw_update_renderbuffer_surface(struct brw_context *brw,
struct gl_renderbuffer *rb,
- bool layered,
- unsigned int unit)
+ bool layered, unsigned unit,
+uint32_t surf_index)
{
struct gl_context *ctx = &brw->ctx;
struct intel_renderbuffer *irb = intel_renderbuffer(rb);
@@ -638,11 +638,10 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
uint32_t *surf;
uint32_t tile_x, tile_y;
uint32_t format = 0;
+ uint32_t offset;
/* _NEW_BUFFERS */
mesa_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb));
/* BRW_NEW_FS_PROG_DATA */
- uint32_t surf_index =
- brw->wm.prog_data->binding_table.render_target_start + unit;
assert(!layered);
@@ -663,8 +662,7 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
intel_miptree_used_for_rendering(irb->mt);
- surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32,
- &brw->wm.base.surf_offset[surf_index]);
+ surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32, &offset);
format = brw->render_target_format[rb_format];
if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
@@ -721,11 +719,13 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
}
drm_intel_bo_emit_reloc(brw->batch.bo,
- brw->wm.base.surf_offset[surf_index] + 4,
+ offset + 4,
mt->bo,
surf[1] - mt->bo->offset64,
I915_GEM_DOMAIN_RENDER,
I915_GEM_DOMAIN_RENDER);
+
+ return offset;
}
/**
@@ -743,13 +743,15 @@ brw_update_renderbuffer_surfaces(struct brw_context *brw)
/* Update surfaces for drawing buffers */
if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) {
for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
+ const uint32_t surf_index =
+brw->wm.prog_data->binding_table.render_target_start + i;
+
if (intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[i])) {
- brw->vtbl.update_renderbuffer_surface(brw,
ctx->DrawBuffer->_ColorDrawBuffers[i],
-
ctx->DrawBuffer->MaxNumLayers > 0, i);
+brw->wm.base.surf_offset[surf_index] =
+ brw->vtbl.update_renderbuffer_surface(
+ brw, ctx->DrawBuffer->_ColorDrawBuffers[i],
+ ctx->DrawBuffer->MaxNumLayers > 0, i, surf_index);
} else {
-const uint32_t surf_index =
- brw->wm.prog_data->binding_table.render_target_start + i;
-
brw->vtbl.emit_null_surface
[Mesa-dev] [PATCH 03/18] i965: Refactor and expose brw_upload_binding_table()
Read and write parts of the state stage are also split into
explicit arguments allowing future patches to use constant
program data.
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_binding_tables.c | 21 ++---
src/mesa/drivers/dri/i965/brw_state.h | 7 +++
2 files changed, 21 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_binding_tables.c
b/src/mesa/drivers/dri/i965/brw_binding_tables.c
index 459165a..1142c67 100644
--- a/src/mesa/drivers/dri/i965/brw_binding_tables.c
+++ b/src/mesa/drivers/dri/i965/brw_binding_tables.c
@@ -50,15 +50,13 @@
* This copies brw_stage_state::surf_offset[] into the indirect state section
* of the batchbuffer (allocated by brw_state_batch()).
*/
-static void
+void
brw_upload_binding_table(struct brw_context *brw,
uint32_t packet_name,
GLbitfield brw_new_binding_table,
+ const struct brw_stage_prog_data *prog_data,
struct brw_stage_state *stage_state)
{
- /* BRW_NEW_*_PROG_DATA */
- struct brw_stage_prog_data *prog_data = stage_state->prog_data;
-
if (prog_data->binding_table.size_bytes == 0) {
/* There are no surfaces; skip making the binding table altogether. */
if (stage_state->bind_bo_offset == 0 && brw->gen < 9)
@@ -103,9 +101,12 @@ brw_upload_binding_table(struct brw_context *brw,
static void
brw_vs_upload_binding_table(struct brw_context *brw)
{
+ /* BRW_NEW_VS_PROG_DATA */
+ const struct brw_stage_prog_data *prog_data = brw->vs.base.prog_data;
brw_upload_binding_table(brw,
_3DSTATE_BINDING_TABLE_POINTERS_VS,
-BRW_NEW_VS_BINDING_TABLE, &brw->vs.base);
+BRW_NEW_VS_BINDING_TABLE, prog_data,
+&brw->vs.base);
}
const struct brw_tracked_state brw_vs_binding_table = {
@@ -124,9 +125,12 @@ const struct brw_tracked_state brw_vs_binding_table = {
static void
brw_upload_wm_binding_table(struct brw_context *brw)
{
+ /* BRW_NEW_WM_PROG_DATA */
+ const struct brw_stage_prog_data *prog_data = brw->wm.base.prog_data;
brw_upload_binding_table(brw,
_3DSTATE_BINDING_TABLE_POINTERS_PS,
-BRW_NEW_PS_BINDING_TABLE, &brw->wm.base);
+BRW_NEW_PS_BINDING_TABLE, prog_data,
+&brw->wm.base);
}
const struct brw_tracked_state brw_wm_binding_table = {
@@ -147,9 +151,12 @@ brw_gs_upload_binding_table(struct brw_context *brw)
if (brw->geometry_program == NULL)
return;
+ /* BRW_NEW_GS_PROG_DATA */
+ const struct brw_stage_prog_data *prog_data = brw->gs.base.prog_data;
brw_upload_binding_table(brw,
_3DSTATE_BINDING_TABLE_POINTERS_GS,
-BRW_NEW_GS_BINDING_TABLE, &brw->gs.base);
+BRW_NEW_GS_BINDING_TABLE, prog_data,
+&brw->gs.base);
}
const struct brw_tracked_state brw_gs_binding_table = {
diff --git a/src/mesa/drivers/dri/i965/brw_state.h
b/src/mesa/drivers/dri/i965/brw_state.h
index 83058b9..8798369 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -159,6 +159,13 @@ brw_state_dirty(struct brw_context *brw, GLuint
mesa_flags, uint64_t brw_flags)
(brw->ctx.NewDriverState & brw_flags)) != 0;
}
+/* brw_binding_tables.c */
+void brw_upload_binding_table(struct brw_context *brw,
+ uint32_t packet_name,
+ GLbitfield brw_new_binding_table,
+ const struct brw_stage_prog_data *prog_data,
+ struct brw_stage_state *stage_state);
+
/* brw_misc_state.c */
void brw_upload_invariant_state(struct brw_context *brw);
uint32_t
--
1.9.3
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[Mesa-dev] [PATCH 10/18] i965: Pass integer format flag as parameter to surface setup
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_context.h | 4 +++-
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 7 +--
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 6 +++---
src/mesa/drivers/dri/i965/gen8_surface_state.c| 5 +++--
4 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index 6bb46e3..1461310 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -965,7 +965,9 @@ struct brw_context
void (*update_texture_surface)(struct brw_context *brw,
const struct intel_mipmap_tree *mt,
struct gl_texture_object *tObj,
- uint32_t tex_format, int swizzle,
+ uint32_t tex_format,
+ bool is_integer_format,
+ int swizzle,
uint32_t *surf_offset,
bool for_gather);
uint32_t (*update_renderbuffer_surface)(struct brw_context *brw,
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 0d81576..c76d09d 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -311,7 +311,9 @@ static void
brw_update_texture_surface(struct brw_context *brw,
const struct intel_mipmap_tree *mt,
struct gl_texture_object *tObj,
- uint32_t tex_format, int swizzle /* unused */,
+ uint32_t tex_format,
+ bool is_integer_format /* unused */,
+ int swizzle /* unused */,
uint32_t *surf_offset,
bool for_gather)
{
@@ -824,7 +826,8 @@ update_texture_surface(struct gl_context *ctx,
const int swizzle = unlikely(alpha_depth)
? SWIZZLE_XYZW : brw_get_texture_swizzle(ctx, tObj);
- brw->vtbl.update_texture_surface(brw, mt, tObj, tex_format, swizzle,
+ brw->vtbl.update_texture_surface(brw, mt, tObj, tex_format,
+tObj->_IsIntegerFormat, swizzle,
surf_offset, for_gather);
}
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index bb2b889..46c96f7 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -267,8 +267,8 @@ static void
gen7_update_texture_surface(struct brw_context *brw,
const struct intel_mipmap_tree *mt,
struct gl_texture_object *tObj,
-uint32_t tex_format, int swizzle,
-uint32_t *surf_offset,
+uint32_t tex_format, bool is_integer_format,
+int swizzle, uint32_t *surf_offset,
bool for_gather)
{
struct intel_texture_object *intelObj = intel_texture_object(tObj);
@@ -314,7 +314,7 @@ gen7_update_texture_surface(struct brw_context *brw,
surf[3] = SET_FIELD(effective_depth - 1, BRW_SURFACE_DEPTH) |
(mt->pitch - 1);
- if (brw->is_haswell && tObj->_IsIntegerFormat)
+ if (brw->is_haswell && is_integer_format)
surf[3] |= HSW_SURFACE_IS_INTEGER_FORMAT;
surf[4] = gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout) |
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c
b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index af891ff..d7287b8 100644
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -153,8 +153,9 @@ static void
gen8_update_texture_surface(struct brw_context *brw,
const struct intel_mipmap_tree *mt,
struct gl_texture_object *tObj,
-uint32_t tex_format, int swizzle,
-uint32_t *surf_offset,
+uint32_t tex_format,
+bool is_integer_format /* unused */,
+int swizzle, uint32_t *surf_offset,
bool for_gather)
{
struct intel_texture_object *intelObj = intel_texture_object(tObj);
--
1.9.3
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[Mesa-dev] [PATCH 04/18] i965: Remove dependency to tex object in default color setup
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_sampler_state.c | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_sampler_state.c
b/src/mesa/drivers/dri/i965/brw_sampler_state.c
index c4bd949..c78e2e3 100644
--- a/src/mesa/drivers/dri/i965/brw_sampler_state.c
+++ b/src/mesa/drivers/dri/i965/brw_sampler_state.c
@@ -201,16 +201,13 @@ wrap_mode_needs_border_color(unsigned wrap_mode)
static void
upload_default_color(struct brw_context *brw,
const struct gl_sampler_object *sampler,
- int unit,
+ mesa_format format, GLenum base_format,
+ bool is_integer_format,
uint32_t *sdc_offset)
{
- struct gl_context *ctx = &brw->ctx;
- struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit];
- struct gl_texture_object *texObj = texUnit->_Current;
- struct gl_texture_image *firstImage = texObj->Image[0][texObj->BaseLevel];
union gl_color_union color;
- switch (firstImage->_BaseFormat) {
+ switch (base_format) {
case GL_DEPTH_COMPONENT:
/* GL specs that border color for depth textures is taken from the
* R channel, while the hardware uses A. Spam R into all the
@@ -257,7 +254,7 @@ upload_default_color(struct brw_context *brw,
* where we've initialized the A channel to 1.0. We also have to set
* the border color alpha to 1.0 in that case.
*/
- if (firstImage->_BaseFormat == GL_RGB)
+ if (base_format == GL_RGB)
color.ui[3] = float_as_int(1.0);
if (brw->gen >= 8) {
@@ -269,7 +266,7 @@ upload_default_color(struct brw_context *brw,
uint32_t *sdc = brw_state_batch(brw, AUB_TRACE_SAMPLER_DEFAULT_COLOR,
4 * 4, 64, sdc_offset);
memcpy(sdc, color.ui, 4 * 4);
- } else if (brw->is_haswell && texObj->_IsIntegerFormat) {
+ } else if (brw->is_haswell && is_integer_format) {
/* Haswell's integer border color support is completely insane:
* SAMPLER_BORDER_COLOR_STATE is 20 DWords. The first four are
* for float colors. The next 12 DWords are MBZ and only exist to
@@ -283,7 +280,6 @@ upload_default_color(struct brw_context *brw,
memset(sdc, 0, 20 * 4);
sdc = &sdc[16];
- mesa_format format = firstImage->TexFormat;
int bits_per_channel = _mesa_get_format_bits(format, GL_RED_BITS);
/* From the Haswell PRM, "Command Reference: Structures", Page 36:
@@ -314,7 +310,7 @@ upload_default_color(struct brw_context *brw,
((uint16_t *) sdc)[5] = c[3]; /* A -> DWord 3, bits 31:16 */
break;
case 32:
- if (firstImage->_BaseFormat == GL_RG) {
+ if (base_format == GL_RG) {
/* Careful inspection of the tables reveals that for RG32 formats,
* the green channel needs to go where blue normally belongs.
*/
@@ -510,7 +506,11 @@ brw_update_sampler_state(struct brw_context *brw,
if (wrap_mode_needs_border_color(wrap_s) ||
wrap_mode_needs_border_color(wrap_t) ||
wrap_mode_needs_border_color(wrap_r)) {
- upload_default_color(brw, sampler, unit, &border_color_offset);
+ const struct gl_texture_image *first_image =
+ texObj->Image[0][texObj->BaseLevel];
+ upload_default_color(brw, sampler,
+ first_image->TexFormat, first_image->_BaseFormat,
+ texObj->_IsIntegerFormat, &border_color_offset);
}
const bool non_normalized_coords = texObj->Target == GL_TEXTURE_RECTANGLE;
--
1.9.3
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[Mesa-dev] [PATCH 08/18] i965: Move tex miptree and format resolving into dispatcher
All hardware platforms have this in common, so do it in the
hardware independent dispatcher.
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_context.h | 4 ++-
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 30 ---
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 11 +++--
src/mesa/drivers/dri/i965/gen8_surface_state.c| 16 +++-
4 files changed, 30 insertions(+), 31 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index 76d4630..096bc4d 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -963,7 +963,9 @@ struct brw_context
struct
{
void (*update_texture_surface)(struct gl_context *ctx,
- unsigned unit,
+ const struct intel_mipmap_tree *mt,
+ struct gl_texture_object *tObj,
+ uint32_t tex_format,
uint32_t *surf_offset,
bool for_gather);
uint32_t (*update_renderbuffer_surface)(struct brw_context *brw,
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 0f739bb..d8faf82 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -309,23 +309,19 @@ update_buffer_texture_surface(struct gl_context *ctx,
static void
brw_update_texture_surface(struct gl_context *ctx,
- unsigned unit,
+ const struct intel_mipmap_tree *mt,
+ struct gl_texture_object *tObj,
+ uint32_t tex_format,
uint32_t *surf_offset,
bool for_gather)
{
struct brw_context *brw = brw_context(ctx);
- struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
struct intel_texture_object *intelObj = intel_texture_object(tObj);
- struct intel_mipmap_tree *mt = intelObj->mt;
- struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
uint32_t *surf;
surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
6 * 4, 32, surf_offset);
- uint32_t tex_format = translate_tex_format(brw, mt->format,
- sampler->sRGBDecode);
-
if (for_gather) {
/* Sandybridge's gather4 message is broken for integer formats.
* To work around this, we pretend the surface is UNORM for
@@ -796,14 +792,30 @@ update_texture_surface(struct gl_context *ctx,
bool for_gather)
{
struct brw_context *brw = brw_context(ctx);
- const struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
+ struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
+ struct intel_texture_object *intelObj = intel_texture_object(tObj);
+ const struct intel_mipmap_tree *mt = intelObj->mt;
+ const struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
+ const struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
if (tObj->Target == GL_TEXTURE_BUFFER) {
update_buffer_texture_surface(ctx, unit, surf_offset);
return;
}
- brw->vtbl.update_texture_surface(ctx, unit, surf_offset, for_gather);
+ mesa_format format = intelObj->_Format;
+ if (tObj->StencilSampling && firstImage->_BaseFormat == GL_DEPTH_STENCIL) {
+ assert(brw->gen >= 8);
+ mt = mt->stencil_mt;
+ assert(mt->format == MESA_FORMAT_S_UINT8);
+ format = mt->format;
+ }
+
+ const uint32_t tex_format = translate_tex_format(brw, format,
+sampler->sRGBDecode);
+
+ brw->vtbl.update_texture_surface(ctx, mt, tObj, tex_format, surf_offset,
+for_gather);
}
static void
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index 8a7ff25..9a1af98 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -265,25 +265,20 @@ gen7_emit_buffer_surface_state(struct brw_context *brw,
static void
gen7_update_texture_surface(struct gl_context *ctx,
-unsigned unit,
+const struct intel_mipmap_tree *mt,
+struct gl_texture_object *tObj,
+uint32_t tex_format,
uint32_t *surf_offset,
bool for_gather)
{
struct brw_context *brw = brw_context(ctx);
- struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
struct intel_texture_object *intelObj = intel_texture_object(tObj);
- struct intel_mipmap_tree *m
[Mesa-dev] [PATCH 07/18] i965/gen8: Use miptree format in the surface setup
No functional change but this allows to drop the texture object's
mesa format in later patches.
Stencil buffer has fixed hardware format corresponding to fixed
mesa format. (This is in fact already specfically tested in
intel_fbo.c::intel_validate_framebuffer()).
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/gen8_surface_state.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c
b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index 304e5fe..5a94117 100644
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -169,10 +169,11 @@ gen8_update_texture_surface(struct gl_context *ctx,
if (tObj->StencilSampling && firstImage->_BaseFormat == GL_DEPTH_STENCIL) {
mt = mt->stencil_mt;
format = MESA_FORMAT_S_UINT8;
+ assert(mt->format == MESA_FORMAT_S_UINT8);
}
unsigned tiling_mode, pitch;
- if (format == MESA_FORMAT_S_UINT8) {
+ if (mt->format == MESA_FORMAT_S_UINT8) {
tiling_mode = GEN8_SURFACE_TILING_W;
pitch = 2 * mt->pitch;
} else {
--
1.9.3
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[Mesa-dev] i965: Batch emission refactoring
Currently batch emission logic is bolted into using the current gl-state and currently bound user shader programs as input. This series refactors the api to allow caller to give individual bits of information needed explicitly instead of the emission logic deducing them from the current state. This is needed to support blorp style gl-state-agnostic launching of internal utility shaders - shaders used for 2D blitting and buffer clearing/resolving. I have a follow-up series ready that is actually leveraging this, this series is simple set of refactors. I didn't mean it to, but it actually fixes one pigit test on ILK due to the way formats are set for texture surfaces: arb_copy_image.arb_copy_image-formats. Patches 6-13 all address texture surface setup. They move all the decision making of values into the hardware agnostic dispatcher leaving the hw-specific part just to deal with formatting. Topi Pohjolainen (18): i965: Refactor rb surface setup to allow caller to store offsets i965: Expose and refactor brw_update_renderbuffer_surfaces() i965: Refactor and expose brw_upload_binding_table() i965: Remove dependency to tex object in default color setup i965: Refactor sampler state setup i965: Move texture buffer dispatch into single location i965/gen8: Use miptree format in the surface setup i965: Move tex miptree and format resolving into dispatcher i965: Move texture swizzle resolving into dispatcher i965: Pass integer format flag as parameter to surface setup i965: Refactor effective depth calculation i965: Pass texture target as parameter for surface setup i965: Pass slice details as parameters for surface setup i965/wm/gen6: Refactor program offset setup i965/wm/gen6: Refactor push constant state uploading i965/ps/gen7: Refactor state uploading i965/ps/gen8: Refactor state uploading i965/gen8: Expose state base address setup src/mesa/drivers/dri/i965/brw_binding_tables.c| 21 ++- src/mesa/drivers/dri/i965/brw_context.h | 22 +-- src/mesa/drivers/dri/i965/brw_sampler_state.c | 74 + src/mesa/drivers/dri/i965/brw_state.h | 58 +++ src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 183 ++ src/mesa/drivers/dri/i965/gen6_surface_state.c| 17 +- src/mesa/drivers/dri/i965/gen6_wm_state.c | 102 +++- src/mesa/drivers/dri/i965/gen7_wm_state.c | 58 --- src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 83 +++--- src/mesa/drivers/dri/i965/gen8_misc_state.c | 4 +- src/mesa/drivers/dri/i965/gen8_ps_state.c | 74 + src/mesa/drivers/dri/i965/gen8_surface_state.c| 84 +++--- 12 files changed, 454 insertions(+), 326 deletions(-) -- 1.9.3 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 06/18] i965: Move texture buffer dispatch into single location
All generations do the same exacr dispatch and it could be
therefore done in the hardware independent stage.
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_context.h | 3 ---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 32 +++
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 5
src/mesa/drivers/dri/i965/gen8_surface_state.c| 5
4 files changed, 21 insertions(+), 24 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index 9f4eddd..76d4630 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1662,9 +1662,6 @@ void brw_create_constant_surface(struct brw_context *brw,
uint32_t size,
uint32_t *out_offset,
bool dword_pitch);
-void brw_update_buffer_texture_surface(struct gl_context *ctx,
- unsigned unit,
- uint32_t *surf_offset);
void
brw_update_sol_surface(struct brw_context *brw,
struct gl_buffer_object *buffer_obj,
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 82dd92b..0f739bb 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -274,10 +274,10 @@ gen4_emit_buffer_surface_state(struct brw_context *brw,
}
}
-void
-brw_update_buffer_texture_surface(struct gl_context *ctx,
- unsigned unit,
- uint32_t *surf_offset)
+static void
+update_buffer_texture_surface(struct gl_context *ctx,
+ unsigned unit,
+ uint32_t *surf_offset)
{
struct brw_context *brw = brw_context(ctx);
struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
@@ -320,12 +320,6 @@ brw_update_texture_surface(struct gl_context *ctx,
struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
uint32_t *surf;
- /* BRW_NEW_TEXTURE_BUFFER */
- if (tObj->Target == GL_TEXTURE_BUFFER) {
- brw_update_buffer_texture_surface(ctx, unit, surf_offset);
- return;
- }
-
surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
6 * 4, 32, surf_offset);
@@ -795,6 +789,22 @@ const struct brw_tracked_state gen6_renderbuffer_surfaces
= {
.emit = update_renderbuffer_surfaces,
};
+static void
+update_texture_surface(struct gl_context *ctx,
+ unsigned unit,
+ uint32_t *surf_offset,
+ bool for_gather)
+{
+ struct brw_context *brw = brw_context(ctx);
+ const struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
+
+ if (tObj->Target == GL_TEXTURE_BUFFER) {
+ update_buffer_texture_surface(ctx, unit, surf_offset);
+ return;
+ }
+
+ brw->vtbl.update_texture_surface(ctx, unit, surf_offset, for_gather);
+}
static void
update_stage_texture_surfaces(struct brw_context *brw,
@@ -824,7 +834,7 @@ update_stage_texture_surfaces(struct brw_context *brw,
/* _NEW_TEXTURE */
if (ctx->Texture.Unit[unit]._Current) {
-brw->vtbl.update_texture_surface(ctx, unit, surf_offset + s,
for_gather);
+update_texture_surface(ctx, unit, surf_offset + s, for_gather);
}
}
}
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index 9605019..8a7ff25 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -276,11 +276,6 @@ gen7_update_texture_surface(struct gl_context *ctx,
struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
- if (tObj->Target == GL_TEXTURE_BUFFER) {
- brw_update_buffer_texture_surface(ctx, unit, surf_offset);
- return;
- }
-
uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
8 * 4, 32, surf_offset);
memset(surf, 0, 8 * 4);
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c
b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index 941dfc0..304e5fe 100644
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -166,11 +166,6 @@ gen8_update_texture_surface(struct gl_context *ctx,
mesa_format format = intelObj->_Format;
uint32_t mocs_wb = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
- if (tObj->Target == GL_TEXTURE_BUFFER) {
- brw_update_buffer_texture_surface(ctx, unit, surf_offset);
- return;
- }
-
if (tObj->StencilSampling && firstImage->_BaseFormat == GL_DEPTH_STENCIL) {
mt = mt->stencil_mt;
form
[Mesa-dev] [PATCH 18/18] i965/gen8: Expose state base address setup
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_state.h | 3 +++
src/mesa/drivers/dri/i965/gen8_misc_state.c | 4 ++--
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_state.h
b/src/mesa/drivers/dri/i965/brw_state.h
index 0c4f65e..73dcca1 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -171,6 +171,9 @@ void brw_upload_invariant_state(struct brw_context *brw);
uint32_t
brw_depthbuffer_format(struct brw_context *brw);
+/* gen8_misc_state.c */
+void gen8_upload_state_base_address(struct brw_context *brw);
+
/***
* brw_state.c
diff --git a/src/mesa/drivers/dri/i965/gen8_misc_state.c
b/src/mesa/drivers/dri/i965/gen8_misc_state.c
index 88e425f..b20038e 100644
--- a/src/mesa/drivers/dri/i965/gen8_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_misc_state.c
@@ -29,7 +29,7 @@
/**
* Define the base addresses which some state is referenced from.
*/
-static void upload_state_base_address(struct brw_context *brw)
+void gen8_upload_state_base_address(struct brw_context *brw)
{
uint32_t mocs_wb = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
int pkt_len = brw->gen >= 9 ? 19 : 16;
@@ -78,5 +78,5 @@ const struct brw_tracked_state gen8_state_base_address = {
.brw = BRW_NEW_BATCH |
BRW_NEW_PROGRAM_CACHE,
},
- .emit = upload_state_base_address
+ .emit = gen8_upload_state_base_address
};
--
1.9.3
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[Mesa-dev] [PATCH 05/18] i965: Refactor sampler state setup
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_sampler_state.c | 60 +--
src/mesa/drivers/dri/i965/brw_state.h | 9
2 files changed, 47 insertions(+), 22 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_sampler_state.c
b/src/mesa/drivers/dri/i965/brw_sampler_state.c
index c78e2e3..c1daa44 100644
--- a/src/mesa/drivers/dri/i965/brw_sampler_state.c
+++ b/src/mesa/drivers/dri/i965/brw_sampler_state.c
@@ -375,21 +375,16 @@ upload_default_color(struct brw_context *brw,
* Sets the sampler state for a single unit based off of the sampler key
* entry.
*/
-static void
+void
brw_update_sampler_state(struct brw_context *brw,
- int unit,
+ GLenum target, bool tex_cube_map_seamless,
+ GLfloat tex_unit_lod_bias,
+ mesa_format format, GLenum base_format,
+ bool is_integer_format,
+ const struct gl_sampler_object* sampler,
uint32_t *sampler_state,
uint32_t batch_offset_for_sampler_state)
{
- struct gl_context *ctx = &brw->ctx;
- const struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit];
- const struct gl_texture_object *texObj = texUnit->_Current;
- const struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
-
- /* These don't use samplers at all. */
- if (texObj->Target == GL_TEXTURE_BUFFER)
- return;
-
unsigned min_filter, mag_filter, mip_filter;
/* Select min and mip filters. */
@@ -459,12 +454,12 @@ brw_update_sampler_state(struct brw_context *brw,
unsigned wrap_t = translate_wrap_mode(brw, sampler->WrapT, either_nearest);
unsigned wrap_r = translate_wrap_mode(brw, sampler->WrapR, either_nearest);
- if (texObj->Target == GL_TEXTURE_CUBE_MAP ||
- texObj->Target == GL_TEXTURE_CUBE_MAP_ARRAY) {
+ if (target == GL_TEXTURE_CUBE_MAP ||
+ target == GL_TEXTURE_CUBE_MAP_ARRAY) {
/* Cube maps must use the same wrap mode for all three coordinate
* dimensions. Prior to Haswell, only CUBE and CLAMP are valid.
*/
- if ((ctx->Texture.CubeMapSeamless || sampler->CubeMapSeamless) &&
+ if ((tex_cube_map_seamless || sampler->CubeMapSeamless) &&
(sampler->MinFilter != GL_NEAREST ||
sampler->MagFilter != GL_NEAREST)) {
wrap_s = BRW_TEXCOORDMODE_CUBE;
@@ -475,7 +470,7 @@ brw_update_sampler_state(struct brw_context *brw,
wrap_t = BRW_TEXCOORDMODE_CLAMP;
wrap_r = BRW_TEXCOORDMODE_CLAMP;
}
- } else if (texObj->Target == GL_TEXTURE_1D) {
+ } else if (target == GL_TEXTURE_1D) {
/* There's a bug in 1D texture sampling - it actually pays
* attention to the wrap_t value, though it should not.
* Override the wrap_t value here to GL_REPEAT to keep
@@ -495,7 +490,7 @@ brw_update_sampler_state(struct brw_context *brw,
const unsigned min_lod = U_FIXED(CLAMP(sampler->MinLod, 0, 13), lod_bits);
const unsigned max_lod = U_FIXED(CLAMP(sampler->MaxLod, 0, 13), lod_bits);
const int lod_bias =
- S_FIXED(CLAMP(texUnit->LodBias + sampler->LodBias, -16, 15), lod_bits);
+ S_FIXED(CLAMP(tex_unit_lod_bias + sampler->LodBias, -16, 15), lod_bits);
const unsigned base_level = U_FIXED(0, 1);
/* Upload the border color if necessary. If not, just point it at
@@ -506,14 +501,12 @@ brw_update_sampler_state(struct brw_context *brw,
if (wrap_mode_needs_border_color(wrap_s) ||
wrap_mode_needs_border_color(wrap_t) ||
wrap_mode_needs_border_color(wrap_r)) {
- const struct gl_texture_image *first_image =
- texObj->Image[0][texObj->BaseLevel];
upload_default_color(brw, sampler,
- first_image->TexFormat, first_image->_BaseFormat,
- texObj->_IsIntegerFormat, &border_color_offset);
+ format, base_format, is_integer_format,
+ &border_color_offset);
}
- const bool non_normalized_coords = texObj->Target == GL_TEXTURE_RECTANGLE;
+ const bool non_normalized_coords = target == GL_TEXTURE_RECTANGLE;
brw_emit_sampler_state(brw,
sampler_state,
@@ -528,6 +521,29 @@ brw_update_sampler_state(struct brw_context *brw,
border_color_offset);
}
+static void
+update_sampler_state(struct brw_context *brw,
+ int unit,
+ uint32_t *sampler_state,
+ uint32_t batch_offset_for_sampler_state)
+{
+ struct gl_context *ctx = &brw->ctx;
+ const struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit];
+ const struct gl_texture_object *texObj = texUnit->_Current;
+ const struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
+
+ /* These don't use samplers at all. */
+ if (texObj->Target == GL_TEXTURE_BUFFER)
+ return;
+
+
[Mesa-dev] [PATCH 17/18] i965/ps/gen8: Refactor state uploading
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_state.h | 12 +
src/mesa/drivers/dri/i965/gen8_ps_state.c | 74 ---
2 files changed, 59 insertions(+), 27 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_state.h
b/src/mesa/drivers/dri/i965/brw_state.h
index 178f039..0c4f65e 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -265,6 +265,18 @@ void gen7_set_surface_mcs_info(struct brw_context *brw,
void gen7_check_surface_setup(uint32_t *surf, bool is_render_target);
void gen7_init_vtable_surface_functions(struct brw_context *brw);
+/* gen8_ps_state.c */
+void gen8_upload_ps_state(struct brw_context *brw,
+ const struct gl_fragment_program *fp,
+ const struct brw_stage_state *stage_state,
+ const struct brw_wm_prog_data *prog_data,
+ uint32_t fast_clear_op);
+
+void gen8_upload_ps_extra(struct brw_context *brw,
+ const struct gl_fragment_program *fp,
+ const struct brw_wm_prog_data *prog_data,
+ bool multisampled_fbo);
+
/* gen7_sol_state.c */
void gen7_upload_3dstate_so_decl_list(struct brw_context *brw,
const struct brw_vue_map *vue_map);
diff --git a/src/mesa/drivers/dri/i965/gen8_ps_state.c
b/src/mesa/drivers/dri/i965/gen8_ps_state.c
index 5f39e12..da6136b 100644
--- a/src/mesa/drivers/dri/i965/gen8_ps_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_ps_state.c
@@ -27,15 +27,13 @@
#include "brw_defines.h"
#include "intel_batchbuffer.h"
-static void
-upload_ps_extra(struct brw_context *brw)
+void
+gen8_upload_ps_extra(struct brw_context *brw,
+ const struct gl_fragment_program *fp,
+ const struct brw_wm_prog_data *prog_data,
+ bool multisampled_fbo)
{
struct gl_context *ctx = &brw->ctx;
- /* BRW_NEW_FRAGMENT_PROGRAM */
- const struct brw_fragment_program *fp =
- brw_fragment_program_const(brw->fragment_program);
- /* BRW_NEW_FS_PROG_DATA */
- const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
uint32_t dw1 = 0;
dw1 |= GEN8_PSX_PIXEL_SHADER_VALID;
@@ -47,16 +45,14 @@ upload_ps_extra(struct brw_context *brw)
if (prog_data->num_varying_inputs != 0)
dw1 |= GEN8_PSX_ATTRIBUTE_ENABLE;
- if (fp->program.Base.InputsRead & VARYING_BIT_POS)
+ if (fp->Base.InputsRead & VARYING_BIT_POS)
dw1 |= GEN8_PSX_USES_SOURCE_DEPTH | GEN8_PSX_USES_SOURCE_W;
- /* BRW_NEW_NUM_SAMPLES | _NEW_MULTISAMPLE */
- bool multisampled_fbo = brw->num_samples > 1;
if (multisampled_fbo &&
- _mesa_get_min_invocations_per_fragment(ctx, &fp->program, false) > 1)
+ _mesa_get_min_invocations_per_fragment(ctx, fp, false) > 1)
dw1 |= GEN8_PSX_SHADER_IS_PER_SAMPLE;
- if (fp->program.Base.SystemValuesRead & SYSTEM_BIT_SAMPLE_MASK_IN)
+ if (fp->Base.SystemValuesRead & SYSTEM_BIT_SAMPLE_MASK_IN)
dw1 |= GEN8_PSX_SHADER_USES_INPUT_COVERAGE_MASK;
if (prog_data->uses_omask)
@@ -68,6 +64,20 @@ upload_ps_extra(struct brw_context *brw)
ADVANCE_BATCH();
}
+static void
+upload_ps_extra(struct brw_context *brw)
+{
+ /* BRW_NEW_FRAGMENT_PROGRAM */
+ const struct brw_fragment_program *fp =
+ brw_fragment_program_const(brw->fragment_program);
+ /* BRW_NEW_FS_PROG_DATA */
+ const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
+ /* BRW_NEW_NUM_SAMPLES | _NEW_MULTISAMPLE */
+ const bool multisampled_fbo = brw->num_samples > 1;
+
+ gen8_upload_ps_extra(brw, &fp->program, prog_data, multisampled_fbo);
+}
+
const struct brw_tracked_state gen8_ps_extra = {
.dirty = {
.mesa = _NEW_MULTISAMPLE,
@@ -118,23 +128,24 @@ const struct brw_tracked_state gen8_wm_state = {
.emit = upload_wm_state,
};
-static void
-upload_ps_state(struct brw_context *brw)
+void
+gen8_upload_ps_state(struct brw_context *brw,
+ const struct gl_fragment_program *fp,
+ const struct brw_stage_state *stage_state,
+ const struct brw_wm_prog_data *prog_data,
+ uint32_t fast_clear_op)
{
struct gl_context *ctx = &brw->ctx;
uint32_t dw3 = 0, dw6 = 0, dw7 = 0, ksp0, ksp2 = 0;
- /* BRW_NEW_FS_PROG_DATA */
- const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
-
/* Initialize the execution mask with VMask. Otherwise, derivatives are
* incorrect for subspans where some of the pixels are unlit. We believe
* the bit just didn't take effect in previous generations.
*/
dw3 |= GEN7_PS_VECTOR_MASK_ENABLE;
- dw3 |=
- (ALIGN(brw->wm.base.sampler_count, 4) / 4) <<
GEN7_PS_SAMPLER_COUNT_SHIFT;
+ dw3 |= (ALIGN(stage_state->sampler_count, 4) / 4) <<
+ GEN7_PS_SAMPLER_COUNT_SHIFT;
/* BRW_NEW_FS_PROG_DATA */
dw3 |=
@@ -170,1
[Mesa-dev] [PATCH 14/18] i965/wm/gen6: Refactor program offset setup
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_state.h | 8 +
src/mesa/drivers/dri/i965/gen6_wm_state.c | 56 ++-
2 files changed, 41 insertions(+), 23 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_state.h
b/src/mesa/drivers/dri/i965/brw_state.h
index 23f36c0..ca3274d 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -292,6 +292,14 @@ void brw_update_sampler_state(struct brw_context *brw,
uint32_t *sampler_state,
uint32_t batch_offset_for_sampler_state);
+/* gen6_wm_state.c */
+void
+gen6_wm_state_set_programs(const struct brw_wm_prog_data *prog_data,
+ const struct brw_stage_state *stage_state,
+ int min_inv_per_frag,
+ uint32_t *ksp0, uint32_t *ksp2,
+ uint32_t *dw4, uint32_t *dw5, uint32_t *dw6);
+
/* gen6_sf_state.c */
void
calculate_attr_overrides(const struct brw_context *brw,
diff --git a/src/mesa/drivers/dri/i965/gen6_wm_state.c
b/src/mesa/drivers/dri/i965/gen6_wm_state.c
index 8e673a4..bc921e5 100644
--- a/src/mesa/drivers/dri/i965/gen6_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_wm_state.c
@@ -65,6 +65,37 @@ const struct brw_tracked_state gen6_wm_push_constants = {
.emit = gen6_upload_wm_push_constants,
};
+void
+gen6_wm_state_set_programs(const struct brw_wm_prog_data *prog_data,
+ const struct brw_stage_state *stage_state,
+ int min_inv_per_frag,
+ uint32_t *ksp0, uint32_t *ksp2,
+ uint32_t *dw4, uint32_t *dw5, uint32_t *dw6)
+{
+ if (prog_data->prog_offset_16 || prog_data->no_8) {
+ *dw5 |= GEN6_WM_16_DISPATCH_ENABLE;
+
+ if (!prog_data->no_8 && min_inv_per_frag == 1) {
+ *dw5 |= GEN6_WM_8_DISPATCH_ENABLE;
+ *dw4 |= (prog_data->base.dispatch_grf_start_reg <<
+ GEN6_WM_DISPATCH_START_GRF_SHIFT_0);
+ *dw4 |= (prog_data->dispatch_grf_start_reg_16 <<
+ GEN6_WM_DISPATCH_START_GRF_SHIFT_2);
+ *ksp0 = stage_state->prog_offset;
+ *ksp2 = stage_state->prog_offset + prog_data->prog_offset_16;
+ } else {
+ *dw4 |= (prog_data->dispatch_grf_start_reg_16 <<
+ GEN6_WM_DISPATCH_START_GRF_SHIFT_0);
+ *ksp0 = stage_state->prog_offset + prog_data->prog_offset_16;
+ }
+ } else {
+ *dw5 |= GEN6_WM_8_DISPATCH_ENABLE;
+ *dw4 |= (prog_data->base.dispatch_grf_start_reg <<
+ GEN6_WM_DISPATCH_START_GRF_SHIFT_0);
+ *ksp0 = stage_state->prog_offset;
+ }
+}
+
static void
upload_wm_state(struct brw_context *brw)
{
@@ -135,29 +166,8 @@ upload_wm_state(struct brw_context *brw)
_mesa_get_min_invocations_per_fragment(ctx, brw->fragment_program,
false);
assert(min_inv_per_frag >= 1);
- if (prog_data->prog_offset_16 || prog_data->no_8) {
- dw5 |= GEN6_WM_16_DISPATCH_ENABLE;
-
- if (!prog_data->no_8 && min_inv_per_frag == 1) {
- dw5 |= GEN6_WM_8_DISPATCH_ENABLE;
- dw4 |= (prog_data->base.dispatch_grf_start_reg <<
- GEN6_WM_DISPATCH_START_GRF_SHIFT_0);
- dw4 |= (prog_data->dispatch_grf_start_reg_16 <<
- GEN6_WM_DISPATCH_START_GRF_SHIFT_2);
- ksp0 = brw->wm.base.prog_offset;
- ksp2 = brw->wm.base.prog_offset + prog_data->prog_offset_16;
- } else {
- dw4 |= (prog_data->dispatch_grf_start_reg_16 <<
-GEN6_WM_DISPATCH_START_GRF_SHIFT_0);
- ksp0 = brw->wm.base.prog_offset + prog_data->prog_offset_16;
- }
- }
- else {
- dw5 |= GEN6_WM_8_DISPATCH_ENABLE;
- dw4 |= (prog_data->base.dispatch_grf_start_reg <<
- GEN6_WM_DISPATCH_START_GRF_SHIFT_0);
- ksp0 = brw->wm.base.prog_offset;
- }
+ gen6_wm_state_set_programs(prog_data, &brw->wm.base, min_inv_per_frag,
+ &ksp0, &ksp2, &dw4, &dw5, &dw6);
/* BRW_NEW_FS_PROG_DATA | _NEW_COLOR */
if (prog_data->dual_src_blend &&
--
1.9.3
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[Mesa-dev] [PATCH 15/18] i965/wm/gen6: Refactor push constant state uploading
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_state.h | 5
src/mesa/drivers/dri/i965/gen6_wm_state.c | 50 ++-
2 files changed, 34 insertions(+), 21 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_state.h
b/src/mesa/drivers/dri/i965/brw_state.h
index ca3274d..5be8035 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -300,6 +300,11 @@ gen6_wm_state_set_programs(const struct brw_wm_prog_data
*prog_data,
uint32_t *ksp0, uint32_t *ksp2,
uint32_t *dw4, uint32_t *dw5, uint32_t *dw6);
+void
+gen6_upload_constant_state(struct brw_context *brw,
+ const struct brw_wm_prog_data *prog_data,
+ const struct brw_stage_state *stage_state);
+
/* gen6_sf_state.c */
void
calculate_attr_overrides(const struct brw_context *brw,
diff --git a/src/mesa/drivers/dri/i965/gen6_wm_state.c
b/src/mesa/drivers/dri/i965/gen6_wm_state.c
index bc921e5..9edaf81 100644
--- a/src/mesa/drivers/dri/i965/gen6_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_wm_state.c
@@ -96,26 +96,11 @@ gen6_wm_state_set_programs(const struct brw_wm_prog_data
*prog_data,
}
}
-static void
-upload_wm_state(struct brw_context *brw)
+void
+gen6_upload_constant_state(struct brw_context *brw,
+ const struct brw_wm_prog_data *prog_data,
+ const struct brw_stage_state *stage_state)
{
- struct gl_context *ctx = &brw->ctx;
- /* BRW_NEW_FRAGMENT_PROGRAM */
- const struct brw_fragment_program *fp =
- brw_fragment_program_const(brw->fragment_program);
- /* BRW_NEW_FS_PROG_DATA */
- const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
- uint32_t dw2, dw4, dw5, dw6, ksp0, ksp2;
-
- /* _NEW_BUFFERS */
- bool multisampled_fbo = ctx->DrawBuffer->Visual.samples > 1;
-
- /* We can't fold this into gen6_upload_wm_push_constants(), because
-* according to the SNB PRM, vol 2 part 1 section 7.2.2
-* (3DSTATE_CONSTANT_PS [DevSNB]):
-*
-* "[DevSNB]: This packet must be followed by WM_STATE."
-*/
if (prog_data->base.nr_params == 0) {
/* Disable the push constant buffers. */
BEGIN_BATCH(5);
@@ -133,13 +118,36 @@ upload_wm_state(struct brw_context *brw)
/* Pointer to the WM constant buffer. Covered by the set of
* state flags from gen6_upload_wm_push_constants.
*/
- OUT_BATCH(brw->wm.base.push_const_offset +
- brw->wm.base.push_const_size - 1);
+ OUT_BATCH(stage_state->push_const_offset +
+ stage_state->push_const_size - 1);
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
ADVANCE_BATCH();
}
+}
+
+static void
+upload_wm_state(struct brw_context *brw)
+{
+ struct gl_context *ctx = &brw->ctx;
+ /* BRW_NEW_FRAGMENT_PROGRAM */
+ const struct brw_fragment_program *fp =
+ brw_fragment_program_const(brw->fragment_program);
+ /* BRW_NEW_FS_PROG_DATA */
+ const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
+ uint32_t dw2, dw4, dw5, dw6, ksp0, ksp2;
+
+ /* _NEW_BUFFERS */
+ const bool multisampled_fbo = ctx->DrawBuffer->Visual.samples > 1;
+
+ /* We can't fold this into gen6_upload_wm_push_constants(), because
+* according to the SNB PRM, vol 2 part 1 section 7.2.2
+* (3DSTATE_CONSTANT_PS [DevSNB]):
+*
+* "[DevSNB]: This packet must be followed by WM_STATE."
+*/
+ gen6_upload_constant_state(brw, prog_data, &brw->wm.base);
dw2 = dw4 = dw5 = dw6 = ksp2 = 0;
dw4 |= GEN6_WM_STATISTICS_ENABLE;
--
1.9.3
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[Mesa-dev] [PATCH 13/18] i965: Pass slice details as parameters for surface setup
Also changed a couple of direct shifts into SET_FIELD().
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_context.h | 3 ++-
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 30 +--
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 14 +--
src/mesa/drivers/dri/i965/gen8_surface_state.c| 10 +++-
4 files changed, 29 insertions(+), 28 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index b90d329..ae28955 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -964,10 +964,11 @@ struct brw_context
{
void (*update_texture_surface)(struct brw_context *brw,
const struct intel_mipmap_tree *mt,
- struct gl_texture_object *tObj,
uint32_t tex_format,
bool is_integer_format,
GLenum target, uint32_t effective_depth,
+ uint32_t min_layer,
+ uint32_t min_lod, uint32_t mip_count,
int swizzle, uint32_t *surf_offset,
bool for_gather);
uint32_t (*update_renderbuffer_surface)(struct brw_context *brw,
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index f7acad4..ad5ddb5 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -310,16 +310,16 @@ update_buffer_texture_surface(struct gl_context *ctx,
static void
brw_update_texture_surface(struct brw_context *brw,
const struct intel_mipmap_tree *mt,
- struct gl_texture_object *tObj,
uint32_t tex_format,
bool is_integer_format /* unused */,
GLenum target,
uint32_t effective_depth /* unused */,
+ uint32_t min_layer /* unused */,
+ uint32_t min_lod, uint32_t mip_count,
int swizzle /* unused */,
uint32_t *surf_offset,
bool for_gather)
{
- struct intel_texture_object *intelObj = intel_texture_object(tObj);
uint32_t *surf;
surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
@@ -361,16 +361,16 @@ brw_update_texture_surface(struct brw_context *brw,
surf[1] = mt->bo->offset64 + mt->offset; /* reloc */
- surf[2] = ((intelObj->_MaxLevel - tObj->BaseLevel) << BRW_SURFACE_LOD_SHIFT
|
- (mt->logical_width0 - 1) << BRW_SURFACE_WIDTH_SHIFT |
- (mt->logical_height0 - 1) << BRW_SURFACE_HEIGHT_SHIFT);
+ surf[2] = SET_FIELD(mip_count, BRW_SURFACE_LOD) |
+ SET_FIELD(mt->logical_width0 - 1, BRW_SURFACE_WIDTH) |
+ SET_FIELD(mt->logical_height0 - 1, BRW_SURFACE_HEIGHT);
- surf[3] = (brw_get_surface_tiling_bits(mt->tiling) |
- (mt->logical_depth0 - 1) << BRW_SURFACE_DEPTH_SHIFT |
- (mt->pitch - 1) << BRW_SURFACE_PITCH_SHIFT);
+ surf[3] = brw_get_surface_tiling_bits(mt->tiling) |
+SET_FIELD(mt->logical_depth0 - 1, BRW_SURFACE_DEPTH) |
+SET_FIELD(mt->pitch - 1, BRW_SURFACE_PITCH);
- surf[4] = (brw_get_surface_num_multisamples(mt->num_samples) |
- SET_FIELD(tObj->BaseLevel - mt->first_level,
BRW_SURFACE_MIN_LOD));
+ surf[4] = brw_get_surface_num_multisamples(mt->num_samples) |
+ SET_FIELD(min_lod, BRW_SURFACE_MIN_LOD);
surf[5] = mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0;
@@ -834,10 +834,14 @@ update_texture_surface(struct gl_context *ctx,
uint32_t effective_depth = (tObj->Immutable && tObj->Target !=
GL_TEXTURE_3D)
? tObj->NumLayers : mt->logical_depth0;
- brw->vtbl.update_texture_surface(brw, mt, tObj, tex_format,
+ const uint32_t mip_count = intelObj->_MaxLevel - tObj->BaseLevel;
+ const uint32_t min_lod = tObj->MinLevel + tObj->BaseLevel - mt->first_level;
+
+ brw->vtbl.update_texture_surface(brw, mt, tex_format,
tObj->_IsIntegerFormat, tObj->Target,
-effective_depth,
-swizzle, surf_offset, for_gather);
+effective_depth, tObj->MinLayer,
+min_lod, mip_count, swizzle, surf_offset,
+for_gather);
}
static void
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index b87680b..5370cef 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/
[Mesa-dev] [PATCH 02/18] i965: Expose and refactor brw_update_renderbuffer_surfaces()
Note that brw_update_renderbuffer_surfaces() already had a helper
variable which was used in parallel to direct access of the current
draw buffer of the context.
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_state.h| 5 +++
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 51 ++--
2 files changed, 35 insertions(+), 21 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_state.h
b/src/mesa/drivers/dri/i965/brw_state.h
index cfa67b6..83058b9 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -233,6 +233,11 @@ GLuint translate_tex_format(struct brw_context *brw,
int brw_get_texture_swizzle(const struct gl_context *ctx,
const struct gl_texture_object *t);
+void brw_update_renderbuffer_surfaces(struct brw_context *brw,
+ const struct gl_framebuffer *fb,
+ uint32_t render_target_start,
+ uint32_t *surf_offset);
+
/* gen7_wm_surface_state.c */
uint32_t gen7_surface_tiling_mode(uint32_t tiling);
uint32_t gen7_surface_msaa_bits(unsigned num_samples, enum intel_msaa_layout
l);
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 959d6c2..82dd92b 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -731,40 +731,49 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
/**
* Construct SURFACE_STATE objects for renderbuffers/draw buffers.
*/
-static void
-brw_update_renderbuffer_surfaces(struct brw_context *brw)
+void
+brw_update_renderbuffer_surfaces(struct brw_context *brw,
+ const struct gl_framebuffer *fb,
+ uint32_t render_target_start,
+ uint32_t *surf_offset)
{
- struct gl_context *ctx = &brw->ctx;
- /* _NEW_BUFFERS */
- const struct gl_framebuffer *fb = ctx->DrawBuffer;
GLuint i;
- /* _NEW_BUFFERS | _NEW_COLOR */
/* Update surfaces for drawing buffers */
- if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) {
- for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
- const uint32_t surf_index =
-brw->wm.prog_data->binding_table.render_target_start + i;
+ if (fb->_NumColorDrawBuffers >= 1) {
+ for (i = 0; i < fb->_NumColorDrawBuffers; i++) {
+ const uint32_t surf_index = render_target_start + i;
-if (intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[i])) {
-brw->wm.base.surf_offset[surf_index] =
+if (intel_renderbuffer(fb->_ColorDrawBuffers[i])) {
+surf_offset[surf_index] =
brw->vtbl.update_renderbuffer_surface(
- brw, ctx->DrawBuffer->_ColorDrawBuffers[i],
- ctx->DrawBuffer->MaxNumLayers > 0, i, surf_index);
+ brw, fb->_ColorDrawBuffers[i],
+ fb->MaxNumLayers > 0, i, surf_index);
} else {
brw->vtbl.emit_null_surface_state(
brw, fb->Width, fb->Height, fb->Visual.samples,
- &brw->wm.base.surf_offset[surf_index]);
+ &surf_offset[surf_index]);
}
}
} else {
- const uint32_t surf_index =
- brw->wm.prog_data->binding_table.render_target_start;
-
+ const uint32_t surf_index = render_target_start;
brw->vtbl.emit_null_surface_state(
brw, fb->Width, fb->Height, fb->Visual.samples,
- &brw->wm.base.surf_offset[surf_index]);
+ &surf_offset[surf_index]);
}
+}
+
+static void
+update_renderbuffer_surfaces(struct brw_context *brw)
+{
+ const struct gl_context *ctx = &brw->ctx;
+
+ /* _NEW_BUFFERS | _NEW_COLOR */
+ const struct gl_framebuffer *fb = ctx->DrawBuffer;
+ brw_update_renderbuffer_surfaces(
+ brw, fb,
+ brw->wm.prog_data->binding_table.render_target_start,
+ brw->wm.base.surf_offset);
brw->ctx.NewDriverState |= BRW_NEW_SURFACES;
}
@@ -775,7 +784,7 @@ const struct brw_tracked_state brw_renderbuffer_surfaces = {
.brw = BRW_NEW_BATCH |
BRW_NEW_FS_PROG_DATA,
},
- .emit = brw_update_renderbuffer_surfaces,
+ .emit = update_renderbuffer_surfaces,
};
const struct brw_tracked_state gen6_renderbuffer_surfaces = {
@@ -783,7 +792,7 @@ const struct brw_tracked_state gen6_renderbuffer_surfaces =
{
.mesa = _NEW_BUFFERS,
.brw = BRW_NEW_BATCH,
},
- .emit = brw_update_renderbuffer_surfaces,
+ .emit = update_renderbuffer_surfaces,
};
--
1.9.3
___
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mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 12/18] i965: Pass texture target as parameter for surface setup
Also changed a couple of direct shifts into SET_FIELD().
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_context.h | 2 +-
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 12 +++-
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 11 +--
src/mesa/drivers/dri/i965/gen8_surface_state.c| 13 +
4 files changed, 18 insertions(+), 20 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index bb375df..b90d329 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -967,7 +967,7 @@ struct brw_context
struct gl_texture_object *tObj,
uint32_t tex_format,
bool is_integer_format,
- uint32_t effective_depth,
+ GLenum target, uint32_t effective_depth,
int swizzle, uint32_t *surf_offset,
bool for_gather);
uint32_t (*update_renderbuffer_surface)(struct brw_context *brw,
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index ad03ffe..f7acad4 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -313,6 +313,7 @@ brw_update_texture_surface(struct brw_context *brw,
struct gl_texture_object *tObj,
uint32_t tex_format,
bool is_integer_format /* unused */,
+ GLenum target,
uint32_t effective_depth /* unused */,
int swizzle /* unused */,
uint32_t *surf_offset,
@@ -353,10 +354,10 @@ brw_update_texture_surface(struct brw_context *brw,
}
}
- surf[0] = (translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
- BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
- BRW_SURFACE_CUBEFACE_ENABLES |
- tex_format << BRW_SURFACE_FORMAT_SHIFT);
+ surf[0] = SET_FIELD(translate_tex_target(target), BRW_SURFACE_TYPE) |
+ BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
+ BRW_SURFACE_CUBEFACE_ENABLES |
+ tex_format << BRW_SURFACE_FORMAT_SHIFT;
surf[1] = mt->bo->offset64 + mt->offset; /* reloc */
@@ -834,7 +835,8 @@ update_texture_surface(struct gl_context *ctx,
? tObj->NumLayers : mt->logical_depth0;
brw->vtbl.update_texture_surface(brw, mt, tObj, tex_format,
-tObj->_IsIntegerFormat, effective_depth,
+tObj->_IsIntegerFormat, tObj->Target,
+effective_depth,
swizzle, surf_offset, for_gather);
}
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index 005b4eb..b87680b 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -268,7 +268,7 @@ gen7_update_texture_surface(struct brw_context *brw,
const struct intel_mipmap_tree *mt,
struct gl_texture_object *tObj,
uint32_t tex_format, bool is_integer_format,
-uint32_t effective_depth,
+GLenum target, uint32_t effective_depth,
int swizzle, uint32_t *surf_offset,
bool for_gather)
{
@@ -281,12 +281,12 @@ gen7_update_texture_surface(struct brw_context *brw,
if (for_gather && tex_format == BRW_SURFACEFORMAT_R32G32_FLOAT)
tex_format = BRW_SURFACEFORMAT_R32G32_FLOAT_LD;
- surf[0] = translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
- tex_format << BRW_SURFACE_FORMAT_SHIFT |
+ surf[0] = SET_FIELD(translate_tex_target(target), BRW_SURFACE_TYPE) |
+ SET_FIELD(tex_format, BRW_SURFACE_FORMAT) |
gen7_surface_tiling_mode(mt->tiling);
/* mask of faces present in cube map; for other surfaces MBZ. */
- if (tObj->Target == GL_TEXTURE_CUBE_MAP || tObj->Target ==
GL_TEXTURE_CUBE_MAP_ARRAY)
+ if (target == GL_TEXTURE_CUBE_MAP || target == GL_TEXTURE_CUBE_MAP_ARRAY)
surf[0] |= BRW_SURFACE_CUBEFACE_ENABLES;
if (mt->align_h == 4)
@@ -294,8 +294,7 @@ gen7_update_texture_surface(struct brw_context *brw,
if (mt->align_w == 8)
surf[0] |= GEN7_SURFACE_HALIGN_8;
- if (_mesa_is_array_texture(tObj->Target) ||
- tObj->Target == GL_TEXTURE_CUBE_MAP)
+ if (_mesa_is_array_texture(target) || target == GL_TEXTURE_CUBE_MAP)
surf[0] |= GE
[Mesa-dev] [PATCH 09/18] i965: Move texture swizzle resolving into dispatcher
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_context.h | 4 ++--
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 20 +++-
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 17 ++---
src/mesa/drivers/dri/i965/gen8_surface_state.c| 16 ++--
4 files changed, 21 insertions(+), 36 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index 096bc4d..6bb46e3 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -962,10 +962,10 @@ struct brw_context
struct
{
- void (*update_texture_surface)(struct gl_context *ctx,
+ void (*update_texture_surface)(struct brw_context *brw,
const struct intel_mipmap_tree *mt,
struct gl_texture_object *tObj,
- uint32_t tex_format,
+ uint32_t tex_format, int swizzle,
uint32_t *surf_offset,
bool for_gather);
uint32_t (*update_renderbuffer_surface)(struct brw_context *brw,
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index d8faf82..0d81576 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -308,14 +308,13 @@ update_buffer_texture_surface(struct gl_context *ctx,
}
static void
-brw_update_texture_surface(struct gl_context *ctx,
+brw_update_texture_surface(struct brw_context *brw,
const struct intel_mipmap_tree *mt,
struct gl_texture_object *tObj,
- uint32_t tex_format,
+ uint32_t tex_format, int swizzle /* unused */,
uint32_t *surf_offset,
bool for_gather)
{
- struct brw_context *brw = brw_context(ctx);
struct intel_texture_object *intelObj = intel_texture_object(tObj);
uint32_t *surf;
@@ -814,8 +813,19 @@ update_texture_surface(struct gl_context *ctx,
const uint32_t tex_format = translate_tex_format(brw, format,
sampler->sRGBDecode);
- brw->vtbl.update_texture_surface(ctx, mt, tObj, tex_format, surf_offset,
-for_gather);
+ /* Handling GL_ALPHA as a surface format override breaks 1.30+ style
+* texturing functions that return a float, as our code generation always
+* selects the .x channel (which would always be 0).
+*/
+ const bool alpha_depth = tObj->DepthMode == GL_ALPHA &&
+ (firstImage->_BaseFormat == GL_DEPTH_COMPONENT ||
+ firstImage->_BaseFormat == GL_DEPTH_STENCIL);
+
+ const int swizzle = unlikely(alpha_depth)
+ ? SWIZZLE_XYZW : brw_get_texture_swizzle(ctx, tObj);
+
+ brw->vtbl.update_texture_surface(brw, mt, tObj, tex_format, swizzle,
+surf_offset, for_gather);
}
static void
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index 9a1af98..bb2b889 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -264,16 +264,14 @@ gen7_emit_buffer_surface_state(struct brw_context *brw,
}
static void
-gen7_update_texture_surface(struct gl_context *ctx,
+gen7_update_texture_surface(struct brw_context *brw,
const struct intel_mipmap_tree *mt,
struct gl_texture_object *tObj,
-uint32_t tex_format,
+uint32_t tex_format, int swizzle,
uint32_t *surf_offset,
bool for_gather)
{
- struct brw_context *brw = brw_context(ctx);
struct intel_texture_object *intelObj = intel_texture_object(tObj);
- struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
8 * 4, 32, surf_offset);
@@ -332,17 +330,6 @@ gen7_update_texture_surface(struct gl_context *ctx,
surf[7] = mt->fast_clear_color_value;
if (brw->is_haswell) {
- /* Handling GL_ALPHA as a surface format override breaks 1.30+ style
- * texturing functions that return a float, as our code generation always
- * selects the .x channel (which would always be 0).
- */
- const bool alpha_depth = tObj->DepthMode == GL_ALPHA &&
- (firstImage->_BaseFormat == GL_DEPTH_COMPONENT ||
- firstImage->_BaseFormat == GL_DEPTH_STENCIL);
-
- const int swizzle = unlikely(alpha_depth)
- ? SWIZZLE_XYZW : brw_get_texture_swizzle(ctx, tObj);
-
const bool need_scs_gree
[Mesa-dev] [PATCH 11/18] i965: Refactor effective depth calculation
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_context.h | 4 ++--
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 11 +--
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 7 +--
src/mesa/drivers/dri/i965/gen8_surface_state.c| 8 +---
4 files changed, 13 insertions(+), 17 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index 1461310..bb375df 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -967,8 +967,8 @@ struct brw_context
struct gl_texture_object *tObj,
uint32_t tex_format,
bool is_integer_format,
- int swizzle,
- uint32_t *surf_offset,
+ uint32_t effective_depth,
+ int swizzle, uint32_t *surf_offset,
bool for_gather);
uint32_t (*update_renderbuffer_surface)(struct brw_context *brw,
struct gl_renderbuffer *rb,
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index c76d09d..ad03ffe 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -313,6 +313,7 @@ brw_update_texture_surface(struct brw_context *brw,
struct gl_texture_object *tObj,
uint32_t tex_format,
bool is_integer_format /* unused */,
+ uint32_t effective_depth /* unused */,
int swizzle /* unused */,
uint32_t *surf_offset,
bool for_gather)
@@ -826,9 +827,15 @@ update_texture_surface(struct gl_context *ctx,
const int swizzle = unlikely(alpha_depth)
? SWIZZLE_XYZW : brw_get_texture_swizzle(ctx, tObj);
+ /* if this is a view with restricted NumLayers, then
+* our effective depth is not just the miptree depth.
+*/
+ uint32_t effective_depth = (tObj->Immutable && tObj->Target !=
GL_TEXTURE_3D)
+ ? tObj->NumLayers : mt->logical_depth0;
+
brw->vtbl.update_texture_surface(brw, mt, tObj, tex_format,
-tObj->_IsIntegerFormat, swizzle,
-surf_offset, for_gather);
+tObj->_IsIntegerFormat, effective_depth,
+swizzle, surf_offset, for_gather);
}
static void
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index 46c96f7..005b4eb 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -268,6 +268,7 @@ gen7_update_texture_surface(struct brw_context *brw,
const struct intel_mipmap_tree *mt,
struct gl_texture_object *tObj,
uint32_t tex_format, bool is_integer_format,
+uint32_t effective_depth,
int swizzle, uint32_t *surf_offset,
bool for_gather)
{
@@ -297,12 +298,6 @@ gen7_update_texture_surface(struct brw_context *brw,
tObj->Target == GL_TEXTURE_CUBE_MAP)
surf[0] |= GEN7_SURFACE_IS_ARRAY;
- /* if this is a view with restricted NumLayers, then
-* our effective depth is not just the miptree depth.
-*/
- uint32_t effective_depth = (tObj->Immutable && tObj->Target !=
GL_TEXTURE_3D)
- ? tObj->NumLayers : mt->logical_depth0;
-
if (mt->array_layout == ALL_SLICES_AT_EACH_LOD)
surf[0] |= GEN7_SURFACE_ARYSPC_LOD0;
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c
b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index d7287b8..feed343 100644
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -155,6 +155,7 @@ gen8_update_texture_surface(struct brw_context *brw,
struct gl_texture_object *tObj,
uint32_t tex_format,
bool is_integer_format /* unused */,
+uint32_t effective_depth,
int swizzle, uint32_t *surf_offset,
bool for_gather)
{
@@ -177,13 +178,6 @@ gen8_update_texture_surface(struct brw_context *brw,
aux_mode = GEN8_SURFACE_AUX_MODE_MCS;
}
- /* If this is a view with restricted NumLayers, then our effective depth
-* is not just the miptree depth.
-*/
- uint32_t effective_depth =
- (tObj->Immutable && t
[Mesa-dev] [PATCH 16/18] i965/ps/gen7: Refactor state uploading
Now the uploading depends only on the input parameters instead
of consulting the current gl-state.
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_state.h | 9 +
src/mesa/drivers/dri/i965/gen7_wm_state.c | 58 ---
2 files changed, 46 insertions(+), 21 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_state.h
b/src/mesa/drivers/dri/i965/brw_state.h
index 5be8035..178f039 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -245,6 +245,15 @@ void brw_update_renderbuffer_surfaces(struct brw_context
*brw,
uint32_t render_target_start,
uint32_t *surf_offset);
+/* gen7_wm_state.c */
+void
+gen7_upload_ps_state(struct brw_context *brw,
+ const struct gl_fragment_program *fp,
+ const struct brw_stage_state *stage_state,
+ const struct brw_wm_prog_data *prog_data,
+ bool enable_dual_src_blend, unsigned sample_mask,
+ unsigned fast_clear_op);
+
/* gen7_wm_surface_state.c */
uint32_t gen7_surface_tiling_mode(uint32_t tiling);
uint32_t gen7_surface_msaa_bits(unsigned num_samples, enum intel_msaa_layout
l);
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c
b/src/mesa/drivers/dri/i965/gen7_wm_state.c
index 923414e..dc4264c 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c
@@ -122,21 +122,23 @@ const struct brw_tracked_state gen7_wm_state = {
.emit = upload_wm_state,
};
-static void
-upload_ps_state(struct brw_context *brw)
+void
+gen7_upload_ps_state(struct brw_context *brw,
+ const struct gl_fragment_program *fp,
+ const struct brw_stage_state *stage_state,
+ const struct brw_wm_prog_data *prog_data,
+ bool enable_dual_src_blend, unsigned sample_mask,
+ unsigned fast_clear_op)
{
struct gl_context *ctx = &brw->ctx;
uint32_t dw2, dw4, dw5, ksp0, ksp2;
const int max_threads_shift = brw->is_haswell ?
HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT;
- /* BRW_NEW_FS_PROG_DATA */
- const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
-
dw2 = dw4 = dw5 = ksp2 = 0;
- dw2 |=
- (ALIGN(brw->wm.base.sampler_count, 4) / 4) <<
GEN7_PS_SAMPLER_COUNT_SHIFT;
+ dw2 |= ((ALIGN(stage_state->sampler_count, 4) / 4) <<
+ GEN7_PS_SAMPLER_COUNT_SHIFT);
dw2 |= ((prog_data->base.binding_table.size_bytes / 4) <<
GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT);
@@ -148,7 +150,7 @@ upload_ps_state(struct brw_context *brw)
* in 3DSTATE_SAMPLE_MASK; the values should match. */
/* _NEW_BUFFERS, _NEW_MULTISAMPLE */
if (brw->is_haswell)
- dw4 |= SET_FIELD(gen6_determine_sample_mask(brw), HSW_PS_SAMPLE_MASK);
+ dw4 |= SET_FIELD(sample_mask, HSW_PS_SAMPLE_MASK);
dw4 |= (brw->max_wm_threads - 1) << max_threads_shift;
@@ -181,16 +183,11 @@ upload_ps_state(struct brw_context *brw)
else
dw4 |= GEN7_PS_POSOFFSET_NONE;
- /* BRW_NEW_FS_PROG_DATA | _NEW_COLOR
-*
-* The hardware wedges if you have this bit set but don't turn on any dual
+ /* The hardware wedges if you have this bit set but don't turn on any dual
* source blend factors.
*/
- if (prog_data->dual_src_blend &&
- (ctx->Color.BlendEnabled & 1) &&
- ctx->Color.Blend[0]._UsesDualSrc) {
+ if (enable_dual_src_blend)
dw4 |= GEN7_PS_DUAL_SOURCE_BLEND_ENABLE;
- }
/* BRW_NEW_FS_PROG_DATA */
if (prog_data->num_varying_inputs != 0)
@@ -202,7 +199,7 @@ upload_ps_state(struct brw_context *brw)
* better performance than 'SIMD8 only' dispatch.
*/
int min_inv_per_frag =
- _mesa_get_min_invocations_per_fragment(ctx, brw->fragment_program,
false);
+ _mesa_get_min_invocations_per_fragment(ctx, fp, false);
assert(min_inv_per_frag >= 1);
if (prog_data->prog_offset_16 || prog_data->no_8) {
@@ -213,22 +210,22 @@ upload_ps_state(struct brw_context *brw)
GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
dw5 |= (prog_data->dispatch_grf_start_reg_16 <<
GEN7_PS_DISPATCH_START_GRF_SHIFT_2);
- ksp0 = brw->wm.base.prog_offset;
- ksp2 = brw->wm.base.prog_offset + prog_data->prog_offset_16;
+ ksp0 = stage_state->prog_offset;
+ ksp2 = stage_state->prog_offset + prog_data->prog_offset_16;
} else {
dw5 |= (prog_data->dispatch_grf_start_reg_16 <<
GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
- ksp0 = brw->wm.base.prog_offset + prog_data->prog_offset_16;
+ ksp0 = stage_state->prog_offset + prog_data->prog_offset_16;
}
}
else {
dw4 |= GEN7_PS_8_DISPATCH_ENABLE;
dw5 |= (prog_data->base.dispatch_grf_start_reg <<
GEN7_PS_DISPATCH_START
Re: [Mesa-dev] [PATCH 00/23] i965: Divorce the compiler from brw_context
On Fri, Apr 17, 2015 at 10:10 PM, Matt Turner wrote: > 1-3 are > > Reviewed-by: Matt Turner > > Patch 4 is missing (from the archives too). Okay, 4's a pile of churn and got held in moderation. I've sent comments for 5, 8 (use unreachable), 13 (use unreachable), 14 (remove comments), Typos in the subjects of at least patches 10, 21, and 22. I don't know what's going on with 20. I'm going to say 1-19 are Reviewed-by: Matt Turner I was going to reply with some patches to squash in, but the churn in this series is such a nightmare that it's not possible. It'll have to be follow on clean ups, if at all. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH v4] i965/aa: fixing anti-aliasing bug for thinnest width lines - GEN7
On Thu, Apr 2, 2015 at 4:30 AM, Predut, Marius wrote:
> Please "review by" feedback please :-)
>
> -Original Message-
> From: Predut, Marius
> Sent: Thursday, March 19, 2015 9:34 PM
> To: mesa-dev@lists.freedesktop.org
> Cc: Predut, Marius
> Subject: [Mesa-dev][PATCH v4] i965/aa: fixing anti-aliasing bug for thinnest
> width lines - GEN7
I was confused by the fact that there were separate Gen6 and Gen7
patches. That's fine, though I probably wouldn't bother doing it
myself, but if that's what you want you definitely should send them as
a 2 patch series.
Having just two nearly identically named patches is prone to confusion.
> On SNB and IVB hw, for 1 pixel line thickness or less, the general
> anti-aliasing algorithm give up - garbage line is generated.
> Setting a Line Width of 0.0 specifies the rasterization of the “thinnest”
> (one-pixel-wide), non-antialiased lines.
> Lines rendered with zero Line Width are rasterized using Grid Intersection
> Quantization rules as specified by bspec section 6.3.12.1 Zero-Width
> (Cosmetic) Line Rasterization.
>
> v2: Daniel Stone: Fix = used instead of == in an if-statement.
> v3: Ian Romanick: Use "._Enabled" flag insteed ".Enabled".
> Add code comments. re-word wrap the commit message.
> Add a complete bugzillia list.
> Improve the hardcoded values to produce better results.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=28832
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=9951
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=27007
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60797
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=15006
>
> Signed-off-by: Marius Predut
> ---
> src/mesa/drivers/dri/i965/gen7_sf_state.c | 21 ++---
> 1 file changed, 18 insertions(+), 3 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/gen7_sf_state.c
> b/src/mesa/drivers/dri/i965/gen7_sf_state.c
> index c9815b0..e33cb79 100644
> --- a/src/mesa/drivers/dri/i965/gen7_sf_state.c
> +++ b/src/mesa/drivers/dri/i965/gen7_sf_state.c
> @@ -198,9 +198,24 @@ upload_sf_state(struct brw_context *brw)
>float line_width =
> roundf(CLAMP(ctx->Line.Width, 0.0, ctx->Const.MaxLineWidth));
>uint32_t line_width_u3_7 = U_FIXED(line_width, 7);
> - /* TODO: line width of 0 is not allowed when MSAA enabled */
> - if (line_width_u3_7 == 0)
> - line_width_u3_7 = 1;
> + /* Line width of 0 is not allowed when MSAA enabled */
> + if (ctx->Multisample._Enabled) {
> + if (line_width_u3_7 == 0)
> + line_width_u3_7 = 1;
> + } else if (ctx->Line.SmoothFlag && ctx->Line.Width <= 1.49) {
I don't know what 1.49 is. Presumably you're checking for values that
line widths that round-to-nearest to 1.0? If so, shouldn't that be
ctx->Line.Width < 1.5?
> + /* For lines less than 1 pixel thick, the general
But then the comment says "less than 1 pixel thick", so I don't
understand -- and it's not helping that I don't really know anything
about this code to begin with. :)
Presumably the comment in the commit message saying "for 1 pixel line
thickness or less" is more correct.
For what it's worth, I did confirm that this patch makes the
line-aa-width test in piglit go from fail -> pass on my Haswell.
> + * anti-aliasing algorithm gives up, and a garbage line is
> + * generated. Setting a Line Width of 0.0 specifies the
> + * rasterization of the "thinnest" (one-pixel-wide),
> + * non-antialiased lines.
> + *
> + * Lines rendered with zero Line Width are rasterized using
> + * Grid Intersection Quantization rules as specified by
> + * bspec section 6.3.12.1 Zero-Width (Cosmetic) Line
> + * Rasterization.
> + */
> + line_width_u3_7 = 0;
> + }
>dw2 |= line_width_u3_7 << GEN6_SF_LINE_WIDTH_SHIFT;
> }
> if (ctx->Line.SmoothFlag) {
> --
> 1.7.9.5
>
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Re: [Mesa-dev] [PATCH 09/12] nir: Add a simple growing array data structure
I think it would be better to call this "nir_vector" rather than
"nir_array," since this is essentially a poor man's version of
std::vector<>. Is this ok with you?
On Fri, Apr 10, 2015 at 8:48 PM, Jason Ekstrand wrote:
> ---
> src/glsl/nir/nir_array.h | 96
>
> 1 file changed, 96 insertions(+)
> create mode 100644 src/glsl/nir/nir_array.h
>
> diff --git a/src/glsl/nir/nir_array.h b/src/glsl/nir/nir_array.h
> new file mode 100644
> index 000..1db4e8c
> --- /dev/null
> +++ b/src/glsl/nir/nir_array.h
> @@ -0,0 +1,96 @@
> +/*
> + * Copyright © 2015 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> DEALINGS
> + * IN THE SOFTWARE.
> + *
> + * Authors:
> + *Jason Ekstrand (ja...@jlekstrand.net)
> + *
> + */
> +
> +#pragma once
> +
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +typedef struct {
> + void *mem_ctx;
> + size_t size;
> + size_t alloc;
> + void *data;
> +} nir_array;
> +
> +static inline void
> +nir_array_init(nir_array *arr, void *mem_ctx)
> +{
> + arr->mem_ctx = mem_ctx;
> + arr->size = 0;
> + arr->alloc = 0;
> + arr->data = NULL;
> +}
> +
> +static inline void
> +nir_array_fini(nir_array *arr)
> +{
> + if (arr->mem_ctx)
> + ralloc_free(arr->data);
> + else
> + free(arr->data);
> +}
> +
> +#define NIR_ARRAY_INITIAL_SIZE 64
> +
> +/* Increments the size of the array by the given ammount and returns a
> + * pointer to the beginning of the newly added space.
> + */
> +static inline void *
> +nir_array_grow(nir_array *arr, size_t additional)
> +{
> + size_t new_size = arr->size + additional;
> + if (new_size > arr->alloc) {
> + if (arr->alloc == 0)
> + arr->alloc = NIR_ARRAY_INITIAL_SIZE;
> +
> + while (new_size > arr->alloc)
> + arr->alloc *= 2;
> +
> + if (arr->mem_ctx)
> + arr->data = reralloc_size(arr->mem_ctx, arr->data, arr->alloc);
> + else
> + arr->data = realloc(arr->data, arr->alloc);
> + }
> +
> + void *ptr = (void *)((char *)arr->data + arr->size);
> + arr->size = new_size;
> +
> + return ptr;
> +}
> +
> +#define nir_array_add(arr, type, elem) \
> + *(type *)nir_array_grow(arr, sizeof(type)) = (elem)
> +
> +#define nir_array_foreach(arr, type, elem) \
> + for (type *elem = (type *)(arr)->data; \
> +elem < (type *)((char *)(arr)->data + (arr)->size); elem++)
> +
> +#ifdef __cplusplus
> +} /* extern "C" */
> +#endif
> --
> 2.3.5
>
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Re: [Mesa-dev] [PATCH 09/12] nir: Add a simple growing array data structure
On Wed, Apr 22, 2015 at 3:03 PM, Connor Abbott wrote:
> I think it would be better to call this "nir_vector" rather than
> "nir_array," since this is essentially a poor man's version of
> std::vector<>. Is this ok with you?
I battled over that one for quite a while. In the end, I settled on
nir_array because NIR is a compiler IR for vector architectures and I
was concerned that a datatype called nir_vector that was not, in fact,
a vector in the mathematical sense would be troublesome.
--Jason
> On Fri, Apr 10, 2015 at 8:48 PM, Jason Ekstrand wrote:
>> ---
>> src/glsl/nir/nir_array.h | 96
>>
>> 1 file changed, 96 insertions(+)
>> create mode 100644 src/glsl/nir/nir_array.h
>>
>> diff --git a/src/glsl/nir/nir_array.h b/src/glsl/nir/nir_array.h
>> new file mode 100644
>> index 000..1db4e8c
>> --- /dev/null
>> +++ b/src/glsl/nir/nir_array.h
>> @@ -0,0 +1,96 @@
>> +/*
>> + * Copyright © 2015 Intel Corporation
>> + *
>> + * Permission is hereby granted, free of charge, to any person obtaining a
>> + * copy of this software and associated documentation files (the
>> "Software"),
>> + * to deal in the Software without restriction, including without limitation
>> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>> + * and/or sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice (including the next
>> + * paragraph) shall be included in all copies or substantial portions of the
>> + * Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
>> OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
>> OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
>> DEALINGS
>> + * IN THE SOFTWARE.
>> + *
>> + * Authors:
>> + *Jason Ekstrand (ja...@jlekstrand.net)
>> + *
>> + */
>> +
>> +#pragma once
>> +
>> +#ifdef __cplusplus
>> +extern "C" {
>> +#endif
>> +
>> +typedef struct {
>> + void *mem_ctx;
>> + size_t size;
>> + size_t alloc;
>> + void *data;
>> +} nir_array;
>> +
>> +static inline void
>> +nir_array_init(nir_array *arr, void *mem_ctx)
>> +{
>> + arr->mem_ctx = mem_ctx;
>> + arr->size = 0;
>> + arr->alloc = 0;
>> + arr->data = NULL;
>> +}
>> +
>> +static inline void
>> +nir_array_fini(nir_array *arr)
>> +{
>> + if (arr->mem_ctx)
>> + ralloc_free(arr->data);
>> + else
>> + free(arr->data);
>> +}
>> +
>> +#define NIR_ARRAY_INITIAL_SIZE 64
>> +
>> +/* Increments the size of the array by the given ammount and returns a
>> + * pointer to the beginning of the newly added space.
>> + */
>> +static inline void *
>> +nir_array_grow(nir_array *arr, size_t additional)
>> +{
>> + size_t new_size = arr->size + additional;
>> + if (new_size > arr->alloc) {
>> + if (arr->alloc == 0)
>> + arr->alloc = NIR_ARRAY_INITIAL_SIZE;
>> +
>> + while (new_size > arr->alloc)
>> + arr->alloc *= 2;
>> +
>> + if (arr->mem_ctx)
>> + arr->data = reralloc_size(arr->mem_ctx, arr->data, arr->alloc);
>> + else
>> + arr->data = realloc(arr->data, arr->alloc);
>> + }
>> +
>> + void *ptr = (void *)((char *)arr->data + arr->size);
>> + arr->size = new_size;
>> +
>> + return ptr;
>> +}
>> +
>> +#define nir_array_add(arr, type, elem) \
>> + *(type *)nir_array_grow(arr, sizeof(type)) = (elem)
>> +
>> +#define nir_array_foreach(arr, type, elem) \
>> + for (type *elem = (type *)(arr)->data; \
>> +elem < (type *)((char *)(arr)->data + (arr)->size); elem++)
>> +
>> +#ifdef __cplusplus
>> +} /* extern "C" */
>> +#endif
>> --
>> 2.3.5
>>
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Re: [Mesa-dev] [PATCH 06/12] nir/lower_vars_to_ssa: Pass around the nir_shader instead of a void mem_ctx
On Fri, Apr 10, 2015 at 8:48 PM, Jason Ekstrand wrote:
> ---
> src/glsl/nir/nir_lower_vars_to_ssa.c | 28 ++--
> 1 file changed, 14 insertions(+), 14 deletions(-)
>
> diff --git a/src/glsl/nir/nir_lower_vars_to_ssa.c
> b/src/glsl/nir/nir_lower_vars_to_ssa.c
> index 8b7261c..1afa9b7 100644
> --- a/src/glsl/nir/nir_lower_vars_to_ssa.c
> +++ b/src/glsl/nir/nir_lower_vars_to_ssa.c
> @@ -55,7 +55,7 @@ struct deref_node {
> };
>
> struct lower_variables_state {
> - void *mem_ctx;
> + nir_shader *shader;
> void *dead_ctx;
> nir_function_impl *impl;
>
> @@ -112,12 +112,12 @@ type_get_length(const struct glsl_type *type)
>
> static struct deref_node *
> deref_node_create(struct deref_node *parent,
> - const struct glsl_type *type, void *mem_ctx)
> + const struct glsl_type *type, void *shader)
Any particular reason why you didn't change the type here too? It
seems a little silly to have a parameter called 'shader' that's a void
*.
> {
> size_t size = sizeof(struct deref_node) +
> type_get_length(type) * sizeof(struct deref_node *);
>
> - struct deref_node *node = rzalloc_size(mem_ctx, size);
> + struct deref_node *node = rzalloc_size(shader, size);
> node->type = type;
> node->parent = parent;
> node->deref = NULL;
> @@ -469,7 +469,7 @@ lower_copies_to_load_store(struct deref_node *node,
> set_foreach(node->copies, copy_entry) {
>nir_intrinsic_instr *copy = (void *)copy_entry->key;
>
> - nir_lower_var_copy_instr(copy, state->mem_ctx);
> + nir_lower_var_copy_instr(copy, state->shader);
>
>for (unsigned i = 0; i < 2; ++i) {
> struct deref_node *arg_node =
> @@ -527,7 +527,7 @@ get_const_initializer_load(const nir_deref_var *deref,
> }
>
> nir_load_const_instr *load =
> - nir_load_const_instr_create(state->mem_ctx,
> + nir_load_const_instr_create(state->shader,
>glsl_get_vector_elements(tail->type));
>
> matrix_offset *= load->def.num_components;
> @@ -618,7 +618,7 @@ get_ssa_def_for_block(struct deref_node *node, nir_block
> *block,
> * given block. This means that we need to add an undef and use that.
> */
> nir_ssa_undef_instr *undef =
> - nir_ssa_undef_instr_create(state->mem_ctx,
> + nir_ssa_undef_instr_create(state->shader,
> glsl_get_vector_elements(node->type));
> nir_instr_insert_before_cf_list(&state->impl->body, &undef->instr);
> def_stack_push(node, &undef->def, state);
> @@ -698,7 +698,7 @@ rename_variables_block(nir_block *block, struct
> lower_variables_state *state)
> * should result in an undefined value.
> */
> nir_ssa_undef_instr *undef =
> - nir_ssa_undef_instr_create(state->mem_ctx,
> + nir_ssa_undef_instr_create(state->shader,
> intrin->num_components);
>
> nir_instr_insert_before(&intrin->instr, &undef->instr);
> @@ -706,14 +706,14 @@ rename_variables_block(nir_block *block, struct
> lower_variables_state *state)
>
> nir_ssa_def_rewrite_uses(&intrin->dest.ssa,
> nir_src_for_ssa(&undef->def),
> -state->mem_ctx);
> +state->shader);
> continue;
> }
>
> if (!node->lower_to_ssa)
> continue;
>
> -nir_alu_instr *mov = nir_alu_instr_create(state->mem_ctx,
> +nir_alu_instr *mov = nir_alu_instr_create(state->shader,
>nir_op_imov);
> mov->src[0].src.is_ssa = true;
> mov->src[0].src.ssa = get_ssa_def_for_block(node, block, state);
> @@ -731,7 +731,7 @@ rename_variables_block(nir_block *block, struct
> lower_variables_state *state)
>
> nir_ssa_def_rewrite_uses(&intrin->dest.ssa,
> nir_src_for_ssa(&mov->dest.dest.ssa),
> - state->mem_ctx);
> + state->shader);
> break;
> }
>
> @@ -754,7 +754,7 @@ rename_variables_block(nir_block *block, struct
> lower_variables_state *state)
>
> assert(intrin->src[0].is_ssa);
>
> -nir_alu_instr *mov = nir_alu_instr_create(state->mem_ctx,
> +nir_alu_instr *mov = nir_alu_instr_create(state->shader,
>nir_op_imov);
> mov->src[0].src.is_ssa = true;
> mov->src[0].src.ssa = intrin->src[0].ssa;
> @@ -891,7 +891,7 @@ insert_phi_nodes(struct lower_variables_state *state)
> continue;
>
> if (has_already[next->index] < iter_count) {
> - nir_phi_instr *phi = nir_phi_i
Re: [Mesa-dev] [Mesa-stable] [PATCH 1/2] i965: Make intel_emit_linear_blit handle Gen8+ alignment restrictions.
On Tue, Apr 21, 2015 at 10:13 PM, Kenneth Graunke wrote:
> The BLT engine on Gen8+ requires linear surfaces to be cacheline
> aligned. This restriction was added as part of converting the BLT to
> use 48-bit addressing.
>
> intel_emit_linear_blit needs to handle blits that are not cacheline
> aligned, as we use it for arbitrary glBufferSubData calls and subrange
> mappings.
>
> Since intel_emit_linear_blit uses 1 byte per pixel, we can use the src/dst
> pixel X offset field to represent the unaligned portion, and subtract
> that from the address so it's cacheline aligned.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88521
> Signed-off-by: Kenneth Graunke
> Cc: mesa-sta...@lists.freedesktop.org
> ---
> src/mesa/drivers/dri/i965/intel_blit.c | 22 ++
> 1 file changed, 14 insertions(+), 8 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/intel_blit.c
> b/src/mesa/drivers/dri/i965/intel_blit.c
> index 4993f60..98d414c 100644
> --- a/src/mesa/drivers/dri/i965/intel_blit.c
> +++ b/src/mesa/drivers/dri/i965/intel_blit.c
> @@ -524,6 +524,7 @@ intel_emit_linear_blit(struct brw_context *brw,
> {
> struct gl_context *ctx = &brw->ctx;
> GLuint pitch, height;
> + int16_t src_x, dst_x;
> bool ok;
>
> /* The pitch given to the GPU must be DWORD aligned, and
> @@ -532,11 +533,13 @@ intel_emit_linear_blit(struct brw_context *brw,
> */
> pitch = ROUND_DOWN_TO(MIN2(size, (1 << 15) - 1), 4);
> height = (pitch == 0) ? 1 : size / pitch;
> + src_x = src_offset % 64;
> + dst_x = dst_offset % 64;
> ok = intelEmitCopyBlit(brw, 1,
> - pitch, src_bo, src_offset, I915_TILING_NONE,
> - pitch, dst_bo, dst_offset, I915_TILING_NONE,
> - 0, 0, /* src x/y */
> - 0, 0, /* dst x/y */
> + pitch, src_bo, src_offset - src_x, I915_TILING_NONE,
> + pitch, dst_bo, dst_offset - dst_x, I915_TILING_NONE,
> + src_x, 0, /* src x/y */
> + dst_x, 0, /* dst x/y */
> pitch, height, /* w, h */
> GL_COPY);
> if (!ok)
> @@ -544,15 +547,18 @@ intel_emit_linear_blit(struct brw_context *brw,
>
> src_offset += pitch * height;
> dst_offset += pitch * height;
> + src_x = src_offset % 64;
> + dst_x = dst_offset % 64;
> size -= pitch * height;
> assert (size < (1 << 15));
> pitch = ALIGN(size, 4);
> +
> if (size != 0) {
>ok = intelEmitCopyBlit(brw, 1,
> -pitch, src_bo, src_offset, I915_TILING_NONE,
> -pitch, dst_bo, dst_offset, I915_TILING_NONE,
> -0, 0, /* src x/y */
> -0, 0, /* dst x/y */
> +pitch, src_bo, src_offset - src_x,
> I915_TILING_NONE,
> +pitch, dst_bo, dst_offset - dst_x,
> I915_TILING_NONE,
> +src_x, 0, /* src x/y */
> +dst_x, 0, /* dst x/y */
> size, 1, /* w, h */
> GL_COPY);
>if (!ok)
> --
> 2.3.5
>
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I had a patch which imposed these alignment restrictions in blitter.
But, it caused hangs in piglit run. I was missing the patch 1
of your series. I'm glad you fixed it.
Both patches are:
Reviewed-by: Anuj Phogat
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Re: [Mesa-dev] [PATCH 09/12] nir: Add a simple growing array data structure
On Wed, Apr 22, 2015 at 6:06 PM, Jason Ekstrand wrote:
> On Wed, Apr 22, 2015 at 3:03 PM, Connor Abbott wrote:
>> I think it would be better to call this "nir_vector" rather than
>> "nir_array," since this is essentially a poor man's version of
>> std::vector<>. Is this ok with you?
>
> I battled over that one for quite a while. In the end, I settled on
> nir_array because NIR is a compiler IR for vector architectures and I
> was concerned that a datatype called nir_vector that was not, in fact,
> a vector in the mathematical sense would be troublesome.
> --Jason
Ugh, you're right... I guess nir_array would lead to less confusion,
even if it's not quite the name that everyone else uses.
>
>> On Fri, Apr 10, 2015 at 8:48 PM, Jason Ekstrand wrote:
>>> ---
>>> src/glsl/nir/nir_array.h | 96
>>>
>>> 1 file changed, 96 insertions(+)
>>> create mode 100644 src/glsl/nir/nir_array.h
>>>
>>> diff --git a/src/glsl/nir/nir_array.h b/src/glsl/nir/nir_array.h
>>> new file mode 100644
>>> index 000..1db4e8c
>>> --- /dev/null
>>> +++ b/src/glsl/nir/nir_array.h
>>> @@ -0,0 +1,96 @@
>>> +/*
>>> + * Copyright © 2015 Intel Corporation
>>> + *
>>> + * Permission is hereby granted, free of charge, to any person obtaining a
>>> + * copy of this software and associated documentation files (the
>>> "Software"),
>>> + * to deal in the Software without restriction, including without
>>> limitation
>>> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>>> + * and/or sell copies of the Software, and to permit persons to whom the
>>> + * Software is furnished to do so, subject to the following conditions:
>>> + *
>>> + * The above copyright notice and this permission notice (including the
>>> next
>>> + * paragraph) shall be included in all copies or substantial portions of
>>> the
>>> + * Software.
>>> + *
>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
>>> OR
>>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
>>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
>>> OTHER
>>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
>>> DEALINGS
>>> + * IN THE SOFTWARE.
>>> + *
>>> + * Authors:
>>> + *Jason Ekstrand (ja...@jlekstrand.net)
>>> + *
>>> + */
>>> +
>>> +#pragma once
>>> +
>>> +#ifdef __cplusplus
>>> +extern "C" {
>>> +#endif
>>> +
>>> +typedef struct {
>>> + void *mem_ctx;
>>> + size_t size;
>>> + size_t alloc;
>>> + void *data;
>>> +} nir_array;
>>> +
>>> +static inline void
>>> +nir_array_init(nir_array *arr, void *mem_ctx)
>>> +{
>>> + arr->mem_ctx = mem_ctx;
>>> + arr->size = 0;
>>> + arr->alloc = 0;
>>> + arr->data = NULL;
>>> +}
>>> +
>>> +static inline void
>>> +nir_array_fini(nir_array *arr)
>>> +{
>>> + if (arr->mem_ctx)
>>> + ralloc_free(arr->data);
>>> + else
>>> + free(arr->data);
>>> +}
>>> +
>>> +#define NIR_ARRAY_INITIAL_SIZE 64
>>> +
>>> +/* Increments the size of the array by the given ammount and returns a
>>> + * pointer to the beginning of the newly added space.
>>> + */
>>> +static inline void *
>>> +nir_array_grow(nir_array *arr, size_t additional)
>>> +{
>>> + size_t new_size = arr->size + additional;
>>> + if (new_size > arr->alloc) {
>>> + if (arr->alloc == 0)
>>> + arr->alloc = NIR_ARRAY_INITIAL_SIZE;
>>> +
>>> + while (new_size > arr->alloc)
>>> + arr->alloc *= 2;
>>> +
>>> + if (arr->mem_ctx)
>>> + arr->data = reralloc_size(arr->mem_ctx, arr->data, arr->alloc);
>>> + else
>>> + arr->data = realloc(arr->data, arr->alloc);
>>> + }
>>> +
>>> + void *ptr = (void *)((char *)arr->data + arr->size);
>>> + arr->size = new_size;
>>> +
>>> + return ptr;
>>> +}
>>> +
>>> +#define nir_array_add(arr, type, elem) \
>>> + *(type *)nir_array_grow(arr, sizeof(type)) = (elem)
>>> +
>>> +#define nir_array_foreach(arr, type, elem) \
>>> + for (type *elem = (type *)(arr)->data; \
>>> +elem < (type *)((char *)(arr)->data + (arr)->size); elem++)
>>> +
>>> +#ifdef __cplusplus
>>> +} /* extern "C" */
>>> +#endif
>>> --
>>> 2.3.5
>>>
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Re: [Mesa-dev] [PATCH 06/12] nir/lower_vars_to_ssa: Pass around the nir_shader instead of a void mem_ctx
On Wed, Apr 22, 2015 at 3:09 PM, Connor Abbott wrote:
> On Fri, Apr 10, 2015 at 8:48 PM, Jason Ekstrand wrote:
>> ---
>> src/glsl/nir/nir_lower_vars_to_ssa.c | 28 ++--
>> 1 file changed, 14 insertions(+), 14 deletions(-)
>>
>> diff --git a/src/glsl/nir/nir_lower_vars_to_ssa.c
>> b/src/glsl/nir/nir_lower_vars_to_ssa.c
>> index 8b7261c..1afa9b7 100644
>> --- a/src/glsl/nir/nir_lower_vars_to_ssa.c
>> +++ b/src/glsl/nir/nir_lower_vars_to_ssa.c
>> @@ -55,7 +55,7 @@ struct deref_node {
>> };
>>
>> struct lower_variables_state {
>> - void *mem_ctx;
>> + nir_shader *shader;
>> void *dead_ctx;
>> nir_function_impl *impl;
>>
>> @@ -112,12 +112,12 @@ type_get_length(const struct glsl_type *type)
>>
>> static struct deref_node *
>> deref_node_create(struct deref_node *parent,
>> - const struct glsl_type *type, void *mem_ctx)
>> + const struct glsl_type *type, void *shader)
>
> Any particular reason why you didn't change the type here too? It
> seems a little silly to have a parameter called 'shader' that's a void
> *.
I don't think so. It was probably just a refactor fail.
--Jason
>> {
>> size_t size = sizeof(struct deref_node) +
>> type_get_length(type) * sizeof(struct deref_node *);
>>
>> - struct deref_node *node = rzalloc_size(mem_ctx, size);
>> + struct deref_node *node = rzalloc_size(shader, size);
>> node->type = type;
>> node->parent = parent;
>> node->deref = NULL;
>> @@ -469,7 +469,7 @@ lower_copies_to_load_store(struct deref_node *node,
>> set_foreach(node->copies, copy_entry) {
>>nir_intrinsic_instr *copy = (void *)copy_entry->key;
>>
>> - nir_lower_var_copy_instr(copy, state->mem_ctx);
>> + nir_lower_var_copy_instr(copy, state->shader);
>>
>>for (unsigned i = 0; i < 2; ++i) {
>> struct deref_node *arg_node =
>> @@ -527,7 +527,7 @@ get_const_initializer_load(const nir_deref_var *deref,
>> }
>>
>> nir_load_const_instr *load =
>> - nir_load_const_instr_create(state->mem_ctx,
>> + nir_load_const_instr_create(state->shader,
>>glsl_get_vector_elements(tail->type));
>>
>> matrix_offset *= load->def.num_components;
>> @@ -618,7 +618,7 @@ get_ssa_def_for_block(struct deref_node *node, nir_block
>> *block,
>> * given block. This means that we need to add an undef and use that.
>> */
>> nir_ssa_undef_instr *undef =
>> - nir_ssa_undef_instr_create(state->mem_ctx,
>> + nir_ssa_undef_instr_create(state->shader,
>> glsl_get_vector_elements(node->type));
>> nir_instr_insert_before_cf_list(&state->impl->body, &undef->instr);
>> def_stack_push(node, &undef->def, state);
>> @@ -698,7 +698,7 @@ rename_variables_block(nir_block *block, struct
>> lower_variables_state *state)
>> * should result in an undefined value.
>> */
>> nir_ssa_undef_instr *undef =
>> - nir_ssa_undef_instr_create(state->mem_ctx,
>> + nir_ssa_undef_instr_create(state->shader,
>> intrin->num_components);
>>
>> nir_instr_insert_before(&intrin->instr, &undef->instr);
>> @@ -706,14 +706,14 @@ rename_variables_block(nir_block *block, struct
>> lower_variables_state *state)
>>
>> nir_ssa_def_rewrite_uses(&intrin->dest.ssa,
>> nir_src_for_ssa(&undef->def),
>> -state->mem_ctx);
>> +state->shader);
>> continue;
>> }
>>
>> if (!node->lower_to_ssa)
>> continue;
>>
>> -nir_alu_instr *mov = nir_alu_instr_create(state->mem_ctx,
>> +nir_alu_instr *mov = nir_alu_instr_create(state->shader,
>>nir_op_imov);
>> mov->src[0].src.is_ssa = true;
>> mov->src[0].src.ssa = get_ssa_def_for_block(node, block, state);
>> @@ -731,7 +731,7 @@ rename_variables_block(nir_block *block, struct
>> lower_variables_state *state)
>>
>> nir_ssa_def_rewrite_uses(&intrin->dest.ssa,
>> nir_src_for_ssa(&mov->dest.dest.ssa),
>> - state->mem_ctx);
>> + state->shader);
>> break;
>> }
>>
>> @@ -754,7 +754,7 @@ rename_variables_block(nir_block *block, struct
>> lower_variables_state *state)
>>
>> assert(intrin->src[0].is_ssa);
>>
>> -nir_alu_instr *mov = nir_alu_instr_create(state->mem_ctx,
>> +nir_alu_instr *mov = nir_alu_instr_create(state->shader,
>>nir_op_imov);
>> mov->src[0].src.is_ssa = true;
>> mov->src[0].src.s
[Mesa-dev] [Bug 66346] shader_query.cpp:49: error: invalid conversion from 'void*' to 'GLuint'
https://bugs.freedesktop.org/show_bug.cgi?id=66346 --- Comment #13 from Julien Isorce --- Problem still exists: CXX main/shader_query.lo main/shader_query.cpp:71:7: error: no matching function for call to '_mesa_lookup_shader_program_err' _mesa_lookup_shader_program_err(ctx, program, "glBindAttribLocation"); ^~~ ../../src/mesa/main/shaderobj.h:89:1: note: candidate function not viable: cannot convert argument of incomplete type 'GLhandleARB' (aka 'void *') to 'GLuint' (aka 'unsigned int') _mesa_lookup_shader_program_err(struct gl_context *ctx, GLuint name, ^ main/shader_query.cpp:139:13: error: no matching function for call to '_mesa_lookup_shader_program_err' shProg = _mesa_lookup_shader_program_err(ctx, program, "glGetActiveAttrib"); ^~~ ../../src/mesa/main/shaderobj.h:89:1: note: candidate function not viable: cannot convert argument of incomplete type 'GLhandleARB' (aka 'void *') to 'GLuint' (aka 'unsigned int') _mesa_lookup_shader_program_err(struct gl_context *ctx, GLuint name, ^ main/shader_query.cpp:253:7: error: no matching function for call to '_mesa_lookup_shader_program_err' _mesa_lookup_shader_program_err(ctx, program, "glGetAttribLocation"); ^~~ ../../src/mesa/main/shaderobj.h:89:1: note: candidate function not viable: cannot convert argument of incomplete type 'GLhandleARB' (aka 'void *') to 'GLuint' (aka 'unsigned int') _mesa_lookup_shader_program_err(struct gl_context *ctx, GLuint name, ^ 3 errors generated. gcc --version Configured with: --prefix=/Library/Developer/CommandLineTools/usr --with-gxx-include-dir=/usr/include/c++/4.2.1 Apple LLVM version 6.1.0 (clang-602.0.49) (based on LLVM 3.6.0svn) Target: x86_64-apple-darwin14.3.0 Thread model: posix --- OSX 10.10.3 / Dev Command Line Tools v6.3 -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 66346] shader_query.cpp:49: error: invalid conversion from 'void*' to 'GLuint'
https://bugs.freedesktop.org/show_bug.cgi?id=66346 Julien Isorce changed: What|Removed |Added Attachment #81814|0 |1 is obsolete|| --- Comment #14 from Julien Isorce --- Created attachment 115279 --> https://bugs.freedesktop.org/attachment.cgi?id=115279&action=edit use a function to convert from GLhandleARB to GLuint Brian's patch rebased. Works for me. -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 66346] shader_query.cpp:49: error: invalid conversion from 'void*' to 'GLuint'
https://bugs.freedesktop.org/show_bug.cgi?id=66346 --- Comment #15 from Julien Isorce --- Created attachment 115280 --> https://bugs.freedesktop.org/attachment.cgi?id=115280&action=edit shader_query: convert GLhandleARB to uintptr_t before troncating to GLuint Other suggestion. -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 90147] swrast: build error undeclared _SC_PHYS_PAGES on osx
https://bugs.freedesktop.org/show_bug.cgi?id=90147 Bug ID: 90147 Summary: swrast: build error undeclared _SC_PHYS_PAGES on osx Product: Mesa Version: unspecified Hardware: Other OS: Mac OS X (All) Status: NEW Severity: normal Priority: medium Component: Mesa core Assignee: mesa-dev@lists.freedesktop.org Reporter: julien.iso...@gmail.com QA Contact: mesa-dev@lists.freedesktop.org swrast.c:141:48: error: use of undeclared identifier '_SC_PHYS_PAGES' const long system_memory_pages = sysconf(_SC_PHYS_PAGES); OSX 10.10.3 gcc --version Configured with: --prefix=/Library/Developer/CommandLineTools/usr --with-gxx-include-dir=/usr/include/c++/4.2.1 Apple LLVM version 6.1.0 (clang-602.0.49) (based on LLVM 3.6.0svn) Target: x86_64-apple-darwin14.3.0 Thread model: posix -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 90147] swrast: build error undeclared _SC_PHYS_PAGES on osx
https://bugs.freedesktop.org/show_bug.cgi?id=90147 --- Comment #1 from Julien Isorce --- Created attachment 115281 --> https://bugs.freedesktop.org/attachment.cgi?id=115281&action=edit swrast: can retrieve system memory on osx Based on https://chromium.googlesource.com/chromium/src/base/+/0fe07e993bde909d49fe4e2aac846218daa65809/sys_info_posix.cc -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 00/12] nir: Various indirect variable use fixes
Except for the one minor comment on patch 6, the series (including patches 13 and 14) is Reviewed-by: Connor Abbott On Fri, Apr 10, 2015 at 8:48 PM, Jason Ekstrand wrote: > Right now, most of the code to handle indirect dereferences of variables is > dead. However, I have a patch series (which I haven't cleaned up yet) that > makes it very much alive for the i965 backend. While working on this, I > found a number of bugs in NIR's handling of indirect references. All in > all, it's not nearly as bad as it could have been given that it hasn't ever > been tested. > > While this series does not make the code alive in i965, it does fix all but > one of the NIR bugs I found by turning it on in i965. Together with my > series to enable actual indirects in the i965 scalar backend, there is now > only one piglit regressions on HSW. Hopefully, I'll send a patch 13/12 on > Monday with the fix. This series, on top of my WIP i965 patches, can be > found in my review/nir-indirect-fixes branch on freedesktop.org: > > http://cgit.freedesktop.org/~jekstrand/mesa/log/?h=review/nir-indirect-fixes > > Jason Ekstrand (12): > nir/lower_vars_to_ssa: Actually look for indirects when determining > aliasing > nir: Refactor tex_instr_dest_size to use a switch statement > nir/tex: Use the correct return size for query_levels and lod > nir/print: Print the closing paren on load_const instructions > i965/nir: Use the correct offsets when handling register indirects > nir/lower_vars_to_ssa: Pass around the nir_shader instead of a void > mem_ctx > nir: Move get_const_initializer_load from vars_to_ssa to NIR core > nir/types: Make glsl_get_length smarter > nir: Add a simple growing array data structure > nir/locals_to_regs: Pass around the nir_shader rather than a void * > mem_ctx > nir/locals_to_regs: Initialize registers with constant initializers > nir/locals_to_regs: Hanadle indirect accesses of length-1 arrays > > src/glsl/nir/nir.c | 60 + > src/glsl/nir/nir.h | 17 +++- > src/glsl/nir/nir_array.h | 96 > src/glsl/nir/nir_lower_locals_to_regs.c | 148 > ++- > src/glsl/nir/nir_lower_var_copies.c | 24 + > src/glsl/nir/nir_lower_vars_to_ssa.c | 120 + > src/glsl/nir/nir_print.c | 2 + > src/glsl/nir/nir_types.cpp | 16 +++- > src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 54 +-- > 9 files changed, 363 insertions(+), 174 deletions(-) > create mode 100644 src/glsl/nir/nir_array.h > > -- > 2.3.5 > > ___ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 00/12] nir: Various indirect variable use fixes
On Wed, Apr 22, 2015 at 3:34 PM, Connor Abbott wrote: > Except for the one minor comment on patch 6 Fixed locally. > , the series (including > patches 13 and 14) is > > Reviewed-by: Connor Abbott Thanks! > On Fri, Apr 10, 2015 at 8:48 PM, Jason Ekstrand wrote: >> Right now, most of the code to handle indirect dereferences of variables is >> dead. However, I have a patch series (which I haven't cleaned up yet) that >> makes it very much alive for the i965 backend. While working on this, I >> found a number of bugs in NIR's handling of indirect references. All in >> all, it's not nearly as bad as it could have been given that it hasn't ever >> been tested. >> >> While this series does not make the code alive in i965, it does fix all but >> one of the NIR bugs I found by turning it on in i965. Together with my >> series to enable actual indirects in the i965 scalar backend, there is now >> only one piglit regressions on HSW. Hopefully, I'll send a patch 13/12 on >> Monday with the fix. This series, on top of my WIP i965 patches, can be >> found in my review/nir-indirect-fixes branch on freedesktop.org: >> >> http://cgit.freedesktop.org/~jekstrand/mesa/log/?h=review/nir-indirect-fixes >> >> Jason Ekstrand (12): >> nir/lower_vars_to_ssa: Actually look for indirects when determining >> aliasing >> nir: Refactor tex_instr_dest_size to use a switch statement >> nir/tex: Use the correct return size for query_levels and lod >> nir/print: Print the closing paren on load_const instructions >> i965/nir: Use the correct offsets when handling register indirects >> nir/lower_vars_to_ssa: Pass around the nir_shader instead of a void >> mem_ctx >> nir: Move get_const_initializer_load from vars_to_ssa to NIR core >> nir/types: Make glsl_get_length smarter >> nir: Add a simple growing array data structure >> nir/locals_to_regs: Pass around the nir_shader rather than a void * >> mem_ctx >> nir/locals_to_regs: Initialize registers with constant initializers >> nir/locals_to_regs: Hanadle indirect accesses of length-1 arrays >> >> src/glsl/nir/nir.c | 60 + >> src/glsl/nir/nir.h | 17 +++- >> src/glsl/nir/nir_array.h | 96 >> src/glsl/nir/nir_lower_locals_to_regs.c | 148 >> ++- >> src/glsl/nir/nir_lower_var_copies.c | 24 + >> src/glsl/nir/nir_lower_vars_to_ssa.c | 120 + >> src/glsl/nir/nir_print.c | 2 + >> src/glsl/nir/nir_types.cpp | 16 +++- >> src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 54 +-- >> 9 files changed, 363 insertions(+), 174 deletions(-) >> create mode 100644 src/glsl/nir/nir_array.h >> >> -- >> 2.3.5 >> >> ___ >> mesa-dev mailing list >> mesa-dev@lists.freedesktop.org >> http://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] draw: fix prim ids when there's no gs
From: Roland Scheidegger
We were resetting the prim id count for each run of the prim assembler,
hence this only worked when the draw calls were very small (the exact limit
depending on the vertex size), since larger draw calls get split up.
So, do the same as we do already if there's a gs, reset it to zero explicitly
for every new instance (this possibly could use the same variable but that
isn't doable without some heavy refactoring and I'm not sure it makes sense).
This fixes https://bugs.freedesktop.org/show_bug.cgi?id=90130.
---
src/gallium/auxiliary/draw/draw_context.c| 1 +
src/gallium/auxiliary/draw/draw_prim_assembler.c | 13 +++--
src/gallium/auxiliary/draw/draw_prim_assembler.h | 3 +++
3 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/src/gallium/auxiliary/draw/draw_context.c
b/src/gallium/auxiliary/draw/draw_context.c
index 04cf5b7..ee009c1 100644
--- a/src/gallium/auxiliary/draw/draw_context.c
+++ b/src/gallium/auxiliary/draw/draw_context.c
@@ -182,6 +182,7 @@ boolean draw_init(struct draw_context *draw)
void draw_new_instance(struct draw_context *draw)
{
draw_geometry_shader_new_instance(draw->gs.geometry_shader);
+ draw_prim_assembler_new_instance(draw->ia);
}
diff --git a/src/gallium/auxiliary/draw/draw_prim_assembler.c
b/src/gallium/auxiliary/draw/draw_prim_assembler.c
index 776c172..7ff705a 100644
--- a/src/gallium/auxiliary/draw/draw_prim_assembler.c
+++ b/src/gallium/auxiliary/draw/draw_prim_assembler.c
@@ -189,7 +189,6 @@ draw_prim_assembler_prepare_outputs(struct draw_assembler
*ia)
} else {
ia->primid_slot = -1;
}
- ia->primid = 0;
}
@@ -233,7 +232,6 @@ draw_prim_assembler_run(struct draw_context *draw,
asmblr->input_prims = input_prims;
asmblr->input_verts = input_verts;
asmblr->needs_primid = needs_primid(asmblr->draw);
- asmblr->primid = 0;
asmblr->num_prims = 0;
output_prims->linear = TRUE;
@@ -284,3 +282,14 @@ draw_prim_assembler_destroy(struct draw_assembler *ia)
{
FREE(ia);
}
+
+
+/*
+ * Called at the very begin of the draw call with a new instance
+ * Used to reset state that should persist between primitive restart.
+ */
+void
+draw_prim_assembler_new_instance(struct draw_assembler *asmblr)
+{
+ asmblr->primid = 0;
+}
diff --git a/src/gallium/auxiliary/draw/draw_prim_assembler.h
b/src/gallium/auxiliary/draw/draw_prim_assembler.h
index 5ba715b..5ee7317 100644
--- a/src/gallium/auxiliary/draw/draw_prim_assembler.h
+++ b/src/gallium/auxiliary/draw/draw_prim_assembler.h
@@ -70,5 +70,8 @@ draw_prim_assembler_run(struct draw_context *draw,
void
draw_prim_assembler_prepare_outputs(struct draw_assembler *ia);
+void
+draw_prim_assembler_new_instance(struct draw_assembler *ia);
+
#endif
--
1.9.1
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Re: [Mesa-dev] [Mesa-stable] [PATCH 1/2] i965: Make intel_emit_linear_blit handle Gen8+ alignment restrictions.
On Wednesday, April 22, 2015 03:15:05 PM Anuj Phogat wrote:
> On Tue, Apr 21, 2015 at 10:13 PM, Kenneth Graunke
> wrote:
> > The BLT engine on Gen8+ requires linear surfaces to be cacheline
> > aligned. This restriction was added as part of converting the BLT to
> > use 48-bit addressing.
> >
> > intel_emit_linear_blit needs to handle blits that are not cacheline
> > aligned, as we use it for arbitrary glBufferSubData calls and subrange
> > mappings.
> >
> > Since intel_emit_linear_blit uses 1 byte per pixel, we can use the src/dst
> > pixel X offset field to represent the unaligned portion, and subtract
> > that from the address so it's cacheline aligned.
> >
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88521
> > Signed-off-by: Kenneth Graunke
> > Cc: mesa-sta...@lists.freedesktop.org
> > ---
> > src/mesa/drivers/dri/i965/intel_blit.c | 22 ++
> > 1 file changed, 14 insertions(+), 8 deletions(-)
> >
> > diff --git a/src/mesa/drivers/dri/i965/intel_blit.c
> > b/src/mesa/drivers/dri/i965/intel_blit.c
> > index 4993f60..98d414c 100644
> > --- a/src/mesa/drivers/dri/i965/intel_blit.c
> > +++ b/src/mesa/drivers/dri/i965/intel_blit.c
> > @@ -524,6 +524,7 @@ intel_emit_linear_blit(struct brw_context *brw,
> > {
> > struct gl_context *ctx = &brw->ctx;
> > GLuint pitch, height;
> > + int16_t src_x, dst_x;
> > bool ok;
> >
> > /* The pitch given to the GPU must be DWORD aligned, and
> > @@ -532,11 +533,13 @@ intel_emit_linear_blit(struct brw_context *brw,
> > */
> > pitch = ROUND_DOWN_TO(MIN2(size, (1 << 15) - 1), 4);
> > height = (pitch == 0) ? 1 : size / pitch;
> > + src_x = src_offset % 64;
> > + dst_x = dst_offset % 64;
> > ok = intelEmitCopyBlit(brw, 1,
> > - pitch, src_bo, src_offset, I915_TILING_NONE,
> > - pitch, dst_bo, dst_offset, I915_TILING_NONE,
> > - 0, 0, /* src x/y */
> > - 0, 0, /* dst x/y */
> > + pitch, src_bo, src_offset - src_x,
> > I915_TILING_NONE,
> > + pitch, dst_bo, dst_offset - dst_x,
> > I915_TILING_NONE,
> > + src_x, 0, /* src x/y */
> > + dst_x, 0, /* dst x/y */
> > pitch, height, /* w, h */
> > GL_COPY);
> > if (!ok)
> > @@ -544,15 +547,18 @@ intel_emit_linear_blit(struct brw_context *brw,
> >
> > src_offset += pitch * height;
> > dst_offset += pitch * height;
> > + src_x = src_offset % 64;
> > + dst_x = dst_offset % 64;
> > size -= pitch * height;
> > assert (size < (1 << 15));
> > pitch = ALIGN(size, 4);
> > +
> > if (size != 0) {
> >ok = intelEmitCopyBlit(brw, 1,
> > -pitch, src_bo, src_offset, I915_TILING_NONE,
> > -pitch, dst_bo, dst_offset, I915_TILING_NONE,
> > -0, 0, /* src x/y */
> > -0, 0, /* dst x/y */
> > +pitch, src_bo, src_offset - src_x,
> > I915_TILING_NONE,
> > +pitch, dst_bo, dst_offset - dst_x,
> > I915_TILING_NONE,
> > +src_x, 0, /* src x/y */
> > +dst_x, 0, /* dst x/y */
> > size, 1, /* w, h */
> > GL_COPY);
> >if (!ok)
> > --
> > 2.3.5
> >
> > ___
> > mesa-stable mailing list
> > mesa-sta...@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/mesa-stable
>
> I had a patch which imposed these alignment restrictions in blitter.
> But, it caused hangs in piglit run. I was missing the patch 1
> of your series. I'm glad you fixed it.
>
> Both patches are:
> Reviewed-by: Anuj Phogat
Ah, right - intel_emit_linear_blit isn't allowed to fail, so we have to
make it work somehow. Hence, patch 1 :)
Thanks, Anuj!
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Re: [Mesa-dev] [PATCH] draw: fix prim ids when there's no gs
On Wed, Apr 22, 2015 at 4:06 PM, wrote: > From: Roland Scheidegger > > We were resetting the prim id count for each run of the prim assembler, > hence this only worked when the draw calls were very small (the exact limit > depending on the vertex size), since larger draw calls get split up. > So, do the same as we do already if there's a gs, reset it to zero explicitly > for every new instance (this possibly could use the same variable but that > isn't doable without some heavy refactoring and I'm not sure it makes sense). > > This fixes https://bugs.freedesktop.org/show_bug.cgi?id=90130. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90130 so that the bin/bugzilla_mesa.sh script can find it. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] i965: Label the repclear shader "repclear" rather than "meta clear".
Color clears can be performed via two separate shaders - one is the generic "meta clear" shader (in meta.c); the other is the i965 specific "repclear" shader (in brw_meta_fast_clear.c). Giving them separate names makes them distinguishable when reading INTEL_DEBUG=shader_time output. Signed-off-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_meta_fast_clear.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c index 06916e2..498ea37 100644 --- a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c +++ b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c @@ -128,7 +128,7 @@ brw_bind_rep_write_shader(struct brw_context *brw, float *color) _mesa_AttachShader(clear->shader_prog, vs); _mesa_DeleteShader(vs); _mesa_BindAttribLocation(clear->shader_prog, 0, "position"); - _mesa_ObjectLabel(GL_PROGRAM, clear->shader_prog, -1, "meta clear"); + _mesa_ObjectLabel(GL_PROGRAM, clear->shader_prog, -1, "repclear"); _mesa_LinkProgram(clear->shader_prog); clear->color_location = -- 2.3.5 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] i965: Label the repclear shader "repclear" rather than "meta clear".
Maybe meta repclear? Either way, Reviewed-by: Jason Ekstrand On Wed, Apr 22, 2015 at 5:46 PM, Kenneth Graunke wrote: > Color clears can be performed via two separate shaders - one is the > generic "meta clear" shader (in meta.c); the other is the i965 specific > "repclear" shader (in brw_meta_fast_clear.c). > > Giving them separate names makes them distinguishable when reading > INTEL_DEBUG=shader_time output. > > Signed-off-by: Kenneth Graunke > --- > src/mesa/drivers/dri/i965/brw_meta_fast_clear.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c > b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c > index 06916e2..498ea37 100644 > --- a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c > +++ b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c > @@ -128,7 +128,7 @@ brw_bind_rep_write_shader(struct brw_context *brw, float > *color) > _mesa_AttachShader(clear->shader_prog, vs); > _mesa_DeleteShader(vs); > _mesa_BindAttribLocation(clear->shader_prog, 0, "position"); > - _mesa_ObjectLabel(GL_PROGRAM, clear->shader_prog, -1, "meta clear"); > + _mesa_ObjectLabel(GL_PROGRAM, clear->shader_prog, -1, "repclear"); > _mesa_LinkProgram(clear->shader_prog); > > clear->color_location = > -- > 2.3.5 > > ___ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] draw: fix prim ids when there's no gs
Am 23.04.2015 um 02:35 schrieb Matt Turner: > On Wed, Apr 22, 2015 at 4:06 PM, wrote: >> From: Roland Scheidegger >> >> We were resetting the prim id count for each run of the prim assembler, >> hence this only worked when the draw calls were very small (the exact limit >> depending on the vertex size), since larger draw calls get split up. >> So, do the same as we do already if there's a gs, reset it to zero explicitly >> for every new instance (this possibly could use the same variable but that >> isn't doable without some heavy refactoring and I'm not sure it makes sense). >> >> This fixes https://bugs.freedesktop.org/show_bug.cgi?id=90130. > >Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90130 > > so that the bin/bugzilla_mesa.sh script can find it. I don't think this really matters, but it's probably a good idea anyway. DRYRUN=yes ./bin/bugzilla_mesa.sh HEAD~1..HEAD https://bugs.freedesktop.org/show_bug.cgi?id=90130 I probably should add a mesa-stable cc too... Roland ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
