Re: [llvm-commits] [llvm] r45620 - /llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
On Jan 4, 2008, at 11:21 PM, Bill Wendling wrote: > On Jan 4, 2008, at 11:02 PM, Chris Lattner wrote: >> You aren't looking for loads *from the global*, you're looking for >> loads from the *stub for the global*, which are always invariant. >> You >> just need to know whether the load is from a global or from its stub. >> > Okay. I just don't know how to check that it's a load from a *stub* > for the global. :-) I am not 100% sure, but I think that X86Subtarget::GVRequiresExtraLoad is the place to start looking. -Chris ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] [llvm] r45623 - /llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
Hrm. ReMat of load from argument area is being handled as a special case in LiveIntervals::isReMaterializable(). Having isReallyTrivallyReMaterializable() returns true for it shouldn't make any difference. I'll look at this. Evan On Jan 4, 2008, at 10:10 PM, Chris Lattner wrote: > Author: lattner > Date: Sat Jan 5 00:10:42 2008 > New Revision: 45623 > > URL: http://llvm.org/viewvc/llvm-project?rev=45623&view=rev > Log: > enable sinking and licm of loads from the argument area. I'd like > to enable this > for remat, but can't due to an RA bug. > > Modified: > llvm/trunk/lib/Target/X86/X86InstrInfo.cpp > > Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/ > X86InstrInfo.cpp?rev=45623&r1=45622&r2=45623&view=diff > > == > > --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original) > +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Sat Jan 5 00:10:42 > 2008 > @@ -141,6 +141,18 @@ > MI->getOperand(2).getImm() == 1 && > MI->getOperand(3).getReg() == 0) >return true; > + > +// If this is a load from a fixed argument slot, we know the > value is > +// invariant across the whole function, because we don't > redefine argument > +// values. > +#if 0 > +// FIXME: This is disabled due to a remat bug. rdar://5671644 > +MachineFunction *MF = MI->getParent()->getParent(); > +if (MI->getOperand(1).isFI() && > +MF->getFrameInfo()->isFixedObjectIndex(MI->getOperand > (1).getIndex())) > + return true; > +#endif > + > return false; >} >// All other instructions marked M_REMATERIALIZABLE are always > trivially > @@ -188,6 +200,15 @@ > MI->getOperand(2).getImm() == 1 && > MI->getOperand(3).getReg() == 0) >return true; > + > +// If this is a load from a fixed argument slot, we know the > value is > +// invariant across the whole function, because we don't > redefine argument > +// values. > +MachineFunction *MF = MI->getParent()->getParent(); > +if (MI->getOperand(1).isFI() && > +MF->getFrameInfo()->isFixedObjectIndex(MI->getOperand > (1).getIndex())) > + return true; > + > return false; >} > > > > ___ > llvm-commits mailing list > llvm-commits@cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] [llvm] r45620 - /llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
On Jan 5, 2008, at 12:28 AM, Chris Lattner wrote: > > On Jan 4, 2008, at 11:21 PM, Bill Wendling wrote: > >> On Jan 4, 2008, at 11:02 PM, Chris Lattner wrote: >>> You aren't looking for loads *from the global*, you're looking for >>> loads from the *stub for the global*, which are always invariant. >>> You >>> just need to know whether the load is from a global or from its >>> stub. >>> >> Okay. I just don't know how to check that it's a load from a *stub* >> for the global. :-) > > I am not 100% sure, but I think that X86Subtarget::GVRequiresExtraLoad > is the place to start looking. Right. If it's a load from GV and GVRequiresExtraLoad() returns true then it's a load from a stub. Here is something to consider for further enhancement. There are potentially other GV loads which can be side effect free though. As the comment says, if the value in the GV isn't redefined (in the loop), then it can be moved. Should there be some kind of callback function provided by caller of isReallySideEffectFree() that checks if a register or a GV operand is considered side effect free? In the case of LICM, if a register or GV operand is considered a loop invariant, then the instruction is really side effect free. In the case of remat, if an operand is "available", then it's side effect free, etc. etc. BTW, what do we do about volatile loads? I don't think the property is transferred to target instructions. Or perhaps volatile property should be on the location (GV) instead of the instruction? Evan > > -Chris > ___ > llvm-commits mailing list > llvm-commits@cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] [llvm] r45605 - in /llvm/trunk/lib/Target/X86: X86ATTAsmPrinter.cpp X86CodeEmitter.cpp X86ISelDAGToDAG.cpp X86InstrInfo.td X86MachineFunctionInfo.h
Cool!
Evan
On Jan 4, 2008, at 5:04 PM, Chris Lattner wrote:
> On Jan 4, 2008, at 4:41 PM, Evan Cheng wrote:
>> Author: evancheng
>> Date: Fri Jan 4 18:41:47 2008
>> New Revision: 45605
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=45605&view=rev
>> Log:
>> Combine MovePCtoStack + POP32r into one instruction MOVPC32r so it
>> can be moved if needed.
>
> Nice evan! With this, sinking is now able to compile code like this:
>
> int G;
> int test(int X, int Y) {
>if (X)
> return G+Y;
>return 0;
> }
>
> into:
>
> _test:
> cmpl$0, 4(%esp)
> je LBB2_2 # UnifiedReturnBlock
> LBB2_1: # cond_true
> call"L2$pb"
> "L2$pb":
> popl%ecx
> movl8(%esp), %eax
> movlL_G$non_lazy_ptr-"L2$pb"(%ecx), %ecx
> addl(%ecx), %eax
> ret
> LBB2_2: # UnifiedReturnBlock
> xorl%eax, %eax
> ret
>
> instead of:
>
> _test:
> call"L2$pb"
> "L2$pb":
> popl%ecx
> cmpl$0, 4(%esp)
> movl8(%esp), %eax
> je LBB2_2 # UnifiedReturnBlock
> LBB2_1: # cond_true
> movlL_G$non_lazy_ptr-"L2$pb"(%ecx), %ecx
> addl(%ecx), %eax
> ret
> LBB2_2: # UnifiedReturnBlock
> xorl%eax, %eax
> ret
>
>
> -Chris
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Re: [llvm-commits] [llvm] r45620 - /llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
On Jan 5, 2008, at 12:53 AM, Evan Cheng wrote: > > On Jan 5, 2008, at 12:28 AM, Chris Lattner wrote: > >> >> On Jan 4, 2008, at 11:21 PM, Bill Wendling wrote: >> >>> On Jan 4, 2008, at 11:02 PM, Chris Lattner wrote: You aren't looking for loads *from the global*, you're looking for loads from the *stub for the global*, which are always invariant. You just need to know whether the load is from a global or from its stub. >>> Okay. I just don't know how to check that it's a load from a *stub* >>> for the global. :-) >> >> I am not 100% sure, but I think that >> X86Subtarget::GVRequiresExtraLoad >> is the place to start looking. > > Right. If it's a load from GV and GVRequiresExtraLoad() returns true > then it's a load from a stub. > > Here is something to consider for further enhancement. There are > potentially other GV loads which can be side effect free though. As > the comment says, if the value in the GV isn't redefined (in the > loop), then it can be moved. Should there be some kind of callback > function provided by caller of isReallySideEffectFree() that checks > if a register or a GV operand is considered side effect free? In the > case of LICM, if a register or GV operand is considered a loop > invariant, then the instruction is really side effect free. In the > case of remat, if an operand is "available", then it's side effect > free, etc. etc. Alternatively, the caller should pass a vector operands that require checking in addition to the MI in question. Evan > > BTW, what do we do about volatile loads? I don't think the property > is transferred to target instructions. Or perhaps volatile property > should be on the location (GV) instead of the instruction? > > Evan > > >> >> -Chris >> ___ >> llvm-commits mailing list >> llvm-commits@cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > ___ > llvm-commits mailing list > llvm-commits@cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r45626 - /llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
Author: void
Date: Sat Jan 5 03:18:04 2008
New Revision: 45626
URL: http://llvm.org/viewvc/llvm-project?rev=45626&view=rev
Log:
Chris and Evan noticed that this check was compleatly fubared. I was
checking that there was a from a global instead of a load from the stub
for a global, which is the one that's safe to hoist.
Consider this program:
volatile char G[100];
int B(char *F, int N) {
for (; N > 0; --N)
F[N] = G[N];
}
In static mode, we shouldn't be hoisting the load from G:
$ llc -relocation-model=static -o - a.bc -march=x86 -machine-licm
LBB1_1: # bb.preheader
leal-1(%eax), %edx
testl %edx, %edx
movl$1, %edx
cmovns %eax, %edx
xorl%esi, %esi
LBB1_2: # bb
movb_G(%eax), %bl
movb%bl, (%ecx,%eax)
Modified:
llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=45626&r1=45625&r2=45626&view=diff
==
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Sat Jan 5 03:18:04 2008
@@ -171,12 +171,15 @@
case X86::MOV32rm:
if (MI->getOperand(1).isRegister()) {
unsigned Reg = MI->getOperand(1).getReg();
+ const X86Subtarget &ST = TM.getSubtarget();
// Loads from global addresses which aren't redefined in the function are
// side effect free.
if (Reg != 0 && MRegisterInfo::isVirtualRegister(Reg) &&
MI->getOperand(2).isImm() && MI->getOperand(3).isReg() &&
- MI->getOperand(4).isGlobal() && MI->getOperand(2).getImm() == 1 &&
+ MI->getOperand(4).isGlobal() &&
+ ST.GVRequiresExtraLoad(MI->getOperand(4).getGlobal(), TM, false) &&
+ MI->getOperand(2).getImm() == 1 &&
MI->getOperand(3).getReg() == 0)
return true;
}
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Re: [llvm-commits] [llvm] r45620 - /llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
On Jan 5, 2008, at 12:53 AM, Evan Cheng wrote:
> Right. If it's a load from GV and GVRequiresExtraLoad() returns true
> then it's a load from a stub.
>
Okay. Once I did the check, it now seems to treat the example program:
volatile char G[100];
int B(char *F, int N) {
for (; N > 0; --N)
F[N] = G[N];
}
correctly for static compilation. Thanks Evan & Chris. :-)
> Here is something to consider for further enhancement. There are
> potentially other GV loads which can be side effect free though. As
> the comment says, if the value in the GV isn't redefined (in the
> loop), then it can be moved. Should there be some kind of callback
> function provided by caller of isReallySideEffectFree() that checks
> if a register or a GV operand is considered side effect free? In the
> case of LICM, if a register or GV operand is considered a loop
> invariant, then the instruction is really side effect free. In the
> case of remat, if an operand is "available", then it's side effect
> free, etc. etc.
>
> BTW, what do we do about volatile loads? I don't think the property
> is transferred to target instructions. Or perhaps volatile property
> should be on the location (GV) instead of the instruction?
>
-bw
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Re: [llvm-commits] [llvm] r45626 - /llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
On Jan 5, 2008, at 1:18 AM, Bill Wendling <[EMAIL PROTECTED]> wrote:
> Author: void
> Date: Sat Jan 5 03:18:04 2008
> New Revision: 45626
>
> URL: http://llvm.org/viewvc/llvm-project?rev=45626&view=rev
> Log:
> Chris and Evan noticed that this check was compleatly fubared. I was
> checking that there was a from a global instead of a load from the
> stub
> for a global, which is the one that's safe to hoist.
>
> Consider this program:
>
> volatile char G[100];
> int B(char *F, int N) {
> for (; N > 0; --N)
>F[N] = G[N];
> }
>
> In static mode, we shouldn't be hoisting the load from G:
>
> $ llc -relocation-model=static -o - a.bc -march=x86 -machine-licm
>
> LBB1_1: # bb.preheader
>leal-1(%eax), %edx
>testl %edx, %edx
>movl$1, %edx
>cmovns %eax, %edx
>xorl%esi, %esi
> LBB1_2: # bb
>movb_G(%eax), %bl
>movb%bl, (%ecx,%eax)
>
>
> Modified:
>llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=45626&r1=45625&r2=45626&view=diff
>
> ===
> ===
> ===
> =
> --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Sat Jan 5 03:18:04
> 2008
> @@ -171,12 +171,15 @@
> case X86::MOV32rm:
> if (MI->getOperand(1).isRegister()) {
> unsigned Reg = MI->getOperand(1).getReg();
> + const X86Subtarget &ST = TM.getSubtarget();
>
> // Loads from global addresses which aren't redefined in the
> function are
> // side effect free.
> if (Reg != 0 &&
I assume caller ensure this operant is side effect free? Can you
change this to accept a list of operands which should be checked? For
LICM, that means non-invariant operands.
Also, please fix the comment.
Thx,
Evan
> MRegisterInfo::isVirtualRegister(Reg) &&
> MI->getOperand(2).isImm() && MI->getOperand(3).isReg() &&
> - MI->getOperand(4).isGlobal() && MI->getOperand(2).getImm
> () == 1 &&
> + MI->getOperand(4).isGlobal() &&
> + ST.GVRequiresExtraLoad(MI->getOperand(4).getGlobal(), TM,
> false) &&
> + MI->getOperand(2).getImm() == 1 &&
> MI->getOperand(3).getReg() == 0)
> return true;
> }
>
>
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Re: [llvm-commits] [llvm] r45605 - in /llvm/tr unk/lib/Target/X86: X86ATTAsmPrinter.cp p X86CodeEmitter.cpp X86ISelDAGToDAG.cp p X86InstrInfo.td X86MachineFunctionInf o.h
> Nice evan! With this, sinking is now able to compile code like this: Nifty! I would like to test Mozilla & Qt with this change: they heavily use shared libraries thus almost everything is PIC. -- WBR, Anton Korobeynikov ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm-gcc-4.2] r45628 - /llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
Author: baldrick
Date: Sat Jan 5 11:48:09 2008
New Revision: 45628
URL: http://llvm.org/viewvc/llvm-project?rev=45628&view=rev
Log:
The Ada front-end only sets flag_exceptions after
processing the file (but before gimplification).
At system init time flag_exceptions is thus never
set, which means that --enable-eh will never be
passed to the code generators. Make it possible
to specify options like flag_exceptions late in
the day. This requires setting up optimization
passes late too, since otherwise a LowerInvoke
pass will be scheduled because ExceptionHandling
is not set.
Modified:
llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=45628&r1=45627&r2=45628&view=diff
==
--- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Sat Jan 5 11:48:09 2008
@@ -43,6 +43,7 @@
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetMachineRegistry.h"
+#include "llvm/Target/TargetOptions.h"
#include "llvm/Transforms/Scalar.h"
#include "llvm/Transforms/IPO.h"
#include "llvm/ADT/StringExtras.h"
@@ -97,6 +98,8 @@
static FunctionPassManager *CodeGenPasses = 0;
static void createOptimizationPasses();
+bool OptimizationPassesCreated = false;
+static void destroyOptimizationPasses();
void llvm_initialize_backend(void) {
// Initialize LLVM options.
@@ -123,8 +126,6 @@
Args.push_back("--debug-pass=Structure");
if (flag_debug_pass_arguments)
Args.push_back("--debug-pass=Arguments");
- if (flag_exceptions)
-Args.push_back("--enable-eh");
// If there are options that should be passed through to the LLVM backend
// directly from the command line, do so now. This is mainly for debugging
@@ -197,6 +198,12 @@
TheDebugInfo = new DebugInfo(TheModule);
}
+/// Set backend options that may only be known at codegen time.
+void performLateBackendInitialization(void) {
+ // The Ada front-end sets flag_exceptions only after processing the file.
+ ExceptionHandling = flag_exceptions;
+}
+
void llvm_lang_dependent_init(const char *Name) {
if (Name)
TheModule->setModuleIdentifier(Name);
@@ -227,18 +234,14 @@
exit(1);
}
- if (PerFunctionPasses || PerModulePasses || CodeGenPasses) {
-delete PerFunctionPasses;
-delete PerModulePasses;
-delete CodeGenPasses;
+ if (OptimizationPassesCreated) {
+destroyOptimizationPasses();
// Don't run codegen, when we should output PCH
-if (!flag_pch_file)
- createOptimizationPasses();
-else
+if (flag_pch_file)
llvm_pch_write_init();
}
-
+
// Read LLVM Types string table
readLLVMTypesStringTable();
readLLVMValues();
@@ -255,6 +258,8 @@
AsmOutStream = new oFILEstream(asm_out_file);
AsmOutFile = new OStream(*AsmOutStream);
+ assert(!OptimizationPassesCreated);
+ OptimizationPassesCreated = true;
PerModulePasses = new PassManager();
PerModulePasses->add(new TargetData(*TheTarget->getTargetData()));
@@ -271,7 +276,28 @@
timevar_pop(TV_LLVM_INIT);
}
+static void destroyOptimizationPasses() {
+ assert(OptimizationPassesCreated ||
+ (!PerFunctionPasses && !PerModulePasses && !CodeGenPasses));
+
+ delete PerFunctionPasses;
+ delete PerModulePasses;
+ delete CodeGenPasses;
+
+ PerFunctionPasses = 0;
+ PerModulePasses = 0;
+ CodeGenPasses = 0;
+ OptimizationPassesCreated = false;
+}
+
static void createOptimizationPasses() {
+ assert(OptimizationPassesCreated ||
+ (!PerFunctionPasses && !PerModulePasses && !CodeGenPasses));
+
+ if (OptimizationPassesCreated)
+return;
+ OptimizationPassesCreated = true;
+
// Create and set up the per-function pass manager.
// FIXME: Move the code generator to be function-at-a-time.
PerFunctionPasses =
@@ -368,19 +394,11 @@
// Emit an LLVM .bc file to the output. This is used when passed
// -emit-llvm -c to the GCC driver.
PerModulePasses->add(CreateBitcodeWriterPass(*AsmOutStream));
-
-// Disable emission of .ident into the output file... which is completely
-// wrong for llvm/.bc emission cases.
-flag_no_ident = 1;
HasPerModulePasses = true;
} else if (emit_llvm) {
// Emit an LLVM .ll file to the output. This is used when passed
// -emit-llvm -S to the GCC driver.
PerModulePasses->add(new PrintModulePass(AsmOutFile));
-
-// Disable emission of .ident into the output file... which is completely
-// wrong for llvm/.bc emission cases.
-flag_no_ident = 1;
HasPerModulePasses = true;
} else {
FunctionPassManager *PM;
@@ -436,11 +454,14 @@
timevar_push(TV_LLVM_INIT);
AsmOutStream = new oFILEstream(asm_out_file);
AsmOutFile = new OStream(*AsmOutStream);
-
+
flag_llvm_pch_read = 0;
- createOptimizati
Re: [llvm-commits] [llvm] r45620 - /llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
>> I am not 100% sure, but I think that >> X86Subtarget::GVRequiresExtraLoad >> is the place to start looking. > > Right. If it's a load from GV and GVRequiresExtraLoad() returns true > then it's a load from a stub. > > Here is something to consider for further enhancement. There are > potentially other GV loads which can be side effect free though. As LICM at the LLVM level should catch these. > > the comment says, if the value in the GV isn't redefined (in the > loop), then it can be moved. Should there be some kind of callback > function provided by caller of isReallySideEffectFree() that checks > if a register or a GV operand is considered side effect free? In the > case of LICM, if a register or GV operand is considered a loop > invariant, then the instruction is really side effect free. In the > case of remat, if an operand is "available", then it's side effect > free, etc. etc. You could theoretically check to see that it is a load from a global which is marked constant, but... > BTW, what do we do about volatile loads? I don't think the property > is transferred to target instructions. Or perhaps volatile property > should be on the location (GV) instead of the instruction? Right, this isn't captured. It's safe to do the xform from loads from stubs because we know they are never volatile. A load from a global could be volatile. -Chris ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] [llvm] r45623 - /llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
On Jan 5, 2008, at 12:36 AM, Evan Cheng wrote: > Hrm. ReMat of load from argument area is being handled as a special > case in LiveIntervals::isReMaterializable(). Having > isReallyTrivallyReMaterializable() returns true for it shouldn't make > any difference. I'll look at this. Thanks for investigating. Empirically, this improves codegen in a *lot* of cases when it works, so I think it's important to do. -Chris ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] [llvm] r45605 - in /llvm/trunk/lib/Target/X86: X86ATTAsmPrinter.cpp X86CodeEmitter.cpp X86ISelDAGToDAG.cpp X86InstrInfo.td X86MachineFunctionInfo.h
On Jan 5, 2008, at 8:58 AM, Anton Korobeynikov wrote: >> Nice evan! With this, sinking is now able to compile code like this: > Nifty! I would like to test Mozilla & Qt with this change: they > heavily > use shared libraries thus almost everything is PIC. Nice, I hope to get this enabled by default before the 2.2 release. -Chris ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r45629 - /llvm/trunk/lib/CodeGen/MachineDominators.cpp
Author: lattner
Date: Sat Jan 5 14:15:42 2008
New Revision: 45629
URL: http://llvm.org/viewvc/llvm-project?rev=45629&view=rev
Log:
Fix build issue on certain compilers.
Modified:
llvm/trunk/lib/CodeGen/MachineDominators.cpp
Modified: llvm/trunk/lib/CodeGen/MachineDominators.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineDominators.cpp?rev=45629&r1=45628&r2=45629&view=diff
==
--- llvm/trunk/lib/CodeGen/MachineDominators.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineDominators.cpp Sat Jan 5 14:15:42 2008
@@ -20,8 +20,9 @@
TEMPLATE_INSTANTIATION(class DomTreeNodeBase);
TEMPLATE_INSTANTIATION(class DominatorTreeBase);
+char MachineDominatorTree::ID = 0;
+
namespace {
- char MachineDominatorTree::ID = 0;
RegisterPass
E("machinedomtree", "MachineDominator Tree Construction", true);
}
___
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[llvm-commits] [llvm] r45630 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Author: sampo
Date: Sat Jan 5 14:47:37 2008
New Revision: 45630
URL: http://llvm.org/viewvc/llvm-project?rev=45630&view=rev
Log:
If custom lowering of insert element fails, the result Val will be 0.
Don't overwrite a variable used by the fallthrough code path in this
case.
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=45630&r1=45629&r2=45630&view=diff
==
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sat Jan 5 14:47:37 2008
@@ -1243,9 +1243,9 @@
case TargetLowering::Legal:
break;
case TargetLowering::Custom:
- Tmp3 = TLI.LowerOperation(Result, DAG);
- if (Tmp3.Val) {
-Result = Tmp3;
+ Tmp4 = TLI.LowerOperation(Result, DAG);
+ if (Tmp4.Val) {
+Result = Tmp4;
break;
}
// FALLTHROUGH
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[llvm-commits] [llvm] r45631 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Author: sampo Date: Sat Jan 5 14:51:30 2008 New Revision: 45631 URL: http://llvm.org/viewvc/llvm-project?rev=45631&view=rev Log: Remove an incorrect optimization that is performed correctly by the target independent legalizer. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=45631&r1=45630&r2=45631&view=diff == --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sat Jan 5 14:51:30 2008 @@ -3608,17 +3608,7 @@ N2 = DAG.getConstant(cast(N2)->getValue(),getPointerTy()); return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2); } - - N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, N1); - unsigned Idx = cast(N2)->getValue(); - MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4); - MVT::ValueType MaskEVT = MVT::getVectorElementType(MaskVT); - SmallVector MaskVec; - for (unsigned i = 0; i < 4; ++i) -MaskVec.push_back(DAG.getConstant((i == Idx) ? i+4 : i, MaskEVT)); - return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, N0, N1, - DAG.getNode(ISD::BUILD_VECTOR, MaskVT, - &MaskVec[0], MaskVec.size())); + return SDOperand(); } SDOperand ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r45635 - in /llvm/trunk/utils/TableGen: CodeGenDAGPatterns.cpp CodeGenDAGPatterns.h DAGISelEmitter.cpp DAGISelEmitter.h
Author: lattner
Date: Sat Jan 5 16:54:53 2008
New Revision: 45635
URL: http://llvm.org/viewvc/llvm-project?rev=45635&view=rev
Log:
move Node Transformation printing from CodeGenDAGPatterns -> DAGISelEmitter.
The only difference in output is that we now print them in alphabetical
order instead of reverse alphabetical order.
Modified:
llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp
llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h
llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
llvm/trunk/utils/TableGen/DAGISelEmitter.h
Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp?rev=45635&r1=45634&r2=45635&view=diff
==
--- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp Sat Jan 5 16:54:53 2008
@@ -1112,12 +1112,10 @@
//
// FIXME: REMOVE OSTREAM ARGUMENT
-CodegenDAGPatterns::CodegenDAGPatterns(RecordKeeper &R, std::ostream &OS)
- : Records(R) {
-
+CodegenDAGPatterns::CodegenDAGPatterns(RecordKeeper &R) : Records(R) {
Intrinsics = LoadIntrinsics(Records);
ParseNodeInfo();
- ParseNodeTransforms(OS);
+ ParseNodeTransforms();
ParseComplexPatterns();
ParsePatternFragments();
ParseDefaultOperands();
@@ -1161,26 +1159,13 @@
/// ParseNodeTransforms - Parse all SDNodeXForm instances into the SDNodeXForms
/// map, and emit them to the file as functions.
-void CodegenDAGPatterns::ParseNodeTransforms(std::ostream &OS) {
- OS << "\n// Node transformations.\n";
+void CodegenDAGPatterns::ParseNodeTransforms() {
std::vector Xforms =
Records.getAllDerivedDefinitions("SDNodeXForm");
while (!Xforms.empty()) {
Record *XFormNode = Xforms.back();
Record *SDNode = XFormNode->getValueAsDef("Opcode");
std::string Code = XFormNode->getValueAsCode("XFormFunction");
-SDNodeXForms.insert(std::make_pair(XFormNode,
- std::make_pair(SDNode, Code)));
-
-if (!Code.empty()) {
- std::string ClassName = getSDNodeInfo(SDNode).getSDClassName();
- const char *C2 = ClassName == "SDNode" ? "N" : "inN";
-
- OS << "inline SDOperand Transform_" << XFormNode->getName()
- << "(SDNode *" << C2 << ") {\n";
- if (ClassName != "SDNode")
-OS << " " << ClassName << " *N = cast<" << ClassName << ">(inN);\n";
- OS << Code << "\n}\n";
-}
+SDNodeXForms.insert(std::make_pair(XFormNode, NodeXForm(SDNode, Code)));
Xforms.pop_back();
}
Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h?rev=45635&r1=45634&r2=45635&view=diff
==
--- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h (original)
+++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h Sat Jan 5 16:54:53 2008
@@ -451,7 +451,7 @@
/// emit.
std::vector PatternsToMatch;
public:
- CodegenDAGPatterns(RecordKeeper &R, std::ostream &OS);
+ CodegenDAGPatterns(RecordKeeper &R);
~CodegenDAGPatterns();
const CodeGenTarget &getTargetInfo() const { return Target; }
@@ -463,11 +463,18 @@
return SDNodes.find(R)->second;
}
- const std::pair &getSDNodeTransform(Record *R) const {
+ // Node transformation lookups.
+ typedef std::pair NodeXForm;
+ const NodeXForm &getSDNodeTransform(Record *R) const {
assert(SDNodeXForms.count(R) && "Invalid transform!");
return SDNodeXForms.find(R)->second;
}
+ typedef std::map::const_iterator nx_iterator;
+ nx_iterator nx_begin() const { return SDNodeXForms.begin(); }
+ nx_iterator nx_end() const { return SDNodeXForms.end(); }
+
+
const ComplexPattern &getComplexPattern(Record *R) const {
assert(ComplexPatterns.count(R) && "Unknown addressing mode!");
return ComplexPatterns.find(R)->second;
@@ -530,7 +537,7 @@
private:
void ParseNodeInfo();
- void ParseNodeTransforms(std::ostream &OS);
+ void ParseNodeTransforms();
void ParseComplexPatterns();
void ParsePatternFragments();
void ParseDefaultOperands();
Modified: llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelEmitter.cpp?rev=45635&r1=45634&r2=45635&view=diff
==
--- llvm/trunk/utils/TableGen/DAGISelEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Sat Jan 5 16:54:53 2008
@@ -207,6 +207,39 @@
}
//===--===//
+// Node Transformation emitter implementation.
+//
+void DAGISelEmitter::EmitNodeTransforms(std::ostream &OS) {
+ // Walk the pattern fragments, adding them to a map, which sorts them by
+ // name.
+ typedef std::map NXsByNameTy;
+ NXsByNameTy N
[llvm-commits] [llvm] r45634 - in /llvm/trunk/utils/TableGen: CodeGenDAGPatterns.cpp CodeGenDAGPatterns.h DAGISelEmitter.cpp DAGISelEmitter.h
Author: lattner
Date: Sat Jan 5 16:43:57 2008
New Revision: 45634
URL: http://llvm.org/viewvc/llvm-project?rev=45634&view=rev
Log:
move predicate printing code from CodeGenDAGPatterns -> DAGISelEmitter.
Modified:
llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp
llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h
llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
llvm/trunk/utils/TableGen/DAGISelEmitter.h
Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp?rev=45634&r1=45633&r2=45634&view=diff
==
--- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp Sat Jan 5 16:43:57 2008
@@ -1119,7 +1119,7 @@
ParseNodeInfo();
ParseNodeTransforms(OS);
ParseComplexPatterns();
- ParsePatternFragments(OS);
+ ParsePatternFragments();
ParseDefaultOperands();
ParseInstructions();
ParsePatterns();
@@ -1200,23 +1200,20 @@
/// inline fragments together as necessary, so that there are no references
left
/// inside a pattern fragment to a pattern fragment.
///
-/// This also emits all of the predicate functions to the output file.
-///
-void CodegenDAGPatterns::ParsePatternFragments(std::ostream &OS) {
+void CodegenDAGPatterns::ParsePatternFragments() {
std::vector Fragments = Records.getAllDerivedDefinitions("PatFrag");
- // First step, parse all of the fragments and emit predicate functions.
- OS << "\n// Predicate functions.\n";
+ // First step, parse all of the fragments.
for (unsigned i = 0, e = Fragments.size(); i != e; ++i) {
DagInit *Tree = Fragments[i]->getValueAsDag("Fragment");
TreePattern *P = new TreePattern(Fragments[i], Tree, true, *this);
PatternFragments[Fragments[i]] = P;
-// Validate the argument list, converting it to map, to discard duplicates.
+// Validate the argument list, converting it to set, to discard duplicates.
std::vector &Args = P->getArgList();
-std::set OperandsMap(Args.begin(), Args.end());
+std::set OperandsSet(Args.begin(), Args.end());
-if (OperandsMap.count(""))
+if (OperandsSet.count(""))
P->error("Cannot have unnamed 'node' values in pattern fragment!");
// Parse the operands list.
@@ -1239,37 +1236,22 @@
P->error("Operands list should all be 'node' values.");
if (OpsList->getArgName(j).empty())
P->error("Operands list should have names for each operand!");
- if (!OperandsMap.count(OpsList->getArgName(j)))
+ if (!OperandsSet.count(OpsList->getArgName(j)))
P->error("'" + OpsList->getArgName(j) +
"' does not occur in pattern or was multiply specified!");
- OperandsMap.erase(OpsList->getArgName(j));
+ OperandsSet.erase(OpsList->getArgName(j));
Args.push_back(OpsList->getArgName(j));
}
-if (!OperandsMap.empty())
+if (!OperandsSet.empty())
P->error("Operands list does not contain an entry for operand '" +
- *OperandsMap.begin() + "'!");
+ *OperandsSet.begin() + "'!");
-// If there is a code init for this fragment, emit the predicate code and
-// keep track of the fact that this fragment uses it.
+// If there is a code init for this fragment, keep track of the fact that
+// this fragment uses it.
std::string Code = Fragments[i]->getValueAsCode("Predicate");
-if (!Code.empty()) {
- if (P->getOnlyTree()->isLeaf())
-OS << "inline bool Predicate_" << Fragments[i]->getName()
- << "(SDNode *N) {\n";
- else {
-std::string ClassName =
- getSDNodeInfo(P->getOnlyTree()->getOperator()).getSDClassName();
-const char *C2 = ClassName == "SDNode" ? "N" : "inN";
-
-OS << "inline bool Predicate_" << Fragments[i]->getName()
- << "(SDNode *" << C2 << ") {\n";
-if (ClassName != "SDNode")
- OS << " " << ClassName << " *N = cast<" << ClassName << ">(inN);\n";
- }
- OS << Code << "\n}\n";
+if (!Code.empty())
P->getOnlyTree()->setPredicateFn("Predicate_"+Fragments[i]->getName());
-}
// If there is a node transformation corresponding to this, keep track of
// it.
@@ -1278,8 +1260,6 @@
P->getOnlyTree()->setTransformFn(Transform);
}
- OS << "\n\n";
-
// Now that we've parsed all of the tree fragments, do a closure on them so
// that there are not references to PatFrags left inside of them.
for (std::map::iterator I = PatternFragments.begin(),
Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h?rev=45634&r1=45633&r2=45634&view=diff
==
--- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h (origin
[llvm-commits] [llvm] r45633 - in /llvm/trunk/utils/TableGen: CodeGenDAGPatterns.h DAGISelEmitter.cpp DAGISelEmitter.h
Author: lattner
Date: Sat Jan 5 16:30:17 2008
New Revision: 45633
URL: http://llvm.org/viewvc/llvm-project?rev=45633&view=rev
Log:
fix a fixme by improving const correctness.
Modified:
llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h
llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
llvm/trunk/utils/TableGen/DAGISelEmitter.h
Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h?rev=45633&r1=45632&r2=45633&view=diff
==
--- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h (original)
+++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h Sat Jan 5 16:30:17 2008
@@ -507,10 +507,9 @@
pf_iterator pf_end() const { return PatternFragments.end(); }
// Patterns to match information.
- // FIXME: make a const_iterator.
- typedef std::vector::iterator ptm_iterator;
- ptm_iterator ptm_begin() { return PatternsToMatch.begin(); }
- ptm_iterator ptm_end() { return PatternsToMatch.end(); }
+ typedef std::vector::const_iterator ptm_iterator;
+ ptm_iterator ptm_begin() const { return PatternsToMatch.begin(); }
+ ptm_iterator ptm_end() const { return PatternsToMatch.end(); }
Modified: llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelEmitter.cpp?rev=45633&r1=45632&r2=45633&view=diff
==
--- llvm/trunk/utils/TableGen/DAGISelEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Sat Jan 5 16:30:17 2008
@@ -139,8 +139,8 @@
PatternSortingPredicate(CodegenDAGPatterns &cgp) : CGP(cgp) {}
CodegenDAGPatterns &CGP;
- bool operator()(PatternToMatch *LHS,
- PatternToMatch *RHS) {
+ bool operator()(const PatternToMatch *LHS,
+ const PatternToMatch *RHS) {
unsigned LHSSize = getPatternSize(LHS->getSrcPattern(), CGP);
unsigned RHSSize = getPatternSize(RHS->getSrcPattern(), CGP);
LHSSize += LHS->getAddedComplexity();
@@ -1194,7 +1194,7 @@
/// EmitCodeForPattern - Given a pattern to match, emit code to the specified
/// stream to match the pattern, and generate the code for the match if it
/// succeeds. Returns true if the pattern is not guaranteed to match.
-void DAGISelEmitter::GenerateCodeForPattern(PatternToMatch &Pattern,
+void DAGISelEmitter::GenerateCodeForPattern(const PatternToMatch &Pattern,
std::vector >
&GeneratedCode,
std::set
&GeneratedDecl,
std::vector
&TargetOpcodes,
@@ -1252,7 +1252,7 @@
/// EraseCodeLine - Erase one code line from all of the patterns. If removing
/// a line causes any of them to be empty, remove them and return true when
/// done.
-static bool EraseCodeLine(std::vector > > >
&Patterns) {
bool ErasedPatterns = false;
@@ -1269,13 +1269,13 @@
/// EmitPatterns - Emit code for at least one pattern, but try to group common
/// code together between the patterns.
-void DAGISelEmitter::EmitPatterns(std::vector > >
>
&Patterns, unsigned Indent,
std::ostream &OS) {
typedef std::pair CodeLine;
typedef std::vector CodeList;
- typedef std::vector > PatternList;
+ typedef std::vector > PatternList;
if (Patterns.empty()) return;
@@ -1295,7 +1295,7 @@
// FIXME: Emit braces?
if (Shared.size() == 1) {
- PatternToMatch &Pattern = *Shared.back().first;
+ const PatternToMatch &Pattern = *Shared.back().first;
OS << "\n" << std::string(Indent, ' ') << "// Pattern: ";
Pattern.getSrcPattern()->print(OS);
OS << "\n" << std::string(Indent, ' ') << "// Emits: ";
@@ -1320,7 +1320,7 @@
}
if (Other.size() == 1) {
- PatternToMatch &Pattern = *Other.back().first;
+ const PatternToMatch &Pattern = *Other.back().first;
OS << "\n" << std::string(Indent, ' ') << "// Pattern: ";
Pattern.getSrcPattern()->print(OS);
OS << "\n" << std::string(Indent, ' ') << "// Emits: ";
@@ -1408,12 +1408,12 @@
if (!InstNS.empty()) InstNS += "::";
// Group the patterns by their top-level opcodes.
- std::map > PatternsByOpcode;
+ std::map > PatternsByOpcode;
// All unique target node emission functions.
std::map EmitFunctions;
for (CodegenDAGPatterns::ptm_iterator I = CGP->ptm_begin(),
E = CGP->ptm_end(); I != E; ++I) {
-PatternToMatch &Pattern = *I;
+const PatternToMatch &Pattern = *I;
TreePatternNode *Node = Pattern.getSrcPattern();
if (!Node->isLeaf()) {
@@ -1449,11 +1449,11 @@
// Emit one Select_* method for each top-level opcode. We do this instead of
// emitting one giant switch statement to support compilers where this will
// result in the recursive functio
[llvm-commits] [llvm] r45636 - in /llvm/trunk/utils/TableGen: DAGISelEmitter.cpp DAGISelEmitter.h
Author: lattner
Date: Sat Jan 5 16:58:54 2008
New Revision: 45636
URL: http://llvm.org/viewvc/llvm-project?rev=45636&view=rev
Log:
now that computing CodegenDAGPatterns doesn't implicitly print stuff
out, DAGISelEmitter can compute it in its ctor, which simplifies some code.
Now we can use CodegenDAGPatterns in other parts of tblgen that want access
to dag pattern info, woo!
Modified:
llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
llvm/trunk/utils/TableGen/DAGISelEmitter.h
Modified: llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelEmitter.cpp?rev=45636&r1=45635&r2=45636&view=diff
==
--- llvm/trunk/utils/TableGen/DAGISelEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Sat Jan 5 16:58:54 2008
@@ -215,7 +215,7 @@
typedef std::map NXsByNameTy;
NXsByNameTy NXsByName;
- for (CodegenDAGPatterns::nx_iterator I = CGP->nx_begin(), E = CGP->nx_end();
+ for (CodegenDAGPatterns::nx_iterator I = CGP.nx_begin(), E = CGP.nx_end();
I != E; ++I)
NXsByName.insert(std::make_pair(I->first->getName(), I->second));
@@ -228,7 +228,7 @@
if (Code.empty()) continue; // Empty code? Skip it.
-std::string ClassName = CGP->getSDNodeInfo(SDNode).getSDClassName();
+std::string ClassName = CGP.getSDNodeInfo(SDNode).getSDClassName();
const char *C2 = ClassName == "SDNode" ? "N" : "inN";
OS << "inline SDOperand Transform_" << I->first << "(SDNode *" << C2
@@ -251,7 +251,7 @@
typedef std::map > PFsByNameTy;
PFsByNameTy PFsByName;
- for (CodegenDAGPatterns::pf_iterator I = CGP->pf_begin(), E = CGP->pf_end();
+ for (CodegenDAGPatterns::pf_iterator I = CGP.pf_begin(), E = CGP.pf_end();
I != E; ++I)
PFsByName.insert(std::make_pair(I->first->getName(), *I));
@@ -270,7 +270,7 @@
<< "(SDNode *N) {\n";
else {
std::string ClassName =
-CGP->getSDNodeInfo(P->getOnlyTree()->getOperator()).getSDClassName();
+CGP.getSDNodeInfo(P->getOnlyTree()->getOperator()).getSDClassName();
const char *C2 = ClassName == "SDNode" ? "N" : "inN";
OS << "inline bool Predicate_" << PatFragRecord->getName()
@@ -1280,7 +1280,7 @@
std::set
&GeneratedDecl,
std::vector
&TargetOpcodes,
std::vector &TargetVTs)
{
- PatternCodeEmitter Emitter(*CGP, Pattern.getPredicates(),
+ PatternCodeEmitter Emitter(CGP, Pattern.getPredicates(),
Pattern.getSrcPattern(), Pattern.getDstPattern(),
GeneratedCode, GeneratedDecl,
TargetOpcodes, TargetVTs);
@@ -1290,7 +1290,7 @@
Emitter.EmitMatchCode(Pattern.getSrcPattern(), NULL, "N", "", FoundChain);
// TP - Get *SOME* tree pattern, we don't care which.
- TreePattern &TP = *CGP->pf_begin()->second;
+ TreePattern &TP = *CGP.pf_begin()->second;
// At this point, we know that we structurally match the pattern, but the
// types of the nodes may not match. Figure out the fewest number of type
@@ -1384,11 +1384,11 @@
OS << "\n";
unsigned AddedComplexity = Pattern.getAddedComplexity();
OS << std::string(Indent, ' ') << "// Pattern complexity = "
- << getPatternSize(Pattern.getSrcPattern(), *CGP) + AddedComplexity
+ << getPatternSize(Pattern.getSrcPattern(), CGP) + AddedComplexity
<< " cost = "
- << getResultPatternCost(Pattern.getDstPattern(), *CGP)
+ << getResultPatternCost(Pattern.getDstPattern(), CGP)
<< " size = "
- << getResultPatternSize(Pattern.getDstPattern(), *CGP) << "\n";
+ << getResultPatternSize(Pattern.getDstPattern(), CGP) << "\n";
}
if (FirstCodeLine.first != 1) {
OS << std::string(Indent, ' ') << "{\n";
@@ -1409,11 +1409,11 @@
OS << "\n";
unsigned AddedComplexity = Pattern.getAddedComplexity();
OS << std::string(Indent, ' ') << "// Pattern complexity = "
- << getPatternSize(Pattern.getSrcPattern(), *CGP) + AddedComplexity
+ << getPatternSize(Pattern.getSrcPattern(), CGP) + AddedComplexity
<< " cost = "
- << getResultPatternCost(Pattern.getDstPattern(), *CGP)
+ << getResultPatternCost(Pattern.getDstPattern(), CGP)
<< " size = "
- << getResultPatternSize(Pattern.getDstPattern(), *CGP) << "\n";
+ << getResultPatternSize(Pattern.getDstPattern(), CGP) << "\n";
}
EmitPatterns(Other, Indent, OS);
return;
@@ -1473,7 +1473,7 @@
}
void DAGISelEmitter::EmitInstructionSelector(std::ostream &OS) {
- const CodeGenTarget &Target = CGP->getTargetInfo();
+ const CodeGenTarget &Target = CGP.getTargetInfo();
// Get the namespace to insert instructions into. Make sure n
[llvm-commits] [llvm] r45639 - /llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp
Author: lattner Date: Sat Jan 5 17:37:52 2008 New Revision: 45639 URL: http://llvm.org/viewvc/llvm-project?rev=45639&view=rev Log: fix build on case sensitive file systems. Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp?rev=45639&r1=45638&r2=45639&view=diff == --- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp (original) +++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp Sat Jan 5 17:37:52 2008 @@ -12,13 +12,11 @@ // //===--===// -#include "CodegenDAGPatterns.h" +#include "CodeGenDAGPatterns.h" #include "Record.h" #include "llvm/ADT/StringExtras.h" #include "llvm/Support/Debug.h" -//#include "llvm/Support/MathExtras.h" #include "llvm/Support/Streams.h" -//#include #include using namespace llvm; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r45638 - /llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
Author: void Date: Sat Jan 5 17:30:51 2008 New Revision: 45638 URL: http://llvm.org/viewvc/llvm-project?rev=45638&view=rev Log: Fix comment. Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=45638&r1=45637&r2=45638&view=diff == --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Sat Jan 5 17:30:51 2008 @@ -173,8 +173,7 @@ unsigned Reg = MI->getOperand(1).getReg(); const X86Subtarget &ST = TM.getSubtarget(); - // Loads from global addresses which aren't redefined in the function are - // side effect free. + // Loads from stubs of global addresses are side effect free. if (Reg != 0 && MRegisterInfo::isVirtualRegister(Reg) && MI->getOperand(2).isImm() && MI->getOperand(3).isReg() && MI->getOperand(4).isGlobal() && ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r45637 - /llvm/trunk/lib/CodeGen/MachineLoopInfo.cpp
Author: lattner
Date: Sat Jan 5 17:29:51 2008
New Revision: 45637
URL: http://llvm.org/viewvc/llvm-project?rev=45637&view=rev
Log:
make this build with newer gcc's
Modified:
llvm/trunk/lib/CodeGen/MachineLoopInfo.cpp
Modified: llvm/trunk/lib/CodeGen/MachineLoopInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineLoopInfo.cpp?rev=45637&r1=45636&r2=45637&view=diff
==
--- llvm/trunk/lib/CodeGen/MachineLoopInfo.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineLoopInfo.cpp Sat Jan 5 17:29:51 2008
@@ -17,14 +17,13 @@
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/Passes.h"
-
using namespace llvm;
TEMPLATE_INSTANTIATION(class LoopBase);
TEMPLATE_INSTANTIATION(class LoopInfoBase);
+char MachineLoopInfo::ID = 0;
namespace {
- char MachineLoopInfo::ID = 0;
RegisterPass
X("machine-loops", "Machine Natural Loop Construction", true);
}
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Re: [llvm-commits] [llvm] r45626 - /llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
On Jan 5, 2008, at 2:49 AM, Evan Cheng wrote:
> On Jan 5, 2008, at 1:18 AM, Bill Wendling <[EMAIL PROTECTED]> wrote:
>
>> --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
>> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Sat Jan 5 03:18:04
>> 2008
>> @@ -171,12 +171,15 @@
>> case X86::MOV32rm:
>> if (MI->getOperand(1).isRegister()) {
>> unsigned Reg = MI->getOperand(1).getReg();
>> + const X86Subtarget &ST = TM.getSubtarget();
>>
>> // Loads from global addresses which aren't redefined in the
>> function are
>> // side effect free.
>> if (Reg != 0 &&
>
> I assume caller ensure this operant is side effect free?
It ensures that all of the operands are loop-invariant. Reg is
defined outside of the loop at this point.
> Can you change this to accept a list of operands which should be
> checked? For
> LICM, that means non-invariant operands.
>
I'm not sure why this is necessary. Like I said, all of the operands
should be loop-invariant at this point...
> Also, please fix the comment.
>
Okay.
-bw
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[llvm-commits] [llvm] r45640 - in /llvm/trunk/utils/TableGen: InstrEnumEmitter.cpp InstrEnumEmitter.h InstrInfoEmitter.cpp InstrInfoEmitter.h TableGen.cpp
Author: lattner
Date: Sat Jan 5 18:49:05 2008
New Revision: 45640
URL: http://llvm.org/viewvc/llvm-project?rev=45640&view=rev
Log:
split enum emission out from InstrInfoEmitter into it's own tblgen backend.
Added:
llvm/trunk/utils/TableGen/InstrEnumEmitter.cpp
llvm/trunk/utils/TableGen/InstrEnumEmitter.h
Modified:
llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp
llvm/trunk/utils/TableGen/InstrInfoEmitter.h
llvm/trunk/utils/TableGen/TableGen.cpp
Added: llvm/trunk/utils/TableGen/InstrEnumEmitter.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/InstrEnumEmitter.cpp?rev=45640&view=auto
==
--- llvm/trunk/utils/TableGen/InstrEnumEmitter.cpp (added)
+++ llvm/trunk/utils/TableGen/InstrEnumEmitter.cpp Sat Jan 5 18:49:05 2008
@@ -0,0 +1,54 @@
+//===- InstrEnumEmitter.cpp - Generate Instruction Set Enums
--===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===--===//
+//
+// This tablegen backend is responsible for emitting enums for each machine
+// instruction.
+//
+//===--===//
+
+#include "InstrEnumEmitter.h"
+#include "CodeGenTarget.h"
+#include "Record.h"
+using namespace llvm;
+
+// runEnums - Print out enum values for all of the instructions.
+void InstrEnumEmitter::run(std::ostream &OS) {
+ EmitSourceFileHeader("Target Instruction Enum Values", OS);
+ OS << "namespace llvm {\n\n";
+
+ CodeGenTarget Target;
+
+ // We must emit the PHI opcode first...
+ std::string Namespace;
+ for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
+ E = Target.inst_end(); II != E; ++II) {
+if (II->second.Namespace != "TargetInstrInfo") {
+ Namespace = II->second.Namespace;
+ break;
+}
+ }
+
+ if (Namespace.empty()) {
+fprintf(stderr, "No instructions defined!\n");
+exit(1);
+ }
+
+ std::vector NumberedInstructions;
+ Target.getInstructionsByEnumValue(NumberedInstructions);
+
+ OS << "namespace " << Namespace << " {\n";
+ OS << " enum {\n";
+ for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
+OS << "" << NumberedInstructions[i]->TheDef->getName()
+ << "\t= " << i << ",\n";
+ }
+ OS << "INSTRUCTION_LIST_END = " << NumberedInstructions.size() << "\n";
+ OS << " };\n}\n";
+ OS << "} // End llvm namespace \n";
+}
Added: llvm/trunk/utils/TableGen/InstrEnumEmitter.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/InstrEnumEmitter.h?rev=45640&view=auto
==
--- llvm/trunk/utils/TableGen/InstrEnumEmitter.h (added)
+++ llvm/trunk/utils/TableGen/InstrEnumEmitter.h Sat Jan 5 18:49:05 2008
@@ -0,0 +1,33 @@
+//===- InstrEnumEmitter.h - Generate Instruction Set Enums --*- C++
-*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===--===//
+//
+// This tablegen backend is responsible for emitting enums for each machine
+// instruction.
+//
+//===--===//
+
+#ifndef INSTRENUM_EMITTER_H
+#define INSTRENUM_EMITTER_H
+
+#include "TableGenBackend.h"
+
+namespace llvm {
+
+class InstrEnumEmitter : public TableGenBackend {
+ RecordKeeper &Records;
+public:
+ InstrEnumEmitter(RecordKeeper &R) : Records(R) {}
+
+ // run - Output the instruction set description, returning true on failure.
+ void run(std::ostream &OS);
+};
+
+} // End llvm namespace
+
+#endif
Modified: llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp?rev=45640&r1=45639&r2=45640&view=diff
==
--- llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp Sat Jan 5 18:49:05 2008
@@ -19,42 +19,6 @@
#include
using namespace llvm;
-// runEnums - Print out enum values for all of the instructions.
-void InstrInfoEmitter::runEnums(std::ostream &OS) {
- EmitSourceFileHeader("Target Instruction Enum Values", OS);
- OS << "namespace llvm {\n\n";
-
- CodeGenTarget Target;
-
- // We must emit the PHI opcode first...
- std::string Namespace;
- for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
- E = Target.inst_end(); II != E; ++II) {
-if (II->second.Namespace != "TargetInstrInfo") {
- Namespace = II->second.Namespace;
- break;
-}
- }
-
- if (Namespace.empty())
[llvm-commits] [llvm] r45643 - in /llvm/trunk/utils/TableGen: InstrInfoEmitter.cpp InstrInfoEmitter.h
Author: lattner
Date: Sat Jan 5 19:20:13 2008
New Revision: 45643
URL: http://llvm.org/viewvc/llvm-project?rev=45643&view=rev
Log:
further simplifications and cleanup
Modified:
llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp
llvm/trunk/utils/TableGen/InstrInfoEmitter.h
Modified: llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp?rev=45643&r1=45642&r2=45643&view=diff
==
--- llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp Sat Jan 5 19:20:13 2008
@@ -27,6 +27,33 @@
OS << "0 };\n";
}
+//===--===//
+// Instruction Itinerary Information.
+//===--===//
+
+struct RecordNameComparator {
+ bool operator()(const Record *Rec1, const Record *Rec2) const {
+return Rec1->getName() < Rec2->getName();
+ }
+};
+
+void InstrInfoEmitter::GatherItinClasses() {
+ std::vector DefList =
+ Records.getAllDerivedDefinitions("InstrItinClass");
+ std::sort(DefList.begin(), DefList.end(), RecordNameComparator());
+
+ for (unsigned i = 0, N = DefList.size(); i < N; i++)
+ItinClassMap[DefList[i]->getName()] = i;
+}
+
+unsigned InstrInfoEmitter::getItinClassNumber(const Record *InstRec) {
+ return ItinClassMap[InstRec->getValueAsDef("Itinerary")->getName()];
+}
+
+//===--===//
+// Operand Info Emission.
+//===--===//
+
std::vector
InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
std::vector Result;
@@ -88,6 +115,31 @@
return Result;
}
+void InstrInfoEmitter::EmitOperandInfo(std::ostream &OS,
+ OperandInfoMapTy &OperandInfoIDs) {
+ // ID #0 is for no operand info.
+ unsigned OperandListNum = 0;
+ OperandInfoIDs[std::vector()] = ++OperandListNum;
+
+ OS << "\n";
+ const CodeGenTarget &Target = CDP.getTargetInfo();
+ for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
+ E = Target.inst_end(); II != E; ++II) {
+std::vector OperandInfo = GetOperandInfo(II->second);
+unsigned &N = OperandInfoIDs[OperandInfo];
+if (N != 0) continue;
+
+N = ++OperandListNum;
+OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { ";
+for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i)
+ OS << "{ " << OperandInfo[i] << " }, ";
+OS << "};\n";
+ }
+}
+
+//===--===//
+// Main Output.
+//===--===//
// run - Emit the main instruction description records for the target...
void InstrInfoEmitter::run(std::ostream &OS) {
@@ -120,24 +172,10 @@
}
}
- std::map, unsigned> OperandInfosEmitted;
- unsigned OperandListNum = 0;
- OperandInfosEmitted[std::vector()] = ++OperandListNum;
+ OperandInfoMapTy OperandInfoIDs;
// Emit all of the operand info records.
- OS << "\n";
- for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
- E = Target.inst_end(); II != E; ++II) {
-std::vector OperandInfo = GetOperandInfo(II->second);
-unsigned &N = OperandInfosEmitted[OperandInfo];
-if (N == 0) {
- N = ++OperandListNum;
- OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { ";
- for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i)
-OS << "{ " << OperandInfo[i] << " }, ";
- OS << "};\n";
-}
- }
+ EmitOperandInfo(OS, OperandInfoIDs);
// Emit all of the TargetInstrDescriptor records in their ENUM ordering.
//
@@ -148,7 +186,7 @@
for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i)
emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists,
- OperandInfosEmitted, OS);
+ OperandInfoIDs, OS);
OS << "};\n";
OS << "} // End llvm namespace \n";
}
@@ -156,7 +194,7 @@
void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
Record *InstrInfo,
std::map, unsigned>
&EmittedLists,
- std::map, unsigned>
&OpInfo,
+ const OperandInfoMapTy &OpInfo,
std::ostream &OS) {
int MinOperands;
if (!Inst.OperandList.empty())
@@ -250,29 +288,11 @@
if (OperandInfo.empty())
OS << "0";
else
-OS << "OperandInfo" << OpInfo[OperandInfo];
+OS << "OperandInfo" << OpInfo.find(OperandInfo)->second;
OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
}
-struct RecordNameComparator {
- bool operator()(const Record *Rec1, const
[llvm-commits] [llvm] r45644 - in /llvm/trunk/utils/TableGen: InstrInfoEmitter.cpp InstrInfoEmitter.h
Author: lattner
Date: Sat Jan 5 19:21:51 2008
New Revision: 45644
URL: http://llvm.org/viewvc/llvm-project?rev=45644&view=rev
Log:
final cleanups.
Modified:
llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp
llvm/trunk/utils/TableGen/InstrInfoEmitter.h
Modified: llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp?rev=45644&r1=45643&r2=45644&view=diff
==
--- llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp Sat Jan 5 19:21:51 2008
@@ -19,8 +19,8 @@
#include
using namespace llvm;
-void InstrInfoEmitter::printDefList(const std::vector &Uses,
-unsigned Num, std::ostream &OS) const {
+static void PrintDefList(const std::vector &Uses,
+ unsigned Num, std::ostream &OS) {
OS << "static const unsigned ImplicitList" << Num << "[] = { ";
for (unsigned i = 0, e = Uses.size(); i != e; ++i)
OS << getQualifiedName(Uses[i]) << ", ";
@@ -163,12 +163,12 @@
std::vector Uses = Inst->getValueAsListOfDefs("Uses");
if (!Uses.empty()) {
unsigned &IL = EmittedLists[Uses];
- if (!IL) printDefList(Uses, IL = ++ListNumber, OS);
+ if (!IL) PrintDefList(Uses, IL = ++ListNumber, OS);
}
std::vector Defs = Inst->getValueAsListOfDefs("Defs");
if (!Defs.empty()) {
unsigned &IL = EmittedLists[Defs];
- if (!IL) printDefList(Defs, IL = ++ListNumber, OS);
+ if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS);
}
}
Modified: llvm/trunk/utils/TableGen/InstrInfoEmitter.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/InstrInfoEmitter.h?rev=45644&r1=45643&r2=45644&view=diff
==
--- llvm/trunk/utils/TableGen/InstrInfoEmitter.h (original)
+++ llvm/trunk/utils/TableGen/InstrInfoEmitter.h Sat Jan 5 19:21:51 2008
@@ -41,22 +41,21 @@
private:
typedef std::map, unsigned> OperandInfoMapTy;
- void printDefList(const std::vector &Uses, unsigned Num,
-std::ostream &OS) const;
void emitRecord(const CodeGenInstruction &Inst, unsigned Num,
Record *InstrInfo,
std::map, unsigned> &EL,
const OperandInfoMapTy &OpInfo,
std::ostream &OS);
+ void emitShiftedValue(Record *R, StringInit *Val, IntInit *Shift,
+std::ostream &OS);
+ // Itinerary information.
void GatherItinClasses();
unsigned getItinClassNumber(const Record *InstRec);
+ // Operand information.
void EmitOperandInfo(std::ostream &OS, OperandInfoMapTy &OperandInfoIDs);
std::vector GetOperandInfo(const CodeGenInstruction &Inst);
-
- void emitShiftedValue(Record *R, StringInit *Val, IntInit *Shift,
-std::ostream &OS);
};
} // End llvm namespace
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[llvm-commits] [llvm] r45642 - in /llvm/trunk/utils/TableGen: InstrInfoEmitter.cpp InstrInfoEmitter.h
Author: lattner
Date: Sat Jan 5 19:12:44 2008
New Revision: 45642
URL: http://llvm.org/viewvc/llvm-project?rev=45642&view=rev
Log:
simplify some code
Modified:
llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp
llvm/trunk/utils/TableGen/InstrInfoEmitter.h
Modified: llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp?rev=45642&r1=45641&r2=45642&view=diff
==
--- llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp Sat Jan 5 19:12:44 2008
@@ -175,10 +175,7 @@
else
OS << Inst.Name;
- unsigned ItinClass = !IsItineraries ? 0 :
-
ItinClassNumber(Inst.TheDef->getValueAsDef("Itinerary")->getName());
-
- OS << "\",\t" << ItinClass << ", 0";
+ OS << "\",\t" << getItinClassNumber(Inst.TheDef) << ", 0";
// Try to determine (from the pattern), if the instruction is a store.
bool isStore = false;
@@ -258,28 +255,23 @@
OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
}
-struct LessRecord {
+struct RecordNameComparator {
bool operator()(const Record *Rec1, const Record *Rec2) const {
return Rec1->getName() < Rec2->getName();
}
};
+
void InstrInfoEmitter::GatherItinClasses() {
std::vector DefList =
Records.getAllDerivedDefinitions("InstrItinClass");
- IsItineraries = !DefList.empty();
-
- if (!IsItineraries) return;
-
- std::sort(DefList.begin(), DefList.end(), LessRecord());
+ std::sort(DefList.begin(), DefList.end(), RecordNameComparator());
- for (unsigned i = 0, N = DefList.size(); i < N; i++) {
-Record *Def = DefList[i];
-ItinClassMap[Def->getName()] = i;
- }
+ for (unsigned i = 0, N = DefList.size(); i < N; i++)
+ItinClassMap[DefList[i]->getName()] = i;
}
-unsigned InstrInfoEmitter::ItinClassNumber(std::string ItinName) {
- return ItinClassMap[ItinName];
+unsigned InstrInfoEmitter::getItinClassNumber(const Record *InstRec) {
+ return ItinClassMap[InstRec->getValueAsDef("Itinerary")->getName()];
}
void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val,
Modified: llvm/trunk/utils/TableGen/InstrInfoEmitter.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/InstrInfoEmitter.h?rev=45642&r1=45641&r2=45642&view=diff
==
--- llvm/trunk/utils/TableGen/InstrInfoEmitter.h (original)
+++ llvm/trunk/utils/TableGen/InstrInfoEmitter.h Sat Jan 5 19:12:44 2008
@@ -16,6 +16,7 @@
#define INSTRINFO_EMITTER_H
#include "TableGenBackend.h"
+#include "CodeGenDAGPatterns.h"
#include
#include
@@ -28,11 +29,11 @@
class InstrInfoEmitter : public TableGenBackend {
RecordKeeper &Records;
- bool IsItineraries;
+ CodeGenDAGPatterns CDP;
std::map ItinClassMap;
public:
- InstrInfoEmitter(RecordKeeper &R) : Records(R), IsItineraries(false) {}
+ InstrInfoEmitter(RecordKeeper &R) : Records(R), CDP(R) { }
// run - Output the instruction set description, returning true on failure.
void run(std::ostream &OS);
@@ -46,7 +47,7 @@
std::map, unsigned> &OpInfo,
std::ostream &OS);
void GatherItinClasses();
- unsigned ItinClassNumber(std::string ItinName);
+ unsigned getItinClassNumber(const Record *InstRec);
void emitShiftedValue(Record *R, StringInit *Val, IntInit *Shift,
std::ostream &OS);
std::vector GetOperandInfo(const CodeGenInstruction &Inst);
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[llvm-commits] [llvm] r45641 - in /llvm/trunk/utils/TableGen: CodeGenDAGPatterns.cpp CodeGenDAGPatterns.h DAGISelEmitter.cpp DAGISelEmitter.h
Author: lattner
Date: Sat Jan 5 19:10:31 2008
New Revision: 45641
URL: http://llvm.org/viewvc/llvm-project?rev=45641&view=rev
Log:
rename CodegenDAGPatterns -> CodeGenDAGPatterns
Modified:
llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp
llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h
llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
llvm/trunk/utils/TableGen/DAGISelEmitter.h
Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp?rev=45641&r1=45640&r2=45641&view=diff
==
--- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp Sat Jan 5 19:10:31 2008
@@ -1,4 +1,4 @@
-//===- CodegenDAGPatterns.cpp - Read DAG patterns from .td file
---===//
+//===- CodeGenDAGPatterns.cpp - Read DAG patterns from .td file
---===//
//
// The LLVM Compiler Infrastructure
//
@@ -7,7 +7,7 @@
//
//===--===//
//
-// This file implements the CodegenDAGPatterns class, which is used to read and
+// This file implements the CodeGenDAGPatterns class, which is used to read and
// represent the patterns present in a .td file for instructions.
//
//===--===//
@@ -638,7 +638,7 @@
/// change, false otherwise. If a type contradiction is found, throw an
/// exception.
bool TreePatternNode::ApplyTypeConstraints(TreePattern &TP, bool NotRegisters)
{
- CodegenDAGPatterns &CDP = TP.getDAGPatterns();
+ CodeGenDAGPatterns &CDP = TP.getDAGPatterns();
if (isLeaf()) {
if (DefInit *DI = dynamic_cast(getLeafValue())) {
// If it's a regclass or something else known, include the type.
@@ -862,7 +862,7 @@
/// that can never possibly work), and to prevent the pattern permuter from
/// generating stuff that is useless.
bool TreePatternNode::canPatternMatch(std::string &Reason,
- CodegenDAGPatterns &CDP){
+ CodeGenDAGPatterns &CDP){
if (isLeaf()) return true;
for (unsigned i = 0, e = getNumChildren(); i != e; ++i)
@@ -899,20 +899,20 @@
//
TreePattern::TreePattern(Record *TheRec, ListInit *RawPat, bool isInput,
- CodegenDAGPatterns &cdp) : TheRecord(TheRec),
CDP(cdp){
+ CodeGenDAGPatterns &cdp) : TheRecord(TheRec),
CDP(cdp){
isInputPattern = isInput;
for (unsigned i = 0, e = RawPat->getSize(); i != e; ++i)
Trees.push_back(ParseTreePattern((DagInit*)RawPat->getElement(i)));
}
TreePattern::TreePattern(Record *TheRec, DagInit *Pat, bool isInput,
- CodegenDAGPatterns &cdp) : TheRecord(TheRec),
CDP(cdp){
+ CodeGenDAGPatterns &cdp) : TheRecord(TheRec),
CDP(cdp){
isInputPattern = isInput;
Trees.push_back(ParseTreePattern(Pat));
}
TreePattern::TreePattern(Record *TheRec, TreePatternNode *Pat, bool isInput,
- CodegenDAGPatterns &cdp) : TheRecord(TheRec),
CDP(cdp){
+ CodeGenDAGPatterns &cdp) : TheRecord(TheRec),
CDP(cdp){
isInputPattern = isInput;
Trees.push_back(Pat);
}
@@ -1106,11 +1106,11 @@
void TreePattern::dump() const { print(*cerr.stream()); }
//===--===//
-// CodegenDAGPatterns implementation
+// CodeGenDAGPatterns implementation
//
// FIXME: REMOVE OSTREAM ARGUMENT
-CodegenDAGPatterns::CodegenDAGPatterns(RecordKeeper &R) : Records(R) {
+CodeGenDAGPatterns::CodeGenDAGPatterns(RecordKeeper &R) : Records(R) {
Intrinsics = LoadIntrinsics(Records);
ParseNodeInfo();
ParseNodeTransforms();
@@ -1125,14 +1125,14 @@
GenerateVariants();
}
-CodegenDAGPatterns::~CodegenDAGPatterns() {
+CodeGenDAGPatterns::~CodeGenDAGPatterns() {
for (std::map::iterator I = PatternFragments.begin(),
E = PatternFragments.end(); I != E; ++I)
delete I->second;
}
-Record *CodegenDAGPatterns::getSDNodeNamed(const std::string &Name) const {
+Record *CodeGenDAGPatterns::getSDNodeNamed(const std::string &Name) const {
Record *N = Records.getDef(Name);
if (!N || !N->isSubClassOf("SDNode")) {
cerr << "Error getting SDNode '" << Name << "'!\n";
@@ -1142,7 +1142,7 @@
}
// Parse all of the SDNode definitions for the target, populating SDNodes.
-void CodegenDAGPatterns::ParseNodeInfo() {
+void CodeGenDAGPatterns::ParseNodeInfo() {
std::vector Nodes = Records.getAllDerivedDefinitions("SDNode");
while (!Nodes.empty()) {
SDNodes.insert(std::make_pair(Nodes.back(), Nodes.back()));
@@ -1157,7 +1157,7 @@
/// ParseNodeTransforms - Parse all SDNodeXForm instances into the SDNodeXForms
/// map, and emit them to the file as functions.
-void CodegenDAGPatterns::
[llvm-commits] [llvm] r45647 - in /llvm/trunk/utils/TableGen: InstrInfoEmitter.cpp InstrInfoEmitter.h
Author: lattner
Date: Sat Jan 5 19:53:37 2008
New Revision: 45647
URL: http://llvm.org/viewvc/llvm-project?rev=45647&view=rev
Log:
rearrange some code to allow inferring instr info from the pattern of the
instr, but don't do so yet.
Modified:
llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp
llvm/trunk/utils/TableGen/InstrInfoEmitter.h
Modified: llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp?rev=45647&r1=45646&r2=45647&view=diff
==
--- llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp Sat Jan 5 19:53:37 2008
@@ -138,6 +138,40 @@
}
//===--===//
+// Instruction Analysis
+//===--===//
+
+void InstrInfoEmitter::InferFromPattern(const CodeGenInstruction &Inst,
+bool &isStore, bool &isLoad,
+bool &NeverHasSideEffects) {
+ isStore = Inst.isStore;
+ isLoad = Inst.isLoad;
+ NeverHasSideEffects = Inst.neverHasSideEffects;
+
+ const TreePattern *Pattern = CDP.getInstruction(Inst.TheDef).getPattern();
+ if (Pattern == 0) return; // No pattern.
+
+ // FIXME: Change this to use pattern info.
+ if (dynamic_cast(Inst.TheDef->getValueInit("Pattern"))) {
+ListInit *LI = Inst.TheDef->getValueAsListInit("Pattern");
+if (LI && LI->getSize() > 0) {
+ DagInit *Dag = (DagInit *)LI->getElement(0);
+ DefInit *OpDef = dynamic_cast(Dag->getOperator());
+ if (OpDef) {
+Record *Operator = OpDef->getDef();
+if (Operator->isSubClassOf("SDNode")) {
+ const std::string Opcode = Operator->getValueAsString("Opcode");
+ if (Opcode == "ISD::STORE" || Opcode == "ISD::TRUNCSTORE")
+isStore = true;
+}
+ }
+}
+ }
+
+}
+
+
+//===--===//
// Main Output.
//===--===//
@@ -196,43 +230,27 @@
std::map, unsigned>
&EmittedLists,
const OperandInfoMapTy &OpInfo,
std::ostream &OS) {
- int MinOperands;
+ // Determine properties of the instruction from its pattern.
+ bool isStore, isLoad, NeverHasSideEffects;
+ InferFromPattern(Inst, isStore, isLoad, NeverHasSideEffects);
+
+ if (NeverHasSideEffects && Inst.mayHaveSideEffects) {
+std::cerr << "error: Instruction '" << Inst.getName()
+ << "' is marked with 'mayHaveSideEffects', but it can never have
them!\n";
+exit(1);
+ }
+
+ int MinOperands = 0;
if (!Inst.OperandList.empty())
// Each logical operand can be multiple MI operands.
MinOperands = Inst.OperandList.back().MIOperandNo +
Inst.OperandList.back().MINumOperands;
- else
-MinOperands = 0;
OS << " { ";
OS << Num << ",\t" << MinOperands << ",\t"
- << Inst.NumDefs << ",\t\"";
-
- if (Inst.Name.empty())
-OS << Inst.TheDef->getName();
- else
-OS << Inst.Name;
-
+ << Inst.NumDefs << ",\t\"" << Inst.getName();
OS << "\",\t" << getItinClassNumber(Inst.TheDef) << ", 0";
- // Try to determine (from the pattern), if the instruction is a store.
- bool isStore = false;
- if (dynamic_cast(Inst.TheDef->getValueInit("Pattern"))) {
-ListInit *LI = Inst.TheDef->getValueAsListInit("Pattern");
-if (LI && LI->getSize() > 0) {
- DagInit *Dag = (DagInit *)LI->getElement(0);
- DefInit *OpDef = dynamic_cast(Dag->getOperator());
- if (OpDef) {
-Record *Operator = OpDef->getDef();
-if (Operator->isSubClassOf("SDNode")) {
- const std::string Opcode = Operator->getValueAsString("Opcode");
- if (Opcode == "ISD::STORE" || Opcode == "ISD::TRUNCSTORE")
-isStore = true;
-}
- }
-}
- }
-
// Emit all of the target indepedent flags...
if (Inst.isReturn) OS << "|M_RET_FLAG";
if (Inst.isBranch) OS << "|M_BRANCH_FLAG";
@@ -240,21 +258,21 @@
if (Inst.isBarrier)OS << "|M_BARRIER_FLAG";
if (Inst.hasDelaySlot) OS << "|M_DELAY_SLOT_FLAG";
if (Inst.isCall) OS << "|M_CALL_FLAG";
- if (Inst.isLoad) OS << "|M_LOAD_FLAG";
- if (Inst.isStore || isStore) OS << "|M_STORE_FLAG";
+ if (isLoad)OS << "|M_LOAD_FLAG";
+ if (isStore) OS << "|M_STORE_FLAG";
if (Inst.isImplicitDef)OS << "|M_IMPLICIT_DEF_FLAG";
if (Inst.isPredicable) OS << "|M_PREDICABLE";
if (Inst.isConvertibleToThreeAddress) OS << "|M_CONVERTIBLE_TO_3_ADDR";
if (Inst.isCommutable) OS << "|M_COMMUTABLE";
if (Inst.isTerminator) OS << "|M_TERMINATOR_FLAG";
if (Inst.isReMaterializa
[llvm-commits] [llvm] r45646 - in /llvm/trunk/utils/TableGen: CodeGenDAGPatterns.cpp CodeGenDAGPatterns.h DAGISelEmitter.cpp
Author: lattner
Date: Sat Jan 5 19:52:22 2008
New Revision: 45646
URL: http://llvm.org/viewvc/llvm-project?rev=45646&view=rev
Log:
improve const correctness.
Modified:
llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp
llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h
llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp?rev=45646&r1=45645&r2=45646&view=diff
==
--- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp Sat Jan 5 19:52:22 2008
@@ -1661,7 +1661,7 @@
for (std::map::iterator II = Instructions.begin(),
E = Instructions.end(); II != E; ++II) {
DAGInstruction &TheInst = II->second;
-TreePattern *I = TheInst.getPattern();
+const TreePattern *I = TheInst.getPattern();
if (I == 0) continue; // No pattern.
// FIXME: Assume only the first tree is the pattern. The others are clobber
Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h?rev=45646&r1=45645&r2=45646&view=diff
==
--- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h (original)
+++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h Sat Jan 5 19:52:22 2008
@@ -374,7 +374,7 @@
ImpResults(impresults), ImpOperands(impoperands),
ResultPattern(0) {}
- TreePattern *getPattern() const { return Pattern; }
+ const TreePattern *getPattern() const { return Pattern; }
unsigned getNumResults() const { return Results.size(); }
unsigned getNumOperands() const { return Operands.size(); }
unsigned getNumImpResults() const { return ImpResults.size(); }
Modified: llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelEmitter.cpp?rev=45646&r1=45645&r2=45646&view=diff
==
--- llvm/trunk/utils/TableGen/DAGISelEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Sat Jan 5 19:52:22 2008
@@ -827,7 +827,7 @@
const CodeGenTarget &CGT = CGP.getTargetInfo();
CodeGenInstruction &II = CGT.getInstruction(Op->getName());
const DAGInstruction &Inst = CGP.getInstruction(Op);
- TreePattern *InstPat = Inst.getPattern();
+ const TreePattern *InstPat = Inst.getPattern();
// FIXME: Assume actual pattern comes before "implicit".
TreePatternNode *InstPatNode =
isRoot ? (InstPat ? InstPat->getTree(0) : Pattern)
___
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[llvm-commits] [llvm] r45648 - in /llvm/trunk/utils/TableGen: InstrInfoEmitter.cpp InstrInfoEmitter.h
Author: lattner
Date: Sat Jan 5 20:16:26 2008
New Revision: 45648
URL: http://llvm.org/viewvc/llvm-project?rev=45648&view=rev
Log:
remove some old hacky code that tried to infer whether a store
occured in a pattern, but failed miserably. The new code works for
any instruction that has a store in its pattern, including all the
x86 mem op mem instructions.
The only target-independent code that uses this is branch folding,
so this won't change anything in practice.
Modified:
llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp
llvm/trunk/utils/TableGen/InstrInfoEmitter.h
Modified: llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp?rev=45648&r1=45647&r2=45648&view=diff
==
--- llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp Sat Jan 5 20:16:26 2008
@@ -141,6 +141,51 @@
// Instruction Analysis
//===--===//
+class InstAnalyzer {
+ const CodeGenDAGPatterns &CDP;
+ bool &isStore;
+ bool &isLoad;
+ bool &NeverHasSideEffects;
+public:
+ InstAnalyzer(const CodeGenDAGPatterns &cdp,
+ bool &isstore, bool &isload, bool &nhse)
+: CDP(cdp), isStore(isstore), isLoad(isload), NeverHasSideEffects(nhse) {
+ }
+
+ void Analyze(Record *InstRecord) {
+const TreePattern *Pattern = CDP.getInstruction(InstRecord).getPattern();
+if (Pattern == 0) return; // No pattern.
+
+// Assume there is no side-effect unless we see one.
+// FIXME: Enable this.
+//NeverHasSideEffects = true;
+
+
+// FIXME: Assume only the first tree is the pattern. The others are clobber
+// nodes.
+AnalyzeNode(Pattern->getTree(0));
+ }
+
+private:
+ void AnalyzeNode(const TreePatternNode *N) {
+if (N->isLeaf()) {
+ return;
+}
+
+if (N->getOperator()->getName() != "set") {
+ // Get information about the SDNode for the operator.
+ const SDNodeInfo &OpInfo = CDP.getSDNodeInfo(N->getOperator());
+
+ if (OpInfo.getEnumName() == "ISD::STORE")
+isStore = true;
+}
+
+for (unsigned i = 0, e = N->getNumChildren(); i != e; ++i)
+ AnalyzeNode(N->getChild(i));
+ }
+
+};
+
void InstrInfoEmitter::InferFromPattern(const CodeGenInstruction &Inst,
bool &isStore, bool &isLoad,
bool &NeverHasSideEffects) {
@@ -148,26 +193,11 @@
isLoad = Inst.isLoad;
NeverHasSideEffects = Inst.neverHasSideEffects;
- const TreePattern *Pattern = CDP.getInstruction(Inst.TheDef).getPattern();
- if (Pattern == 0) return; // No pattern.
-
- // FIXME: Change this to use pattern info.
- if (dynamic_cast(Inst.TheDef->getValueInit("Pattern"))) {
-ListInit *LI = Inst.TheDef->getValueAsListInit("Pattern");
-if (LI && LI->getSize() > 0) {
- DagInit *Dag = (DagInit *)LI->getElement(0);
- DefInit *OpDef = dynamic_cast(Dag->getOperator());
- if (OpDef) {
-Record *Operator = OpDef->getDef();
-if (Operator->isSubClassOf("SDNode")) {
- const std::string Opcode = Operator->getValueAsString("Opcode");
- if (Opcode == "ISD::STORE" || Opcode == "ISD::TRUNCSTORE")
-isStore = true;
-}
- }
-}
- }
+ InstAnalyzer(CDP, isStore, isLoad, NeverHasSideEffects).Analyze(Inst.TheDef);
+ // If the .td file explicitly says there is no side effect, believe it.
+ if (Inst.neverHasSideEffects)
+NeverHasSideEffects = true;
}
Modified: llvm/trunk/utils/TableGen/InstrInfoEmitter.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/InstrInfoEmitter.h?rev=45648&r1=45647&r2=45648&view=diff
==
--- llvm/trunk/utils/TableGen/InstrInfoEmitter.h (original)
+++ llvm/trunk/utils/TableGen/InstrInfoEmitter.h Sat Jan 5 20:16:26 2008
@@ -29,7 +29,7 @@
class InstrInfoEmitter : public TableGenBackend {
RecordKeeper &Records;
- CodeGenDAGPatterns CDP;
+ const CodeGenDAGPatterns CDP;
std::map ItinClassMap;
public:
___
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[llvm-commits] [llvm] r45645 - in /llvm/trunk/utils/TableGen: CodeGenInstruction.cpp CodeGenInstruction.h CodeGenTarget.cpp
Author: lattner
Date: Sat Jan 5 19:35:39 2008
New Revision: 45645
URL: http://llvm.org/viewvc/llvm-project?rev=45645&view=rev
Log:
Split the impl of CodeGenInstruction out to its own .cpp file, add a getName()
accessor.
Added:
llvm/trunk/utils/TableGen/CodeGenInstruction.cpp
Modified:
llvm/trunk/utils/TableGen/CodeGenInstruction.h
llvm/trunk/utils/TableGen/CodeGenTarget.cpp
Added: llvm/trunk/utils/TableGen/CodeGenInstruction.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenInstruction.cpp?rev=45645&view=auto
==
--- llvm/trunk/utils/TableGen/CodeGenInstruction.cpp (added)
+++ llvm/trunk/utils/TableGen/CodeGenInstruction.cpp Sat Jan 5 19:35:39 2008
@@ -0,0 +1,280 @@
+//===- CodeGenInstruction.cpp - CodeGen Instruction Class Wrapper
-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===--===//
+//
+// This file implements the CodeGenInstruction class.
+//
+//===--===//
+
+#include "CodeGenInstruction.h"
+#include "Record.h"
+#include "llvm/ADT/StringExtras.h"
+#include
+using namespace llvm;
+
+static void ParseConstraint(const std::string &CStr, CodeGenInstruction *I) {
+ // FIXME: Only supports TIED_TO for now.
+ std::string::size_type pos = CStr.find_first_of('=');
+ assert(pos != std::string::npos && "Unrecognized constraint");
+ std::string Name = CStr.substr(0, pos);
+
+ // TIED_TO: $src1 = $dst
+ std::string::size_type wpos = Name.find_first_of(" \t");
+ if (wpos == std::string::npos)
+throw "Illegal format for tied-to constraint: '" + CStr + "'";
+ std::string DestOpName = Name.substr(0, wpos);
+ std::pair DestOp = I->ParseOperandName(DestOpName, false);
+
+ Name = CStr.substr(pos+1);
+ wpos = Name.find_first_not_of(" \t");
+ if (wpos == std::string::npos)
+throw "Illegal format for tied-to constraint: '" + CStr + "'";
+
+ std::pair SrcOp =
+ I->ParseOperandName(Name.substr(wpos), false);
+ if (SrcOp > DestOp)
+throw "Illegal tied-to operand constraint '" + CStr + "'";
+
+
+ unsigned FlatOpNo = I->getFlattenedOperandNumber(SrcOp);
+ // Build the string for the operand.
+ std::string OpConstraint =
+ "((" + utostr(FlatOpNo) + " << 16) | (1 << TOI::TIED_TO))";
+
+
+ if (!I->OperandList[DestOp.first].Constraints[DestOp.second].empty())
+throw "Operand '" + DestOpName + "' cannot have multiple constraints!";
+ I->OperandList[DestOp.first].Constraints[DestOp.second] = OpConstraint;
+}
+
+static void ParseConstraints(const std::string &CStr, CodeGenInstruction *I) {
+ // Make sure the constraints list for each operand is large enough to hold
+ // constraint info, even if none is present.
+ for (unsigned i = 0, e = I->OperandList.size(); i != e; ++i)
+I->OperandList[i].Constraints.resize(I->OperandList[i].MINumOperands);
+
+ if (CStr.empty()) return;
+
+ const std::string delims(",");
+ std::string::size_type bidx, eidx;
+
+ bidx = CStr.find_first_not_of(delims);
+ while (bidx != std::string::npos) {
+eidx = CStr.find_first_of(delims, bidx);
+if (eidx == std::string::npos)
+ eidx = CStr.length();
+
+ParseConstraint(CStr.substr(bidx, eidx), I);
+bidx = CStr.find_first_not_of(delims, eidx);
+ }
+}
+
+CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr)
+ : TheDef(R), AsmString(AsmStr) {
+ Name = R->getValueAsString("Name");
+ Namespace = R->getValueAsString("Namespace");
+
+ isReturn = R->getValueAsBit("isReturn");
+ isBranch = R->getValueAsBit("isBranch");
+ isIndirectBranch = R->getValueAsBit("isIndirectBranch");
+ isBarrier= R->getValueAsBit("isBarrier");
+ isCall = R->getValueAsBit("isCall");
+ isLoad = R->getValueAsBit("isLoad");
+ isStore = R->getValueAsBit("isStore");
+ isImplicitDef= R->getValueAsBit("isImplicitDef");
+ bool isTwoAddress = R->getValueAsBit("isTwoAddress");
+ isPredicable = R->getValueAsBit("isPredicable");
+ isConvertibleToThreeAddress =
R->getValueAsBit("isConvertibleToThreeAddress");
+ isCommutable = R->getValueAsBit("isCommutable");
+ isTerminator = R->getValueAsBit("isTerminator");
+ isReMaterializable = R->getValueAsBit("isReMaterializable");
+ hasDelaySlot = R->getValueAsBit("hasDelaySlot");
+ usesCustomDAGSchedInserter = R->getValueAsBit("usesCustomDAGSchedInserter");
+ hasCtrlDep = R->getValueAsBit("hasCtrlDep");
+ isNotDuplicable = R->getValueAsBit("isNotDuplicable");
+ mayHaveSideEffects = R->getValueAsBit("mayHaveSideEffects");
+ neverHasSideEffects = R->getValueAsBit("neverHasSideEffects");
+ hasOptionalDef = false;
+ hasVariableNumberOfOperands = false;
+
+ if (mayHaveSideEffects && nev
[llvm-commits] [llvm] r45649 - /llvm/trunk/test/Analysis/BasicAA/2007-08-01-NoAliasAndCalls.ll
Author: nicholas
Date: Sat Jan 5 21:12:44 2008
New Revision: 45649
URL: http://llvm.org/viewvc/llvm-project?rev=45649&view=rev
Log:
Accept both %y, %x and %x, %y as valid answers.
Modified:
llvm/trunk/test/Analysis/BasicAA/2007-08-01-NoAliasAndCalls.ll
Modified: llvm/trunk/test/Analysis/BasicAA/2007-08-01-NoAliasAndCalls.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/BasicAA/2007-08-01-NoAliasAndCalls.ll?rev=45649&r1=45648&r2=45649&view=diff
==
--- llvm/trunk/test/Analysis/BasicAA/2007-08-01-NoAliasAndCalls.ll (original)
+++ llvm/trunk/test/Analysis/BasicAA/2007-08-01-NoAliasAndCalls.ll Sat Jan 5
21:12:44 2008
@@ -1,4 +1,4 @@
-; RUN: llvm-as %s -o - | opt -basicaa -aa-eval -print-all-alias-modref-info
-disable-output |& grep {MayAlias:.*i32\\* %y, i32\\* %x}
+; RUN: llvm-as %s -o - | opt -basicaa -aa-eval -print-all-alias-modref-info
-disable-output |& grep {MayAlias:.*i32\\* %., i32\\* %.} | grep {%x} | grep
{%y}
declare i32* @unclear(i32* %a)
___
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[llvm-commits] [llvm] r45650 - in /llvm/trunk/utils/TableGen: CodeGenDAGPatterns.cpp CodeGenDAGPatterns.h InstrInfoEmitter.cpp
Author: lattner
Date: Sat Jan 5 23:36:50 2008
New Revision: 45650
URL: http://llvm.org/viewvc/llvm-project?rev=45650&view=rev
Log:
set the 'isstore' flag for instructions whose pattern is an
intrinsic that writes to memory.
Modified:
llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp
llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h
llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp
Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp?rev=45650&r1=45649&r2=45650&view=diff
==
--- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp Sat Jan 5 23:36:50 2008
@@ -633,6 +633,22 @@
return Other;
}
+
+/// getIntrinsicInfo - If this node corresponds to an intrinsic, return the
+/// CodeGenIntrinsic information for it, otherwise return a null pointer.
+const CodeGenIntrinsic *TreePatternNode::
+getIntrinsicInfo(const CodeGenDAGPatterns &CDP) const {
+ if (getOperator() != CDP.get_intrinsic_void_sdnode() &&
+ getOperator() != CDP.get_intrinsic_w_chain_sdnode() &&
+ getOperator() != CDP.get_intrinsic_wo_chain_sdnode())
+return 0;
+
+ unsigned IID =
+dynamic_cast(getChild(0)->getLeafValue())->getValue();
+ return &CDP.getIntrinsicInfo(IID);
+}
+
+
/// ApplyTypeConstraints - Apply all of the type constraints relevent to
/// this node and its children in the tree. This returns true if it makes a
/// change, false otherwise. If a type contradiction is found, throw an
@@ -699,27 +715,22 @@
MadeChange = getChild(i)->ApplyTypeConstraints(TP, NotRegisters);
MadeChange |= UpdateNodeType(MVT::isVoid, TP);
return MadeChange;
- } else if (getOperator() == CDP.get_intrinsic_void_sdnode() ||
- getOperator() == CDP.get_intrinsic_w_chain_sdnode() ||
- getOperator() == CDP.get_intrinsic_wo_chain_sdnode()) {
-unsigned IID =
-dynamic_cast(getChild(0)->getLeafValue())->getValue();
-const CodeGenIntrinsic &Int = CDP.getIntrinsicInfo(IID);
+ } else if (const CodeGenIntrinsic *Int = getIntrinsicInfo(CDP)) {
bool MadeChange = false;
// Apply the result type to the node.
-MadeChange = UpdateNodeType(Int.ArgVTs[0], TP);
+MadeChange = UpdateNodeType(Int->ArgVTs[0], TP);
-if (getNumChildren() != Int.ArgVTs.size())
- TP.error("Intrinsic '" + Int.Name + "' expects " +
- utostr(Int.ArgVTs.size()-1) + " operands, not " +
+if (getNumChildren() != Int->ArgVTs.size())
+ TP.error("Intrinsic '" + Int->Name + "' expects " +
+ utostr(Int->ArgVTs.size()-1) + " operands, not " +
utostr(getNumChildren()-1) + " operands!");
// Apply type info to the intrinsic ID.
MadeChange |= getChild(0)->UpdateNodeType(MVT::iPTR, TP);
for (unsigned i = 1, e = getNumChildren(); i != e; ++i) {
- MVT::ValueType OpVT = Int.ArgVTs[i];
+ MVT::ValueType OpVT = Int->ArgVTs[i];
MadeChange |= getChild(i)->UpdateNodeType(OpVT, TP);
MadeChange |= getChild(i)->ApplyTypeConstraints(TP, NotRegisters);
}
Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h?rev=45650&r1=45649&r2=45650&view=diff
==
--- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h (original)
+++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h Sat Jan 5 23:36:50 2008
@@ -203,14 +203,17 @@
void setChild(unsigned i, TreePatternNode *N) {
Children[i] = N;
}
-
-
+
const std::string &getPredicateFn() const { return PredicateFn; }
void setPredicateFn(const std::string &Fn) { PredicateFn = Fn; }
Record *getTransformFn() const { return TransformFn; }
void setTransformFn(Record *Fn) { TransformFn = Fn; }
+ /// getIntrinsicInfo - If this node corresponds to an intrinsic, return the
+ /// CodeGenIntrinsic information for it, otherwise return a null pointer.
+ const CodeGenIntrinsic *getIntrinsicInfo(const CodeGenDAGPatterns &CDP)
const;
+
void print(std::ostream &OS) const;
void dump() const;
Modified: llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp?rev=45650&r1=45649&r2=45650&view=diff
==
--- llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp Sat Jan 5 23:36:50 2008
@@ -176,8 +176,15 @@
// Get information about the SDNode for the operator.
const SDNodeInfo &OpInfo = CDP.getSDNodeInfo(N->getOperator());
- if (OpInfo.getEnumName() == "ISD::STORE")
+ // If this is a store node, it obviously stores to
[llvm-commits] [llvm] r45651 - /llvm/trunk/include/llvm/Target/TargetInstrInfo.h
Author: lattner
Date: Sat Jan 5 23:43:21 2008
New Revision: 45651
URL: http://llvm.org/viewvc/llvm-project?rev=45651&view=rev
Log:
describe isStore and simplify the implementation of hasUnmodelledSideEffects.
No functionality change.
Modified:
llvm/trunk/include/llvm/Target/TargetInstrInfo.h
Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=45651&r1=45650&r2=45651&view=diff
==
--- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Sat Jan 5 23:43:21 2008
@@ -49,7 +49,13 @@
const unsigned M_BARRIER_FLAG = 1 << 3;
const unsigned M_DELAY_SLOT_FLAG = 1 << 4;
const unsigned M_LOAD_FLAG = 1 << 5;
+
+/// M_STORE_FLAG - This flag is set to any instruction that could possibly
+/// modify memory. Instructions with this flag set are not necessarily simple
+/// store instructions, they may store a modified value based on their
operands,
+/// or may not actually modify anything, for example.
const unsigned M_STORE_FLAG= 1 << 6;
+
const unsigned M_INDIRECT_FLAG = 1 << 7;
const unsigned M_IMPLICIT_DEF_FLAG = 1 << 8;
@@ -276,6 +282,11 @@
bool isLoad(MachineOpCode Opcode) const {
return get(Opcode).Flags & M_LOAD_FLAG;
}
+
+ /// isStore - Return true if this instruction could possibly modify memory.
+ /// Instructions with this flag set are not necessarily simple store
+ /// instructions, they may store a modified value based on their operands, or
+ /// may not actually modify anything, for example.
bool isStore(MachineOpCode Opcode) const {
return get(Opcode).Flags & M_STORE_FLAG;
}
@@ -322,9 +333,8 @@
/// flags.
bool hasUnmodelledSideEffects(MachineInstr *MI) const {
const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
-if (!(TID->Flags & M_NEVER_HAS_SIDE_EFFECTS ||
- TID->Flags & M_MAY_HAVE_SIDE_EFFECTS)) return true;
if (TID->Flags & M_NEVER_HAS_SIDE_EFFECTS) return false;
+if (!(TID->Flags & M_MAY_HAVE_SIDE_EFFECTS)) return true;
return !isReallySideEffectFree(MI); // May have side effects
}
protected:
___
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[llvm-commits] [llvm] r45652 - in /llvm/trunk/lib/Target/PowerPC: PPCInstr64Bit.td PPCInstrAltivec.td PPCInstrInfo.td
Author: lattner
Date: Sat Jan 5 23:53:26 2008
New Revision: 45652
URL: http://llvm.org/viewvc/llvm-project?rev=45652&view=rev
Log:
remove some isStore flags that are now inferred automatically.
Modified:
llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td
llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td?rev=45652&r1=45651&r2=45652&view=diff
==
--- llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td Sat Jan 5 23:53:26 2008
@@ -448,7 +448,7 @@
}
-let isStore = 1, PPC970_Unit = 2 in {
+let PPC970_Unit = 2 in {
// Truncating stores.
def STB8 : DForm_1<38, (outs), (ins G8RC:$rS, memri:$src),
"stb $rS, $src", LdStGeneral,
@@ -481,7 +481,7 @@
PPC970_DGroup_Cracked;
}
-let isStore = 1, PPC970_Unit = 2 in {
+let PPC970_Unit = 2 in {
def STBU8 : DForm_1<38, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
symbolLo:$ptroff, ptr_rc:$ptrreg),
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td?rev=45652&r1=45651&r2=45652&view=diff
==
--- llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td Sat Jan 5 23:53:26 2008
@@ -229,7 +229,7 @@
[(set VRRC:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>,
PPC970_Unit_LSU;
-let isStore = 1, PPC970_Unit = 2 in { // Stores.
+let PPC970_Unit = 2 in { // Stores.
def STVEBX: XForm_8<31, 135, (outs), (ins VRRC:$rS, memrr:$dst),
"stvebx $rS, $dst", LdStGeneral,
[(int_ppc_altivec_stvebx VRRC:$rS, xoaddr:$dst)]>;
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=45652&r1=45651&r2=45652&view=diff
==
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Sat Jan 5 23:53:26 2008
@@ -564,7 +564,7 @@
//
// Unindexed (r+i) Stores.
-let isStore = 1, PPC970_Unit = 2 in {
+let PPC970_Unit = 2 in {
def STB : DForm_1<38, (outs), (ins GPRC:$rS, memri:$src),
"stb $rS, $src", LdStGeneral,
[(truncstorei8 GPRC:$rS, iaddr:$src)]>;
@@ -583,7 +583,7 @@
}
// Unindexed (r+i) Stores with Update (preinc).
-let isStore = 1, PPC970_Unit = 2 in {
+let PPC970_Unit = 2 in {
def STBU : DForm_1<39, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
symbolLo:$ptroff, ptr_rc:$ptrreg),
"stbu $rS, $ptroff($ptrreg)", LdStGeneral,
@@ -621,7 +621,7 @@
// Indexed (r+r) Stores.
//
-let isStore = 1, PPC970_Unit = 2 in {
+let PPC970_Unit = 2 in {
def STBX : XForm_8<31, 215, (outs), (ins GPRC:$rS, memrr:$dst),
"stbx $rS, $dst", LdStGeneral,
[(truncstorei8 GPRC:$rS, xaddr:$dst)]>,
@@ -634,6 +634,8 @@
"stwx $rS, $dst", LdStGeneral,
[(store GPRC:$rS, xaddr:$dst)]>,
PPC970_DGroup_Cracked;
+
+let isStore = 1 in {
def STWUX : XForm_8<31, 183, (outs), (ins GPRC:$rS, GPRC:$rA, GPRC:$rB),
"stwux $rS, $rA, $rB", LdStGeneral,
[]>;
@@ -649,6 +651,7 @@
def STFIWX: XForm_28<31, 983, (outs), (ins F8RC:$frS, memrr:$dst),
"stfiwx $frS, $dst", LdStUX,
[(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>;
+}
def STFSX : XForm_28<31, 663, (outs), (ins F4RC:$frS, memrr:$dst),
"stfsx $frS, $dst", LdStUX,
[(store F4RC:$frS, xaddr:$dst)]>;
___
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[llvm-commits] [llvm] r45653 - in /llvm/trunk/lib/Target/ARM: ARMInstrInfo.td ARMInstrThumb.td ARMInstrVFP.td
Author: lattner
Date: Sat Jan 5 23:55:01 2008
New Revision: 45653
URL: http://llvm.org/viewvc/llvm-project?rev=45653&view=rev
Log:
remove explicit isStore flags that are now inferrable.
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=45653&r1=45652&r2=45653&view=diff
==
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Sat Jan 5 23:55:01 2008
@@ -713,7 +713,7 @@
Pseudo, "${addr:label}:\n\tldr${p}sb $dst, $addr",
[(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
}
-let isStore = 1, AddedComplexity = 10 in {
+let AddedComplexity = 10 in {
def PICSTR : AXI2<0x0, (outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
Pseudo, "${addr:label}:\n\tstr$p $src, $addr",
[(store GPR:$src, addrmodepc:$addr)]>;
@@ -878,7 +878,6 @@
} // isLoad
// Store
-let isStore = 1 in {
def STR : AI2<0x0, (outs), (ins GPR:$src, addrmode2:$addr), StFrm,
"str", " $src, $addr",
[(store GPR:$src, addrmode2:$addr)]>;
@@ -893,6 +892,7 @@
[(truncstorei8 GPR:$src, addrmode2:$addr)]>;
// Store doubleword
+let isStore = 1 in
def STRD : AI3<0xF, (outs), (ins GPR:$src, addrmode3:$addr), StFrm,
"str", "d $src, $addr",
[]>, Requires<[IsARM, HasV5T]>;
@@ -933,7 +933,6 @@
"str", "b $src, [$base], $offset", "$base = $base_wb",
[(set GPR:$base_wb, (post_truncsti8 GPR:$src,
GPR:$base, am2offset:$offset))]>;
-} // isStore
//===--===//
// Load / store multiple Instructions.
Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=45653&r1=45652&r2=45653&view=diff
==
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Sat Jan 5 23:55:01 2008
@@ -278,7 +278,6 @@
"ldr $dst, $addr", []>;
} // isLoad
-let isStore = 1 in {
def tSTR : TI4<(outs), (ins GPR:$src, t_addrmode_s4:$addr),
"str $src, $addr",
[(store GPR:$src, t_addrmode_s4:$addr)]>;
@@ -295,6 +294,7 @@
"str $src, $addr",
[(store GPR:$src, t_addrmode_sp:$addr)]>;
+let isStore = 1 in {
// Special instruction for spill. It cannot clobber condition register
// when it's expanded by eliminateCallFramePseudoInstr().
def tSpill : TIs<(outs), (ins GPR:$src, t_addrmode_sp:$addr),
Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=45653&r1=45652&r2=45653&view=diff
==
--- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Sat Jan 5 23:55:01 2008
@@ -98,7 +98,6 @@
[(set SPR:$dst, (load addrmode5:$addr))]>;
} // isLoad
-let isStore = 1 in {
def FSTD : ADI5<(outs), (ins DPR:$src, addrmode5:$addr),
"fstd", " $src, $addr",
[(store DPR:$src, addrmode5:$addr)]>;
@@ -106,7 +105,6 @@
def FSTS : ASI5<(outs), (ins SPR:$src, addrmode5:$addr),
"fsts", " $src, $addr",
[(store SPR:$src, addrmode5:$addr)]>;
-} // isStore
//===--===//
// Load / store multiple Instructions.
___
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[llvm-commits] [llvm] r45654 - in /llvm/trunk: lib/Target/Alpha/AlphaInstrFormats.td lib/Target/Alpha/AlphaInstrInfo.td lib/Target/CellSPU/SPUInstrInfo.td lib/Target/Mips/MipsInstrInfo.td lib/Target/P
Author: lattner
Date: Sun Jan 6 00:44:58 2008
New Revision: 45654
URL: http://llvm.org/viewvc/llvm-project?rev=45654&view=rev
Log:
Change the 'isStore' inferrer to look for 'SDNPMayStore'
instead of "ISD::STORE". This allows us to mark target-specific dag
nodes as storing (such as ppc byteswap stores). This allows us to remove
more explicit isStore flags from the .td files.
Finally, add a warning for when a .td file contains an explicit
isStore and tblgen is able to infer it.
Modified:
llvm/trunk/lib/Target/Alpha/AlphaInstrFormats.td
llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.td
llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
llvm/trunk/lib/Target/TargetSelectionDAG.td
llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp
llvm/trunk/utils/TableGen/CodeGenTarget.h
llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp
Modified: llvm/trunk/lib/Target/Alpha/AlphaInstrFormats.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaInstrFormats.td?rev=45654&r1=45653&r2=45654&view=diff
==
--- llvm/trunk/lib/Target/Alpha/AlphaInstrFormats.td (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaInstrFormats.td Sun Jan 6 00:44:58 2008
@@ -38,10 +38,9 @@
//3.3.1
-class MForm opcode, bit store, bit load, string asmstr, list
pattern, InstrItinClass itin>
+class MForm opcode, bit load, string asmstr, list pattern,
InstrItinClass itin>
: InstAlpha {
let Pattern = pattern;
- let isStore = store;
let isLoad = load;
let Defs = [R28]; //We may use this for frame index calculations, so reserve
it here
Modified: llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.td?rev=45654&r1=45653&r2=45654&view=diff
==
--- llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.td Sun Jan 6 00:44:58 2008
@@ -412,78 +412,78 @@
let OutOperandList = (ops GPRC:$RA), InOperandList = (ops s64imm:$DISP,
GPRC:$RB) in {
-def LDQ : MForm<0x29, 0, 1, "ldq $RA,$DISP($RB)",
+def LDQ : MForm<0x29, 1, "ldq $RA,$DISP($RB)",
[(set GPRC:$RA, (load (add GPRC:$RB, immSExt16:$DISP)))],
s_ild>;
-def LDQr : MForm<0x29, 0, 1, "ldq $RA,$DISP($RB)\t\t!gprellow",
+def LDQr : MForm<0x29, 1, "ldq $RA,$DISP($RB)\t\t!gprellow",
[(set GPRC:$RA, (load (Alpha_gprello tglobaladdr:$DISP,
GPRC:$RB)))], s_ild>;
-def LDL : MForm<0x28, 0, 1, "ldl $RA,$DISP($RB)",
+def LDL : MForm<0x28, 1, "ldl $RA,$DISP($RB)",
[(set GPRC:$RA, (sextloadi32 (add GPRC:$RB,
immSExt16:$DISP)))], s_ild>;
-def LDLr : MForm<0x28, 0, 1, "ldl $RA,$DISP($RB)\t\t!gprellow",
+def LDLr : MForm<0x28, 1, "ldl $RA,$DISP($RB)\t\t!gprellow",
[(set GPRC:$RA, (sextloadi32 (Alpha_gprello
tglobaladdr:$DISP, GPRC:$RB)))], s_ild>;
-def LDBU : MForm<0x0A, 0, 1, "ldbu $RA,$DISP($RB)",
+def LDBU : MForm<0x0A, 1, "ldbu $RA,$DISP($RB)",
[(set GPRC:$RA, (zextloadi8 (add GPRC:$RB,
immSExt16:$DISP)))], s_ild>;
-def LDBUr : MForm<0x0A, 0, 1, "ldbu $RA,$DISP($RB)\t\t!gprellow",
+def LDBUr : MForm<0x0A, 1, "ldbu $RA,$DISP($RB)\t\t!gprellow",
[(set GPRC:$RA, (zextloadi8 (Alpha_gprello tglobaladdr:$DISP,
GPRC:$RB)))], s_ild>;
-def LDWU : MForm<0x0C, 0, 1, "ldwu $RA,$DISP($RB)",
+def LDWU : MForm<0x0C, 1, "ldwu $RA,$DISP($RB)",
[(set GPRC:$RA, (zextloadi16 (add GPRC:$RB,
immSExt16:$DISP)))], s_ild>;
-def LDWUr : MForm<0x0C, 0, 1, "ldwu $RA,$DISP($RB)\t\t!gprellow",
+def LDWUr : MForm<0x0C, 1, "ldwu $RA,$DISP($RB)\t\t!gprellow",
[(set GPRC:$RA, (zextloadi16 (Alpha_gprello
tglobaladdr:$DISP, GPRC:$RB)))], s_ild>;
}
let OutOperandList = (ops), InOperandList = (ops GPRC:$RA, s64imm:$DISP,
GPRC:$RB) in {
-def STB : MForm<0x0E, 1, 0, "stb $RA,$DISP($RB)",
+def STB : MForm<0x0E, 0, "stb $RA,$DISP($RB)",
[(truncstorei8 GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))],
s_ist>;
-def STBr : MForm<0x0E, 1, 0, "stb $RA,$DISP($RB)\t\t!gprellow",
+def STBr : MForm<0x0E, 0, "stb $RA,$DISP($RB)\t\t!gprellow",
[(truncstorei8 GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP,
GPRC:$RB))], s_ist>;
-def STW : MForm<0x0D, 1, 0, "stw $RA,$DISP($RB)",
+def STW : MForm<0x0D, 0, "stw $RA,$DISP($RB)",
[(truncstorei16 GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))],
s_ist>;
-def STWr : MForm<0x0D, 1, 0, "stw $RA,$DISP($RB)\t\t!gprellow",
+def STWr : MForm<0x0D, 0, "stw $RA,$DISP($RB)\t\t!gprellow",
[(truncstorei16 GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP,
GPRC:$RB))], s_ist>;
-def STL : MForm<0x2C, 1, 0, "stl $RA,$DISP
[llvm-commits] [llvm] r45655 - /llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp
Author: baldrick Date: Sun Jan 6 01:43:13 2008 New Revision: 45655 URL: http://llvm.org/viewvc/llvm-project?rev=45655&view=rev Log: Remove an unused variable. Modified: llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp Modified: llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp?rev=45655&r1=45654&r2=45655&view=diff == --- llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp (original) +++ llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp Sun Jan 6 01:43:13 2008 @@ -242,7 +242,6 @@ if (CSI.empty()) return; - const MRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo(); const TargetInstrInfo &TII = *Fn.getTarget().getInstrInfo(); // Now that we have a stack slot for each register to be saved, insert spill ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
