Author: lattner
Date: Sun Jan 6 00:44:58 2008
New Revision: 45654
URL: http://llvm.org/viewvc/llvm-project?rev=45654&view=rev
Log:
Change the 'isStore' inferrer to look for 'SDNPMayStore'
instead of "ISD::STORE". This allows us to mark target-specific dag
nodes as storing (such as ppc byteswap stores). This allows us to remove
more explicit isStore flags from the .td files.
Finally, add a warning for when a .td file contains an explicit
isStore and tblgen is able to infer it.
Modified:
llvm/trunk/lib/Target/Alpha/AlphaInstrFormats.td
llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.td
llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
llvm/trunk/lib/Target/TargetSelectionDAG.td
llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp
llvm/trunk/utils/TableGen/CodeGenTarget.h
llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp
Modified: llvm/trunk/lib/Target/Alpha/AlphaInstrFormats.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaInstrFormats.td?rev=45654&r1=45653&r2=45654&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaInstrFormats.td (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaInstrFormats.td Sun Jan 6 00:44:58 2008
@@ -38,10 +38,9 @@
//3.3.1
-class MForm<bits<6> opcode, bit store, bit load, string asmstr, list<dag>
pattern, InstrItinClass itin>
+class MForm<bits<6> opcode, bit load, string asmstr, list<dag> pattern,
InstrItinClass itin>
: InstAlpha<opcode, asmstr, itin> {
let Pattern = pattern;
- let isStore = store;
let isLoad = load;
let Defs = [R28]; //We may use this for frame index calculations, so reserve
it here
Modified: llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.td?rev=45654&r1=45653&r2=45654&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.td Sun Jan 6 00:44:58 2008
@@ -412,78 +412,78 @@
let OutOperandList = (ops GPRC:$RA), InOperandList = (ops s64imm:$DISP,
GPRC:$RB) in {
-def LDQ : MForm<0x29, 0, 1, "ldq $RA,$DISP($RB)",
+def LDQ : MForm<0x29, 1, "ldq $RA,$DISP($RB)",
[(set GPRC:$RA, (load (add GPRC:$RB, immSExt16:$DISP)))],
s_ild>;
-def LDQr : MForm<0x29, 0, 1, "ldq $RA,$DISP($RB)\t\t!gprellow",
+def LDQr : MForm<0x29, 1, "ldq $RA,$DISP($RB)\t\t!gprellow",
[(set GPRC:$RA, (load (Alpha_gprello tglobaladdr:$DISP,
GPRC:$RB)))], s_ild>;
-def LDL : MForm<0x28, 0, 1, "ldl $RA,$DISP($RB)",
+def LDL : MForm<0x28, 1, "ldl $RA,$DISP($RB)",
[(set GPRC:$RA, (sextloadi32 (add GPRC:$RB,
immSExt16:$DISP)))], s_ild>;
-def LDLr : MForm<0x28, 0, 1, "ldl $RA,$DISP($RB)\t\t!gprellow",
+def LDLr : MForm<0x28, 1, "ldl $RA,$DISP($RB)\t\t!gprellow",
[(set GPRC:$RA, (sextloadi32 (Alpha_gprello
tglobaladdr:$DISP, GPRC:$RB)))], s_ild>;
-def LDBU : MForm<0x0A, 0, 1, "ldbu $RA,$DISP($RB)",
+def LDBU : MForm<0x0A, 1, "ldbu $RA,$DISP($RB)",
[(set GPRC:$RA, (zextloadi8 (add GPRC:$RB,
immSExt16:$DISP)))], s_ild>;
-def LDBUr : MForm<0x0A, 0, 1, "ldbu $RA,$DISP($RB)\t\t!gprellow",
+def LDBUr : MForm<0x0A, 1, "ldbu $RA,$DISP($RB)\t\t!gprellow",
[(set GPRC:$RA, (zextloadi8 (Alpha_gprello tglobaladdr:$DISP,
GPRC:$RB)))], s_ild>;
-def LDWU : MForm<0x0C, 0, 1, "ldwu $RA,$DISP($RB)",
+def LDWU : MForm<0x0C, 1, "ldwu $RA,$DISP($RB)",
[(set GPRC:$RA, (zextloadi16 (add GPRC:$RB,
immSExt16:$DISP)))], s_ild>;
-def LDWUr : MForm<0x0C, 0, 1, "ldwu $RA,$DISP($RB)\t\t!gprellow",
+def LDWUr : MForm<0x0C, 1, "ldwu $RA,$DISP($RB)\t\t!gprellow",
[(set GPRC:$RA, (zextloadi16 (Alpha_gprello
tglobaladdr:$DISP, GPRC:$RB)))], s_ild>;
}
let OutOperandList = (ops), InOperandList = (ops GPRC:$RA, s64imm:$DISP,
GPRC:$RB) in {
-def STB : MForm<0x0E, 1, 0, "stb $RA,$DISP($RB)",
+def STB : MForm<0x0E, 0, "stb $RA,$DISP($RB)",
[(truncstorei8 GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))],
s_ist>;
-def STBr : MForm<0x0E, 1, 0, "stb $RA,$DISP($RB)\t\t!gprellow",
+def STBr : MForm<0x0E, 0, "stb $RA,$DISP($RB)\t\t!gprellow",
[(truncstorei8 GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP,
GPRC:$RB))], s_ist>;
-def STW : MForm<0x0D, 1, 0, "stw $RA,$DISP($RB)",
+def STW : MForm<0x0D, 0, "stw $RA,$DISP($RB)",
[(truncstorei16 GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))],
s_ist>;
-def STWr : MForm<0x0D, 1, 0, "stw $RA,$DISP($RB)\t\t!gprellow",
+def STWr : MForm<0x0D, 0, "stw $RA,$DISP($RB)\t\t!gprellow",
[(truncstorei16 GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP,
GPRC:$RB))], s_ist>;
-def STL : MForm<0x2C, 1, 0, "stl $RA,$DISP($RB)",
+def STL : MForm<0x2C, 0, "stl $RA,$DISP($RB)",
[(truncstorei32 GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))],
s_ist>;
-def STLr : MForm<0x2C, 1, 0, "stl $RA,$DISP($RB)\t\t!gprellow",
+def STLr : MForm<0x2C, 0, "stl $RA,$DISP($RB)\t\t!gprellow",
[(truncstorei32 GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP,
GPRC:$RB))], s_ist>;
-def STQ : MForm<0x2D, 1, 0, "stq $RA,$DISP($RB)",
+def STQ : MForm<0x2D, 0, "stq $RA,$DISP($RB)",
[(store GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_ist>;
-def STQr : MForm<0x2D, 1, 0, "stq $RA,$DISP($RB)\t\t!gprellow",
+def STQr : MForm<0x2D, 0, "stq $RA,$DISP($RB)\t\t!gprellow",
[(store GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP,
GPRC:$RB))], s_ist>;
}
//Load address
let OutOperandList = (ops GPRC:$RA), InOperandList = (ops s64imm:$DISP,
GPRC:$RB) in {
-def LDA : MForm<0x08, 0, 0, "lda $RA,$DISP($RB)",
+def LDA : MForm<0x08, 0, "lda $RA,$DISP($RB)",
[(set GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_lda>;
-def LDAr : MForm<0x08, 0, 0, "lda $RA,$DISP($RB)\t\t!gprellow",
+def LDAr : MForm<0x08, 0, "lda $RA,$DISP($RB)\t\t!gprellow",
[(set GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP,
GPRC:$RB))], s_lda>; //Load address
-def LDAH : MForm<0x09, 0, 0, "ldah $RA,$DISP($RB)",
+def LDAH : MForm<0x09, 0, "ldah $RA,$DISP($RB)",
[], s_lda>; //Load address high
-def LDAHr : MForm<0x09, 0, 0, "ldah $RA,$DISP($RB)\t\t!gprelhigh",
+def LDAHr : MForm<0x09, 0, "ldah $RA,$DISP($RB)\t\t!gprelhigh",
[(set GPRC:$RA, (Alpha_gprelhi tglobaladdr:$DISP,
GPRC:$RB))], s_lda>; //Load address high
}
let OutOperandList = (ops), InOperandList = (ops F4RC:$RA, s64imm:$DISP,
GPRC:$RB) in {
-def STS : MForm<0x26, 1, 0, "sts $RA,$DISP($RB)",
+def STS : MForm<0x26, 0, "sts $RA,$DISP($RB)",
[(store F4RC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_fst>;
-def STSr : MForm<0x26, 1, 0, "sts $RA,$DISP($RB)\t\t!gprellow",
+def STSr : MForm<0x26, 0, "sts $RA,$DISP($RB)\t\t!gprellow",
[(store F4RC:$RA, (Alpha_gprello tglobaladdr:$DISP,
GPRC:$RB))], s_fst>;
}
let OutOperandList = (ops F4RC:$RA), InOperandList = (ops s64imm:$DISP,
GPRC:$RB) in {
-def LDS : MForm<0x22, 0, 1, "lds $RA,$DISP($RB)",
+def LDS : MForm<0x22, 1, "lds $RA,$DISP($RB)",
[(set F4RC:$RA, (load (add GPRC:$RB, immSExt16:$DISP)))],
s_fld>;
-def LDSr : MForm<0x22, 0, 1, "lds $RA,$DISP($RB)\t\t!gprellow",
+def LDSr : MForm<0x22, 1, "lds $RA,$DISP($RB)\t\t!gprellow",
[(set F4RC:$RA, (load (Alpha_gprello tglobaladdr:$DISP,
GPRC:$RB)))], s_fld>;
}
let OutOperandList = (ops), InOperandList = (ops F8RC:$RA, s64imm:$DISP,
GPRC:$RB) in {
-def STT : MForm<0x27, 1, 0, "stt $RA,$DISP($RB)",
+def STT : MForm<0x27, 0, "stt $RA,$DISP($RB)",
[(store F8RC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_fst>;
-def STTr : MForm<0x27, 1, 0, "stt $RA,$DISP($RB)\t\t!gprellow",
+def STTr : MForm<0x27, 0, "stt $RA,$DISP($RB)\t\t!gprellow",
[(store F8RC:$RA, (Alpha_gprello tglobaladdr:$DISP,
GPRC:$RB))], s_fst>;
}
let OutOperandList = (ops F8RC:$RA), InOperandList = (ops s64imm:$DISP,
GPRC:$RB) in {
-def LDT : MForm<0x23, 0, 1, "ldt $RA,$DISP($RB)",
+def LDT : MForm<0x23, 1, "ldt $RA,$DISP($RB)",
[(set F8RC:$RA, (load (add GPRC:$RB, immSExt16:$DISP)))],
s_fld>;
-def LDTr : MForm<0x23, 0, 1, "ldt $RA,$DISP($RB)\t\t!gprellow",
+def LDTr : MForm<0x23, 1, "ldt $RA,$DISP($RB)\t\t!gprellow",
[(set F8RC:$RA, (load (Alpha_gprello tglobaladdr:$DISP,
GPRC:$RB)))], s_fld>;
}
@@ -557,13 +557,13 @@
//load address, rellocated gpdist form
let OutOperandList = (ops GPRC:$RA), InOperandList = (ops s16imm:$DISP,
GPRC:$RB, s16imm:$NUM) in {
-def LDAg : MForm<0x08, 0, 1, "lda $RA,0($RB)\t\t!gpdisp!$NUM", [], s_lda>;
//Load address
-def LDAHg : MForm<0x09, 0, 1, "ldah $RA,0($RB)\t\t!gpdisp!$NUM", [], s_lda>;
//Load address
+def LDAg : MForm<0x08, 1, "lda $RA,0($RB)\t\t!gpdisp!$NUM", [], s_lda>;
//Load address
+def LDAHg : MForm<0x09, 1, "ldah $RA,0($RB)\t\t!gpdisp!$NUM", [], s_lda>;
//Load address
}
//Load quad, rellocated literal form
let OutOperandList = (ops GPRC:$RA), InOperandList = (ops s64imm:$DISP,
GPRC:$RB) in
-def LDQl : MForm<0x29, 0, 1, "ldq $RA,$DISP($RB)\t\t!literal",
+def LDQl : MForm<0x29, 1, "ldq $RA,$DISP($RB)\t\t!literal",
[(set GPRC:$RA, (Alpha_rellit tglobaladdr:$DISP, GPRC:$RB))],
s_ild>;
def : Pat<(Alpha_rellit texternalsym:$ext, GPRC:$RB),
(LDQl texternalsym:$ext, GPRC:$RB)>;
Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td?rev=45654&r1=45653&r2=45654&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td Sun Jan 6 00:44:58 2008
@@ -257,179 +257,177 @@
// Stores:
//===----------------------------------------------------------------------===//
-let isStore = 1 in {
- def STQDv16i8 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
- "stqd\t$rT, $src", LoadStore,
- [(store (v16i8 VECREG:$rT), dform_addr:$src)]>;
-
- def STQDv8i16 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
- "stqd\t$rT, $src", LoadStore,
- [(store (v8i16 VECREG:$rT), dform_addr:$src)]>;
-
- def STQDv4i32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
- "stqd\t$rT, $src", LoadStore,
- [(store (v4i32 VECREG:$rT), dform_addr:$src)]>;
-
- def STQDv2i64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
- "stqd\t$rT, $src", LoadStore,
- [(store (v2i64 VECREG:$rT), dform_addr:$src)]>;
-
- def STQDv4f32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
- "stqd\t$rT, $src", LoadStore,
- [(store (v4f32 VECREG:$rT), dform_addr:$src)]>;
-
- def STQDv2f64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
- "stqd\t$rT, $src", LoadStore,
- [(store (v2f64 VECREG:$rT), dform_addr:$src)]>;
-
- def STQDr128 : RI10Form<0b00100100, (outs), (ins GPRC:$rT, memri10:$src),
- "stqd\t$rT, $src", LoadStore,
- [(store GPRC:$rT, dform_addr:$src)]>;
-
- def STQDr64 : RI10Form<0b00100100, (outs), (ins R64C:$rT, memri10:$src),
- "stqd\t$rT, $src", LoadStore,
- [(store R64C:$rT, dform_addr:$src)]>;
-
- def STQDr32 : RI10Form<0b00100100, (outs), (ins R32C:$rT, memri10:$src),
- "stqd\t$rT, $src", LoadStore,
- [(store R32C:$rT, dform_addr:$src)]>;
-
- // Floating Point
- def STQDf32 : RI10Form<0b00100100, (outs), (ins R32FP:$rT, memri10:$src),
- "stqd\t$rT, $src", LoadStore,
- [(store R32FP:$rT, dform_addr:$src)]>;
-
- def STQDf64 : RI10Form<0b00100100, (outs), (ins R64FP:$rT, memri10:$src),
- "stqd\t$rT, $src", LoadStore,
- [(store R64FP:$rT, dform_addr:$src)]>;
-
- def STQDr16 : RI10Form<0b00100100, (outs), (ins R16C:$rT, memri10:$src),
- "stqd\t$rT, $src", LoadStore,
- [(store R16C:$rT, dform_addr:$src)]>;
-
- def STQDr8 : RI10Form<0b00100100, (outs), (ins R8C:$rT, memri10:$src),
- "stqd\t$rT, $src", LoadStore,
- [(store R8C:$rT, dform_addr:$src)]>;
-
- def STQAv16i8 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
- "stqa\t$rT, $src", LoadStore,
- [(store (v16i8 VECREG:$rT), aform_addr:$src)]>;
-
- def STQAv8i16 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
- "stqa\t$rT, $src", LoadStore,
- [(store (v8i16 VECREG:$rT), aform_addr:$src)]>;
-
- def STQAv4i32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
- "stqa\t$rT, $src", LoadStore,
- [(store (v4i32 VECREG:$rT), aform_addr:$src)]>;
-
- def STQAv2i64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
- "stqa\t$rT, $src", LoadStore,
- [(store (v2i64 VECREG:$rT), aform_addr:$src)]>;
-
- def STQAv4f32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
- "stqa\t$rT, $src", LoadStore,
- [(store (v4f32 VECREG:$rT), aform_addr:$src)]>;
-
- def STQAv2f64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
- "stqa\t$rT, $src", LoadStore,
- [(store (v2f64 VECREG:$rT), aform_addr:$src)]>;
-
- def STQAr128 : RI10Form<0b00100100, (outs), (ins GPRC:$rT, addr256k:$src),
- "stqa\t$rT, $src", LoadStore,
- [(store GPRC:$rT, aform_addr:$src)]>;
-
- def STQAr64 : RI10Form<0b00100100, (outs), (ins R64C:$rT, addr256k:$src),
- "stqa\t$rT, $src", LoadStore,
- [(store R64C:$rT, aform_addr:$src)]>;
-
- def STQAr32 : RI10Form<0b00100100, (outs), (ins R32C:$rT, addr256k:$src),
- "stqa\t$rT, $src", LoadStore,
- [(store R32C:$rT, aform_addr:$src)]>;
-
- // Floating Point
- def STQAf32 : RI10Form<0b00100100, (outs), (ins R32FP:$rT, addr256k:$src),
- "stqa\t$rT, $src", LoadStore,
- [(store R32FP:$rT, aform_addr:$src)]>;
-
- def STQAf64 : RI10Form<0b00100100, (outs), (ins R64FP:$rT, addr256k:$src),
- "stqa\t$rT, $src", LoadStore,
- [(store R64FP:$rT, aform_addr:$src)]>;
-
- def STQAr16 : RI10Form<0b00100100, (outs), (ins R16C:$rT, addr256k:$src),
- "stqa\t$rT, $src", LoadStore,
- [(store R16C:$rT, aform_addr:$src)]>;
-
- def STQAr8 : RI10Form<0b00100100, (outs), (ins R8C:$rT, addr256k:$src),
- "stqa\t$rT, $src", LoadStore,
- [(store R8C:$rT, aform_addr:$src)]>;
-
- def STQXv16i8 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
- "stqx\t$rT, $src", LoadStore,
- [(store (v16i8 VECREG:$rT), xform_addr:$src)]>;
-
- def STQXv8i16 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
- "stqx\t$rT, $src", LoadStore,
- [(store (v8i16 VECREG:$rT), xform_addr:$src)]>;
-
- def STQXv4i32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
- "stqx\t$rT, $src", LoadStore,
- [(store (v4i32 VECREG:$rT), xform_addr:$src)]>;
-
- def STQXv2i64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
- "stqx\t$rT, $src", LoadStore,
- [(store (v2i64 VECREG:$rT), xform_addr:$src)]>;
-
- def STQXv4f32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
- "stqx\t$rT, $src", LoadStore,
- [(store (v4f32 VECREG:$rT), xform_addr:$src)]>;
-
- def STQXv2f64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
- "stqx\t$rT, $src", LoadStore,
- [(store (v2f64 VECREG:$rT), xform_addr:$src)]>;
-
- def STQXr128 : RI10Form<0b00100100, (outs), (ins GPRC:$rT, memrr:$src),
- "stqx\t$rT, $src", LoadStore,
- [(store GPRC:$rT, xform_addr:$src)]>;
-
- def STQXr64:
- RI10Form<0b00100100, (outs), (ins R64C:$rT, memrr:$src),
- "stqx\t$rT, $src", LoadStore,
- [(store R64C:$rT, xform_addr:$src)]>;
-
- def STQXr32:
- RI10Form<0b00100100, (outs), (ins R32C:$rT, memrr:$src),
- "stqx\t$rT, $src", LoadStore,
- [(store R32C:$rT, xform_addr:$src)]>;
-
- // Floating Point
- def STQXf32:
- RI10Form<0b00100100, (outs), (ins R32FP:$rT, memrr:$src),
- "stqx\t$rT, $src", LoadStore,
- [(store R32FP:$rT, xform_addr:$src)]>;
-
- def STQXf64:
- RI10Form<0b00100100, (outs), (ins R64FP:$rT, memrr:$src),
- "stqx\t$rT, $src", LoadStore,
- [(store R64FP:$rT, xform_addr:$src)]>;
-
- def STQXr16:
- RI10Form<0b00100100, (outs), (ins R16C:$rT, memrr:$src),
- "stqx\t$rT, $src", LoadStore,
- [(store R16C:$rT, xform_addr:$src)]>;
-
- def STQXr8:
- RI10Form<0b00100100, (outs), (ins R8C:$rT, memrr:$src),
- "stqx\t$rT, $src", LoadStore,
- [(store R8C:$rT, xform_addr:$src)]>;
+def STQDv16i8 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
+ "stqd\t$rT, $src", LoadStore,
+ [(store (v16i8 VECREG:$rT), dform_addr:$src)]>;
+
+def STQDv8i16 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
+ "stqd\t$rT, $src", LoadStore,
+ [(store (v8i16 VECREG:$rT), dform_addr:$src)]>;
+
+def STQDv4i32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
+ "stqd\t$rT, $src", LoadStore,
+ [(store (v4i32 VECREG:$rT), dform_addr:$src)]>;
+
+def STQDv2i64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
+ "stqd\t$rT, $src", LoadStore,
+ [(store (v2i64 VECREG:$rT), dform_addr:$src)]>;
+
+def STQDv4f32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
+ "stqd\t$rT, $src", LoadStore,
+ [(store (v4f32 VECREG:$rT), dform_addr:$src)]>;
+
+def STQDv2f64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
+ "stqd\t$rT, $src", LoadStore,
+ [(store (v2f64 VECREG:$rT), dform_addr:$src)]>;
+
+def STQDr128 : RI10Form<0b00100100, (outs), (ins GPRC:$rT, memri10:$src),
+ "stqd\t$rT, $src", LoadStore,
+ [(store GPRC:$rT, dform_addr:$src)]>;
+
+def STQDr64 : RI10Form<0b00100100, (outs), (ins R64C:$rT, memri10:$src),
+ "stqd\t$rT, $src", LoadStore,
+ [(store R64C:$rT, dform_addr:$src)]>;
+
+def STQDr32 : RI10Form<0b00100100, (outs), (ins R32C:$rT, memri10:$src),
+ "stqd\t$rT, $src", LoadStore,
+ [(store R32C:$rT, dform_addr:$src)]>;
+
+// Floating Point
+def STQDf32 : RI10Form<0b00100100, (outs), (ins R32FP:$rT, memri10:$src),
+ "stqd\t$rT, $src", LoadStore,
+ [(store R32FP:$rT, dform_addr:$src)]>;
+
+def STQDf64 : RI10Form<0b00100100, (outs), (ins R64FP:$rT, memri10:$src),
+ "stqd\t$rT, $src", LoadStore,
+ [(store R64FP:$rT, dform_addr:$src)]>;
+
+def STQDr16 : RI10Form<0b00100100, (outs), (ins R16C:$rT, memri10:$src),
+ "stqd\t$rT, $src", LoadStore,
+ [(store R16C:$rT, dform_addr:$src)]>;
+
+def STQDr8 : RI10Form<0b00100100, (outs), (ins R8C:$rT, memri10:$src),
+ "stqd\t$rT, $src", LoadStore,
+ [(store R8C:$rT, dform_addr:$src)]>;
+
+def STQAv16i8 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
+ "stqa\t$rT, $src", LoadStore,
+ [(store (v16i8 VECREG:$rT), aform_addr:$src)]>;
+
+def STQAv8i16 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
+ "stqa\t$rT, $src", LoadStore,
+ [(store (v8i16 VECREG:$rT), aform_addr:$src)]>;
+
+def STQAv4i32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
+ "stqa\t$rT, $src", LoadStore,
+ [(store (v4i32 VECREG:$rT), aform_addr:$src)]>;
+
+def STQAv2i64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
+ "stqa\t$rT, $src", LoadStore,
+ [(store (v2i64 VECREG:$rT), aform_addr:$src)]>;
+
+def STQAv4f32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
+ "stqa\t$rT, $src", LoadStore,
+ [(store (v4f32 VECREG:$rT), aform_addr:$src)]>;
+
+def STQAv2f64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
+ "stqa\t$rT, $src", LoadStore,
+ [(store (v2f64 VECREG:$rT), aform_addr:$src)]>;
+
+def STQAr128 : RI10Form<0b00100100, (outs), (ins GPRC:$rT, addr256k:$src),
+ "stqa\t$rT, $src", LoadStore,
+ [(store GPRC:$rT, aform_addr:$src)]>;
+
+def STQAr64 : RI10Form<0b00100100, (outs), (ins R64C:$rT, addr256k:$src),
+ "stqa\t$rT, $src", LoadStore,
+ [(store R64C:$rT, aform_addr:$src)]>;
+
+def STQAr32 : RI10Form<0b00100100, (outs), (ins R32C:$rT, addr256k:$src),
+ "stqa\t$rT, $src", LoadStore,
+ [(store R32C:$rT, aform_addr:$src)]>;
+
+// Floating Point
+def STQAf32 : RI10Form<0b00100100, (outs), (ins R32FP:$rT, addr256k:$src),
+ "stqa\t$rT, $src", LoadStore,
+ [(store R32FP:$rT, aform_addr:$src)]>;
+
+def STQAf64 : RI10Form<0b00100100, (outs), (ins R64FP:$rT, addr256k:$src),
+ "stqa\t$rT, $src", LoadStore,
+ [(store R64FP:$rT, aform_addr:$src)]>;
+
+def STQAr16 : RI10Form<0b00100100, (outs), (ins R16C:$rT, addr256k:$src),
+ "stqa\t$rT, $src", LoadStore,
+ [(store R16C:$rT, aform_addr:$src)]>;
+
+def STQAr8 : RI10Form<0b00100100, (outs), (ins R8C:$rT, addr256k:$src),
+ "stqa\t$rT, $src", LoadStore,
+ [(store R8C:$rT, aform_addr:$src)]>;
+
+def STQXv16i8 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
+ "stqx\t$rT, $src", LoadStore,
+ [(store (v16i8 VECREG:$rT), xform_addr:$src)]>;
+
+def STQXv8i16 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
+ "stqx\t$rT, $src", LoadStore,
+ [(store (v8i16 VECREG:$rT), xform_addr:$src)]>;
+
+def STQXv4i32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
+ "stqx\t$rT, $src", LoadStore,
+ [(store (v4i32 VECREG:$rT), xform_addr:$src)]>;
+
+def STQXv2i64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
+ "stqx\t$rT, $src", LoadStore,
+ [(store (v2i64 VECREG:$rT), xform_addr:$src)]>;
+
+def STQXv4f32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
+ "stqx\t$rT, $src", LoadStore,
+ [(store (v4f32 VECREG:$rT), xform_addr:$src)]>;
+
+def STQXv2f64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
+ "stqx\t$rT, $src", LoadStore,
+ [(store (v2f64 VECREG:$rT), xform_addr:$src)]>;
+
+def STQXr128 : RI10Form<0b00100100, (outs), (ins GPRC:$rT, memrr:$src),
+ "stqx\t$rT, $src", LoadStore,
+ [(store GPRC:$rT, xform_addr:$src)]>;
+
+def STQXr64:
+ RI10Form<0b00100100, (outs), (ins R64C:$rT, memrr:$src),
+ "stqx\t$rT, $src", LoadStore,
+ [(store R64C:$rT, xform_addr:$src)]>;
+
+def STQXr32:
+ RI10Form<0b00100100, (outs), (ins R32C:$rT, memrr:$src),
+ "stqx\t$rT, $src", LoadStore,
+ [(store R32C:$rT, xform_addr:$src)]>;
+
+// Floating Point
+def STQXf32:
+ RI10Form<0b00100100, (outs), (ins R32FP:$rT, memrr:$src),
+ "stqx\t$rT, $src", LoadStore,
+ [(store R32FP:$rT, xform_addr:$src)]>;
+
+def STQXf64:
+ RI10Form<0b00100100, (outs), (ins R64FP:$rT, memrr:$src),
+ "stqx\t$rT, $src", LoadStore,
+ [(store R64FP:$rT, xform_addr:$src)]>;
+
+def STQXr16:
+ RI10Form<0b00100100, (outs), (ins R16C:$rT, memrr:$src),
+ "stqx\t$rT, $src", LoadStore,
+ [(store R16C:$rT, xform_addr:$src)]>;
+
+def STQXr8:
+ RI10Form<0b00100100, (outs), (ins R8C:$rT, memrr:$src),
+ "stqx\t$rT, $src", LoadStore,
+ [(store R8C:$rT, xform_addr:$src)]>;
/* Store quadword, PC relative: Not much use at this point in time. Might
- be useful for relocatable code.
- def STQR : RI16Form<0b111000100, (outs), (ins VECREG:$rT, s16imm:$disp),
- "stqr\t$rT, $disp", LoadStore,
- [(store VECREG:$rT, iaddr:$disp)]>;
- */
-}
+ be useful for relocatable code.
+def STQR : RI16Form<0b111000100, (outs), (ins VECREG:$rT, s16imm:$disp),
+ "stqr\t$rT, $disp", LoadStore,
+ [(store VECREG:$rT, iaddr:$disp)]>;
+*/
//===----------------------------------------------------------------------===//
// Generate Controls for Insertion:
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=45654&r1=45653&r2=45654&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Sun Jan 6 00:44:58 2008
@@ -213,7 +213,6 @@
!strconcat(instr_asm, " $dst, $addr"),
[(set CPURegs:$dst, (OpNode addr:$addr))], IILoad>;
-let isStore = 1 in
class StoreM<bits<6> op, string instr_asm, PatFrag OpNode>:
FI< op,
(outs),
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td?rev=45654&r1=45653&r2=45654&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td Sun Jan 6 00:44:58 2008
@@ -513,14 +513,10 @@
RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">,
isPPC64;
-}
-
-let isStore = 1, PPC970_Unit = 2 in {
-
+let isStore = 1 in
def STDUX : XForm_8<31, 181, (outs), (ins G8RC:$rS, memrr:$dst),
"stdux $rS, $dst", LdStSTD,
[]>, isPPC64;
-
// STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register.
def STD_32 : DSForm_1<62, 0, (outs), (ins GPRC:$rT, memrix:$dst),
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=45654&r1=45653&r2=45654&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Sun Jan 6 00:44:58 2008
@@ -52,7 +52,8 @@
def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
-def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, [SDNPHasChain]>;
+def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
+ [SDNPHasChain, SDNPMayStore]>;
// This sequence is used for long double->int conversions. It changes the
// bits in the FPSCR which is not modelled.
@@ -88,7 +89,8 @@
def PPCshl : SDNode<"PPCISD::SHL" , SDT_PPCShiftOp>;
def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>;
-def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore, [SDNPHasChain]>;
+def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore,
+ [SDNPHasChain, SDNPMayStore]>;
// These are target-independent nodes, but have target-specific formats.
def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
@@ -119,7 +121,8 @@
[SDNPHasChain, SDNPOptInFlag]>;
def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx, [SDNPHasChain]>;
-def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx, [SDNPHasChain]>;
+def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
+ [SDNPHasChain, SDNPMayStore]>;
// Instructions to support dynamic alloca.
def SDTDynOp : SDTypeProfile<1, 2, []>;
@@ -639,6 +642,7 @@
def STWUX : XForm_8<31, 183, (outs), (ins GPRC:$rS, GPRC:$rA, GPRC:$rB),
"stwux $rS, $rA, $rB", LdStGeneral,
[]>;
+}
def STHBRX: XForm_8<31, 918, (outs), (ins GPRC:$rS, memrr:$dst),
"sthbrx $rS, $dst", LdStGeneral,
[(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i16)]>,
@@ -651,7 +655,7 @@
def STFIWX: XForm_28<31, 983, (outs), (ins F8RC:$frS, memrr:$dst),
"stfiwx $frS, $dst", LdStUX,
[(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>;
-}
+
def STFSX : XForm_28<31, 663, (outs), (ins F4RC:$frS, memrr:$dst),
"stfsx $frS, $dst", LdStUX,
[(store F4RC:$frS, xaddr:$dst)]>;
Modified: llvm/trunk/lib/Target/TargetSelectionDAG.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetSelectionDAG.td?rev=45654&r1=45653&r2=45654&view=diff
==============================================================================
--- llvm/trunk/lib/Target/TargetSelectionDAG.td (original)
+++ llvm/trunk/lib/Target/TargetSelectionDAG.td Sun Jan 6 00:44:58 2008
@@ -189,6 +189,7 @@
def SDNPOutFlag : SDNodeProperty; // Write a flag result
def SDNPInFlag : SDNodeProperty; // Read a flag operand
def SDNPOptInFlag : SDNodeProperty; // Optionally read a flag operand
+def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'isStore'.
//===----------------------------------------------------------------------===//
// Selection DAG Node definitions.
@@ -313,8 +314,10 @@
// Do not use ld, st directly. Use load, extload, sextload, zextload, store,
// and truncst (see below).
def ld : SDNode<"ISD::LOAD" , SDTLoad, [SDNPHasChain]>;
-def st : SDNode<"ISD::STORE" , SDTStore, [SDNPHasChain]>;
-def ist : SDNode<"ISD::STORE" , SDTIStore, [SDNPHasChain]>;
+def st : SDNode<"ISD::STORE" , SDTStore,
+ [SDNPHasChain, SDNPMayStore]>;
+def ist : SDNode<"ISD::STORE" , SDTIStore,
+ [SDNPHasChain, SDNPMayStore]>;
def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, 0, []>, []>;
Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp?rev=45654&r1=45653&r2=45654&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp Sun Jan 6 00:44:58 2008
@@ -317,6 +317,8 @@
Properties |= 1 << SDNPInFlag;
} else if (PropList[i]->getName() == "SDNPOptInFlag") {
Properties |= 1 << SDNPOptInFlag;
+ } else if (PropList[i]->getName() == "SDNPMayStore") {
+ Properties |= 1 << SDNPMayStore;
} else {
cerr << "Unknown SD Node property '" << PropList[i]->getName()
<< "' on node '" << R->getName() << "'!\n";
Modified: llvm/trunk/utils/TableGen/CodeGenTarget.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.h?rev=45654&r1=45653&r2=45654&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenTarget.h (original)
+++ llvm/trunk/utils/TableGen/CodeGenTarget.h Sun Jan 6 00:44:58 2008
@@ -30,8 +30,15 @@
class CodeGenTarget;
// SelectionDAG node properties.
-enum SDNP { SDNPCommutative, SDNPAssociative, SDNPHasChain,
- SDNPOutFlag, SDNPInFlag, SDNPOptInFlag };
+enum SDNP {
+ SDNPCommutative,
+ SDNPAssociative,
+ SDNPHasChain,
+ SDNPOutFlag,
+ SDNPInFlag,
+ SDNPOptInFlag,
+ SDNPMayStore
+};
/// getValueType - Return the MVT::ValueType that the specified TableGen record
/// corresponds to.
Modified: llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp?rev=45654&r1=45653&r2=45654&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp Sun Jan 6 00:44:58 2008
@@ -157,9 +157,7 @@
if (Pattern == 0) return; // No pattern.
// Assume there is no side-effect unless we see one.
- // FIXME: Enable this.
- //NeverHasSideEffects = true;
-
+ NeverHasSideEffects = true;
// FIXME: Assume only the first tree is the pattern. The others are clobber
// nodes.
@@ -176,10 +174,9 @@
// Get information about the SDNode for the operator.
const SDNodeInfo &OpInfo = CDP.getSDNodeInfo(N->getOperator());
- // If this is a store node, it obviously stores to memory.
- if (OpInfo.getEnumName() == "ISD::STORE") {
+ // If node writes to memory, it obviously stores to memory.
+ if (OpInfo.hasProperty(SDNPMayStore)) {
isStore = true;
-
} else if (const CodeGenIntrinsic *IntInfo = N->getIntrinsicInfo(CDP)) {
// If this is an intrinsic, analyze it.
if (IntInfo->ModRef >= CodeGenIntrinsic::WriteArgMem)
@@ -196,15 +193,30 @@
void InstrInfoEmitter::InferFromPattern(const CodeGenInstruction &Inst,
bool &isStore, bool &isLoad,
bool &NeverHasSideEffects) {
- isStore = Inst.isStore;
- isLoad = Inst.isLoad;
- NeverHasSideEffects = Inst.neverHasSideEffects;
+ isStore = isLoad = NeverHasSideEffects = false;
InstAnalyzer(CDP, isStore, isLoad, NeverHasSideEffects).Analyze(Inst.TheDef);
-
+
+ // InstAnalyzer only correctly analyzes isStore so far.
+ if (Inst.isStore) { // If the .td file explicitly sets isStore, use it.
+ // If we decided that this is a store from the pattern, then the .td file
+ // entry is redundant.
+ if (isStore)
+ fprintf(stderr, "Warning: isStore flag explicitly set on instruction
'%s'"
+ " but flag already inferred from pattern.\n",
+ Inst.getName().c_str());
+ isStore = true;
+ }
+
+ // These two override everything.
+ isLoad = Inst.isLoad;
+ NeverHasSideEffects = Inst.neverHasSideEffects;
+
+#if 0
// If the .td file explicitly says there is no side effect, believe it.
if (Inst.neverHasSideEffects)
NeverHasSideEffects = true;
+#endif
}
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